CN103761942A - Digital tube display and key control chip with array display multiplexing algorithm - Google Patents
Digital tube display and key control chip with array display multiplexing algorithm Download PDFInfo
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Abstract
The invention relates to an LED digital tube display and key control chip with an array display multiplexing algorithm. The chip is internally provided with a second-line-type serial interface module, a command decoder module, an array display multiplexing control module, an output latch module, a brightness adjusting module, a key scanning time sequence control module, a shifting storage module, a key input judging module, a key scanning storage module and an output driving module, and meanwhile internally provided with an oscillating circuit module and a reset circuit module. According to the LED digital tube display and key control special chip with the array display multiplexing algorithm, the 12-digit and 8-segment digital tube display driving and 4*8=32-key control function inside a 16-pin packaging chip can be achieved.
Description
Technical field
The present invention relates to the demonstration of LED charactron and button control chip that a kind of tool array shows multiplexing algorithm.
Background technology
At present, LED (light emitting diode) charactron display driver is widely used in the small household appliances such as Set Top Box, electromagnetic oven, micro-stove, electronic scale, massager, instrument and meter, the demonstration of the each field of medicine equipment product.The display driver of this type of charactron adopts section, the position direct driving technologies of charactron mostly, with the present invention, can reach, drive and show that 12 charactrons are example, at least need pin+8, a 12 positions section pin, add power supply and ground and data communication pin, 24 pins of minimum need coordinate and can realize, and too many output pin, will make wafer area increase, and packaging cost is also high simultaneously.Array of the present invention shows that multiplex technique can improve these shortcomings.
Summary of the invention
Task of the present invention is that existing LED charactron display driver and button control chip structure are improved, provide (LED) charactron that a kind of tool array shows multiplexing algorithm to show and by key control special chip, task of the present invention is achieved through the following technical solutions: in described chip, be provided with TW two wire serial interface module, command decoder module; Array shows multiplexing control module, output latch module; Briliancy adjustment module; Key is swept time-sequence control module, shift LD module; Key-press input judging module, key are swept storage module and output driver module; Be built-in with oscillatory circuit module, reset circuit module etc. simultaneously.In chip, each module connects as follows: TW two wire serial signal DIO/CLK is connected with command decoder module by two-wire serial interface module, and the communication of intermodule is two-way communication; Command decoder module shows that with briliancy adjustment module, array multiplexing time-sequence control module, key are swept time-sequence control module, key is swept storage module and is connected; Briliancy adjustment module is receiving orders after code translator dependent instruction, and output briliancy grade command information carries out latch to output latch; Array shows that multiplexing tfi module is receiving orders after code translator dependent instruction, and the corresponding demonstration of output steering order information is carried out latch to output latch; Output signal one tunnel that key is swept time-sequence control module outputs to output latch module, another road Output Shift Register; The output terminal of shift register module is connected with an input end of output driver module; Output latch module and shift register module are taken from the signal input of output driver module, and export D1-D12 Gong12 road output display and be interfaced to the physical pin of chip; D9-D12 tetra-road signals output to key-press input decision circuit simultaneously; The output terminal of key-press input decision circuit is connected to key and sweeps memory module; Key sweeps that the output terminal of memory module is swept sequential control circuit with key, command decoder is connected; Built-in chip type reset circuit and oscillatory circuit, for the each module of whole system provides timing reference.
Compared with the prior art, tool array of the present invention shows that the LED charactron of multiplexing algorithm shows and by key control special chip, completes and in the case chip of 16 pins, realizes 12 8 segment numeral pipe display drivers and 4*8=32 by key control function.Tool of the present invention has the following advantages:
1. the present invention adopts array to show multiplexing algorithm, can drive interface by 12 outputs, and the driving that realizes 12 * 8 sections shows, optimized interface pin number.
2. the built-in 8 grades of briliancy regulating circuits of the present invention, are suitable for different size charactron display application, and dirigibility is high
3. the present invention adopts interface button multiplexing technology, and in the situation that not increasing any pin interface, time division multiplex display driver interface carries out key scan, realizes by key control function.
4. the built-in pull-up resistor of the present invention, simultaneously built-in oscillatory circuit, electrify restoration circuit, without peripheral cell, further optimization system cost.
5. the present invention adopts two-wire serial interface (DIO CLK) mode, add indispensable power pins VDD, pin GND, only need altogether 16 chip pins.
6. two-wire serial interface built-in level change-over circuit of the present invention, can realize and different host computer interface level compatible communications in 3.0～5V.
7. the present invention optimizes peripheral pin sequence, can realize PCB placement-and-routing and sort flexibly, improves the ease for use of machine product PCB design.
Accompanying drawing explanation
Fig. 1 is the chip structure block scheme of a kind of embodiment of the present invention;
Fig. 2 is that the chip interface of a kind of embodiment of the present invention distributes schematic diagram;
Fig. 3 is chip pin definition and the encapsulation sequence schematic diagram of a kind of embodiment of the present invention.
Embodiment
Below in conjunction with the specific embodiment of accompanying drawing, the present invention is further described.(but not being limitation of the present invention).
As shown in Figure 1, be the chip structure block scheme of a kind of embodiment of the present invention, of the present invention
In chip, be provided with TW two wire serial interface module, command decoder module; Array shows multiplexing control module, output latch module; Briliancy adjustment module; Key is swept time-sequence control module, shift LD module; Key-press input judging module, key are swept storage module and output driver module; Be built-in with oscillatory circuit module, reset circuit module etc. simultaneously; TW two wire serial signal DIO/CLK is connected with command decoder module by two-wire serial interface module, and the communication of intermodule is two-way communication; Command decoder module shows that with briliancy adjustment module, array multiplexing time-sequence control module, key are swept time-sequence control module, key is swept storage module and is connected; Briliancy adjustment module is receiving orders after code translator dependent instruction, and output briliancy grade command information carries out latch to output latch; Array shows that multiplexing tfi module is receiving orders after code translator dependent instruction, and the corresponding demonstration of output steering order information is carried out latch to output latch; Output signal one tunnel that key is swept time-sequence control module outputs to output latch module, another road Output Shift Register; The output terminal of shift register module is connected with an input end of output driver module; Output latch module and shift register module are taken from the signal input of output driver module, and export D1-D12 Gong12 road output display and be interfaced to the physical pin of chip; D9-D12 tetra-road signals output to key-press input decision circuit simultaneously; The output terminal of key-press input decision circuit is connected to key and sweeps memory module; Key sweeps that the output terminal of memory module is swept sequential control circuit with key, command decoder is connected; Built-in chip type reset circuit and oscillatory circuit, for the each module of whole system provides timing reference.
Described tool array shows that (LED) charactron of multiplexing algorithm drives and button control chip, adopts array to show multiplexing algorithm, and Jiang12 road display driver interface is divided into three groups, is respectively: D1 D2 D3 D4; D5 D6 D7 D8; D9 D10 D11 D12, and by interface configuration, is configured to respectively a drive pattern by every group, other remaining two groups totally 8 interfaces corresponding configuration become a section drive pattern, so round-robin, can realize 3 groups of 8 sections of * 4=12 positions display drivers; In drive pattern in place, corresponding interface is input state, and in section drive pattern, corresponding interface is output state; By the PAD in java standard library is modified, strengthen the length breadth ratio of driving tube, increase driving force, make interface driver electric current I OL >=360mA, large electric current demand while meeting the multiplexing driving of multidigit demonstration.
Described tool array shows that (LED) charactron of multiplexing algorithm drives and button control chip, increase by 3 display register mode bits, with configuration driven, show the dutycycle of output voltage waveforms, be respectively: 1/16,2/16,4/16,6/16,8/16,10/16,12/16,14/16 totally eight grades of dutycycle outputs, realize 8 grades of brightness regulation.
Described tool array shows that (LED) charactron of multiplexing algorithm drives and button control chip; it is characterized in that adopting time-division multiplex technology; by key, sweep time-sequence control module; key scan signal is inserted in timing; and timesharing output between the each interface of D1-D8, during key scan, D9-D12 is configured to the input end of button; and by key-press input judging module, judge effective actuation of keys; By this technology, can realize 4*8=32 by key control.
Described tool array shows that (LED) charactron of multiplexing algorithm drives and button control chip, it is characterized in that adopting TW two wire serial line interface, and at the built-in pull-up resistor of communication interface, pull-up resistor adopts CMOS trap resistance technique, to improve resistance precision simultaneously, phase mutual interference while reducing with host computer distinct interface level communication, strengthens interface level compatibility.This built-in chip type reset circuit and oscillatory circuit, further optimize complete machine application cost simultaneously.
for array of the present invention, show multiplexing algorithm:
Traditional LED charactron drives and shows, each interface is one to one and drives, and with the driving of period and position, is independently, therefore needs more interface pin.
The present invention adopts the driving thinking of innovation, adopts array to show multiplexing steering logic algorithm, makes the each interface section of having concurrently, two kinds of drive patterns in position simultaneously; By rigorous driving algorithm sequential, adopt time-division dynamic scan pattern, and improve scan clock speed, improve interface driver electric current, complete the array of output interface is shown and multiplexing, as follows:
As Fig. 2 interface assignment schematic diagram:
1.Jiang 12 road display driver interfaces are divided into three groups, are respectively: D1 D2 D3 D4; D5 D6 D7 D8; D9 D10 D11 D12.
2. by interface configuration, be configured to respectively a drive pattern by every group, other remaining two groups totally 8 interfaces corresponding configuration become a section drive pattern, so round-robin, can realize 3 groups of 8 sections of * 4=12 positions display drivers.
3. in a drive pattern, corresponding interface is input state; In section drive pattern, corresponding interface is output state.
4. by the PAD in java standard library is modified, strengthen the length breadth ratio of driving tube, increase driving force, make interface driver electric current I OL >=360mA, large electric current demand while meeting the multiplexing driving of multidigit demonstration.
for 8 grades of briliancy of the present invention, regulate:
The present invention is by increasing by 3 display register mode bits, with configuration driven, show the dutycycle of output voltage waveforms, be respectively: 1/16,2/16,4/16,6/16,8/16,10/16,12/16,14/16 totally eight grades of dutycycle outputs, realize 8 grades of brightness regulation.
interface button multiplexing technology of the present invention
The present invention adopts time-division multiplex technology, by key, sweeps time-sequence control module, and key scan signal is inserted in timing, and timesharing output between the each interface of D1-D8, during key scan, D9-D12 is configured to the input end of button, and by key-press input judging module, judge effective actuation of keys.By this technology, can realize 4*8=32 by key control.
communication interface and cost optimization:
Traditional LED charactron drives and conventionally adopts three-wire type serial communication or TW two wire serial communication pattern by key control special chip, and for improve the driving force of interface and with varying level host computer interface compatibility, need plug-in pull-up resistor or level shifting circuit, cost is high.
The present invention adopts TW two wire serial line interface, and according to practical application experience, at the built-in pull-up resistor of communication interface, pull-up resistor adopts CMOS trap resistance technique, to improve resistance precision simultaneously, the phase mutual interference while reducing with host computer distinct interface level communication, strengthens interface level compatibility.The built-in reset circuit of the present invention and oscillatory circuit, further optimize complete machine application cost simultaneously
package layout
Described tool array shows that the LED charactron of multiplexing algorithm drives and button control chip, it is characterized in that this chip height is integrated in the 16 pin package sheets of SOP16 or DIP16, and according to the placement-and-routing's needs of PCB in practical application, and most of display panel PCB single-side brass plate selection demands, optimize output pin layout of the present invention, signal pins and power pins are kept to the side to arrange, PCB layout with raising key signal is unobstructed, D1-D12 arranges in order simultaneously, facilitate the cloth general character of PCB circuit, to reduce the consumption of jumper element in one side PCB layout, further Cost optimization.
As Fig. 3. chip pin definition and encapsulation sequence schematic diagram, chip height of the present invention is integrated in the 16 pin package sheets of SOP16 or DIP16, and according to the placement-and-routing's needs of PCB in practical application, and most of display panel PCB single-side brass plate selection demands, optimize output pin layout of the present invention, signal pins and power pins are kept to the side to arrange, PCB layout with raising key signal is unobstructed, D1-D12 arranges in order simultaneously, facilitate the cloth general character of PCB circuit, to reduce the consumption of jumper element in one side PCB layout, further Cost optimization.
The pin definitions of described chip is as following table:
| pin sequence number | title | explanation |
| 1-8 | d1-D8 | lED pin drives, and connects LED anode or negative electrode; Pin is also as key scanning output. |
| 9-12 | d9-D12 | lED pin drives, and connects LED anode or negative electrode; Also as button pin multiplexing, key is swept signal and is latched after the display cycle finishes |
| 14 | dIO | tW two wire serial data interface, in clock negative edge output serial data, from a high position; At rising edge clock input serial data, from a high position.At CLK low-level data, change. |
| 15 | cLK | tW two wire serial clock interface, reads serial data at rising edge, negative edge output data. |
| 13 | vDD | welding system power supply 3.0～5.0V |
| 16 | gND | welding system ground |
Word is repeated: D1-D8 is that LED pin drives, and connects LED anode or negative electrode; Pin is also as key scanning output; D9-D12 is that ED pin drives, and connects LED anode or negative electrode; Also as button pin multiplexing, key is swept signal and is latched after the display cycle finishes; DIO is TW two wire serial data interface, in clock negative edge output serial data, from a high position; At rising edge clock input serial data, from a high position, at CLK low-level data, change; CLK is TW two wire serial clock interface, at rising edge, reads serial data, negative edge output data; VDD welding system power supply 3.0～5.0V, GND welding system ground.
Be more than specific embodiments of the invention, all similar changes of doing according to above-mentioned design, ought to belong to scope of the present invention.
Claims (7)
1. the array of having shows that the charactron of multiplexing algorithm shows and by key control special chip, it is characterized in that, is provided with TW two wire serial interface module, command decoder module in described chip; Array shows multiplexing control module, output latch module; Briliancy adjustment module; Key is swept time-sequence control module, shift LD module; Key-press input judging module, key are swept storage module and output driver module; Be built-in with oscillatory circuit module, reset circuit module simultaneously; TW two wire serial signal DIO/CLK is connected with command decoder module by two-wire serial interface module, and the communication of intermodule is two-way communication; Command decoder module shows that with briliancy adjustment module, array multiplexing time-sequence control module, key are swept time-sequence control module, key is swept storage module and is connected; Briliancy adjustment module is receiving orders after code translator dependent instruction, and output briliancy grade command information carries out latch to output latch; Array shows that multiplexing tfi module is receiving orders after code translator dependent instruction, and the corresponding demonstration of output steering order information is carried out latch to output latch; Output signal one tunnel that key is swept time-sequence control module outputs to output latch module, another road Output Shift Register; The output terminal of shift register module is connected with an input end of output driver module; Output latch module and shift register module are taken from the signal input of output driver module, and export D1-D12 Gong12 road output display and be interfaced to the physical pin of chip; D9-D12 tetra-road signals output to key-press input decision circuit simultaneously; The output terminal of key-press input decision circuit is connected to key and sweeps memory module; Key sweeps that the output terminal of memory module is swept sequential control circuit with key, command decoder is connected; Built-in chip type reset circuit and oscillatory circuit, for the each module of whole system provides timing reference.
2. tool array according to claim 1 shows that the charactron of multiplexing algorithm drives and button control chip; it is characterized in that; described chip adopts array to show multiplexing algorithm, and Jiang12 road display driver interface is divided into three groups, is respectively: D1 D2 D3 D4; D5 D6 D7 D8; D9 D10 D11 D12, and by interface configuration, is configured to respectively a drive pattern by every group, other remaining two groups totally 8 interfaces corresponding configuration become a section drive pattern, so round-robin, realizes 3 groups of 8 sections of * 4=12 positions display drivers; In drive pattern in place, corresponding interface is input state, and in section drive pattern, corresponding interface is output state; By the PAD in java standard library is modified, strengthen the length breadth ratio of driving tube, increase driving force, make interface driver electric current I OL >=360mA, large electric current demand while meeting the multiplexing driving of multidigit demonstration.
3. tool array according to claim 1 shows that the charactron of multiplexing algorithm drives and button control chip, it is characterized in that, described chip increases by 3 display register mode bits, with configuration driven, show the dutycycle of output voltage waveforms, be respectively: 1/16,2/16,4/16,6/16,8/16,10/16,12/16,14/16 totally eight grades of dutycycle outputs, realize 8 grades of brightness regulation.
4. tool array according to claim 1 shows that the charactron of multiplexing algorithm drives and button control chip; it is characterized in that; described chip adopts time-division multiplex technology; by key, sweep time-sequence control module, key scan signal is inserted in timing, and timesharing output between the each interface of D1-D8; during key scan; D9-D12 is configured to the input end of button, and by key-press input judging module, judges effective actuation of keys; By this technology, realize 4*8=32 by key control.
5. tool array according to claim 1 shows that the charactron of multiplexing algorithm drives and button control chip; it is characterized in that; described chip adopts TW two wire serial line interface; and at the built-in pull-up resistor of communication interface; pull-up resistor adopts CMOS trap resistance technique; to improve resistance precision simultaneously, the phase mutual interference while reducing with host computer distinct interface level communication, strengthens interface level compatibility; This built-in chip type reset circuit and oscillatory circuit, further optimize complete machine application cost simultaneously.
6. tool array according to claim 1 shows that the charactron of multiplexing algorithm drives and button control chip, it is characterized in that, described chip height is integrated in the 16 pin package sheets of SOP16 or DIP16, and according to the placement-and-routing's needs of PCB in practical application, and most of display panel PCB single-side brass plate selection demands, optimize output pin layout of the present invention, signal pins and power pins are kept to the side to arrange, PCB layout with raising key signal is unobstructed, D1-D12 arranges in order simultaneously, facilitate the cloth general character of PCB circuit, to reduce the consumption of jumper element in one side PCB layout, further Cost optimization.
7. tool array according to claim 1 shows that the charactron of multiplexing algorithm drives and button control chip, it is characterized in that, the pin D1-D8 of described chip is that LED pin drives, and connects LED anode or negative electrode; Pin is also as key scanning output; D9-D12 is that LED pin drives, and connects LED anode or negative electrode; Also as key-press input pin multiplexing, key is swept signal and is latched after the display cycle finishes; DIO is TW two wire serial data interface, in clock negative edge output serial data, from a high position; At rising edge clock input serial data, from a high position, at CLK low-level data, change; CLK is TW two wire serial clock interface, at rising edge, reads serial data, negative edge output data; VDD welding system power supply 3.0～5.0V, GND welding system ground.
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| CN201410051204.8A CN103761942B (en) | 2014-02-14 | 2014-02-14 | The numeral method of tool array display multiplexing algorithm and key control chip |
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| CN104050924A (en) * | 2014-06-27 | 2014-09-17 | 杭州士兰微电子股份有限公司 | LED drive chip, control method of LED drive chip and LED module |
| CN104077990A (en) * | 2014-07-02 | 2014-10-01 | 福州福大海矽微电子有限公司 | LED nixie tube display and key control chip using time division multiplexing technology |
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| CN110148370A (en) * | 2019-05-23 | 2019-08-20 | 福建船政交通职业学院 | A kind of novel scanning circuit |
| CN110176201A (en) * | 2019-05-23 | 2019-08-27 | 福建船政交通职业学院 | It is a kind of display and key scan sequential control method and device |
| CN110176201B (en) * | 2019-05-23 | 2023-02-28 | 福建船政交通职业学院 | Time sequence control method and device for display and key scanning |
| CN114631847A (en) * | 2022-05-20 | 2022-06-17 | 之江实验室 | Time-sharing multiplexing method for inhibiting crosstalk of medical ultrasonic transducer array |
| CN114631847B (en) * | 2022-05-20 | 2022-09-09 | 之江实验室 | Time-sharing multiplexing method for inhibiting crosstalk of medical ultrasonic transducer array |
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