CN207924015U - A kind of Intelligent high-precision analog signal sampling system - Google Patents

Abstract

The utility model discloses a kind of Intelligent high-precision analog signal sampling system, sampling system includes multiple ADC module, fpga chip, Signal-regulated kinase, data cache module；The sampling input pin of ADC module interconnects, and connection signal conditioning module output end, Signal-regulated kinase input terminal are connected with sampling probe；Fpga chip connects host computer by serial driver, and each ADC chips are connected by different control pins；Module occurs for fpga chip onboard clock, generates multiple sampling clocks, each sampling clock output pin is respectively connected with the clock input pin of an ADC module.The utility model realizes the multiplication of ADC sample rates under the premise of not changing ADC models.The utility model is simple in structure, easy to use, of low cost.

Description

A kind of Intelligent high-precision analog signal sampling system

Technical field

The utility model is related to a kind of analog signal measurement apparatus, specifically a kind of Intelligent high-precision analog signal sampling System.

Background technology

ADC chips have its corresponding maximum sample frequency Fmax, when the analog signal for needing to sample includes more frequency When rate is more than the signal spectrum of Fmax, it just will appear prodigious error using the measurement result of the ADC, if to ensure higher Sampling precision, it is necessary to replace the ADC of more high sampling rate.

However the ADC chip prices of high sampling rate are expensive, in general, sample rate doubles, and the promotion of price is much More than one times.Therefore, in actual product research and development, for cost consideration, it is therefore desirable under the premise of not changing ADC models, improve The precision of sampling system.

Utility model content

The utility model is exactly to solve the above-mentioned problems, to provide a kind of Intelligent high-precision analog signal sampling system System.

The utility model is implemented according to following technical scheme.

A kind of Intelligent high-precision analog signal sampling system, system include sampling terminal and host computer；The sampling Terminal includes N（N>1）A ADC module, fpga chip, Signal-regulated kinase, data cache module；The reference of the ADC module Voltage input pin is all connected with the output end of the same voltage reference block；The sampling input pin of the ADC module mutually interconnects It is connected together, and connection signal conditioning module output end, Signal-regulated kinase input terminal are connected with sampling probe；The signal tune Reason module input connects the in-phase input end of operational amplifier U1A, the both ends resistance R2 point by resistance R1, R2 for being serially connected Reference ground is not connected with capacitance C2 by capacitance C1；The inverting input of operational amplifier U1A by resistance R3 connection reference grounds, Also pass through resistance R4 connection power supplys VCC；The in-phase input end of the output end connection operational amplifier U1B of operational amplifier U1A, fortune Output end of the output end of amplifier U1B as Signal-regulated kinase is calculated, and is connected with the inverting input of U1B；The FPGA Chip connects host computer by serial driver, and each ADC chips are connected by different control pins；Fpga chip is circumscribed with Source crystal oscillator, which is used as, refers to clock, and module occurs for fpga chip onboard clock, and the Clock generation module generates N number of sampling clock； The cycle T all same of each sampling clock, phase differ T/N successively, and each sampling clock output pin of fpga chip is divided equally It is not connected with the clock input pin of an ADC module；Fpga chip accesses data buffer storage mould by full duplex digital interface Block, and mark off in cache module that N number of size is identical and the nonoverlapping data buffer area in address；Fpga chip is also externally drawn N number of data input channel, is separately connected the digital output end of each ADC module, and each data input channel corresponds to a data Buffer area.

Further, the ADC module is encapsulated as IC chip；The operational amplifier U1A and U1B is integrated in together In a piece of IC chip.

Further, the serial driver is usb driver, and the data cache module is DDR chips.

Further, the host computer is the PC machine with display.

Further, it is additionally provided in the sampling system for the power module for sampling terminal power supply.

Further, resistance R1=R2=15 Ω, R3=10K Ω, R4=10K Ω；Capacitance C1=10pF, C2=10pF.

The utility model obtains following advantageous effect.

The utility model provides a kind of Intelligent high-precision analog signal sampling system, before not changing ADC models It puts, realizes the multiplication of ADC sample rates.The utility model is simple in structure, easy to use, of low cost.

Description of the drawings

Fig. 1 is the structure diagram of the utility model；

Fig. 2 is the oscillogram of signal sampling clock and ADC sample reference clocks in the utility model；

Fig. 3 is sampling point distributions figure when monolithic ADC is sampled in the utility model；

Fig. 4 is sampling point distributions figure when two panels ADC is sampled in the utility model；

Fig. 5 is the circuit diagram of Signal-regulated kinase in the utility model.

Specific implementation mode

Referring to the drawings and embodiment carries out further technology explanation to the utility model.

As shown in Fig. 1~5, a kind of Intelligent high-precision analog signal sampling system, system includes sampling terminal and upper Position machine；The sampling terminal includes N（N>1）A ADC module, fpga chip, Signal-regulated kinase, data cache module；It is described The reference voltage input pin of ADC module is all connected with the output end of the same voltage reference block；The sampling of the ADC module is defeated Enter pin to interconnect, and connection signal conditioning module output end, Signal-regulated kinase input terminal and sampling probe phase Even；The Signal-regulated kinase input terminal connects the homophase input of operational amplifier U1A by resistance R1, R2 for being serially connected End, the both ends resistance R2 connect reference ground by capacitance C1 with capacitance C2 respectively；The inverting input of operational amplifier U1A passes through electricity R3 connection reference grounds are hindered, resistance R4 connection power supplys VCC is also passed through；The output end connection operational amplifier U1B of operational amplifier U1A In-phase input end, the output end of the output end of operational amplifier U1B as Signal-regulated kinase, and with the anti-phase input of U1B End is connected；The fpga chip connects host computer by serial driver, and each ADC cores are connected by different control pins Piece；Fpga chip is circumscribed with source crystal oscillator and is used as with reference to clock, and module, the Clock generation module occur for fpga chip onboard clock Generate N number of sampling clock；The cycle T all same of each sampling clock, phase differ T/N, each sampling of fpga chip successively Clock output pin is respectively connected with the clock input pin of an ADC module；Fpga chip is connect by full duplex number Mouthful data cache module is accessed, and marks off in cache module that N number of size is identical and the nonoverlapping data buffer area in address； Fpga chip also externally draws N number of data input channel, is separately connected the digital output end of each ADC module, and each data are defeated Enter channel and corresponds to a data buffer area.

The ADC module is encapsulated as IC chip；The operational amplifier U1A and U1B is integrated in a piece of integrated In circuit chip.

The serial driver is usb driver, and the data cache module is DDR chips.

The host computer is the PC machine with display.

It is additionally provided in the sampling system for the power module for sampling terminal power supply.

Resistance R1=R2=15 Ω, R3=10K Ω, R4=10K Ω；Capacitance C1=10pF, C2=10pF.

A kind of method of sampling stacked based on ADC, is included the following steps,

S1：Sampling system power-up initializing, probe generate physical contact with analog signal to be measured；

S2：Host computer is sent to FPGA by serial ports and is ordered, and sampling period T1 is set, and FPGA judges 1/T1 and monolithic ADC The relationship of the maximum sample clock frequency f of chip；For causing sampling periods of the 1/T1 less than or equal to f to set, walked into S3 Suddenly；For causing sampling periods of the 1/T1 more than f and less than or equal to Nf to set, into S4 steps；For causing 1/T to be more than Nf Sampling period setting, fpga chip is replied to host computer can not execute the prompt message of sampling；

S3：Fpga chip selects a piece of ADC chips to enter enabled state by controlling pin, while by other ADC chips It is set as disabled state；Fpga chip provides the sample reference clock that frequency is 1/T1 to the ADC chips that are enabled, while will be from Data after the quantization that the ADC chips are read are written in the corresponding data buffer area of ADC chips；

S4：Fpga chip selects M by controlling pin（M is the positive integer less than N）Piece ADC chips enter enabled state, Other ADC chips are set as disabled state simultaneously；It is adopting for 1/M*T1 that fpga chip provides frequency to the ADC chips being enabled Sample reference clock, while the corresponding number of ADC chips from the data after the quantization that each ADC chips are read, will be respectively written into According in buffer area；

S5：After measurement, fpga chip reads data from data buffer area, and host computer is sent to by serial ports, on Position machine draws the signal waveform that sampling generates by trace-point method.

The principles of the present invention and application method are：

Analog signal has some useless high-frequency signals when input and is disturbed into, and the prime of modulate circuit is Low-pass filter circuit.Rear stage is driving enhancing circuit.

The input terminal of ADC is high resistant input, only there are one when ADC, the decaying of signal because ADC influence, can be with It ignores.When multiple ADC are stacked, the load of the signal of input will become smaller, then just will produce to signal It influences, at this time, needs to improve signal, and enhance the driving capability of signal.

ADC is analog-digital converter, exactly converts analog signals into digital signal.It is all in transfer process Sequential is all controlled by external clock.Each clock carries out the conversion of an analog to digital, then when next Clock transfers out the digital signal that conversion finishes by data-interface.Increase a FPGA in systems to be controlled, by FPGA generates clock circuit, and the data acquired are also communicated in FPGA.When there are two ADC, what FPGA was generated The clock of each ADC differs 180 degree, and the frequency entirely sampled will double, and the digital signal of generation also will be alternately sent to In FPGA, and alternately combine.Two such works alternatively, then the time interval entirely acquired will just shorten one Half.If there is N number of ADC, then sample frequency will be just N times of one.

1. in input terminal, since ADC inputs for high resistant, after analog signal is adjusted and drives enhancing, it is input to each ADC chips, for signal almost without loss.

2. being controlled the clock of ADC by FPGA, allow ADC to work successively, thus sample rate is made to double, if core Piece number is that N number of so this sample rate for being is just N times.

3. applying FPGA high-speed parallel processing capacities, adc data acquisition is come in, is then put into buffering area, and pass through Serial ports is sent to host computer.

Application method：The circuit major function of the utility model is exactly the acquisition of analog signal, is then communicated to host computer. The Signal-regulated kinase of the utility model is designed into the collection terminal of analog signal, the analog signal converted is needed to be directly connected to letter The input terminal of number conditioning module, by the data conditioning of prime, the ADC collecting units stacked into rear class, ADC is by analog signal Digitlization, then export and data acquisition comes, is placed in buffer memory, passes through port high speed serialization later to FPGA, FPGA In port transmission to host computer.

Claims (5)

1. a kind of Intelligent high-precision analog signal sampling system, which is characterized in that system includes sampling terminal and host computer； The sampling terminal includes N number of ADC module, fpga chip, Signal-regulated kinase, data cache module, N number of ADC module In N>1；The reference voltage input pin of the ADC module is all connected with the output end of the same voltage reference block；The ADC The sampling input pin of module interconnects, and connection signal conditioning module output end, Signal-regulated kinase input terminal It is connected with sampling probe；The Signal-regulated kinase input terminal connects operational amplifier U1A by resistance R1, the R2 being serially connected In-phase input end, the both ends resistance R2 connect reference ground by capacitance C1 with capacitance C2 respectively；The reverse phase of operational amplifier U1A is defeated Enter end by resistance R3 connection reference grounds, also passes through resistance R4 connection power supplys VCC；The output end connection fortune of operational amplifier U1A Calculate the in-phase input end of amplifier U1B, the output end of the output end of operational amplifier U1B as Signal-regulated kinase, and and U1B Inverting input be connected；The fpga chip connects host computer by serial driver, is connected by different control pins Each ADC chips；Fpga chip is circumscribed with source crystal oscillator and is used as with reference to clock, and module occurs for fpga chip onboard clock, when described Clock occurs module and generates N number of sampling clock；The cycle T all same of each sampling clock, phase differ T/N, fpga chip successively Each sampling clock output pin be respectively connected with the clock input pin of an ADC module；Fpga chip passes through complete Duplexing digital interface accesses data cache module, and marks off in cache module that N number of size is identical and the nonoverlapping number in address According to buffer area；Fpga chip also externally draws N number of data input channel, is separately connected the digital output end of each ADC module, often A data input channel corresponds to a data buffer area.

2. a kind of Intelligent high-precision analog signal sampling system according to claim 1, which is characterized in that the ADC Module is encapsulated as IC chip；The operational amplifier U1A and U1B is integrated in in a piece of IC chip.

3. a kind of Intelligent high-precision analog signal sampling system according to claim 1, which is characterized in that the serial ports Driver is usb driver, and the data cache module is DDR chips.

4. a kind of Intelligent high-precision analog signal sampling system according to claim 1, which is characterized in that described upper Machine is the PC machine with display.

5. a kind of Intelligent high-precision analog signal sampling system according to claim 1, which is characterized in that the sampling It is additionally provided in system for the power module for sampling terminal power supply.