CN117410391A

CN117410391A - LED module, manufacturing method thereof and LED display device

Info

Publication number: CN117410391A
Application number: CN202310865347.1A
Authority: CN
Inventors: 延智慧; 成汉圭; 沈成铉; 李东建; 崔荣进
Original assignee: Samsung Electronics Co Ltd
Current assignee: Samsung Electronics Co Ltd
Priority date: 2022-07-15
Filing date: 2023-07-14
Publication date: 2024-01-16

Abstract

A method of manufacturing an LED module, and a display device are provided. The method comprises the following steps: forming a semiconductor base layer of a first conductivity type on a growth substrate; forming a mask pattern having first to third openings on the semiconductor base layer of the first conductivity type, wherein the first to third openings have different widths and are arranged at the same pitch; simultaneously forming first to third light emitting stacks in the first to third openings, respectively; removing the mask pattern from the semiconductor base layer of the first conductivity type; and removing an edge region of each of the first to third light emitting stacks, wherein the first to third light emitting stacks respectively include first to third active layers configured to emit light of different wavelengths.

Description

LED module, manufacturing method thereof and LED display device

Cross Reference to Related Applications

The present application claims priority from korean patent application No.10-2022-0087472 filed at the korean intellectual property office at the date of 2022, 7, and 15, and korean patent application No.10-2023-0024820 filed at the date of 2023, 2, and the disclosures of each of the above applications are incorporated herein by reference in their entirety.

Technical Field

Example embodiments relate to an LED module, a method of manufacturing the same, and an LED display device.

Background

Semiconductor Light Emitting Diodes (LEDs) have been used as light sources for lighting devices and various electronic products. In addition, LEDs have been widely used as light sources for various display devices such as TVs, mobile phones, PCs, notebook PCs, and PDAs.

The related art display device may be mainly composed of a display panel including a Liquid Crystal Display (LCD) and a backlight, but recently, LEDs may be used as pixels so that the backlight may not be required. A display device using LEDs as pixels can be miniaturized, and a display device having high brightness and excellent light efficiency can also be realized as compared with LCDs.

Disclosure of Invention

An aspect is to provide an LED module having high efficiency that can be manufactured through a simple process and a method of manufacturing the same.

Another aspect is to provide a display device having high efficiency that can be manufactured through a simple process.

According to an aspect of one or more example embodiments, there is provided a method comprising: forming a semiconductor base layer of a first conductivity type on a growth substrate; forming a mask pattern on the semiconductor substrate layer of the first conductivity type, wherein the mask pattern includes first, second and third openings having different widths, and the first, second and third openings are arranged at the same pitch; simultaneously forming a first light emitting stack, a second light emitting stack, and a third light emitting stack in the first opening, the second opening, and the third opening, respectively, by sequentially growing a first active layer, a second active layer, and a third active layer, and a semiconductor layer of the second conductivity type on regions of the semiconductor base layer of the first conductivity type that are opened through the first opening, the second opening, and the third opening, respectively; removing the mask pattern from the semiconductor base layer of the first conductivity type; and removing an edge region of each of the first, second, and third light emitting stacks, wherein the forming of the first, second, and third light emitting stacks is performed by the same growth process, and the first, second, and third active layers have first, second, and third quantum well layers that respectively emit light of different wavelengths.

According to another aspect of one or more example embodiments, there is provided a method comprising: forming a semiconductor base layer of a first conductivity type on a growth substrate; forming a first mask pattern on the semiconductor base layer of the first conductivity type, wherein the first mask pattern includes first and second openings having different widths, the first and second openings being arranged at a first pitch; simultaneously growing a first active layer and a second active layer on a first region and a second region of the semiconductor substrate layer of the first conductivity type, which are opened through the first opening and the second opening, respectively, wherein the first active layer and the second active layer respectively include a first quantum well layer and a second quantum well layer respectively emitting first light and second light of different wavelengths; forming a second mask pattern covering the first opening and the second opening, the second mask pattern having a third opening configured to open a third region of the semiconductor substrate layer of the first conductivity type, wherein the third opening is arranged at a second pitch with adjacent ones of the first opening and the second opening, the second pitch being the same as the first pitch; forming a third active layer in a third region of the semiconductor base layer of the first conductivity type, wherein the third active layer includes a third quantum well layer configured to emit third light having a wavelength different from that of each of the first light and the second light; forming fourth and fifth openings exposing the first and second active layers, respectively, in the second mask pattern; forming a first light emitting stack, a second light emitting stack, and a third light emitting stack by growing a semiconductor layer of a second conductivity type on each of the first active layer, the second active layer, and the third active layer; removing the first and second mask patterns from the first, second and third light emitting stacks and the semiconductor substrate layer of the first conductivity type; and removing an edge region of each of the first, second, and third light emitting stacks.

According to yet another aspect of one or more example embodiments, there is provided a method comprising: forming a semiconductor base layer of a first conductivity type on a growth substrate; forming a mask pattern having first, second and third openings arranged at the same pitch on a semiconductor base layer of a first conductivity type, wherein the first opening has a first width, the second opening has a second width, the third opening has a third width, and the first width is greater than the second width, the first width being the same as the third width; forming a first light emitting stack, a second light emitting stack, and a third light emitting stack in the first opening, the second opening, and the third opening, respectively, by sequentially growing a first active layer, a second active layer, and a third active layer, and a semiconductor layer of the second conductivity type on regions of the semiconductor base layer of the first conductivity type that are opened through the first opening, the second opening, and the third opening, respectively; removing the mask pattern from the semiconductor base layer of the first conductivity type; and removing an edge region of each of the first, second, and third light emitting stacks, wherein the forming of the first, second, and third light emitting stacks is performed by the same growth process, the first and third active layers respectively including first and third quantum well layers emitting light of the same wavelength, and the second active layer including a second quantum well layer configured to emit light of a different wavelength than the same wavelength of the first and third quantum well layers.

According to another aspect of one or more example embodiments, there is provided an LED module including: a semiconductor base layer of a first conductivity type; and a first LED unit, a second LED unit, and a third LED unit arranged on the semiconductor base layer of the first conductivity type at the same pitch and including semiconductor layers corresponding to each other, wherein each of the first LED unit, the second LED unit, and the third LED unit includes a nitride single crystal laminate, wherein the first conductivity type cap layer, the active layer, and the semiconductor layers of the second conductivity type are laminated In order, the nitride single crystal laminate has an upper surface as a (0001) plane and a side surface perpendicular to the semiconductor base layer of the first conductivity type, and wherein the active layer of the first LED unit includes a first quantum well layer configured to emit light having a wavelength of 440nm to 480nm, the active layer of the second LED unit includes a second quantum well layer configured to emit light having a wavelength of 510nm to 550nm, the active layer of the third LED unit includes a third quantum layer configured to emit light having a wavelength of 610nm to 650nm, the first quantum layer, the second quantum layer, and the third quantum layer include quantum wells having different indium (In) content satisfying the respective layers _x Ga _1-x N.

According to another aspect of one or more example embodiments, there is provided a display device including: a circuit board having a driver circuit; and a pixel array disposed on the circuit board and including pixel units each including first, second, and third sub-pixels arranged therein. The pixel array includes: a semiconductor base layer of a first conductivity type having a first surface facing the circuit board and a second surface opposite the first surface; a plurality of first LED units arranged to correspond to the first sub-pixels, a plurality of second LED units arranged to correspond to the second sub-pixels, and a plurality of third LED units arranged to correspond to the third sub-pixels on the first surface of the semiconductor base layer of the first conductivity type, each of the plurality of first LED units, each of the plurality of second LED units, each of the plurality of third LED units including a semiconductor cap layer of the first conductivity type, an active layer, and a semiconductor layer of the second conductivity type stacked in order; a light blocking separation structure disposed on the second surface of the first conductive type semiconductor substrate layer and having light emission windows corresponding to the first, second, and third sub-pixels, respectively; a passivation layer disposed on the first surface of the first conductive type semiconductor base layer and side and upper surfaces of the plurality of first LED units, the plurality of second LED units, and the plurality of third LED units; a first electrode disposed on the passivation layer and electrically connected to the semiconductor base layer of the first conductivity type of each of the plurality of first LED units, the plurality of second LED units, and the plurality of third LED units; and a second electrode disposed on the passivation layer and electrically connected to the semiconductor layers of the second conductivity type of the plurality of first LED units, the plurality of second LED units, and the plurality of third LED units, respectively, wherein the plurality of first LED units, the plurality of second LED units, and the plurality of third LED units have a structure as

(0001) An upper surface of the face and a side surface perpendicular to the first surface of the semiconductor base layer of the first conductivity type.

Drawings

The above and other aspects will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings in which:

fig. 1 is a perspective view illustrating a display device according to some example embodiments;

fig. 2 is a plan view illustrating a display device according to some example embodiments;

fig. 3 is a cross-sectional view illustrating a display device according to some example embodiments;

fig. 4A and 4B are a cross-sectional view and a plan view, respectively, illustrating an LED module employed in a display device according to some example embodiments;

fig. 5 is a diagram illustrating a driver circuit implemented in a display device according to some example embodiments;

fig. 6A to 6E are cross-sectional views illustrating a process of a method of manufacturing an LED module according to some example embodiments;

fig. 7 is a plan view illustrating the LED module shown in fig. 6E;

fig. 8A and 8B are cross-sectional views illustrating a process of a method of manufacturing an LED module according to some example embodiments;

fig. 9 is a plan view illustrating the LED module shown in fig. 8B;

fig. 10 is a plan view illustrating an LED module according to some example embodiments;

fig. 11A to 11F are cross-sectional views illustrating a portion of a process of a method of manufacturing a display device according to some example embodiments;

Fig. 12A to 12D are cross-sectional views illustrating a portion of a process of a method of manufacturing a display device according to some example embodiments;

fig. 13 is a cross-sectional view illustrating a display device according to some example embodiments;

fig. 14A and 14B are cross-sectional views illustrating a display device according to some example embodiments;

fig. 15A to 15F are cross-sectional views illustrating a portion of a process of a method of manufacturing a display device according to some example embodiments;

fig. 16A to 16D are cross-sectional views illustrating a portion of a process of a method of manufacturing a display device according to some example embodiments; and

fig. 17 is a diagram illustrating an electronic apparatus including a display device according to some example embodiments.

Detailed Description

Hereinafter, various exemplary embodiments will be described with reference to the drawings.

Fig. 1 is a perspective view illustrating a display device according to some example embodiments. Fig. 2 is a plan view illustrating a display device according to some example embodiments. Fig. 2 shows a portion 'a' of the display device of fig. 1.

Referring to fig. 1 and 2, the display apparatus 10 may include a circuit board 200 having a driver circuit, and a pixel array 100 disposed on the circuit board 200 and having a plurality of pixels PX arranged thereon. The display device 10 may further include a frame 11 surrounding the circuit board 200 and the pixel array 100.

The circuit board 200 may include a driver circuit having a Thin Film Transistor (TFT) unit. In some example embodiments, the circuit board 200 may further include other circuits in addition to the driver circuit for the display device. In some example embodiments, the circuit board 200 may include a flexible substrate and the display device 10 may be implemented as a display device having a curved profile.

The pixel array 100 may include a display area DA and a peripheral area PA on at least one side of the display area DA. The display area DA may include an LED module for display. The pixel array 100 may include a display area DA in which a plurality of pixels PX are arranged. The peripheral area PA may include a PAD area PAD, a connection area CR connecting a plurality of pixels PX to the PAD area PAD, and an outer area ISO.

Each of the plurality of pixels PX may include a first subpixel SP1, a second subpixel SP2, and a third subpixel SP3 configured to emit light of a specific wavelength (e.g., a specific color) to provide a color image. For example, the first to third sub-pixels SP1, SP2 and SP3 may be configured to emit blue (B), green (G) and red (R) light, respectively. The pixel array 100 may include LED modules configured to directly emit blue (B), green (G) and red (R) light without using an additional wavelength converter (see fig. 4A and 4B).

As shown in fig. 2, in each pixel PX (or pixel unit), the first to third sub-pixels SP1, SP2, and SP3 may have a pattern in which the sub-pixels are arranged side by side in one direction (e.g., X direction). However, the example embodiments are not limited thereto, and in some example embodiments, the first to third sub-pixels SP1, SP2, and SP3 may be arranged in other patterns such as a bayer pattern (see, for example, fig. 10). In some example embodiments, each pixel PX may be configured in a different arrangement such as 3×3 or 4×4.

In the pixel array 100 in fig. 1, a plurality of pixels PX may be arranged in a 15×15 array, but the number of rows and columns may be any suitable number, for example, 11024×768. For example, the plurality of pixels PX may have different arrangements according to a desired resolution.

The PAD region PAD may be disposed on at least one side of the plurality of pixels PX along an edge of the display device 10. The PAD area PAD may be electrically connected to a plurality of pixels PX and a driver circuit of the circuit board 200. The PAD area PAD may electrically connect an external device to the display apparatus 10. In some example embodiments, the number of PAD areas PAD may vary, and may be determined according to, for example, the number of pixels PX, a method of driving TFT circuits in the circuit board 200, and the like.

The connection region CR may be disposed between the plurality of pixels PX and the PAD region PAD. A wiring structure (e.g., a common electrode) electrically connected to the plurality of pixels PX may be disposed in the connection region CR. The outer region ISO may be disposed along an edge of the pixel array 100. In the outer region ISO, the semiconductor layer 111 (see fig. 3) may not be provided.

The frame 11 may be arranged around the pixel array 100 to serve as a guide defining an arrangement space of the pixel array 100. For example, the frame 11 may include at least one material such as a polymer, a ceramic, a semiconductor, and a metal. For example, the frame 11 may include a black matrix. However, the frame 11 is not limited to a black matrix, and in some example embodiments, the frame 11 may include a white matrix or another color structure depending on the use of the display device 10. For example, the white matrix may comprise a reflective material or a scattering material. The display device 10 in fig. 1 may have a rectangular planar structure, but example embodiments are not limited thereto, and in some example embodiments, the display device 10 may have other shapes.

Fig. 3 is a cross-sectional view illustrating a display device according to some example embodiments. Fig. 3 shows a combination of a section (peripheral area PA) taken along I-I 'in fig. 1 and a section (display area DA) taken along I I-I I' in fig. 2.

Referring to fig. 3, the display apparatus 10 may include a circuit board 200 and a pixel array 100 disposed on the circuit board 200.

The circuit board 200 may include: a semiconductor substrate 201; a driver circuit including a driving element 220 having a TFT unit formed on a semiconductor substrate 201, an interconnection 230 electrically connected to the driving element 220, a wiring layer 240 on the interconnection 230, and a second bonding insulating layer 290 covering the driver circuit. In some example embodiments, the circuit board 200 may further include a second wiring insulating layer 295 on the second bonding insulating layer 290 and a second bonding electrode 298 disposed in the second bonding insulating layer 290 and connected to the wiring layer 240.

The pixel array 100 may include a display area in which a plurality of pixels PX are arranged, and each of the plurality of pixels PX may include first to third sub-pixels SP1, SP2, and SP3 arranged in a predetermined pattern (e.g., see fig. 2).

The pixel array 100 may include an LED module implemented as a semiconductor stack 110. The LED module in some example embodiments may include first, second, and third LED units LC1, LC2, and LC3 for the first to third sub-pixels SP1, SP2, and SP3 without a wavelength converter. The first to third LED units LC1, LC2 and LC3 may be micro LEDs, and the LED units may be configured to emit light of different wavelengths. In particular, the LED module may include first to third LED units LC1, LC2 and LC3 configured to directly emit blue (B), green (G) and red (R) light, respectively.

Fig. 4A is an enlarged cross-sectional view illustrating a portion "B" (LED module) of the display apparatus of fig. 3 according to some example embodiments, and fig. 4B is a plan view of the example in fig. 4A viewed in the "T" direction, which illustrates a plan view of the LED module presenting pixels corresponding thereto.

The semiconductor stack 110 in some example embodiments may include a first conductive type semiconductor base layer 111B having a first surface facing the circuit board 200 and a second surface opposite to the first surface, and first to third LED units LC1, LC2, and LC3 disposed on the first surface of the first conductive type semiconductor base layer 111B.

The first to third LED units LC1, LC2, and LC3 included in each pixel PX may be arranged at the same pitch (p1=p2). Here, the pitch may be defined as a distance between centers of adjacent LED units. In some example embodiments, the pitch P3 of the LED units with another neighboring pixel PX may be the same as the pitches P1 and P2 (i.e., p1=p2=p3). In some example embodiments, the first to third LED units LC1, LC2, and LC3 may have the same width (w1=w2=w3) (or the same area (when seen in a plan view)) and the same distance (d1=d2). In some example embodiments, the distance d3 from the LED unit of another neighboring pixel PX may be the same as the distances d1 and d2 (i.e., d1=d2=d3). However, some example embodiments are not limited thereto, and in some example embodiments, the widths and/or distances of the first to third LED units LC1, LC2, and LC3 may be different. For example, considering efficiency according to the wavelength of light, the width (or area) of the LED unit having relatively low efficiency may be configured to be large, and the distance from the LED unit adjacent thereto may be configured to be relatively narrow (fig. 8B and 9).

In some example embodiments, the separation structure 111P may be disposed on the second surface of the semiconductor base layer 111B of the first conductivity type. For example, the partition structure 111P may be obtained by etching the semiconductor layer 111 (also referred to as "bottom semiconductor layer") integral with the semiconductor base layer 111B of the first conductivity type (see fig. 16B). The semiconductor layer 111 may be a semiconductor layer of the first conductivity type or an undoped semiconductor layer, or may include a stack of a semiconductor layer of the first conductivity type and an undoped semiconductor layer. However, example embodiments are not limited thereto, and in some example embodiments, the separation structure may include a structure formed of another material (e.g., a light blocking material or a reflective material) (see fig. 13).

The first to third LED units LC1, LC2 and LC3 in some example embodiments may include nitride single crystal stacks grown in the same growth process. Since the nitride single crystal stacks are formed by the same growth process, these layers may correspond to each other. As shown in fig. 4A, the nitride single crystal stack may include: a semiconductor cap layer 112 of the first conductive type for each of the first to third LED units LC1, LC2 and LC 3; a first active layer 114a, a second active layer 114b, and a third active layer 114c for the first to third LED units LC1, LC2, and LC3, respectively; and a second conductive type semiconductor layer 116 for sequentially stacking each of the first to third LED units LC1, LC2 and LC3 on the first surface of the first conductive type semiconductor base layer 111B.

The semiconductor base layer 111B of the first conductivity type and the semiconductor cap layer 112 of the first conductivity type may be composed of n-type In _x Al _y Ga _1-x-y N (x is more than or equal to 0 and less than 1, y is more than or equal to 0 and less than 1, and x+y is more than or equal to 0 and less than 1). For example, the first conductive type semiconductor cap layer 112 may be an n-type gallium nitride (n-GaN) layer doped with silicon (Si), germanium (Ge), or carbon (C). The semiconductor layer 116 of the second conductivity type may be a p-type In composition _x Al _y Ga _1-x-y N (x is more than or equal to 0 and less than 1, y is more than or equal to 0 and less than 1, and x+y is more than or equal to 0 and less than 1). For example, the second conductive type semiconductor layer 116 may be a p-type gallium nitride (p-GaN) layer doped with magnesium (Mg) or zinc (Zn). Each of the first conductive type semiconductor cap layer 112 and the second conductive type semiconductor layer 116 may be formed as a single layer, or may include a plurality of layers having different characteristics, such as different doping concentrations and compositions.

The first to third active layers 114a, 114b and 114c may emit light having a predetermined energy by recombination of electrons and holes. The first to third LED units LC1, LC2, and LC3 in some example embodiments may include first to third active layers 114a, 114b, and 114c configured to emit light of different wavelengths, respectively. The active layer 114 may have a Single Quantum Well (SQW) structure, or a Multiple Quantum Well (MQW) structure in which quantum barrier layers and quantum well layers are alternately arranged.

In some example embodiments, since the first to third active layers 114a, 114b and 114c are simultaneously formed through the same growth process, the active layers may further include layers corresponding to each other. For example, the first to third active layers 114a, 114b and 114c may include the same number of quantum barrier layers and quantum well layers.

The first active layer 114a may include a first quantum well layer configured to emit blue light (e.g., light having a wavelength of 440nm to 480 nm). The second active layer 114b may include a second quantum well layer configured to emit green light (e.g., light having a wavelength of 510nm to 550 nm). The third active layer 114c may include a third quantum well layer configured to emit red light (e.g., light having a wavelength of 610nm to 650 nm).

The first to third quantum well layers may include In having different indium content (x) _x Ga _1-x N (x is more than 0 and less than or equal to 1). For example, the indium content of the first quantum well layer may be in the range of 0.15-0.2, the indium content of the second quantum well layer may be in the range of 0.25-0.3, and the indium content of the third quantum well layer may be in the range of 0.3-0.35. For example, the quantum barrier layer may be GaN or AlGaN.

As described above, the first to third quantum well layers may be simultaneously formed in the same growth process, and a difference in indium content may be caused by adjusting the areas of the growth regions for the first to third LED units LC1, LC2, and LC3, and thus, the first to third LED units LC1, LC2, and LC3 may be configured to emit light of different wavelengths (see fig. 6A to 6C).

In some example embodiments, the thickness t 1 of the first active layer 114a may be greater than the thickness t2 of the second active layer 114b, and the thickness t2 of the second active layer 114b may be greater than the thickness t3 of the third active layer 114b (see fig. 6C). Specifically, the thickness of the first quantum well layer may be greater than the thickness of the second quantum well layer, and the thickness of the second quantum well layer may be greater than the thickness of the third quantum well layer. For example, the thickness of the first quantum well layer may be in the range of 2.5nm to 4nm, the thickness of the second quantum well layer may be in the range of 2.5nm to 3.5nm, and the thickness of the third quantum well layer may be in the range of 2nm to 3 nm.

The first to third LED units LC1, LC2, and LC3 in some example embodiments may include single crystal stacks 112, 114, and 116 having an upper surface ((0001) plane) and a side surface substantially perpendicular to the first surface of the first conductivity-type semiconductor base layer 111B. For example, the upper surface of the second conductive type semiconductor layer 116 may be a (0001) plane. The side surfaces of nitride single crystal stacks 112, 114, and 116 may have substantially vertical side surfaces obtained by removing edge regions that cause leakage current through an etching process (see fig. 6E). For example, the angle of the side surfaces of the nitride single crystal stacks 112, 114, and 116 with respect to the semiconductor base layer 111B of the first conductivity type may be in the range of 85 ° to 95 °.

In some example embodiments, since the separation structure 111P dividing the sub-pixels SP1, SP2, and SP3 may include the semiconductor layer 111 having light transmittance to prevent optical interference between the sub-pixels SP1, SP2, and SP3, the separation reflective layer 170 may be disposed on a surface thereof.

The partition reflection layer 170 in some example embodiments may be formed on the upper surface and the sidewalls of the partition structure 111P. As shown in fig. 3, the partition reflective layer 170 in some example embodiments may include a first partition insulating film 172, a reflective metal film 174, and a second partition insulating film 176 stacked in order. The first and second separation insulating films 172 and 176 may include at least one insulating material, for example, siO ₂ SiN, siCN, siOC, siON and SiOCN. The reflective metal film 174 may include at least one reflective metal, for example, silver (Ag), nickel (Ni), and aluminum (Al). The reflective metal film 174 may be formed on the inner sidewalls of the plurality of sub-pixel spaces and may not be formed on the bottom surfaces thereof. With this arrangement, light emitted from each of the LED units LC1, LC2, and LC3 can be emitted from the bottom surfaces of the plurality of sub-pixel spaces. The transparent resin portion 160 may be formed in each sub-pixel space surrounded by the partition reflection layer 170. In some example embodiments, the transparent resin portion 160 may not include a wavelength conversion material such as a phosphor and/or quantum dots, and light (e.g., R, G, B) of a wavelength required for each of the sub-pixels SP1, SP2, and SP3 may be directly emitted from the first to third LED units LC1, LC2, and LC 3. In some example embodiments, the transparent resin portion 160 may further include a light scattering material.

As shown in fig. 3, the first conductive type semiconductor base layer 111B may be set as a common layer shared by the first to third LED units LC1, LC2 and LC3 of the entire pixel PX. The thickness T1 of the semiconductor base layer 111B of the first conductivity type may be, for example, about 0.1 μm or more. In some example embodiments, the thickness T1 of the first conductive type semiconductor base layer 111B may be in a range of about 0.1 μm to about 1.0 μm. The semiconductor base layer 111B of the first conductivity type may be provided to extend from the display area DA to the connection area CR and the PAD area PAD (that is, a portion of the peripheral area PA). The semiconductor base layer 111B of the first conductivity type may be provided as a region for forming a common electrode for all or a portion (e.g., the same row or the same column) of the first to third LED units LC1, LC2, and LC 3.

Referring to fig. 3 and 4A, the passivation layer 120 may cover side and upper surfaces of the first to third LED units LC1, LC2 and LC3 and the first surface of the first conductive type semiconductor base layer 111B. The passivation layer 120 may extend to the peripheral region PA on the first surface of the first conductive-type semiconductor base layer 111B. The passivation layer 120 may be disposed to cover the lower surface of the first conductive type semiconductor layer 112 in the connection region CR and the PAD region PAD (i.e., the peripheral region PA). Passivation layer 120 may include at least one insulating material, e.g., siO ₂ At least one of SiN, siCN, siOC, siON and SiOCN.

The first electrode 130 may be connected to the semiconductor base layer 111B of the first conductive type. In particular, the first electrode 130 may be disposed to be electrically insulated from the first to third LED units LC1, LC2, and LC3 by the passivation layer 120. The first electrode 130 may extend to the peripheral area PA. The first electrode 130 extending to the peripheral region PA may be connected in a region between adjacent first to third LED units LC1, LC2, and LC3, and may be disposed in a single layer. The first electrode 130 may include a reflective metal material. For example, the first electrode 130 may include at least one of silver (Ag), nickel (Ni), aluminum (Al), chromium (Cr), rhodium (Rh), iridium (Ir), palladium (Pd), ruthenium (Ru), magnesium (Mg), zinc (Zn), platinum (Pt), gold (Au), copper (Cu), titanium (Ti), tantalum (Ta), and tungsten (W). In some example embodiments, the first electrode 130 may include a compound such as TaN or TiN, or a transparent electrode material such as ITO, IZO, or GAZO. In some example embodiments, the first electrode 130 may include a single-layer structure or a multi-layer structure formed of a conductive material.

The first electrode 130 may be provided as a reflective electrode (also referred to as a "first reflective electrode"). For example, as shown in fig. 3, the first electrode 130 may have an inverted U-shaped cross section between adjacent LED units LC1, LC2, and LC 3. The first electrode 130 may have a mesh or screen shape including lines extending in the X-direction and the Y-direction along a region between the pixel PX and the first to third sub-pixels SP1, SP2, and SP 3. An end portion of the first electrode 130 may be connected to the common electrode 145. As shown in fig. 3, the outermost portion of the first electrode 130 may be connected to the common electrode 145.

In some example embodiments, the first electrode 130 may extend to the peripheral region PA (i.e., the connection region CR disposed on the outer region of the pixel PX), may be connected to the semiconductor substrate layer 111B of the first conductive type, and may be physically and electrically connected to the common electrode 145. As in some example embodiments, the first electrode 130 may be electrically connected to the first conductive type semiconductor base layer 111B in a region between adjacent LED cells LC1, LC2, and LC 3.

The contact layer 155 and the second electrode 150 may be sequentially disposed on the lower surface of the second conductive type semiconductor layer 116 and may be connected to the second conductive type semiconductor layer 116. In some example embodiments, the contact layer 155 may be disposed to cover almost the entire lower surface of the second conductive type semiconductor layer 116. Similar to the first electrode 130, the second electrode 150 may include a reflective metal material. For example, the second electrode 150 may include at least one of silver (Ag), nickel (Ni), aluminum (Al), chromium (Cr), rhodium (Rh), iridium (Ir), palladium (Pd), ruthenium (Ru), magnesium (Mg), zinc (Zn), platinum (Pt), gold (Au), copper (Cu), titanium (Ti), tantalum (Ta), and tungsten (W). In some example embodiments, the second electrode 150 may include a compound such as TaN or TiN, or a transparent electrode material such as ITO, IZO, or GAZO. In some example embodiments, the second electrode 150 may include a single-layer structure or a multi-layer structure formed of a conductive material.

A second electrode 150 (also referred to as a "second reflective electrode") as a reflective electrode may be disposed under each of the LED units LC1, LC2, and LC3 to overlap with the LED units LC1, LC2, and LC3 in the Z direction. The second electrode 150 may be disposed under the contact layer 155 and may be connected to the contact layer 155. The length of the second electrode 150 in the X direction may be the same as or similar to the lengths of the LED units LC1, LC2, and LC3, but some example embodiments thereof are not limited thereto, but may vary in some example embodiments. In some example embodiments, the second electrode 150 may not be provided, and in this case, the contact layer 155 may be directly connected to the first bonding electrode 198 thereunder.

The contact layer 155 and the second electrode 150 may include, for example, a highly reflective metal such as at least one of silver (Ag), nickel (Ni), aluminum (Al), chromium (Cr), rhodium (Rh), iridium (Ir), palladium (Pd), ruthenium (Ru), magnesium (Mg), zinc (Zn), platinum (Pt), and gold (Au).

The pixel array 100 in some example embodiments may further include a planarization layer 182, a first pad electrode 147, a first wiring insulating layer 195, a first bonding insulating layer 190, a first bonding electrode 198, and a second pad electrode 199 on the partition structure 111P, and a semiconductor layer 111 filled with the transparent resin portion 160.

As described above, the semiconductor layer 111 may include a region integral with or continuous with the semiconductor base layer 111B of the first conductivity type. As shown in fig. 3, the semiconductor layer 111 in the peripheral region PA may have a layer structure other than the partition structure 111P, and the common electrode 145 may extend to the semiconductor layer 111 region of the peripheral region PA. A through structure OP in which a portion of the semiconductor layer 111 is removed may be formed in the peripheral region PA (specifically, the PAD region PAD).

The planarization layer 182 may be a transparent layer formed on the partition structure 111P and the semiconductor layer 111 filled with the transparent resin portion 160. The micro lens 185 may be disposed to correspond to the first to third sub-pixels SP1, SP2 and SP3 on the planarization layer 182, and may collect light emitted from the first to third LED units LC1, LC2 and LC 3. For example, the micro lenses 185 may have a larger diameter than the widths of the LED units LC1, LC2, and LC3 in the X-direction and the Y-direction. The microlenses 185 may be formed of, for example, a transparent photoresist material, or may be formed of a transparent thermosetting resin film.

The common electrode 145 and the first PAD electrode 147 may be disposed in the connection region CR and the PAD region PAD, respectively. The common electrode 145 may be disposed on a lower surface of the first reflective electrode 130 extending from the pixel PX, and may connect the first reflective electrode 130 to the first bonding electrode 198. The common electrode 145 may form a common electrode structure together with the first reflective electrode 130. The common electrode 145 may be disposed in a square ring shape or a ring shape in a plan view to surround the entire pixel PX, and may be connected to an end portion of the first reflective electrode 130. However, the arrangement form of the common electrode 145 is not limited thereto, and may vary in some example embodiments. The first PAD electrode 147 may be disposed under the second PAD electrode 199 in the PAD region PAD and may connect the second PAD electrode 199 to the first bonding electrode 198. For example, the common electrode 145 and the first pad electrode 147 may include a conductive material such as at least one of silver (Ag), nickel (Ni), aluminum (Al), chromium (Cr), rhodium (Rh), iridium (Ir), palladium (Pd), ruthenium (Ru), magnesium (Mg), zinc (Zn), platinum (Pt), and gold (Au).

The first bonding electrode 198 may connect the second reflective electrode 150, the common electrode 145, and the first pad electrode 147 to the second bonding electrode 298 of the circuit board 200. The first bonding electrode 198 may be connected to the second electrode 150 under the second electrode 150 in the pixel PX, may be connected to the common electrode 145 in the connection region CR, and may be connected to the first PAD electrode 147 in the PAD region PAD. In some example embodiments, among the first bonding electrodes 198, the bonding electrodes disposed on the common electrode 145 and the first pad electrode 147 may be referred to as "third bonding electrode" and "fourth bonding electrode", respectively. The first electrode 130 may be connected to the first bonding electrode 198 through the common electrode 145, and the second electrode 150 may be directly connected to the first bonding electrode 198.

The first bonding electrode 198 may be disposed through the first wiring insulating layer 195 and the first bonding insulating layer 190. The first bonding electrode 198 may have a cylindrical shape such as a cylinder. In some example embodiments, the first bonding electrode 198 may have an inclined sidewall such that the size of the upper surface may be smaller than the size of the lower surface thereof. The first bonding electrode 198 may include, for example, copper (Cu). The first bonding electrode 198 may also include barrier metal layers, such as a tantalum (Ta) layer and/or a tantalum nitride (TaN) layer, on its upper and side surfaces.

The first wiring insulating layer 195 may be disposed under the LED units LC1, LC2, and LC3 and the semiconductor layer 111 together with the second bonding insulating layer 290. For example, the first wiring insulating layer 195 may include SiO ₂ At least one of SiN, siCN and SiON. In some cases showIn an example embodiment, the first wiring insulating layer 195 may be tetraethyl orthosilicate (TEOS), undoped Silicate Glass (USG), phosphosilicate glass (PSG), borosilicate glass (BSG), borophosphosilicate glass (BPSG), fluorosilicate glass (FSG), spin-on glass (SOG), tonen silazane (TOSZ), or a combination thereof.

The semiconductor substrate 201 may include impurity regions having source/drain regions 205. For example, the semiconductor substrate 201 may include a semiconductor such as silicon (Si) or germanium (Ge) or a compound semiconductor such as SiGe, siC, gaAs, inAs or InP. The semiconductor substrate 201 may further include a through electrode 250, such as a Through Silicon Via (TSV), connected to the driver circuit, a first substrate wire 261 and a second substrate wire 262 connected with the through electrode 250.

The driver circuit may comprise circuitry for controlling the driving of the pixels, in particular the sub-pixels. The source region 205 of the TFT unit may be electrically connected to electrodes on one side of the LED units LC1, LC2, and LC3 through the interconnection 230, the wiring layer 240, and the second bonding electrode 298. For example, the drain region 205 of the TFT unit may be connected to the first substrate wiring 261 through the through electrode 250, and the first substrate wiring 261 may be connected to a data line. The gate electrode of the TFT unit may be connected to the second substrate wiring 262 through the through electrode 250, and the second substrate wiring 262 may be connected to the gate line. The circuit configuration and operation will be described in more detail below with reference to fig. 5.

The upper surface of the second bonding electrode 298 and the upper surface of the second bonding insulating layer 290 may form an upper surface of the circuit board 200. The second bonding electrode 298 may be bonded to the first bonding electrode 198 of the pixel array 100 and may provide an electrical connection path. The second bonding electrode 298 may include a conductive material, for example, copper (Cu). The second bonding insulating layer 290 may be bonded to the first bonding insulating layer 190 of the pixel array 100. For example, the second bonding insulating layer 290 may include at least one of SiO, siN, siCN, siOC, siON and SiOCN.

The lower surface of the first bonding insulating layer 190 may be arranged to form a lower surface of the pixel array 100 together with the lower surface of the first bonding electrode 198. The second bonding insulating layer 290 may form a dielectric-dielectric bond with the first bonding insulating layer 190. The circuit board 200 and the pixel array 100 may be bonded by bonding between the first bonding electrode 198 and the second bonding electrode 298 and bonding between the first bonding insulating layer 190 and the second bonding insulating layer 290. The bond between the first and second bonding electrodes 198 and 298 may be, for example, a copper (Cu) -copper (Cu) bond, and the bond between the first and second bonding insulating layers 190 and 290 may be, for example, a dielectric-dielectric bond (such as a SiCN-SiCN bond). The circuit board 200 and the pixel array 100 may be bonded to each other by a hybrid bond including a copper (Cu) -copper (Cu) bond and a dielectric-dielectric bond, and may be bonded without an adhesive layer.

In the display apparatus 10 according to some example embodiments, an arrangement of the electrode structures including the first electrode 130 may be optimized, and the circuit board 200 and the pixel array 100 may be bonded to each other using hybrid bonding, thereby realizing a miniaturized high-resolution device.

The second PAD electrode 199 may be disposed on the first PAD electrode 147 in the PAD region PAD. The second pad electrode 199 may be disposed such that at least an upper surface may be exposed upward through the through structure OP passing through the semiconductor layer 111 and the first conductive type semiconductor layer 112. The second pad electrode 199 may be connected to an external device (e.g., an external circuit (external IC)) for applying an electrical signal to the circuit board 200 by wire bonding or anisotropic conductive film (AFC) bonding. The second pad electrode 199 may electrically connect the driver circuit of the circuit board 200 to an external device. The second pad electrode 199 may include a metal such as gold (Au), silver (Ag), or nickel (Ni).

Fig. 5 is a diagram illustrating a driver circuit implemented in a display device according to some example embodiments.

Fig. 5 shows a circuit diagram of the display device 10 in which n×n sub-pixels are arranged. The first to third sub-pixels SP1, SP2 and SP3 may receive data signals through the data lines D1 to Dn as vertical paths in, for example, a column direction. The first to third sub-pixels SP1, SP2 and SP3 may receive a control signal, that is, a gate signal, through the gate lines G1-Gn, which may be horizontal paths (e.g., row direction paths).

The plurality of pixels PX including the first to third sub-pixels SP1, SP2 and SP3 may provide a display area DA, which may be set as an active area for a user. The inactive area NA (or the peripheral area PA) may be formed along one or more edges of the display area DA. The inactive area NA may extend along the outer periphery of the panel of the display device 10.

The first and second driver circuits 12 and 13 may be employed to control the operation of the pixels PX (that is, the first to third sub-pixels SP1, SP2, and SP 3). Part or all of the first driver circuit 12 and the second driver circuit 13 may be implemented on the circuit board 200. The first and second driver circuits 12 and 13 may be formed as integrated circuits, thin film transistor panel circuits, or other suitable circuits, and may be disposed in the inactive area NA of the display device 10. The first driver circuit 12 and the second driver circuit 13 may include a microprocessor, a memory such as a storage section, a processing circuit, and a communication circuit.

In order to display an image through the pixels PX, the first driver circuit 12 may supply image data to the data lines D1 to Dn, and may transmit a clock signal and other control signals to the second driver circuit 13 as a gate driver circuit. The second driver circuit 13 may be implemented using an integrated circuit and/or a thin film transistor circuit. Gate signals for controlling the first to third sub-pixels SP1, SP2 and SP3 arranged in the row direction may be transmitted through the gate lines G1-Gn of the display device 10.

Fig. 6A to 6E are cross-sectional views illustrating a process of a method of manufacturing an LED module according to some example embodiments. Fig. 7 is a plan view illustrating the LED module shown in fig. 6E.

Methods of manufacturing an LED module according to some example embodiments may be understood as a process of manufacturing an LED module corresponding to a pixel in a pixel array of a display (see fig. 4A and 4B).

Referring to fig. 6A, a bottom semiconductor layer 111 may be formed on the growth substrate 101, and a mask pattern 105 may be formed on the bottom semiconductor layer 111.

The upper region of the bottom semiconductor layer 111 in some example embodiments may include a semiconductor base layer 111B of the first conductivity type. In some example embodiments, the lower region of the bottom semiconductor layer 111 may be a semiconductor layer of the first conductivity type or an undoped semiconductor layer, or may include a stack of the semiconductor layer of the first conductivity type and the undoped semiconductor layer.

The mask pattern 105 may have a first opening O1, a second opening O2, and a third opening O3 for an opening region of the semiconductor base layer 111B of the first conductivity type. These regions of the first conductive type semiconductor base layer 111B may be provided as regions for forming the first to third LED units, respectively. The first opening O1, the second opening O2, and the third opening O3 may be arranged at the same pitch (p1=p2). Here, each of the pitches P1 and P2 may be defined as a distance between centers of the openings adjacent to each other.

In some example embodiments, the first to third openings O1, O2, and O3 may have different widths W1', W2', and W3'. Specifically, the width W '1 of the first opening O1 may be greater than the width W2' of the second opening O2, and the width W2 'of the second opening O2 may be greater than the width W3' of the third opening O3. The pattern distances d1, d2, and d3 of the openings O1, O2, and O3 may be different, respectively, according to the same pitch and different widths (i.e., d1+.d2+.d3).

Since the areas of the growth regions provided through the first to third openings O1, O2, and O3 are different as described above, even when active layers (i.e., quantum well layers) are simultaneously grown in the first to third openings O1, O2, and O3, active layers emitting light of different wavelengths can be formed.

Then, referring to fig. 6B, a first conductive type semiconductor cap layer 112 may be formed on the region of the first conductive type semiconductor base layer 111B opened through the first to third openings O1, O2, and O3.

The first conductive type semiconductor cap layer 112 may have n-type In similar to the composition of the first conductive type semiconductor base layer 111B _x Al _y Ga _1-x-y N (x is more than or equal to 0 and less than 1, y is more than or equal to 0 and less than 1, and x+y is more than or equal to 0 and less than 1). For example, the semiconductor base layer 111B of the first conductivity type and the semiconductor cap layer 112 of the first conductivity type may be doped with silicon (S i) An n-type gallium nitride (n-GaN) layer of germanium (Ge) or carbon (C). In some example embodiments, the process may not be performed, but may be added to grow an active layer to be grown on a high quality crystal plane in a subsequent process. In some example embodiments, the first conductive type semiconductor cap layer 112 may be grown to have a c-plane (i.e., (0001) plane), a nitride single crystal having an upper surface, and an edge region adjacent to the mask pattern 105 may have an inclined side surface.

Then, referring to fig. 6C, active layers 114a, 114b, and 114C may be formed on the first conductive type semiconductor cap layer 112, respectively, and second conductive type semiconductor layers 116 may be grown on the active layers 114a, 114b, and 114C, respectively.

The growth processes in the openings O1, O2 and O3 may be performed simultaneously using a single growth process. By this process, the first to third light emitting stacks LC1', LC2', and LC3' may be formed in the first to third openings O1, O2, and O3, respectively. For example, the first light emitting stack LC1' may include a first conductive type semiconductor cap layer 112, a first active layer 114a, and a second conductive type semiconductor layer 116, the second light emitting stack LC2' may include the first conductive type semiconductor cap layer 112, the second active layer 114b, and the second conductive type semiconductor layer 116, and the third light emitting stack LC3' may include the first conductive type semiconductor cap layer 112, the third active layer 114c, and the second conductive type semiconductor layer 116.

As described above, even when the components are grown by the same process, the first to third light emitting stacks LC1', LC2', and LC3' may have the first to third active layers 114a, 114b, and 114c configured to emit light of different wavelengths due to the difference in the area sizes of the openings O1, O2, and O3. The first active layer 114a may include a first quantum well layer configured to emit blue light (e.g., light having a wavelength of 440nm to 480 nm). The second active layer 114b may include a second quantum well layer configured to emit green light (e.g., light having a wavelength of 510nm to 550 nm). In addition, the third active layer 114c may include a third quantum well layer configured to emit red light (e.g., light having a wavelength of 610nm to 650 nm).

Specifically, the first to third active layers 114a, 114b and 114c may have a structure expressed as In _x Ga _1-x N (0 < x.ltoreq.1) from the first quantum well layer to the third quantum well layer. The first to third quantum well layers may have different indium contents (x). For example, the first quantum well layer may have an indium content in the range of 0.15-0.2, the second quantum well layer may have an indium content in the range of 0.25-0.3, and the third quantum well layer may have an indium content in the range of 0.3-0.35.

In some example embodiments, the thickness of the first quantum well layer may be greater than the thickness of the second quantum well layer, and the thickness of the second quantum well layer may be greater than the thickness of the third quantum well layer. Specifically, the thickness t 1 of the first active layer 114a may be greater than the thickness t2 of the second active layer 114b, and the thickness t2 of the second active layer 114b may be greater than the thickness t3 of the third active layer 114 c.

As described above, the first to third quantum well layers may be simultaneously formed in the same growth process, but by controlling the area size of the growth regions for the first to third LED units LC1, LC2 and LC3, a difference in indium content may be caused, and thus, the first to third light emitting stacks LC1', LC2' and LC3' may be configured to emit light of different wavelengths.

The first to third active layers 114a, 114b and 114c may have a Single Quantum Well (SQW) structure or a Multiple Quantum Well (MQW) structure in which quantum barrier layers and quantum well layers are alternately arranged. For example, the quantum barrier layer may be GaN or AlGaN. Since the first to third active layers 114a, 114b and 114c are simultaneously formed through the same growth process, the active layers may include layers corresponding to each other. The first to third active layers 114a, 114b and 114c may include the same number of quantum barrier layers and quantum well layers.

Then, the second conductive type semiconductor layer 116 may be simultaneously formed on the first to third active layers 114a, 114b and 114c, respectively. The semiconductor layer 116 of the second conductivity type may be a p-type In composition _x Al _y Ga _1-x-y N (x is more than or equal to 0 and less than 1, y is more than or equal to 0 and less than 1, and x+y is more than or equal to 0 and less than 1). For example, the firstThe semiconductor layer 116 of the two conductivity types may be a p-type gallium nitride (p-GaN) layer doped with magnesium (Mg) or zinc (Zn).

Then, referring to fig. 6D, the mask pattern 105 may be removed from the semiconductor base layer 111B of the first conductive type.

After removing the mask pattern 105, the first to third light emitting stacks LC1', LC2', and LC3' may remain on the first conductive type semiconductor base layer 111B. As described above, the first to third light emitting stacks LC1', LC2', and LC3' may include a nitride single crystal having an upper surface as a (0001) plane, and may include edge regions DL1, DL2, and DL3 having inclined side surfaces. The edge regions DL1, DL2, and DL3 may be crystal damaged regions that generate non-radiative recombination or leakage current. Thus, a process of removing the edge region may be performed. In some example embodiments, the shape and size (or width) of the first to third light emitting stacks LC1', LC2', and LC3' remaining in the edge area removal process may be controlled.

The widths of the edge regions DL1, DL2, and DL3 to be removed may be differently determined such that the remaining first to third light emitting stacks LC1, LC2, and LC3 may have the same width (i.e., w1=w2=w3). The edge region removal process may be performed by dry etching, wet etching, or a combination of dry etching/wet etching. As shown in fig. 7, the edge regions DL1, DL2, and DL3 to be removed may be disposed to surround the first to third light emitting stacks LC1, LC2, and LC3, respectively, on a plane.

Then, referring to fig. 6E, after the edge regions DL1, DL2, and DL3 are removed, first to third light emitting stacks LC1, LC2, and LC3 having the same width (i.e., w1=w2=w3) may be obtained.

In some example embodiments, the remaining first to third light emitting stacks may also be referred to as first to third LED units LC1, LC2, and LC3, respectively. The first to third LED units LC1, LC2 and LC3 may be provided as light sources for the first to third sub-pixels, respectively. The first to third LED units LC1, LC2 and LC3 may maintain the same pitch therebetween (p1=p2). In some example embodiments, the first to third LED units LC1, LC2, and LC3 may be separated from each other by different distances (d 1 > d 2).

As described above, the first to third LED units LC1, LC2, and LC3 may have an upper surface as a (0001) plane, and a side surface almost perpendicular to the upper surface of the first conductive type semiconductor base layer 111B. For example, the side surface angles of the first to third LED units LC1, LC2 and LC3 with respect to the growth substrate 101 may be in the range of 85 ° -95 °.

The LED module (100A) shown in fig. 6E may then be additionally processed to manufacture it as a pixel array substrate for a display (see "100" in fig. 1). The pixel array substrate manufacturing process may be performed by the processes in fig. 15A to 15E.

For example, the passivation layer 120 may be formed on the upper surface of the first conductive type semiconductor base layer 111B and the side surfaces and upper surfaces of the first to third LED units LC1, LC2, and LC 3. Then, the second electrode 150 as an individual electrode may be formed on the upper surfaces of the first to third LED units LC1, LC2 and LC3 to be connected to the second conductive type semiconductor layer 116, and the first electrode 130 (i.e., the common electrode) connected to the first conductive type semiconductor base layer 111B may be formed.

In the process of removing the edge region of the light emitting laminate, the shape and size of the LED unit may be controlled in various ways. In some example embodiments, the sizes (or widths) of the first to third LED units may be determined to be different. Some example embodiments will be described with reference to fig. 8A, 8B, and 9.

Fig. 8A and 8B are cross-sectional views illustrating a process of a method of manufacturing an LED module according to some example embodiments. Fig. 9 is a plan view illustrating the LED module shown in fig. 8B.

Fig. 8A shows first to third light emitting stacks LC1', LC2', and LC3' disposed on the bottom semiconductor layer 111. The first to third light emitting stacks LC1', LC2', and LC3' may be understood as the results obtained after performing the processes in fig. 6A and 6B in the foregoing example embodiments.

As described above, the first to third light emitting stacks LC1', LC2', and LC3' may include a nitride single crystal having an upper surface ((0001) plane) and an edge region DL having inclined side surfaces. In some example embodiments, after the edge region DL is removed, the first to third light emitting stacks (i.e., the first to third LED units LC1, LC2, and LC 3) may have different widths (Wa > Wb > Wc). For example, considering efficiency according to the wavelength of light, the width (or area) of the LED unit having relatively low efficiency may be configured to be large.

In some example embodiments, the width Wa of the first LED unit LC1 for blue light may be greater than the width Wb of the second LED unit LC2 for green light, and the width Wb of the second LED unit LC2 may be greater than the width Wc of the third LED unit LC3 for red light. The distances (da=db) of the LED units adjacent to each other may be the same or different, but the first to third LED units LC1, LC2, and LC3 may be arranged at the same pitch (p1=p2) therebetween.

In some example embodiments, as shown in fig. 9, the edge region DL surrounding each of the first to third LED units LC1, LC2, and LC3 may be removed with a sufficient width Wd for the damaged region to be removed on a plane. In some example embodiments, the width Wd of the edge region DL removed from the first to third LED units LC1, LC2, and LC3 may be substantially the same.

As such, the LED module 100B manufactured in some example embodiments may include first to third LED units LC1, LC2, and LC3 having different widths (wa+.wb+.wc) and different distances (da+.db) but arranged at the same pitch (p1=p2).

The LED modules 100A and 100B corresponding to the pixels may include first to third LED units arranged in one direction, but may vary according to the arrangement of the sub-pixels. For example, the LED module 100C shown in fig. 10 may include four LED units LC1, LC2a, LC2B, and LC3 arranged at the same pitch (pa=pb=pc) similarly to the bayer pattern (R-G-B), and the four LED units may include blue LED units LC1 and red LED units LC3 arranged on a first diagonal line, and first green LED units LC2a and second green LED units LC2B arranged on a second diagonal line. In fig. 10, the dotted line may represent an outer line of the light emitting stack before the opening or edge regions DL1, DL2, and DL3 of the mask pattern are removed. Four LED units LC1, LC2a, LC2b, and LC3 may be formed in openings having different widths. In some example embodiments, the four LED units LC1, LC2a, LC2b, and LC3 may have the same size (w1=w2=w3) after the edge regions are removed. However, some example embodiments thereof are not limited thereto, and as described in fig. 9, by adjusting the widths of the edge regions DL1, DL2, and DL3 to be removed, the LED units may have different sizes according to the wavelength of each of the LED units LC1, LC2a, LC2b, and LC3.

In the above-described exemplary embodiments, examples in which the first to third LED units (e.g., blue, green, and red LED units) emitting light of different wavelengths may be simultaneously formed are described, but the exemplary embodiments are not limited thereto and may vary in some exemplary embodiments.

According to some example embodiments, in the pixel unit, only the first and second LED units emitting light of different colors may be formed at the same time, and the third LED unit emitting light of other colors may be formed in a different process (see fig. 11A to 11F). According to some example embodiments, in a pixel unit, two LED units emitting one color (e.g., blue) and an LED unit emitting the other color (e.g., green) may be simultaneously formed, and a wavelength converter may be applied to one of the two LED units (see fig. 12A to 12D).

Fig. 11A to 11F are cross-sectional views illustrating a portion of a process of a method of manufacturing a display device according to some example embodiments.

Referring to fig. 11A, a bottom semiconductor layer 111 having a semiconductor base layer 111B of a first conductivity type may be formed on the growth substrate 101, and a first mask pattern 105a may be formed on the semiconductor base layer 111B of the first conductivity type.

The first mask pattern 105a may have first and second openings O1 and O2 having different widths (i.e., w1 'noteqw 2'), and the first and second openings O1 and O2 may be arranged at a first pitch P1. Here, the width W1 'of the first opening O1 may be greater than the width W2' of the second opening O2. For example, a deviation of the width W1 'of the first opening O1 and the width W2' of the second opening O2 may be determined such that active layers for blue and green may be formed in the first opening O1 and the second opening O2, respectively, in the same process. The first mask pattern 105a may have a portion 105a' covering a region for forming the third LED unit in a subsequent process.

Then, referring to fig. 11B, the first conductive type semiconductor cap layer 112 and the first and second active layers 114a and 114B may be simultaneously grown in the region of the first conductive type semiconductor base layer 111B that is opened through the first and second openings O1 and O2.

The first and second active layers 114a and 114b may include first and second quantum well layers that emit first and second light (e.g., blue and green) of different wavelengths, respectively. The first quantum well layer may have an indium content in the range of 0.15 to 0.2, and the second quantum well layer may have an indium content in the range of 0.25 to 0.3. The first quantum well layer may emit light having a wavelength of 440nm to 480nm, and the second quantum well layer may emit light having a wavelength of 510nm to 550 nm. In some example embodiments, the thickness t 1 of the first active layer 114a may be greater than the thickness t2 of the second active layer 114b.

Then, referring to fig. 11C, a second mask pattern 105b covering the first and second openings O1 and O2 may be formed. The second mask pattern 105B may have a third opening O3' so that an opening in another region of the semiconductor base layer 111B of the first conductive type may be formed.

In this process, a process of forming a dielectric layer for the second mask pattern 105b to cover the first and second openings O1 and O2 and the third opening O3' may be performed.

The third openings O3' may be arranged at a second pitch P2 with the adjacent openings (i.e., the second openings O2 of the first and second openings), and the second pitch P2 may be the same as the first pitch P1. The width W3 of the third opening O3 may be arbitrarily determined. For simple process, the width W3 of the third opening O3 may be substantially the same as the width W1 of the first opening O1 or the width W2 of the second opening O2.

Then, referring to fig. 11D, a first conductive type semiconductor cap layer 112' and a third active layer 114c ' may be formed in another region of the first conductive type semiconductor base layer 111B that is opened through the third opening O3 '.

The first conductive type semiconductor cap layer 112 'of the third opening O3' may be the same nitride layer as the first conductive type semiconductor cap layer 112 of the other openings O1 and O2. The third active layer 114c' may include a third quantum well layer configured to emit third light (e.g., red) of a wavelength different from the wavelengths of the first light and the second light. The third quantum well layer may emit light having a wavelength of 610nm to 650 nm.

As such, in some example embodiments, the third active layer 114c' may be formed through a different growth process from that of the first and second active layers 114a and 114 b. In some example embodiments, the first active layer 114a and the second active layer 114b may be simultaneously formed such that the active layers may have different corresponding layer structures (the same number of quantum barrier layers and quantum well layers), and the third active layer 114c' may have a layer structure different from that of the first active layer 114a and the second active layer 114 b.

Then, referring to fig. 11E, fourth and fifth openings O1 'and O2' for opening the first and second active layers 114a and 114b, respectively, may be formed in the second mask pattern 105b, and semiconductor layers 116 of the second conductive type may be grown on the first to third active layers 114a, 114b and 114c, respectively. Accordingly, the first to third light emitting stacks LC1', LC2', and LC3' arranged at the same pitch (p1=p2) may be formed.

Then, referring to fig. 11F, the first and second mask patterns 105a and 105B may be removed from the first conductive type semiconductor base layer 111B, and edge regions of the first to third light emitting stacks LC1', LC2', and LC3' may be removed.

After the entire mask pattern 105 is removed, the first to third light emitting stacks LC1', LC2', and LC3' may remain on the first conductive type semiconductor base layer 111B. As described above, the first to third light emitting stacks LC1', LC2', and LC3' may include damaged edge regions. In some example embodiments, the first to third light emitting stacks LC1, LC2, and LC3 having the same width (i.e., w1=w2=w3) may be obtained after the edge regions DL1, DL2, and DL3 are removed. The LED units LC1, LC2, and LC3 may be provided as light sources for the first to third sub-pixels, respectively. The first to third LED units LC1, LC2, and LC3 may be held at the same pitch (p1=p2).

Fig. 12A to 12D are cross-sectional views illustrating a portion of a process of a method of manufacturing a display device according to some example embodiments.

Referring to fig. 12A, a bottom semiconductor layer 111 having a semiconductor base layer 111B of a first conductivity type may be formed on the growth substrate 101, and a mask pattern 105a having first to third openings O1, O2, and O1' may be formed on the semiconductor base layer 111B of the first conductivity type.

The first to third openings O1, O2 and O1' may be arranged at the same pitch (p1=p2), and the width W1 of the first opening O1 may be greater than the width (W2) of the second opening O2 and may be equal to the width W1' of the third opening O1 '.

Then, referring to fig. 12B, a first conductive type semiconductor cap layer 112, first to third active layers 114a, 114B and 114a ', and a second conductive type semiconductor layer 116 may be grown in each of the regions of the first conductive type semiconductor base layer 111B opened through the first to third openings O1, O2 and O1'.

The first to third light emitting stacks LC1', LC2', and LC1 'may be formed in the first to third openings O1, O2, and O1', respectively. Since the first and third active layers 114a and 114a 'are formed from the openings O1 and O1' having the same width, the active layers may include first and third quantum well layers emitting light of the same wavelength (e.g., blue light). Since the second active layer 114b is formed in the opening O2 having a relatively small width, the second active layer 114b may include a second quantum well layer emitting light of a relatively long wavelength (e.g., green light). Each of the first quantum well layer and the third quantum well layer may emit light having a wavelength of 440nm to 480nm, and the second quantum well layer may emit light having a wavelength of 510nm to 550 nm.

Then, referring to fig. 12C, the mask pattern 105a may be removed from the first conductive type semiconductor base layer 111B, and referring to fig. 12D, each of the edge regions DL1, DL2, and DL1 of the first to third light emitting stacks LC1', LC2', and LC1' may be removed.

After removing the mask pattern 105a, the two first light emitting stacks LC1 'and the second light emitting stack LC2' therebetween may remain on the first conductive type semiconductor base layer 111B. As described above, each of the first and third light emitting stacks LC1 'and LC2' may include a damaged edge region. In some example embodiments, after the edge regions DL1 and DL2 are removed, two first LED cells LC1 and second LED cells LC2 having the same width (w1=w2=w3) may be obtained. The three LED units LC1, LC2, and LC1 may be held at the same pitch (p1=p2), and may be respectively provided as light sources for the first to third sub-pixels.

The LED module (100E) disposed as a pixel may include a first LED unit LC1 and a second LED unit LC2, and the two first LED units LC1 may emit light of a first color (e.g., blue) and the second LED unit LC2 may emit light of a second color (e.g., green). In some example embodiments, one of the two LED units LC1 may form a wavelength converter (see "160R" in fig. 13) that emits light of a third color (e.g., red).

Fig. 13 is a cross-sectional view illustrating a display device according to some example embodiments corresponding to the cross-section in fig. 3.

Referring to fig. 13, a display device 10A according to some example embodiments may be configured similarly to the display device 10 shown in fig. 3 to 4B, except that a configuration in which an LED module obtained from the process in fig. 12D may be employed and a configuration in which the separation structure 170P is formed of a separate material. Unless otherwise stated, components having the same reference numerals may be understood by referring to the description of the same or similar components as the display device 10 shown in fig. 1 to 4B, and repeated descriptions thereof are omitted for the sake of brevity.

In some example embodiments, by polishing the bottom semiconductor layer, a portion of the region including the semiconductor base layer 111B of the first conductivity type may remain, and the separation structure 170P may be disposed on the polished surface of the remaining region. The separation structure 170P in some example embodiments may include a structure formed of another material (e.g., a light blocking material or a reflective material). For example, the separation structure 170P may include a reflective metal material. The separation structure 170P may provide a separation for preventing light interference between the sub-pixels SP1, SP2, and SP 3.

The LED module 100E employed in the pixel array 100 in some example embodiments may be manufactured by the processes in fig. 12A to 12D. The LED module (100E) provided as a pixel may include two first LED units LC1 and second LED units LC2. Here, one of the two first LED units LC1 may emit light of a first color (e.g., blue), and the second LED unit LC2 may emit light of a second color (e.g., green). The transparent resin portion 160 may be disposed in each sub-pixel space corresponding to the first LED unit LC1 for blue and the second LED unit LC2 for green. In some example embodiments, one of the two LED units LC1 may form a wavelength converter 160R that emits light of a third color (e.g., red). The wavelength converter 160R in some example embodiments may include a resin layer in which red phosphors or red quantum dots are mixed.

In the above-described display device, a partition structure for dividing the sub-pixels may be included, but the display device may be implemented without the partition structure. Fig. 14A and 14B are cross-sectional views illustrating a display device according to an example embodiment, which illustrates an example without a partition structure.

Referring to fig. 14A, a display device 10B according to some example embodiments may be configured similarly to the display device 10 shown in fig. 3 to 4B except for a configuration in which a separation structure is not included, a configuration in which a transparent electrode layer 130 'may be included on an upper surface of a semiconductor base layer 111B of a first conductive type as a common electrode of each LED unit LC1, LC2, and LC3, and a configuration in which a second electrode 150' may be formed in a bell-shaped structure to enhance a reflection function. Unless otherwise stated, components having the same reference numerals may be understood through descriptions of the same or similar components as those of the display device 10 illustrated with reference to fig. 1 to 4B, and repetitive descriptions thereof will be omitted for brevity.

In some example embodiments, by polishing the bottom semiconductor layer, a portion of the region including the semiconductor base layer 111B of the first conductivity type may remain, and the transparent electrode layer 130 may be disposed on the polished surface of the remaining region. The remaining semiconductor base layer 111B of the first conductive type may have a sufficiently thin thickness to prevent light leakage between the sub-pixels. For example, the thickness of the remaining semiconductor base layer 111B of the first conductivity type may be 500nm or less.

The transparent electrode layer 130' may be formed on an upper surface (polished surface) of the remaining first conductive type semiconductor base layer 111B. For example, the transparent electrode layer 130' may include a Transparent Conductive Oxide (TCO) such as ITO, IZO, or GAZO. In some example embodiments, the transparent electrode layer 130' may be provided as a common electrode of the LED cells LC1, LC2, and LC 3. The transparent electrode layer 130 'may extend to the peripheral area PA, i.e., the connection area CR disposed outside the pixel PX, and an extension portion of the transparent electrode layer 130' may be connected to the second common electrode pad 145P2 on the other side through the first common electrode pad 145P1, and may be connected to the circuit board 200 through the first bonding electrode 198.

The second electrode 150' in some example embodiments may have a bell-shaped structure formed of a reflective electrode material. The base insulating layer 191 may be relatively conformally formed on the passivation layer 120, and the second electrode 150' electrically connected to the LED unit may be formed on the base insulating layer 191. The second electrode 150' may have a bell-shaped structure surrounding upper and side regions of each of the LED cells LC1, LC2, and LC3 along a surface of the base insulating layer 191. The second electrode 150' may be a reflective structure and may increase the brightness of each of the sub-pixels SP1, SP2, and SP 3. The base insulating layer 191 may help to allow the second electrode 150' to have rounded corners. In some example embodiments, the base insulating layer 191 may not be provided when the base insulating layer 191 is present in the passivation layer 120. The base insulating layer 191 may include the same or similar material as that of the first wiring insulating layer 195 formed to cover the second electrode 150'.

Referring to fig. 14B, a display device 10C according to some example embodiments may be configured similarly to the display device 10B shown in fig. 14A, except for a configuration in which the display device 10C may further include a mesh-shaped electrode layer and a transparent electrode layer 130'. Unless otherwise stated, components having the same reference numerals may be understood as those by referring to the description of the same or similar components of the display device 10B shown in fig. 14A, and repeated descriptions thereof are omitted for brevity.

In some example embodiments, by polishing the bottom semiconductor layer, a portion of the region including the semiconductor base layer 111B of the first conductivity type may remain, and the transparent electrode layer 130' may be disposed on the polished surface of the remaining region. In some example embodiments, a reflective electrode layer 175 may be included on a region overlapping with a region between the LED cells LC1, LC2, and LC3 in the remaining first conductive type semiconductor base layer 111B. In a plane, the overlapping region may have a mesh shape, and the reflective electrode layer 175 may also have a mesh shape. In some example embodiments, by forming the reflective electrode layer 175 after removing at least a portion of the overlapping region of the remaining first conductive type semiconductor base layer 111B, light leakage between sub-pixels may be effectively prevented.

The reflective electrode layer 175 may be connected to the transparent electrode layer 130' and may serve as a part of a common electrode structure of the LED cells LC1, LC2, and LC 3. As such, in some example embodiments, the grid-shaped reflective electrode layer 175 may uniformly supply current to all sub-pixels in the entire area of the display. In some example embodiments, the reflective electrode layer 175 may extend to the peripheral area PA, that is, the connection area CR disposed outside the pixel PX, and an extension portion of the reflective electrode layer 175 may be connected to the second common electrode pad 145P2 on the other side through the first common electrode pad 145P1, and may be connected to the circuit board 200 through the first bonding electrode 198.

Fig. 15A to 15F are cross-sectional views illustrating a portion of a process of a method of manufacturing a display device according to some example embodiments, which illustrate a method of manufacturing the display device in fig. 3. Part of the process may include manufacturing a pixel array substrate and bonding the pixel array substrate to a circuit board.

Referring to fig. 15A, a base semiconductor layer 111 having a first conductive type 111B, a first conductive type semiconductor cap layer 112, first to third active layers 114a, 114B and 114c, and a bottom semiconductor layer 111 of a second conductive type semiconductor layer 116 may be sequentially formed on a growth substrate 101, and a contact layer 155 may be formed.

The growth substrate 101 may be used to grow a nitride single crystal, and may include, for example, sapphire, si, siC, mgAl ₂ O ₄ 、MgO、LiAlO ₂ 、LiGaO ₂ And at least one of GaN. In some example embodiments, to improve crystallinity and light extraction efficiency of the semiconductor layer, the growth substrate 101 may have an uneven structure on at least a portion of an upper surface thereof. In this case, the uneven structure may also be transferred to the layer grown thereon.

The bottom semiconductor layer 111, the first conductive type semiconductor base layer 111B, the first to third active layers 114a, 114B and 114c, and the second conductive type semiconductor layer 116 may be formed using, for example, metal Organic Chemical Vapor Deposition (MOCVD), hydride Vapor Phase Epitaxy (HVPE) or Molecular Beam Epitaxy (MBE) processes.

The bottom semiconductor layer 111 may include a semiconductor base layer 111B of the first conductivity type and a semiconductor layer of the first conductivity type or an undoped semiconductor layer thereunder. In some example embodiments, the bottom semiconductor layer 111 may include a buffer layer and an undoped nitride layer (e.g., gaN). In this case, the buffer layer may serve to mitigate lattice defects of the first conductive type semiconductor cap layer 112 and may include undoped nitride semiconductors such as undoped GaN, undoped AlN, and undoped InGaN. The first conductive type semiconductor base layer 111B and the first conductive type semiconductor cap layer 112 may be n-type nitride semiconductor layers such as n-type GaN, and the second conductive type semiconductor layer 116 may be p-type nitride semiconductor layers such as p-type GaN/p-type AlGaN. The first to third active layers 114a, 114b and 114c may have a single quantum well structure or a multiple quantum well structure such as InGaN/GaN. A contact layer 155 may be formed on the second conductive type semiconductor layer 116. For example, the contact layer 155 may be a high reflection ohmic contact layer.

Then, referring to fig. 15B, a passivation layer 120 may be formed on the first to third LED units LC1, LC2 and LC3, and a portion of the bottom semiconductor layer 111 may be formed in the outer region ISO.

The passivation layer 120 may be formed on the upper surface of the stacked structure with a uniform thickness, and the passivation layer 120 may be removed from a portion of the region that may be a region in which the first reflective electrode 130 (see fig. 3) is to be formed. For example, the passivation layer 120 may include SiO ₂ At least one of SiN, siCN, siOC, siON and SiOCN. The passivation layer 120 may be conformally formed, and thus, the passivation layer 120 may have a substantially uniform thickness. Openings for the first reflective electrode 130 and the common electrode 145 to be formed in a subsequent process may be formed.

In the outer region ISO, the bottom semiconductor layer 111 may be removed to a predetermined depth. The outer zone ISO may be cut off in the following, and the outer zone ISO may be a zone for dividing the module. Accordingly, in order to prevent cracks in the dicing or dicing process, a portion of the bottom semiconductor layer 111 may be removed in the process.

Then, referring to fig. 15C, the first electrode 130, the common electrode 145, and the first pad electrode 147 may be formed.

First, the first reflective electrode 130 may be formed on the passivation layer 120 and the first conductive type semiconductor layer 112. The first electrode 130 may have a substantially uniform thickness. The first electrode 130 may be formed in a region in which the pixel PX in fig. 3 is disposed and a connection region (CR in fig. 3).

Then, the common electrode 145 and the first PAD electrode 147 may be formed in the connection region CR and the PAD region PAD in fig. 3, respectively. The common electrode 145 may be formed on the first reflective electrode 130, and the first pad electrode 147 may be formed on the passivation layer 120. The common electrode 145 and the first pad electrode 147 may be formed together through the same process. The first electrode 130, the common electrode 145, and the first pad electrode 147 may include a conductive material, for example, a metal.

Then, referring to fig. 15D, a first wiring insulating layer 195 may be formed, and a second electrode 150 connected to the contact layer 155 may be formed.

The first wiring insulating layer 195 may be formed to cover the entire structure including the first electrode 130 formed in the previous process, and a process of planarizing the first wiring insulating layer 195 may be performed using a planarization process such as a Chemical Mechanical Polishing (CMP) process or an etchback process. For example, the first wiring insulating layer 195 may be a low dielectric material such as silicon oxide.

The first wiring insulating layer 195 may be additionally formed, a contact hole penetrating the first wiring insulating layer 195 and the passivation layer 120 and exposing the contact layer 155 may be formed, and the second electrode 150 may be formed by filling the contact hole with a conductive material. A portion of the second electrode 150 may extend to an upper surface of the first wiring insulating layer 195.

Referring to fig. 15E, a first bonding insulating layer 190 may be formed on the second electrode 150, and a first bonding electrode 198 may be formed.

The first bonding insulating layer 190 may include the same material as or a different material from that of the first wiring insulating layer 195. In some example embodiments, the first bonding insulating layer 190 may include a material different from that of the first wiring insulating layer 195. The first bonding electrode 198 may be formed by forming a via hole through the first bonding insulating layer 190 and the first wiring insulating layer 195 and filling the via hole with a conductive material. The first bonding electrode 198 may be connected to the second electrode 150, the common electrode 145, and the first pad electrode 147.

Referring to fig. 15F, a pixel array structure including first to third LED units LC1, LC2, and LC3 may be bonded to the circuit board 200.

The circuit board 200 may be prepared through a separate process. The pixel array structure and the circuit board 200 may be bonded to each other on a wafer level by a wafer bonding method (e.g., hybrid bonding as described above). The second bonding electrode 298 may be bonded to the first bonding electrode 198, and the second bonding insulating layer 290 may be bonded to the first bonding insulating layer 190. Accordingly, the structure including the LED units LC1, LC2, and LC3 and the circuit board 200 may be bonded without an adhesive layer.

Fig. 16A to 16D are cross-sectional views illustrating a portion of a process of a method of manufacturing a display device according to some example embodiments, which illustrate a process subsequent to the process in fig. 15F.

Referring to fig. 16A, the growth substrate 101 may be removed from the bottom semiconductor layer 111, and a portion of the bottom semiconductor layer 111 may be removed. In the drawings, for ease of description, a pixel array structure including first to third LED units LC1, LC2, and LC3 may be bonded to the circuit board 200.

The growth substrate 101 may be removed by various processes such as laser lift-off, mechanical polishing, or mechanochemical polishing and etching processes. For example, the bottom semiconductor layer 111 may be partially removed to be reduced to a predetermined thickness using a polishing process such as CMP. The bottom semiconductor layer 111 may be removed so that the bottom semiconductor layer 111 may not remain in the peripheral region (ISO in fig. 3).

Then, referring to fig. 16B, a partition structure 111P defining sub-pixel spaces OP1, OP2, and OP3 may be formed using the bottom semiconductor layer 111.

The separation structure 111P may be formed using an etching process for forming openings in regions corresponding to the first to third LED units LC1, LC2, and LC3 in the bottom semiconductor layer 111. The openings may provide the first to third sub-pixels (SP 1, SP2 and SP3 in fig. 3) as corresponding first to third sub-pixel spaces (OP 1, OP2 and OP 3), respectively.

In some example embodiments, the first conductive type semiconductor base layer 111B may be shared by the first to third LED units LC1, LC2, and LC 3. That is, the first to third LED units LC1, LC2 and LC3 may be connected to each other through the semiconductor base layer 111B of the first conductive type.

Then, referring to fig. 16C, a separation reflective layer 170 may be formed on the separation structure 111P.

The first separation insulating film 172 and the reflective metal film 174 may be formed, and portions of the reflective metal film 174 may be removed from bottom surfaces of the first to third sub-pixel spaces OP1, OP2 and OP3, and the second separation insulating film 176 may be formed, thereby forming the separation reflective layer 170.

Then, referring to fig. 16D, a transparent resin portion 160 and a planarization layer 182 may be formed in the first to third sub-pixel spaces OP1, OP2 and OP3, and a microlens 185 may be formed on the planarization layer 182.

The transparent resin portion 160 formed of transparent resin may be formed on the first to third sub-pixel spaces OP1, OP2 and OP 3. For example, the transparent resin used in the process may include a transparent resin such as a silicone resin or an epoxy resin.

In some example embodiments, the opening may be formed by removing the bottom semiconductor layer 111 and the semiconductor layer 112 of the first conductive type from the first pad electrode 147. An opening may be formed to expose the passivation layer 120 on the first PAD electrode 147 in the PAD region PAD of fig. 3. Then, the passivation layer 120 exposed through the opening portion may be partially removed, the second pad electrode 199 may be formed, and the adjacent module may be cut in the outer region ISO, thereby manufacturing the display device 10 (see fig. 3).

Referring to fig. 17, an electronic device 1000 according to some example embodiments may be a glasses-type display that may be a wearable device. The electronic device 1000 may include a pair of temples 1100, a pair of optocoupler lenses 1200, and a nose bridge 1300. The electronic apparatus 1000 may further comprise a display device 10 comprising an image generator.

The electronic device 1000 may be implemented as a head-mounted, glasses-type, or goggle-type Virtual Reality (VR) device, an Augmented Reality (AR) device, or a Mixed Reality (MR) device for providing a virtual reality or together providing a virtual image and an external real scene.

The temple 1100 may extend in one direction. The temples 1100 may be spaced apart from each other and may extend in parallel. The temple 1100 can be folded toward the nose-bridge 1300. The nose bridge 1300 may be disposed between the optical coupling lenses 1200 and may connect the optical coupling lenses 1200 to each other. The optical coupling lens 1200 may include a light guide plate. The display device 10 may be disposed on each of the temples 1100 and may generate an image on the optical coupling lens 1200. The display device 10 may be implemented as a display device according to the above-described example embodiments.

According to the above-described exemplary embodiments, since LED units emitting light of different wavelengths can be simultaneously grown on the same substrate, an LED module for a display can be manufactured in a simplified manner. In addition, the shape of the LED units included in each sub-pixel may be controlled by a process of selectively removing an edge region that causes leakage current in each LED unit.

While each of the example embodiments has been shown and described above, it will be apparent to those skilled in the art that modifications and variations may be made without departing from the scope of the disclosure as defined by the appended claims.

Claims

1. A method for manufacturing an LED module, comprising:

forming a semiconductor base layer of a first conductivity type on a growth substrate;

forming a mask pattern on the first conductive type semiconductor base layer, wherein the mask pattern includes first, second and third openings having different widths, and the first, second and third openings are arranged at the same pitch;

forming a first light emitting stack, a second light emitting stack, and a third light emitting stack simultaneously in the first opening, the second opening, and the third opening, respectively, by sequentially growing a first active layer, a second active layer, and a third active layer, and a semiconductor layer of a second conductivity type on regions of the semiconductor base layer of the first conductivity type that are opened through the first opening, the second opening, and the third opening, respectively;

removing the mask pattern from the semiconductor base layer of the first conductivity type; and

Removing an edge region of each of the first, second and third light emitting stacks,

wherein the forming of the first, second, and third light emitting stacks is performed by the same growth process, and the first, second, and third active layers have first, second, and third quantum well layers that emit light of different wavelengths, respectively.

2. The method of claim 1, wherein the first opening has a first width, the second opening has a second width, the third opening has a third width, and the first width is greater than the second width, and the second width is greater than the third width.

3. The method of claim 2, wherein the first quantum well layer emits light having a wavelength of 440nm to 480nm, the second quantum well layer emits light having a wavelength of 510nm to 550nm, and the third quantum well layer emits light having a wavelength of 610nm to 650 nm.

4. The method according to claim 1,

wherein the first, second, and third light emitting stacks comprise nitride single crystal stacks, and

Wherein the first quantum well layer, the second quantum well layer, and the third quantum well layer each include In satisfying a content x of indium having a different content _x Ga _1-x N.

5. The method according to claim 4, wherein the method comprises,

wherein the first opening has a first area, the second opening has a second area, the third opening has a third area, and the first area is larger than the second area, the second area is larger than the third area, and

wherein the first quantum well layer has an indium content in a range of 0.15 to 0.2, the second quantum well layer has an indium content in a range of 0.25 to 0.3, and the third quantum well layer has an indium content in a range of 0.3 to 0.35.

6. The method of claim 5, wherein the first quantum well layer has a first thickness, the second quantum well layer has a second thickness, the third quantum well layer has a third thickness, and the first thickness is greater than the second thickness, and the second thickness is greater than the third thickness.

7. The method of claim 1, wherein forming the first, second, and third light emitting stacks comprises: a semiconductor cap layer of a first conductivity type is grown on the regions of the semiconductor base layer of the first conductivity type, respectively, before growing the first, second and third active layers.

8. The method according to claim 1,

wherein each of the first light emitting laminate, the second light emitting laminate, and the third light emitting laminate includes a nitride single crystal laminate having an upper surface as a (0001) plane, and

wherein the edge region of each of the first, second and third light emitting stacks comprises an inclined side surface region.

9. The method of claim 1, wherein removing the edge region comprises: edge regions having different widths are removed from the first, second, and third light emitting stacks such that the first, second, and third light emitting stacks have the same width after the edge regions are removed.

10. The method of claim 1, wherein the first, second, and third light emitting stacks have different widths after removal of the edge regions.

11. The method of claim 1, further comprising:

forming a first electrode layer, a second electrode layer, and a third electrode layer on upper surfaces of the first light emitting stack, the second light emitting stack, and the third light emitting stack, respectively, to be connected to the second conductive type semiconductor layer; and

A common electrode connected to the semiconductor base layer of the first conductivity type is formed.

12. A method for manufacturing an LED module, comprising:

forming a first mask pattern on the first conductive type semiconductor base layer, wherein the first mask pattern includes first and second openings having different widths, and the first and second openings are arranged at a first pitch;

simultaneously growing a first active layer and a second active layer on a first region and a second region of the semiconductor substrate layer of the first conductivity type, which are opened through the first opening and the second opening, respectively, wherein the first active layer and the second active layer respectively include a first quantum well layer and a second quantum well layer respectively emitting first light and second light of different wavelengths;

forming a second mask pattern covering the first and second openings, the second mask pattern having a third opening configured to open a third region of the semiconductor substrate layer of the first conductivity type, wherein the third opening is arranged at a second pitch with adjacent ones of the first and second openings, and the second pitch is the same as the first pitch;

Forming a third active layer in the third region of the first conductive type semiconductor base layer, wherein the third active layer includes a third quantum well layer configured to emit third light having a wavelength different from that of each of the first light and the second light;

forming fourth and fifth openings exposing the first and second active layers, respectively, in the second mask pattern;

forming a first light emitting stack, a second light emitting stack, and a third light emitting stack by growing a semiconductor layer of a second conductivity type on each of the first active layer, the second active layer, and the third active layer;

removing the first and second mask patterns from the first, second and third light emitting stacks and the first conductivity type semiconductor base layer; and

an edge region of each of the first, second, and third light emitting stacks is removed.

13. The method of claim 12, wherein the first opening has a first area, the second opening has a second area, and the first area is greater than the second area.

14. The method of claim 13, wherein the first quantum well layer has an indium content in the range of 0.15 to 0.2 and the second quantum well layer has an indium content in the range of 0.25 to 0.3.

15. The method of claim 13, wherein the third opening has a third area and the third area is equal to the second area.

16. The method of claim 12, wherein the first quantum well layer emits light having a wavelength of 440nm to 480nm, the second quantum well layer emits light having a wavelength of 510nm to 550nm, and the third quantum well layer emits light having a wavelength of 610nm to 650 nm.

17. A method for manufacturing an LED module, comprising:

forming a mask pattern having first, second, and third openings arranged at the same pitch on the first conductive type semiconductor base layer, wherein the first opening has a first width, the second opening has a second width, the third opening has a third width, and the first width is greater than the second width, the first width being the same as the third width;

Forming a first light emitting stack, a second light emitting stack, and a third light emitting stack in the first opening, the second opening, and the third opening, respectively, by sequentially growing a first active layer, a second active layer, and a third active layer, and a semiconductor layer of a second conductivity type on regions of the semiconductor base layer of the first conductivity type that are opened through the first opening, the second opening, and the third opening, respectively;

wherein the forming of the first, second, and third light emitting stacks is performed by a same growth process, the first and third active layers respectively including first and third quantum well layers emitting light of a same wavelength, the second active layer including a second quantum well layer configured to emit light of a different wavelength than the same wavelength of the first and third quantum well layers.

18. The method of claim 17, further comprising:

a wavelength converter configured to convert light emitted from the third quantum well layer is formed on the third light emitting stack.

19. A display device, comprising:

a circuit board having a driver circuit; and

a pixel array disposed on the circuit board and including pixel units each including first, second and third sub-pixels arranged therein,

wherein the pixel array includes:

a semiconductor base layer of a first conductivity type having a first surface facing the circuit board and a second surface opposite the first surface;

a plurality of first LED units arranged to correspond to the first sub-pixels, a plurality of second LED units arranged to correspond to the second sub-pixels, and a plurality of third LED units arranged to correspond to the third sub-pixels on the first surface of the first conductive type semiconductor base layer, each of the plurality of first LED units, each of the plurality of second LED units, and each of the plurality of third LED units including a first conductive type semiconductor cap layer, an active layer, and a second conductive type semiconductor layer stacked in order;

A light blocking separation structure disposed on the second surface of the first conductive type semiconductor base layer and having light emission windows corresponding to the first, second, and third sub-pixels, respectively;

a passivation layer disposed on the first surface of the first conductive type semiconductor base layer and side and upper surfaces of the plurality of first LED units, the plurality of second LED units, and the plurality of third LED units;

a first electrode disposed on the passivation layer and electrically connected to the semiconductor base layer of the first conductivity type of each of the plurality of first LED units, the plurality of second LED units, and the plurality of third LED units; and

a second electrode disposed on the passivation layer and electrically connected to the semiconductor layers of the second conductivity type of the plurality of first LED units, the plurality of second LED units, and the plurality of third LED units, respectively,

wherein the plurality of first LED units, the plurality of second LED units, and the plurality of third LED units have an upper surface that is a (0001) plane and a side surface that is perpendicular to the first surface of the semiconductor base layer of the first conductivity type.

20. The display device of claim 19, wherein the active layer of each of the plurality of first LED units comprises a first quantum well layer configured to emit light having a wavelength of 440nm to 480nm, the active layer of each of the plurality of second LED units comprises a second quantum well layer configured to emit light having a wavelength of 510nm to 550nm, the active layer of each of the plurality of third LED units comprises a third quantum well layer configured to emit light having a wavelength of 610nm to 650nm, the first, second, and third quantum well layers each comprising In satisfying a content x of different indium _x Ga _1-x N.