KR20240010394A - Display apparatus - Google Patents

Abstract

A display device according to an embodiment of the present invention includes a circuit board including driving circuits, and a pixel array disposed on the circuit board and including a plurality of pixels, wherein the pixel array includes the plurality of pixels. A plurality of LED cells forming a plurality of LED cells, a first electrode that covers the upper surfaces of the plurality of LED cells and extends horizontally onto the area between the plurality of LED cells, and is commonly connected to the plurality of LED cells, and the plurality of LEDs A plurality of second electrodes are disposed on the lower surfaces of the cells and respectively connected to the plurality of LED cells, and some of the plurality of LED cells have upper surfaces located at the first level, and among the plurality of LED cells, Others have upper surfaces located at a second level lower than the first level.

Description

Display device {DISPLAY APPARATUS}

The present invention relates to a display device, and to a display device equipped with LEDs.

Semiconductor light-emitting diodes (LEDs) are used not only as light sources for lighting devices, but also as light sources for various electronic products. In particular, LED is widely used as a light source for various display devices such as TVs, mobile phones, PCs, laptop PCs, and PDAs.

Existing display devices mainly consist of a display panel consisting of a liquid crystal display (LCD) and a backlight, but recently, a type that uses LEDs as pixels and does not require a separate backlight has been developed. Such display devices can not only be miniaturized, but also can implement high-brightness display devices with superior light efficiency compared to LCDs.

One of the technical problems to be achieved by the present invention is to provide a high-resolution display device.

A display device according to example embodiments includes a circuit board including driving circuits and first bonding electrodes, and a plurality of pixels disposed on the circuit board, each including first to third subpixels, and and a pixel array including second bonding electrodes bonded to the first bonding electrodes, wherein the pixel array is arranged to correspond to the first and third subpixels, respectively, and each includes a first conductivity type semiconductor layer. , a plurality of first LED cells including a first active layer and a second conductive semiconductor layer, each arranged to correspond to the second sub-pixels, respectively, the first conductive semiconductor layer, the second active layer, and the A plurality of second LED cells including a second conductive semiconductor layer, a first electrode extending to cover the upper surfaces of the plurality of first and second LED cells, and commonly connected to the first conductive semiconductor layers , a plurality of second electrodes respectively disposed on lower surfaces of the plurality of first and second LED cells and respectively connected to the second conductivity type semiconductor layers, and in the third subpixels, It further includes wavelength converters disposed on one LED cell, wherein the lower surface of the first electrode is located at a first level on the plurality of first LED cells and is lower than the first level on the plurality of second LED cells. It may be located at a lower second level.

A display device according to example embodiments includes a circuit board including driving circuits, and a pixel array disposed on the circuit board and including a plurality of pixels, wherein the pixel array includes the plurality of pixels. A plurality of LED cells forming a plurality of LED cells, a first electrode that covers the upper surfaces of the plurality of LED cells and extends horizontally onto the area between the plurality of LED cells, and is commonly connected to the plurality of LED cells, and the plurality of LEDs A plurality of second electrodes are disposed on the lower surfaces of the cells and respectively connected to the plurality of LED cells, and some of the plurality of LED cells have upper surfaces located at the first level, and among the plurality of LED cells, Others may have upper surfaces located at a second level lower than the first level.

A display device according to example embodiments includes a circuit board including driving circuits, and a pixel array disposed on the circuit board and including a plurality of pixels each including first to third subpixels; , the pixel array includes a plurality of LED cells arranged to respectively correspond to the first and third sub-pixels, extends to cover the upper surfaces of the plurality of LED cells, and is commonly connected to the plurality of LED cells. It includes one electrode, and a plurality of second electrodes each disposed on the lower surfaces of the plurality of LED cells and connected to the plurality of LED cells, respectively, and the lower surface of the first electrode is connected to some of the plurality of LED cells. It may be located at a first level on some of the plurality of LED cells, and at a second level lower than the first level on some of the plurality of LED cells, and lower surfaces of the plurality of second electrodes may be located at substantially the same level.

By optimizing the electrode structure while arranging some of the LED cells using a fluidic transfer method, a high-resolution display device can be provided.

The various and beneficial advantages and effects of the present invention are not limited to the above-described content, and may be more easily understood through description of specific embodiments of the present invention.

1 and 2 are schematic perspective and plan views of display devices according to example embodiments.
Figure 3 is a schematic cross-sectional view of a display device according to example embodiments.
4 is a driving circuit diagram implemented in a display device according to example embodiments.
5 to 7 are schematic cross-sectional views of display devices according to example embodiments.
8A to 8M are cross-sectional views for each main process to explain a method of manufacturing a display device according to example embodiments.
9 is a conceptual diagram of an electronic device including a display device according to example embodiments.

Hereinafter, preferred embodiments of the present invention will be described with reference to the attached drawings.

Unless otherwise specified, in this specification, terms such as 'top', 'top surface', 'bottom', 'bottom surface', 'side', etc. are based on the drawings, and in reality, they depend on the direction in which the elements are arranged. It may change.

1 and 2 are schematic perspective and plan views of display devices according to example embodiments. Figure 2 shows an enlarged view of part 'A' of Figure 1.

Referring to FIGS. 1 and 2 , the display device 10 includes a circuit board 200 including driving circuits and a pixel array 100 disposed on the circuit board 200 and having a plurality of pixels (PX) arranged. ) includes. The display device 10 may further include a frame 11 surrounding the circuit board 200 and the pixel array 100.

The circuit board 200 may be a driving circuit board including thin film transistor (TFT) cells. In some embodiments, the circuit board 200 may include only some of the driving circuits for the display device, in which case the display device 10 may further include a driving device including another part of the driving circuits. It can be included. In some embodiments, the circuit board 200 may include a flexible board, thereby enabling a display device with a curved profile to be implemented.

The pixel array 100 may be an LED module for display. The pixel array 100 may include a plurality of pixels (PX). Each of the plurality of pixels (PX) may include first to third sub-pixels (SP1, SP2, SP3) configured to emit light of a different specific wavelength, for example, a specific color, in order to provide a color image. You can. For example, the first to third subpixels SP1, SP2, and SP3 may be configured to emit blue (B) light, green (G) light, and red (R) light, respectively. In each pixel PX, the first to third subpixels SP1, SP2, and SP3 may be arranged in, for example, a diamond pentile structure.

Specifically, each pixel PX includes first and second subpixels SP1 and SP2 in the first column and second and third subpixels in the second column respectively arranged in the first diagonal direction, for example, D1 direction. (SP2, SP3), and the first and second columns may be arranged in a second diagonal direction perpendicular to the D1 direction, for example, the D2 direction. In each pixel PX, the first to third subpixels SP1, SP2, and SP3 may be arranged in a diamond shape, for example, in a clockwise direction, including the first subpixel SP1, the third subpixel SP1, and the third subpixel SP1. They may be arranged in the following order: the second subpixel SP2, the third subpixel SP3, and the second subpixel SP2. Pixels PX may be continuously arranged along D1 and D2 directions. In FIG. 2, each pixel (PX) is illustrated as having four first to third subpixels (SP1, SP2, and SP3) arranged each, but the first to third subpixels (SP1, SP2, SP3) forming each pixel (PX) The number of subpixels SP1, SP2, and SP3 is not limited to this. Along the D1 and D2 directions, the length of each pixel PX may be 5 μm or less, for example in the range of about 2.5 μm to about 5 μm, and the first to third sub-pixels SP1, SP2, SP3, respectively. The length may range from 2 μm or less, such as from about 0.7 μm to about 1.3 μm.

In some embodiments, the first to third subpixels SP1, SP2, and SP3 may be arranged in a Bayer pattern. In some embodiments, some sub-pixels may be configured to emit light in a color other than the illustrated colors (R, G, B), such as yellow light. In the pixel array 100 of FIG. 1, the number of pixels PX arranged may be any appropriate number, for example, 1,024×768.

The frame 11 may be arranged around the pixel array 100 and serve as a guide for defining the arrangement space of the pixel array 100. The frame 11 may include, for example, at least one of polymer, ceramic, semiconductor, and metal. For example, the frame 11 may include a black matrix area. However, the frame 11 may include a white matrix area or structures of other colors depending on the purpose of the display device 10. For example, the white matrix area may include reflective or scattering material. In FIG. 1 , the display device 10 is illustrated as having a rectangular planar structure, but the display device 10 is not limited thereto and may have various shapes depending on the embodiments.

Figure 3 is a schematic cross-sectional view of a display device according to example embodiments. Figure 3 shows a cross section along line I-I' in Figure 2.

Referring to FIG. 3, the display device 10 includes a circuit board 200 and a pixel array 100 disposed on the circuit board 200.

The circuit board 200 includes a semiconductor substrate 201, a driving circuit disposed on the semiconductor substrate 201 and including driving elements 220 including TFT cells, and a contact electrically connected to the driving elements 220. It may include plugs 230, circuit wiring lines 240 on the contact plugs 230, and a circuit insulation layer 290 covering the driving circuit. The circuit board 200 includes through electrodes 250 such as through silicon via (TSV) connected to the driving circuit, first and second board wiring lines 261 and 262 connected to the through electrodes 250, It may further include a first bonding insulating layer 295 on the circuit insulating layer 290, and first bonding electrodes 298 disposed in the first bonding insulating layer 295 and connected to the circuit wiring lines 240. You can.

The semiconductor substrate 201 may include impurity regions including source/drain regions 205 . The semiconductor substrate 201 may include, for example, a semiconductor such as silicon (Si) or germanium (Ge), or a compound semiconductor such as SiGe, SiC, GaAs, InAs, or InP.

The driving circuit may include a circuit for controlling driving of a pixel, particularly a sub-pixel. The source region 205 of the TFT cells may be electrically connected to one electrode of the LED cells 110 through the contact plug 230, the circuit wiring line 240, and the first bonding electrode 298. For example, the drain region 205 of the TFT cells may be connected to the first substrate wiring line 261 through the through electrode 250, and the first substrate wiring line 261 may be connected to the data line. Gate electrodes of the TFT cells may be connected to the second substrate wiring line 262 through a through electrode 250, and the second substrate wiring line 262 may be connected to the gate line. This circuit configuration and operation will be described in more detail with reference to FIG. 4 below.

The top surfaces of the first bonding electrodes 298 and the top surfaces of the first bonding insulating layer 295 may form the top surface of the circuit board 200 . The first bonding electrodes 298 may be bonded to the second bonding electrodes 198 of the pixel array 100 to provide an electrical connection path. The first bonding electrodes 298 may include a conductive material, for example, copper (Cu). The first bonding insulating layer 295 may be bonded to the second bonding insulating layer 195 of the pixel array 100. The first bonding insulating layer 295 may include, for example, at least one of SiO, SiN, SiCN, SiOC, SiON, and SiOCN.

The pixel array 100 includes first and second LED cells 110B and 110G, first passivation layers 122 covering side surfaces of the first LED cells 110B, and covering side surfaces of the second LED cells 110G. Wavelength conversion on a portion of the second passivation layer 124, the first electrode 150 and the second electrodes 130 connected to the first and second LED cells 110B and 110G, and the first LED cells 110B It may include a color filter 170R on the unit 160R, a wavelength conversion unit 160R, and micro lenses 180. The pixel array 100 includes contact layers 135 on the lower surfaces of the first and second LED cells 110B and 110G, a reflective layer 140 surrounding the side of the wavelength conversion unit 160R, and first and second LED cells 110B and 110G. An interlayer insulating layer 192 between the LED cells 110B and 110G, a transparent insulating layer 194 disposed at a level corresponding to the wavelength conversion unit 160R, a second bonding insulating layer 195, and a second bonding electrode. It may further include 198.

The first and second LED cells 110B and 110G may form first to third subpixels SP1, SP2, and SP3, and each may form a micro LED. The first and second LED cells 110B and 110G may be arranged in columns and rows. The first LED cells 110B are placed in an area corresponding to the first and third subpixels SP1 and SP3, and the second LED cells 110G are placed in an area corresponding to the second subpixel SP2. It can be. The first LED cells 110B may generate blue light, for example, light having a wavelength ranging from about 440 nm to about 480 nm. The second LED cell 110G may generate green light, for example, light having a wavelength ranging from about 510 nm to about 550 nm.

It may include a first conductive semiconductor layer 112, a first active layer 114B, and a second conductive semiconductor layer 116 sequentially stacked from the top of the first LED cells 110B. The second LED cell 110G may include a first conductive semiconductor layer 112, a second active layer 114G, and a second conductive semiconductor layer 116 sequentially stacked from the top.

The first conductive semiconductor layer 112, the first and second active layers 114B and 114G, and the second conductive semiconductor layer 116 may each be made of a nitride semiconductor and may be an epitaxial layer. The first conductive semiconductor layer 112 and the second conductive semiconductor layer 116 are n-type and p-type In _x Al _y Ga _1-xy N (0≤x<1, 0≤y<1, 0≤ It may be a nitride semiconductor layer with a composition of x+y<1). For example, the first conductivity type semiconductor layer 112 is an n-type gallium nitride (n-GaN) layer doped with silicon (Si), germanium (Ge), or carbon (C), and the second conductivity type semiconductor layer is (116) may be a p-type gallium nitride (p-GaN) layer doped with magnesium (Mg) or zinc (Zn). However, depending on the embodiment, the first conductivity type semiconductor layer 112 and the second conductivity type semiconductor layer 116 may be a semiconductor of aluminum indium gallium phosphide (AlInGaP) or aluminum indium gallium arsenide (AlInGaAs) in addition to a nitride semiconductor. It may be made up of layers. Each of the first conductivity type semiconductor layer 112 and the second conductivity type semiconductor layer 116 may be composed of a single layer, but may also include a plurality of layers having different characteristics such as doping concentration and composition.

The first and second active layers 114B and 114G may emit light with a predetermined energy by recombination of electrons and holes. The first and second active layers 114B and 114G may have different compositions to emit light of different wavelengths. The first and second active layers 114B and 114G may have a single (SQW) or multiple quantum well (MQW) structure in which quantum barrier layers and quantum well layers are alternately arranged. For example, the quantum well layer and the quantum barrier layer may be In _x Al _y Ga _1-xy N (0≤x≤1, 0≤y≤1, 0≤x+y≤1) layers having different compositions. there is. For example, the quantum well layer may be an In _x Ga _1-x N (0<x≤1) layer, and the quantum barrier layer may be a GaN layer or an AlGaN layer.

The angle between the lower surface and the side surfaces of each of the first and second LED cells 110B and 110G may be a right angle or an angle similar to a right angle. For example, the angle may range from about 85 degrees to about 95 degrees. The first and second LED cells 110B and 110G may have this structure by sequentially performing a dry etching process and a wet etching process, as described below with reference to FIGS. 8A and 8B. .

The second LED cell 110G may be an LED cell transferred through a fluid transfer process onto the base semiconductor layer 111 (see FIG. 8C) on which the first LED cells 110B were grown (see FIG. 8C). Due to the above process, the top surfaces of the first and second LED cells 110B and 110G may have different levels. This process will be described in more detail below with reference to FIG. 8C. The level of the top surface of the second LED cell 110G may be lower than the level of the top surfaces of the first LED cells 110B. The first and second active layers 114B and 114G may be located at substantially the same level, but are not limited thereto. For example, the first and second LED cells 110B and 110G may have different thicknesses, and the thickness of the second LED cell 110G may be smaller than the thickness of the first LED cells 110B.

The first LED cells 110B may have substantially the same width (L1, L3) or horizontal length in the first and third subpixels (SP1, SP3). In this embodiment, the widths (L1, L3) of the first LED cells (110B) may be substantially equal to the width (L2) of the second LED cells (110G).

The first and second passivation layers 122 and 124 may cover a portion of the lower surfaces of the contact layers 135 and the side surfaces of the first and second LED cells 110B and 110G, respectively. The first and second passivation layers 122 and 124 may contact the first electrode 150 through their upper surfaces. The first and second passivation layers 122 and 124 may have a substantially uniform thickness and may extend conformally.

The first and second passivation layers 122 and 124 may include the same or different materials. The first and second passivation layers 122 and 124 may include a light-transmitting and/or insulating material. For example, the first and second passivation layers 122 and 124 may include metal oxide or semiconductor oxide. For example, the first and second passivation layers 122 and 124 include at least one of SiO ₂ , SiN, SiCN, SiOC, SiON, SiOCN, HfO _x , AlO _x , ZrO _x , TiO _x , and AlN can do. In some embodiments, at least one of the first and second passivation layers 122 and 124 may have a multilayer structure. In some embodiments, at least one of the first and second passivation layers 122 and 124 may include a Distributed Bragg Reflector (DBR) layer.

The first and second passivation layers 122 and 124 may also have different upper surfaces or upper levels. The level of the top surface of the second passivation layer 124 may be lower than the level of the top surfaces of the first passivation layers 122, but is not limited to this.

The first electrode 150 may be connected to the first conductive semiconductor layers 112 in common. The first electrode 150 may be connected to each other between adjacent pixels PX (see FIG. 2) and disposed as a single layer, and is commonly connected to the first and second LED cells 110B and 110G. It can be. Specifically, the first electrode 150 may cover the upper surfaces of the first and second LED cells 110B and 110G and extend horizontally. The first electrode 150 covers the top surfaces of the first and second passivation layers 122 and 124 and may extend onto areas between the first and second LED cells 110B and 110G. The first electrode 150 may include a transparent electrode material such as ITO, IZO, or GAZO.

In this embodiment, the first electrode 150 may have a substantially uniform thickness. Accordingly, the first electrode 150 may have steps ST depending on the level difference between the upper surfaces of the first and second LED cells 110B and 110G. The upper surface of the first electrode 150 is located at the first level on the first LED cells 110B and the first passivation layers 122, and is located on the second LED cell 110G and the second passivation layer 124. It may be located at a second level lower than the first level. The top surface of the first electrode 150 may be located at the first level in areas between the first and second LED cells 110B and 110G. The lower surface of the first electrode 150 is located at the third level on the first LED cells 110B and the first passivation layers 122, and is located on the second LED cell 110G and the second passivation layer 124. It may be located at the fourth level, which is lower than the third level. The lower surface of the first electrode 150 may be located at the third level in areas between the first and second LED cells 110B and 110G.

The contact layers 135 and the second electrodes 130 are sequentially disposed on the lower surfaces of the second conductive semiconductor layers 116 and can be connected to the second conductive semiconductor layers 116. there is. For example, each contact layer 135 may be arranged to cover the entire lower surface of the second conductive semiconductor layer 116 .

The second electrodes 130 may be respectively disposed below the contact layers 135 and connected to the contact layers 135 . The second electrodes 130 may be connected to the second conductive semiconductor layers 116 through contact layers 135 . The second electrodes 130 may be located at substantially the same level as each other, for example, at least the lower surfaces may be located at substantially the same level. In some embodiments, the lower surfaces of the second electrodes 130 are located at substantially the same level, and some of the upper surfaces, for example, the upper surfaces of the second electrode 130 connected to the second LED cell 110G, are different from each other. It may be located at a different level from the upper surfaces of the electrodes 130. Here, the lower surfaces of the second electrodes 130 may refer to the lowermost surfaces of the regions disposed on the lower surface of the interlayer insulating layer 192. The second electrode 130 may be disposed under each of the first and second LED cells 110B and 110G so that at least a portion overlaps with the first and second LED cells 110B and 110G in a vertical direction. there is. The length of the second electrode 130 in one direction may be the same or similar to the length of the LED cells 110, but is not limited thereto and may vary in various embodiments. In some embodiments, the second electrodes 130 may be omitted, in which case the contact layers 135 may be referred to as second electrodes, and the second bonding electrodes 198 below and Can be connected directly.

The contact layers 135 and the second electrodes 130 may include a highly reflective metal, for example, silver (Ag), nickel (Ni), aluminum (Al), chromium (Cr), rhodium ( Rh), iridium (Ir), palladium (Pd), ruthenium (Ru), magnesium (Mg), zinc (Zn), platinum (Pt), gold (Au), titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), tungsten (W), ITO, and IZO.

The interlayer insulating layer 192 may be arranged to fill a space between the first and second LED cells 110B and 110G and cover the lower surfaces of the first and second passivation layers 122 and 124. The transparent insulating layer 194 may be disposed on the first electrode 150 at a level corresponding to the wavelength conversion unit 160R. The transparent insulating layer 194 may not include a wavelength conversion material. The interlayer insulating layer 192 and the transparent insulating layer 194 may be transparent layers and may include an insulating material, such as a transparent resin.

The wavelength conversion unit 160R may be disposed on the first LED cell 110B in the third subpixel SP3. A wavelength conversion unit may not be disposed in the first and second subpixels SP1 and SP2, and only a transparent insulating layer 194 may be disposed. The wavelength conversion unit 160R may be a region in which a wavelength conversion material such as quantum dots is dispersed in a liquid binder resin, and is filled and hardened within the opening of the transparent insulating layer 194. The wavelength conversion unit 160R may include quantum dots capable of converting the wavelength of blue light into red light. The wavelength conversion unit 160R may have an inclined side so that the upper width is larger than the lower width, but the shape of the side is not limited to this.

The reflective layer 140 may be arranged to surround the side of the wavelength conversion unit 160R within the transparent insulating layer 194. The reflective layer 140 may include at least one of a reflective metal, for example, silver (Ag), nickel (Ni), and aluminum (Al). In some embodiments, the reflective layer 140 may have a multilayer structure. In some embodiments, the reflective layer 140 may include an omni-directional reflective (ODR) layer.

The color filter 170R may be disposed on the wavelength conversion unit 160R in the third subpixel SP3. The color filter 170R can increase the color purity of light emitted through the wavelength conversion unit 160R. In some embodiments, a color filter may be further disposed on the first subpixel SP1 and/or the second subpixel SP2.

The micro lenses 180 may be arranged to correspond to the first and second LED cells 110B and 110G, respectively, on the transparent insulating layer 194. The micro lenses 180 may converge light incident from the first and second LED cells 110B and 110G and the wavelength conversion unit 160R. For example, the micro lenses 180 may have a diameter larger than the width of the first and second LED cells 110B and 110G along one direction. The micro lenses 180 may include, for example, a transparent photoresist material or a transparent thermosetting resin.

The second bonding electrodes 198 may connect the second electrodes 130 to the first bonding electrodes 298 of the circuit board 200 . The second bonding electrodes 198 may be disposed to penetrate the interlayer insulating layer 192 and the second bonding insulating layer 195. The second bonding electrodes 198 may have a pillar shape, such as a cylinder. Depending on embodiments, the second bonding electrodes 198 may have sidewalls inclined so that the upper surface is smaller than the lower surface. The second bonding electrodes 198 may include copper (Cu), for example. In some embodiments, the second bonding electrodes 198 may further include a barrier metal layer, for example, a tantalum (Ta) layer and/or a tantalum nitride (TaN) layer on the top surface and side surfaces.

The lower surfaces of the second bonding insulating layer 195 may be arranged to form the lower surface of the pixel array 100 together with the lower surfaces of the second bonding electrodes 198 . The second bonding insulating layer 195 may form dielectric-to-dielectric bonding with the first bonding insulating layer 295. The circuit board 200 and the pixel array 100 include bonding of the first bonding electrodes 298 and the second bonding electrodes 198 and the first bonding insulating layer 295 and the second bonding insulating layer 195. It can be bonded by joining. The bonding of the first bonding electrodes 298 and the second bonding electrodes 198 may be, for example, copper-to-copper bonding, and the first bonding insulating layer The bonding of 295 and the second bonding insulating layer 195 may be, for example, dielectric-dielectric bonding such as SiCN-SiCN bonding. The circuit board 200 and the pixel array 100 may be bonded by hybrid bonding including copper (Cu)-copper (Cu) bonding and dielectric-dielectric bonding, and may be bonded without a separate adhesive layer.

The display device 10 according to this embodiment includes a second LED cell 110G transferred through a fluid transfer process and optimizes the arrangement of the first electrode 150 and the second electrodes 130, By bonding the circuit board 200 and the pixel array 100 using hybrid bonding, a compact, high-resolution device with easy processing can be implemented.

4 is a driving circuit diagram implemented in a display device according to example embodiments.

Referring to FIG. 4, a circuit diagram of a display device 10 in which n×n subpixels are arranged is illustrated. The first to third subpixels SP1, SP2, and SP3 may transmit and receive data signals through data lines D1-Dn, which are vertical paths, for example, in a column direction. The first to third subpixels SP1, SP2, and SP3 may transmit and receive control signals, that is, gate signals, through gate lines G1-Gn, which are horizontal paths, for example, row direction paths.

A plurality of pixels (PX) including the first to third sub-pixels (SP1, SP2, SP3) provide an active area (DA) for display, and this active area (DA) serves as a display area for the user. provided. The non-active area (NA) may be formed along one or more edges of the active area (DA). The inactive area NA extends along the outer periphery of the panel of the display device 10, is an area in which pixels PX do not exist, and corresponds to the frame 11 of the display device 10 (see FIG. 1). You can.

The first and second driver circuits 12 and 13 may be employed to control the operation of the pixels PX, that is, the first to third subpixels SP1, SP2, and SP3. Some or all of the first and second driver circuits 12 and 13 may be implemented on the circuit board 200 (see FIG. 1). The first and second driver circuits 12 and 13 may be formed of integrated circuits, thin film transistor panel circuits, or other suitable circuits, and may be disposed in the non-active area (NA) of the display device 10. The first and second driver circuits 12 and 13 may include a microprocessor, memory such as storage, processing circuitry, and communication circuitry.

In order to display an image by pixels PX, the first driver circuit 12 supplies image data to the data lines D1-Dn and provides a clock signal to the second driver circuit 13, which is a gate driver circuit. and other control signals. The second driver circuit 13 may be implemented using an integrated circuit and/or a thin film transistor circuit. A gate signal for controlling the first to third subpixels SP1, SP2, and SP3 arranged in the row direction may be transmitted through the gate lines G1-Gn of the display device 10.

5 to 7 are schematic cross-sectional views of display devices according to example embodiments. Figures 5 to 7 each show areas corresponding to Figure 3.

Referring to FIG. 5, in the display device 10a, the first LED cells 110B and the second LED cells 110G may have different widths or horizontal lengths. Additionally, the pixel array 100 may further include a light blocking layer 155.

The first LED cells 110B may have substantially the same width (L1, L3) or horizontal length in the first and third subpixels (SP1, SP3). In this embodiment, the widths (L1, L3) of the first LED cells (110B) may be smaller than the width (L2a) of the second LED cells (110G). For example, the second LED cell 110G may be grown to a relatively large width for an easy transfer process. In this case, the light blocking layer 155 may be disposed on the first electrode 150 to make the light emission area of the first and second LED cells 110B and 110G the same.

The light blocking layer 155 may be disposed in areas including the interfaces of the first to third subpixels SP1, SP2, and SP3, and in areas between the first and second LED cells 110B and 110G. It can be placed on top. Specifically, the light blocking layer 155 may be disposed on the first electrode 150 in areas including areas between the first and second LED cells 110B and 110G. The light blocking layer 155 may have an overall mesh shape in a plan view. Areas exposed from the light blocking layer 155 may have the same width in one direction. In embodiments, the range of areas exposed from the light blocking layer 155 is not limited to that shown in the drawing, and may be changed in various ways within a range that satisfies the optical characteristics of the display device 10a. The light blocking layer 155 may include a black matrix or a metal material such as tungsten (W), copper (Cu), aluminum (Al), etc.

In some embodiments, even when the first and second LED cells 110B and 110G have the same width, the second LED cell 110G is not exactly aligned and disposed between the first LED cells 110B. Considering the case, an additional light blocking layer 155 may be disposed. The light blocking layer 155 of this embodiment may also be applied to the embodiments of FIGS. 3, 6, and 7.

Referring to FIG. 6, in the display device 10b, the pixel array 100 may include first to third LED cells 110B, 110G, and 110R, and the wavelength conversion unit 160R of FIG. 3 and the color The filter 170R may not be included.

The third LED cell 110R may be disposed in the third subpixel SP3. The third LED cell 110R may generate red light, for example, light having a wavelength ranging from about 610 nm to about 650 nm. The third LED cell 110R may include a first conductivity type semiconductor layer 112, a third active layer 114R, and a second conductivity type semiconductor layer 116 sequentially stacked from the top. The first to third active layers 114B, 114G, and 114R may have different compositions to emit light of different wavelengths.

The third LED cell 110R, similar to the second LED cell 110G, may be an LED cell transferred through a fluid transfer process onto the base semiconductor layer on which the first LED cell 110B was grown. Accordingly, the level of the top surface of the third LED cell 110R may be lower than the level of the top surface of the first LED cell 110B. The level of the top surface of the third LED cell 110R may be the same or similar to the level of the top surface of the second LED cell 110G. In some embodiments, the level of the top surface of the third LED cell 110R may be different from the level of the top surface of the second LED cell 110G. The first to third active layers 114B, 114G, and 114R may be located at substantially the same level, but are not limited thereto.

The first electrode 150 may have first and second steps ST1 and ST2 according to the level difference between the upper surfaces of the first LED cell 110B and the second and third LED cells 110G and 110R. . The depths of the first and second steps ST1 and ST2 may be the same or different from each other. In some embodiments, the pixel array 100 may further include a color filter disposed on at least one of the first to third LED cells 110B, 110G, and 110R.

The arrangement of the first to third LED cells 110B, 110G, and 110R of this embodiment may also be applied to the embodiments of FIGS. 6 and 7.

Referring to FIG. 7, in the display device 10c, the first electrode 150c may have a flat top surface. The upper surface of the first electrode 150c may be located at one level. However, the lower surface of the first electrode 150c may be located at a plurality of levels as described above with reference to FIG. 3. Accordingly, the first electrode 150c may include regions with different thicknesses. The first electrode 150c may have a first thickness T1 on the first LED cells 110B, and may have a second thickness T2 greater than the first thickness T1 on the second LED cells 110G. .

The shape of the first electrode 150c of this embodiment may also be applied to the embodiments of FIGS. 5, 6, and 7.

8A to 8M are cross-sectional views for each main process to explain a method of manufacturing a display device according to example embodiments. FIGS. 8A to 8M exemplarily illustrate a method of manufacturing the display device of the embodiment of FIG. 3.

Referring to FIG. 8A, the base semiconductor layer 111, the first conductive semiconductor layer 112, the first active layer 114B, and the second conductive semiconductor layer 116 are sequentially formed on the growth substrate GS. After forming the contact layer 135, the stacked structure can be etched to form first LED cells 110B.

The growth substrate GS may be for growing a nitride single crystal, and may include, for example, at least one of sapphire, Si, SiC, MgAl ₂ O ₄ , MgO, LiAlO ₂ , LiGaO ₂ , and GaN. According to embodiments, in order to improve the crystallinity and light extraction efficiency of the semiconductor layers, the growth substrate GS may have a convex-convex structure on at least a portion of the upper surface. In this case, irregularities may also be formed in the layers grown on top.

The base semiconductor layer 111, the first conductive semiconductor layer 112, the first active layer 114B, and the second conductive semiconductor layer 116 are formed, for example, by metal organic chemical vapor deposition (Metal Organic Chemical Vapor Deposition). It can be formed using MOCVD), Hydrogen Vapor Phase Epitaxy (HVPE), or Molecular Beam Epitaxy (MBE) processes. The base semiconductor layer 111 and the first conductive semiconductor layer 112 may be an n-type nitride semiconductor layer such as n-type GaN, and the second conductive semiconductor layer 116 may be a p-type nitride semiconductor layer such as p-type GaN/p-type AlGaN. It may be a type nitride semiconductor layer. The first active layer 114B may have a multi-quantum well structure such as InGaN/GaN. Depending on embodiments, the base semiconductor layer 111 may include a buffer layer. In this case, the buffer layer is for alleviating lattice defects of the first conductive semiconductor layer 112, and may include an undoped nitride semiconductor such as undoped GaN, undoped AlN, and undoped InGaN.

The contact layer 135 may be formed on the upper surface of the second conductive semiconductor layer 116. For example, the contact layer 135 may be a highly reflective ohmic contact layer.

Using a dry etching process, a base semiconductor layer 111, a first conductive semiconductor layer 112, a first active layer 114B, a second conductive semiconductor layer 116, and a contact layer 135 are formed. Part of the laminated structure may be removed. Accordingly, first LED cells 110B may be formed in the first and third subpixels SP1 and SP3. All of the stacked structures may be removed from the second subpixel SP2. In this step, the first LED cells 110B may be etched to have inclined sides. Additionally, damage regions DR may be formed on side surfaces of the first LED cells 110B through the dry etching process.

Referring to FIG. 8B, damaged areas DR may be removed from the first LED cells 110B.

Damaged regions DR may be selectively removed by, for example, a wet etching process. During the wet etching process, by controlling the process conditions so that the selectivity between the crystal planes is etched differently, only the damaged regions DR can be selectively removed. As a result, the angle between the top surfaces and side surfaces of the first LED cells 110B may be vertical or close to vertical, and non-radiative recombination due to the damaged regions DR may be reduced, thereby reducing the luminance. can be improved.

In some embodiments, this step may be omitted, in which case the first LED cells 110B may have sloped sides.

Referring to FIG. 8C, the first preliminary passivation layer 122P may be formed, and the second LED cell 110G may be fluid transferred onto the base semiconductor layer 111.

The first preliminary passivation layer 122P may be formed with a uniform thickness on the first LED cells 110B and the base semiconductor layer 111. The first preliminary passivation layer 122P may include, for example, at least one of SiO ₂ , SiN, SiCN, SiOC, SiON, SiOCN, HfO ₂ , Al ₂ O ₃ , ZrO _x , AlN, and TiO _x . In some embodiments, the first preliminary passivation layer 122P may include a metal oxide disposed on top, for example, a sequentially stacked SiO ₂ layer, HfO ₂ layer, and Al ₂ O ₃ layer. It can be included.

The second LED cell 110G may be prepared by growing on a separate growth substrate. A second passivation layer 124 may be formed on the side and top surfaces of the second LED cell 110G, and a bonding layer 121 may be formed on the bottom surface. The bonding layer 121 may include, for example, oxide. The second LED cell 110G may be separated from the growth substrate in a solution of potassium hydroxide (KOH), tetramethylammonium hydroxide, or the like.

The second LED cell structure including the second LED cell 110G, the second passivation layer 124, and the bonding layer 121 forms the second subpixel SP2 in the solution FL by a fluid transfer process. It can be transferred onto the base semiconductor layer 111. The solution (FL) may be, for example, water, ethanol, etc. The second LED cell structure may be transferred to the space between the first LED cells 110B and may be bonded to the first preliminary passivation layer 122P by the bonding layer 121. For example, the bonding layer 121 and the first preliminary passivation layer 122P may be dielectric-dielectric bonded.

Referring to FIG. 8D, an interlayer insulating layer 192 can be formed.

The interlayer insulating layer 192 may fill a space between the first and second LED cells 110B and 110G and may be formed on the first preliminary passivation layer 122P and the second passivation layer 124.

Referring to FIG. 8E, second electrodes 130 connected to the contact layers 135 may be formed.

On the first and second LED cells 110B and 110G, the interlayer insulating layer 192, the first preliminary passivation layer 122P, and the second passivation layer 124 are partially etched to expose the contact layers 135. contact holes can be formed. The second electrodes 130 may be formed by conformally depositing a conductive material in the contact holes. The second electrodes 130 may cover the inner surfaces of the contact holes and extend onto the upper surface of the interlayer insulating layer 192.

Referring to FIG. 8F , a second bonding insulating layer 195 may be formed on the second electrodes 130 and second bonding electrodes 198 may be formed.

The second bonding insulating layer 195 may include the same or different material from the interlayer insulating layer 192. In embodiments, the thickness of the second bonding insulating layer 195 may vary in a range where the second bonding insulating layer 195 forms one side of the pixel array 100 (see FIG. 3).

The second bonding electrodes 198 can be formed by forming via holes penetrating the second bonding insulating layer 195 and the interlayer insulating layer 192 and then filling the via holes with a conductive material. The second bonding electrodes 198 may be formed to be connected to the second electrodes 130 .

Referring to FIG. 8G, the LED structure including the first and second LED cells 110B and 110G and the circuit board 200 may be bonded.

First, the circuit board 200 may be prepared through a separate process. The LED structure and the circuit board 200 may be bonded at the wafer level by a wafer bonding method, such as the hybrid bonding described above. The first bonding electrodes 298 may be bonded to the second bonding electrodes 198, and the first bonding insulating layer 295 may be bonded to the second bonding insulating layer 195. As a result, the LED structure and the circuit board 200 can be connected without a separate adhesive layer.

In some embodiments, the LED structure is not bonded at the wafer level, but is separated into units of pixels (PX) (see FIG. 2) and then attached to the circuit board 200 using a chip-on-wafer (COW) method. ) may also be bonded on.

Referring to FIG. 8H, the growth substrate GS may be removed from the base semiconductor layer 111. In the following drawings, to aid understanding, the LED structure is shown bonded in a form that is a mirror image of the structure shown in FIG. 8G.

The growth substrate GS may be removed by various processes such as laser lift-off, mechanical polishing or mechanical chemical polishing, and an etching process.

Referring to FIG. 8I, the base semiconductor layer 111 can be removed and the bonding layer 121 can be removed.

The base semiconductor layer 111 can be removed using, for example, a dry etching and/or wet etching process. Parts of the first preliminary passivation layer 122P and the first conductive semiconductor layers 112 exposed after removing the base semiconductor layer 111 may also be removed using a dry etching and/or wet etching process. 1 The bonding layer 121 exposed after removing the preliminary passivation layer 122P can also be removed. As a result, a step ST may be formed along the perimeter of the second LED cell 110G and the second passivation layer 124. Additionally, the first preliminary passivation layer 122P may be separated to form first passivation layers 122 surrounding the side surfaces and bottom surfaces of the first LED cells 110B.

Referring to FIG. 8J, the first electrode 150 may be formed on the first and second LED cells 110B and 110G.

The first electrode 150 may be formed by conformally depositing a transparent electrode material. The first electrode 150 may be a single layer extending horizontally. The first electrode 150 may have a step ST along the circumference of the second LED cell 110G and the second passivation layer 124.

Referring to FIG. 8K, after forming the transparent insulating layer 194 on the first electrode 150 and forming the opening OP, the reflective layer 140 can be formed on the inner side of the opening OP. .

The transparent insulating layer 194 may include an inorganic material or an organic material. The opening OP may be formed by removing the transparent insulating layer 194 from the third subpixel SP3 where the wavelength conversion unit 160R (see FIG. 3) will be placed. The reflective layer 140 may be formed by forming a light-reflective material along the inner surface of the opening OP and removing the light-reflective material from the bottom surface of the opening OP.

Referring to FIG. 8L, a wavelength conversion unit 160R may be formed within the opening OP.

The wavelength conversion unit 160R can be formed by forming a transparent resin mixed with a wavelength conversion material in the opening OP. The wavelength conversion material can convert blue light emitted from the first LED cell 110B into red light. The transparent resin may include, for example, a transparent resin such as silicone resin or epoxy resin. In some embodiments, the wavelength conversion unit 160R may be formed of silicon oxide such as SiO ₂ instead of the transparent resin.

Referring to FIG. 8M, a color filter 170R may be formed on the wavelength conversion unit 160R.

In some embodiments, the color filter 170R may be formed after forming a sealing layer on the wavelength conversion unit 160R. In some embodiments, color filters may be further formed in the first and second subpixels SP1 and SP2.

Next, referring to FIG. 3 , a micro lens 180 may be formed on the color filter 170R. Micro lenses 180 may also be formed on the transparent insulating layer 194 in the first and second subpixels SP1 and SP2. The microlenses 180 can be formed, for example, by forming a lens material layer made of an exposeable material using a spray or spin coating process, then directly patterning the layer and reflowing it. Alternatively, the micro lenses 180 may be formed by forming a lens material layer, forming a separate mask layer including lens patterns, and then performing an etching process such as dry etching on the lens material layer using the mask layer. It can be formed by transferring the shapes of the lens patterns.

Next, by dicing the entire structure like this. The display device 10 of FIG. 3 can be manufactured.

9 is a conceptual diagram of an electronic device including a display device according to example embodiments.

Referring to FIG. 9, the electronic device 1000 may be a glasses-type display, which is a wearable device. The electronic device 1000 may include a pair of temples 1100, a pair of optical coupling lenses 1200, and a bridge 1300. The electronic device 1000 may further include a display device 10 including an image generator.

The electronic device 1000 is a head-mounted, glasses-type, or goggle-type virtual reality (VR) device that can provide virtual reality or provide both a virtual image and an actual external scenery, or an augmented reality (VR) device. It may be a reality (AR) device, or a mixed reality (MR) device.

The temples 1100 may be spaced apart from each other and extend in parallel. The display device 10 may be disposed within the temples 1100, and projection lenses may be further disposed. The temples 1100 may be folded toward the bridge 1300. The light coupling lenses 1200 may include a light guide plate and may further include input/output gratings. The bridge 1300 may be provided between the light coupling lenses 1200 to connect the light coupling lenses 1200 to each other.

The display device 10 may be disposed on each of the temples 1100 and may generate images on the light coupling lenses 1200 . Specifically, light from the display device 10 may be incident on the projection lenses and then transmitted along the light guide plate of the light coupling lenses 1200 to generate an image. The display device 10 may be a display device according to the embodiments described above with reference to FIGS. 1 to 7 .

The present invention is not limited by the above-described embodiments and attached drawings, but is intended to be limited by the appended claims. Accordingly, various forms of substitution, modification and change, and combinations of embodiments will be possible by those skilled in the art without departing from the technical spirit of the present invention as set forth in the claims, and this will also be possible in the present invention. It will be said to fall within the scope of the invention.

10: Display device 100: Pixel array
110B: first LED cell 110G: second LED cell
110R: Third LED cell 111: Base semiconductor layer
112: first conductive semiconductor layer 114B: first active layer
114G: second active layer 114R: third active layer
116: second conductive semiconductor layer 122: first passivation layer
124: second passivation layer 130: second electrode
135: contact layer 140: reflective layer
150: first electrode 160R: wavelength conversion unit
170R: Color filter 180: Micro lens
192: Interlayer insulating layer 194: Transparent insulating layer
195: second bonding insulating layer 198: second bonding electrode
200: circuit board

Claims (20)

A circuit board including driving circuits and first bonding electrodes; and
It is disposed on the circuit board and includes a pixel array including a plurality of pixels each including first to third subpixels and second bonding electrodes bonded to the first bonding electrodes,
The pixel array is,
a plurality of first LED cells arranged to correspond to the first and third subpixels, respectively, each including a first conductivity type semiconductor layer, a first active layer, and a second conductivity type semiconductor layer;
a plurality of second LED cells arranged to respectively correspond to the second sub-pixels and each including the first conductivity type semiconductor layer, the second active layer, and the second conductivity type semiconductor layer;
a first electrode extending to cover upper surfaces of the plurality of first and second LED cells and commonly connected to the first conductivity type semiconductor layers;
a plurality of second electrodes respectively disposed on lower surfaces of the plurality of first and second LED cells and respectively connected to the second conductivity type semiconductor layers; and
In the third sub-pixels, further comprising wavelength conversion units disposed on the first LED cells,
A lower surface of the first electrode is located at a first level on the plurality of first LED cells, and is located at a second level lower than the first level on the plurality of second LED cells.
According to claim 1,
A display device wherein the plurality of second electrodes are located at substantially the same level.
According to claim 1,
A top surface of the first electrode is located at a third level on the plurality of first LED cells, and is located at a fourth level lower than the third level on the plurality of second LED cells.
According to claim 1,
The first active layer and the second active layer include materials having different compositions.
According to claim 1,
The pixel array is disposed on the plurality of first and second LED cells at a level corresponding to the wavelength conversion units in the first and second subpixels, and a transparent insulating layer that does not include a wavelength conversion material. A display device further comprising:
According to claim 1,
The pixel array further includes a light blocking layer disposed on the first electrode in areas including areas between the plurality of first and second LED cells.
According to clause 6,
The display device wherein the plurality of first LED cells and the plurality of second LED cells have different widths.
According to claim 1,
The pixel array further includes reflective layers arranged to surround sides of the wavelength conversion units.
According to claim 1,
The pixel array is,
Color filters disposed on the wavelength conversion units; and
The display device further includes micro lenses disposed on the plurality of first and second LED cells in the first and second subpixels and on the color filters in the third subpixels.
According to claim 1,
The circuit board further includes a first bonding insulating layer surrounding the first bonding electrodes and forming an upper surface of the circuit board,
The pixel array surrounds the second bonding electrodes and forms a lower surface of the pixel array, and further includes a second bonding insulating layer bonded to the first bonding insulating layer.
According to claim 1,
The first to third subpixels are arranged in a diamond pentile structure.
a circuit board containing driving circuits; and
disposed on the circuit board, comprising a pixel array including a plurality of pixels;
The pixel array is,
A plurality of LED cells forming the plurality of pixels;
a first electrode that covers upper surfaces of the plurality of LED cells, extends horizontally over an area between the plurality of LED cells, and is commonly connected to the plurality of LED cells; and
A plurality of second electrodes are respectively disposed on lower surfaces of the plurality of LED cells and connected to the plurality of LED cells, respectively,
A display device in which upper surfaces of some of the plurality of LED cells are located at a first level, and upper surfaces of some of the plurality of LED cells are located at a second level lower than the first level.
According to claim 12,
A display device wherein the first electrode is a single layer.
According to claim 12,
Each of the plurality of pixels includes first to third subpixels,
The plurality of LED cells include first LED cells arranged to correspond to each of the first and third subpixels and second LED cells arranged to correspond to each of the second subpixels,
The first LED cells include a first active layer, and the second LED cells include a second active layer.
According to claim 14,
The first LED cells have upper surfaces located at the first level, and the second LED cells have upper surfaces located at the second level.
According to claim 12,
Each of the plurality of pixels includes first to third subpixels,
The plurality of LED cells include first LED cells arranged to correspond to each of the first subpixels, second LED cells arranged to correspond to each of the second subpixels, and each of the third subpixels. Comprising third LED cells corresponding to each other,
The first LED cells include a first active layer, the second LED cells include a second active layer, and the third LED cells include a third active layer.
According to claim 16,
The first LED cells have upper surfaces located at the first level, and at least one of the second LED cells and the third LED cells has upper surfaces located at the second level.
According to claim 12,
A display device wherein the first electrode includes regions with different thicknesses.
a circuit board containing driving circuits; and
disposed on the circuit board, comprising a pixel array including a plurality of pixels each including first to third subpixels;
The pixel array is,
a plurality of LED cells arranged to correspond to the first and third subpixels, respectively;
a first electrode extending to cover upper surfaces of the plurality of LED cells and commonly connected to the plurality of LED cells; and
A plurality of second electrodes are respectively disposed on lower surfaces of the plurality of LED cells and connected to the plurality of LED cells, respectively,
A lower surface of the first electrode is located at a first level on some of the plurality of LED cells, and is located at a second level lower than the first level on some of the plurality of LED cells,
A display device wherein lower surfaces of the plurality of second electrodes are located at substantially the same level.
According to clause 19,
The pixel array further includes wavelength converters disposed on at least some of the LED cells located at the second level among the plurality of LED cells.

Images