KR20240010389A - Led module, method of fabricating the same, and led display apparatus - Google Patents

Abstract

One embodiment of the present invention includes forming a first conductive semiconductor base layer on a growth substrate; Forming a mask pattern on the first conductive semiconductor base layer - the mask pattern has a first opening, a second opening, and a third opening having different widths, and the first opening, the second opening, and the third openings are arranged at the same pitch; By growing first to third active layers in each of the regions of the first conductivity type semiconductor base layer opened by the first to third openings and second conductivity type semiconductor layers thereon, forming first to third light emitting laminates respectively within the three openings; removing a mask pattern from the first conductive semiconductor base layer; and removing edge regions of each of the first to third light emitting laminates, wherein the step of forming the first to third light emitting laminates is performed by the same growth process, and the first to third light emitting laminates are formed using the same growth process. The third active layer provides a method of manufacturing an LED module having first to third quantum well layers, each of which emits light of different wavelengths.

Description

LED module, manufacturing method of LED module, LED display device {LED MODULE, METHOD OF FABRICATING THE SAME, AND LED DISPLAY APPARATUS}

The present invention relates to an LED module, a manufacturing method thereof, and an LED display device.

Semiconductor light-emitting diodes (LEDs) are used not only as light sources for lighting devices, but also as light sources for various electronic products. In particular, LED is widely used as a light source for various display devices such as TVs, mobile phones, PCs, laptop PCs, and PDAs.

Existing display devices mainly consist of a display panel consisting of a liquid crystal display (LCD) and a backlight, but recently, a type that uses LEDs as pixels and does not require a separate backlight has been developed. Such display devices can not only be miniaturized, but also can implement high-brightness display devices with superior light efficiency compared to LCDs.

One of the problems to be solved by the present invention is to provide a high-efficiency LED module that can be manufactured in a simplified process and a manufacturing method thereof.

One of the problems to be solved by the present invention is to provide a high-efficiency display device that can be manufactured through a simplified process.

One embodiment of the present invention includes forming a first conductive semiconductor base layer on a growth substrate; Forming a mask pattern on the first conductive semiconductor base layer - the mask pattern has a first opening, a second opening, and a third opening having different widths, and the first opening, the second opening, and the third openings are arranged at the same pitch; By growing first to third active layers in each of the regions of the first conductivity type semiconductor base layer opened by the first to third openings and second conductivity type semiconductor layers thereon, forming first to third light emitting laminates respectively within the three openings; removing a mask pattern from the first conductive semiconductor base layer; and removing an edge region of each of the first to third light emitting laminates, wherein the step of forming the first to third light emitting laminates is performed by the same growth process, and the first to third light emitting laminates are formed using the same growth process. The third active layer provides a method of manufacturing an LED module having first to third quantum well layers, each of which emits light of different wavelengths.

One embodiment of the present invention includes forming a first conductive semiconductor base layer on a growth substrate; Forming a first mask pattern on the first conductive semiconductor base layer - the first mask pattern has first openings and second openings having different widths, and the first opening and the second opening are Arranged in 1st pitch -; Simultaneously growing first and second active layers in each of the regions of the first conductive semiconductor base layer opened by the first and second openings, wherein the first and second active layers each have different wavelengths. comprising first and second quantum well layers emitting first and second light; Forming a second mask pattern having a third opening that covers the first and second openings and opens another region of the first conductive semiconductor base layer, wherein the third opening is connected to the first and second openings. arranged at a second pitch with adjacent openings, and the second pitch is the same as the first pitch; Forming a third active layer in another area of the first conductivity type semiconductor base layer opened by the third opening - a third quantum well emitting third light having a wavelength different from the wavelength of the first and second light. Contains layers -; forming fourth and fifth openings in the second mask pattern to open the first and second active layers, respectively; forming first to third light emitting laminates by growing second conductive semiconductor layers on the first to third active layers, respectively; removing first and second mask patterns from the first conductive semiconductor base layer; and removing edge regions of each of the first to third light emitting laminates.

One embodiment of the present invention includes forming a first conductive semiconductor base layer on a growth substrate; Forming a mask pattern having first to third openings arranged at the same pitch on the first conductive semiconductor base layer, wherein the first opening is larger than the width of the second opening and is equal to the width of the third opening. has the same width -; The first to third openings are formed by growing first to third active layers and second conductivity type semiconductor layers in each of the regions of the first conductivity type semiconductor base layer opened by the first to third openings. forming first to third light emitting laminates respectively; removing a mask pattern from the first conductive semiconductor base layer; and removing edge regions of each of the first to third light emitting laminates, wherein the step of forming the first to third light emitting laminates is performed by the same growth process, and the first and third light emitting laminates are formed by the same growth process. The third active layers include first and third quantum well layers that each emit light of the same wavelength, and the second active layer includes a second quantum well layer that emits light of a different wavelength than the first and third quantum well layers. A method of manufacturing an LED module including a well layer is provided.

One embodiment of the present invention includes: a first conductive semiconductor base layer; and a plurality of first to third LED cells arranged at the same pitch on a first conductive semiconductor base layer and composed of semiconductor layers corresponding to each other, wherein the plurality of first to third LED cells are each It includes a nitride single crystal laminate in which a first conductive cap layer, an active layer, and a second conductive semiconductor layer are sequentially stacked, wherein the nitride single crystal laminate has an upper surface that is a (0001) plane and perpendicular to the first conductive semiconductor base layer. It has a side surface, and the active layer of the plurality of first LED cells includes a first quantum well layer that emits light with a wavelength of 440 nm to 480 nm, and the active layer of the plurality of second LED cells includes a wavelength of 510 nm to 480 nm. It includes a second quantum well layer that emits light with a wavelength of 550 nm, and the active layer of the plurality of third LED cells emits light with a wavelength of 610 nm to 650 nm nm, and the first to third quantum well layers emit light with a wavelength of 610 nm to 650 nm nm. The well layers provide an LED module including a third quantum well layer including a nitride single crystal satisfying In _x Ga _1-x N, each having a different indium content (x).

One embodiment of the present invention includes a circuit board having a driving circuit; and a pixel array disposed on the circuit board, in which pixel units each composed of first to third subpixels are arranged, wherein the pixel array has a first surface facing the circuit board and the first a first conductivity type semiconductor base layer having a second surface located opposite to the surface, and arranged to correspond to the first to third subpixels on the first surface of the first conductivity type semiconductor base layer, respectively, A plurality of first to third LED cells including a first conductivity type semiconductor cap layer, an active layer, and a second conductivity type semiconductor layer sequentially stacked; a light blocking barrier structure disposed on a second surface of the first conductive semiconductor base layer and having light emission windows corresponding to each of the first to third subpixels; a passivation layer disposed on a first surface of the first conductive semiconductor base layer and side surfaces and top surfaces of the plurality of first to third LED cells; a first electrode disposed on the passivation layer and electrically connected to the first conductive semiconductor base layer of each of the plurality of LED cells; and second electrodes disposed on the passivation layer and electrically connected to the second conductive semiconductor layer of each of the plurality of first to third LED cells, respectively. The LED cell provides a display device having a top surface that is a (0001) plane and a side surface that is perpendicular to the first surface of the first conductive semiconductor base layer.

According to the above-described embodiment, LED cells for emitting light of different wavelengths can be grown simultaneously on the same substrate, so that an LED module for a display can be manufactured in a more simplified manner. Additionally, the shape of the LED cells constituting each subpixel can be controlled through a process of selectively removing edge areas that cause leakage current in each LED cell.

The various and beneficial advantages and effects of the present invention are not limited to the above-described content, and may be more easily understood through description of specific embodiments of the present invention.

1 is a schematic perspective view of a display device according to an embodiment of the present invention.
Figure 2 is a schematic plan view of a display device according to an embodiment of the present invention.
Figure 3 is a schematic cross-sectional view of a display device according to an embodiment of the present invention.
4A and 4B are a cross-sectional view and a plan view, respectively, of an LED module used in a display device according to an embodiment of the present invention.
Figure 5 is a driving circuit implemented in a display device according to an embodiment of the present invention.
FIGS. 6A to 6E are cross-sectional views of each main process for explaining the manufacturing method of the LED module according to an embodiment of the present invention, and FIG. 7 is a plan view showing the LED module of FIG. 6E.
FIGS. 8A and 8B are cross-sectional views of each main process for explaining the manufacturing method of the LED module according to an embodiment of the present invention, and FIG. 9 is a plan view showing the LED module of FIG. 8B.
Figure 10 is a plan view showing an LED module according to an embodiment of the present invention.
Figures 11A to 11F are cross-sectional views for each major process to explain some processes in the method of manufacturing a display device according to an embodiment of the present invention.
Figures 12A to 12D are cross-sectional views for each major process to explain some processes in the method of manufacturing a display device according to an embodiment of the present invention.
Figure 13 is a schematic cross-sectional view of a display device according to an embodiment of the present invention.
14A and 14B are schematic cross-sectional views of a display device according to various embodiments of the present invention.
Figures 15A to 15F are cross-sectional views for each main process to explain some processes in the method of manufacturing a display device according to an embodiment of the present invention.
Figures 16A to 16D are cross-sectional views for each major process to explain some other processes in the method of manufacturing a display device according to an embodiment of the present invention.
Figure 17 is a conceptual diagram of an electronic device including a display device according to an embodiment of the present invention.

Hereinafter, various embodiments of the present disclosure will be described in detail with reference to the attached drawings.

Unless otherwise specified, in this specification, terms such as 'top', 'top surface', 'bottom', 'bottom surface', 'side', etc. are based on the drawings, and in reality, they depend on the direction in which the elements are arranged. It may change.

FIG. 1 is a schematic perspective view of a display device according to an embodiment of the present invention, and FIG. 2 is a schematic plan view of a display device according to an embodiment of the present invention.

Referring to FIGS. 1 and 2 , the display device 10 according to this embodiment is disposed on a circuit board 200 and a circuit board 200 including driving circuits and a plurality of pixels PX are arranged. It includes a pixel array 100. The display device 10 may further include a frame 11 surrounding the circuit board 200 and the pixel array 100.

The circuit board 200 may include a driving circuit including thin film transistor (TFT) cells. In some embodiments, the circuit board 200 may additionally include other circuits in addition to driving circuits for the display device. In some embodiments, the circuit board 200 includes a flexible board, and the display device 10 may be implemented as a display device with a curved profile.

The pixel array 100 may include a display area DA and a peripheral area PA on at least one side of the display area DA. The display area DA may include an LED module for display. The pixel array 100 may include a display area DA where a plurality of pixels PX are arranged. The peripheral area (PA) may include pad areas (PAD), a connection area (CR) connecting the plurality of pixels (PX) and the pad areas (PAD), and an outer area (ISO).

Each of the plurality of pixels (PX) includes first to third sub-pixels (SP1, SP2, SP3) configured to emit light of a specific wavelength, for example, a specific color, in order to provide a color image. can do. For example, the first to third subpixels SP1, SP2, and SP3 may be configured to emit blue (B) light, green (G) light, and red (R) light, respectively. The pixel array 100 of this embodiment is an LED module (see FIGS. 4A and 4B) that directly emits blue (B) light, green (G) light, and red (R) light without using an additional wavelength converter. It can be included.

As shown in FIG. 2, in each pixel PX (or pixel unit), the first to third subpixels SP1, SP2, and SP3 have a pattern arranged side by side in one direction (e.g., X direction). You can have It is not limited to this, and in some embodiments, the first to third subpixels SP1, SP2, and SP3 may be arranged in another pattern such as a Bayer pattern (eg, see FIG. 10). In other embodiments, each pixel PX may be configured in a different arrangement, such as 3×3 or 4×4.

In the pixel array 100 of FIG. 1, the plurality of pixels (PX) are illustrated as arranged in a 15 × 15 format, but the rows and columns can be any appropriate number, for example, 1,024 × 768. It can be implemented as follows. For example, depending on the desired resolution, the plurality of pixels PX may have different arrangements.

The pad areas PAD may be disposed on at least one side of the plurality of pixels PX along the edge of the display device 10 . The pad areas PAD may be electrically connected to the plurality of pixels PX and driving circuits of the circuit board 200. The pad areas (PAD) may electrically connect the display device 10 to an external device. In some embodiments, the number of pad areas PAD may vary and may be determined, for example, depending on the number of pixels PX, a driving method of the TFT circuit in the circuit board 200, etc.

The connection area CR may be an area located between the plurality of pixels PX and the pad areas PAD. A wiring structure, such as a common electrode, that is electrically connected to the plurality of pixels PX may be disposed in the connection region CR. The outer area (ISO) may be an area along the edges of the pixel array 100. The outer area (ISO) may be an area where the upper semiconductor layer 111 is not disposed (see FIG. 3).

The frame 11 may be arranged around the pixel array 100 and serve as a guide for defining the arrangement space of the pixel array 100. Frame 11 may include at least one of materials such as polymer, ceramic, semiconductor, or metal, for example. For example, the frame 11 may include a black matrix. However, the frame 11 is not limited to a black matrix, and may include a white matrix or a structure of another color depending on the purpose of the display device 10. For example, the white matrix may include reflective or scattering materials. The display device 10 in FIG. 1 is illustrated as having a rectangular planar structure, but may have a different shape depending on the embodiments.

FIG. 3 is a schematic cross-section of a display device according to an embodiment of the present invention, showing a combination of the cross-section (peripheral area (PA)) along I-I' of FIG. 1 and the cross-section along II-II of FIG. 2 (display It can be understood as an area (DA)).

Referring to FIG. 3, the display device 10 according to this embodiment includes a circuit board 200 and a pixel array 100 disposed on the circuit board 200.

The circuit board 200 includes a semiconductor substrate 201, a driving circuit including driving elements 220 including TFT cells formed on the semiconductor substrate 201, and an interconnector electrically connected to the driving elements 220. may include wires 230, wiring layers 240 on the interconnections 230, and a second wiring insulating layer 290 covering the driving circuit. In this embodiment, the circuit board 200 includes a second wiring insulating layer 295 on the circuit insulating layer 290, and a second bonding layer disposed within the second wiring insulating layer 295 and connected to the wiring layers 240. It may further include electrodes 298.

The pixel array 100 includes a display area in which a plurality of pixels (PX) are arranged, and each of the plurality of pixels (PX) includes first to third subpixels (e.g., see FIG. 2) arranged in a certain pattern (e.g., see FIG. 2). SP1, SP2, SP3) may be included.

The pixel array 100 may include an LED module implemented as a semiconductor stack 110. The LED module employed in this embodiment may include first to third LED cells (LC1, LC2, LC3) for the first to third subpixels (SP1, SP2, and SP3) without a wavelength converter. The first to third LED cells LC1, LC2, and LC3 are each micro LED and may be configured to emit light of different wavelengths. Specifically, the LED module may include first to third LED cells LC1, LC2, and LC3 that directly emit blue (B) light, green (G) light, and red (R) light.

FIG. 4A is an enlarged cross-sectional view of the “B” portion (LED module) of the display device according to an embodiment of the present invention, and FIG. 4B is a plan view of FIG. 5A viewed in the “T” direction, corresponding to one pixel. This is a floor plan of the LED module.

The semiconductor laminate 110 employed in this embodiment includes a first conductive semiconductor base layer 111B having a first surface facing the circuit board 200 and a second surface located opposite to the circuit board 200, and a first conductive semiconductor base layer 111B. It may include first to third LED cells LC1, LC2, and LC3 disposed on the first surface of the semiconductor base layer 111B.

The first to third LED cells LC1, LC2, and LC3 constituting each pixel PX are arranged at the same pitch (P1=P2). Here, the pitch can be defined as the spacing between the centers of adjacent LED cells. In some embodiments, the pitch P3 of the LED cell of another adjacent pixel PX may be the same as the other pitches P1 and P2. In this embodiment, the first to third LED cells LC1, LC2, and LC3 may each have the same width (W1=W2=W3) (or area) and the same spacing (d1=d2). Additionally, the distance d3 from the LED cell of another adjacent pixel PX may be the same as the other distances d1 and d2. It is not limited to this, and in some embodiments, the width or spacing of the first to third LED cells LC1, LC2, and LC3 may be different from each other. For example, considering the efficiency depending on the wavelength of light, the width (or area) of the LED cell with relatively low efficiency can be made large, and the gap between the adjacent LED cells can be relatively narrow (Figures 8b and 9).

In this embodiment, a partition structure 111P is disposed on the second side of the first conductive semiconductor base layer 111B. For example, the barrier structure 111P may be a structure obtained by etching the semiconductor layer 111 (also referred to as 'under semiconductor layer') integrated with the first conductive semiconductor base layer 111B (see FIG. 16B). . This semiconductor layer 111 may be a first conductivity type semiconductor layer or an undoped semiconductor layer, or may include a stack of a first conductivity type semiconductor layer and an undoped semiconductor layer. It is not limited thereto, and in some embodiments, the partition structure may include a separate structure formed of a different material (eg, a light blocking material or a reflective material) (see FIG. 13).

The first to third LED cells LC1, LC2, and LC3 employed in this embodiment may include a nitride single crystal stack grown in the same growth process. Since the nitride single crystal stack is formed by the same growth process, each layer can correspond to each other. As shown in FIG. 4A, the nitride single crystal laminate includes a first conductive semiconductor cap layer 112 and active layers 114a and 114b sequentially stacked on the first side of the first conductive semiconductor base layer 111B. , 114c), and a second conductive semiconductor layer 116.

The first conductive semiconductor base layer 111B and the first conductive semiconductor cap layer 112 are each n-type In _x Al _y Ga _1-xy N (0≤x<1, 0≤y<1, 0≤x+ It may be a nitride semiconductor layer having a composition of y<1). For example, the first conductive semiconductor cap layer 112 may be an n-type gallium nitride (n-GaN) layer doped with silicon (Si), germanium (Ge), or carbon (C). The second conductive semiconductor layer 116 may be a nitride semiconductor layer having a composition of p-type In _x Al _y Ga _1-xy N (0≤x<1, 0≤y<1, 0≤x+y<1). . For example, the second conductive semiconductor layer 116 may be a p-type gallium nitride (p-GaN) layer doped with magnesium (Mg) or zinc (Zn). Each of the first conductive semiconductor cap layer 112 and the second conductive semiconductor layer 116 may be composed of a single layer, but may also include a plurality of layers having different characteristics such as doping concentration and composition.

The first to third active layers 114a, 114b, and 114c may emit light with a predetermined energy by recombination of electrons and holes. The first to third LED cells LC1, LC2, and LC3 employed in this embodiment include first to third active layers 114a, 114b, and 114c configured to emit light of different wavelengths, respectively. The active layer 114 may have a single (SQW) or multiple quantum well (MQW) structure in which quantum barrier layers and quantum well layers are alternately arranged.

In this embodiment, the first to third active layers 114a, 114b, and 114c are formed simultaneously through the same growth process, so they may also include corresponding layers. For example, the first to third active layers 114a, 114b, and 114c may include the same number of quantum barrier layers and quantum well layers.

The first active layer 114a may include a first quantum well layer configured to emit blue light, for example, light with a wavelength of 440 nm to 480 nm. The second active layer 114b may include a second quantum well layer configured to emit green light, for example, light with a wavelength of 510 nm to 550 nm. Additionally, the third active layer 114c may include a third quantum well layer configured to emit red light, for example, light with a wavelength of 610 nm to 650 nm.

The first to third quantum well layers may include In _x Ga _1-x N (0<x≤1) layers having different indium contents (x). For example, the indium content of the first quantum well layer may range from 0.15 to 0.2, the indium content of the second quantum well layer may range from 0.25 to 0.3, and the indium content of the third quantum well layer may range from 0.3 to 0.35. . For example, the quantum barrier layer may be GaN or AlGaN.

As described above, the first to third quantum well layers are formed simultaneously in the same growth process, but the difference in indium content is reduced by adjusting the area of the growth region for the first to third LED cells (LC1, LC2, LC3). and, as a result, the first to third LED cells LC1, LC2, and LC3 can be configured to emit light of different wavelengths (see FIGS. 6A to 6C).

In some embodiments, the thickness t1 of the first active layer 114a is greater than the thickness t2 of the second active layer 114b, and the thickness t2 of the second active layer 114b is greater than the thickness t2 of the third active layer 114c. It may be larger than the thickness (t3) of. Specifically, the thickness of the first quantum well layer may be greater than the thickness of the second quantum well layer, and the thickness of the second quantum well layer may be greater than the thickness of the third quantum well layer. For example, the thickness of the first quantum well layer is in the range of 2.5 nm to 4 nm, the thickness of the second quantum well layer is in the range of 2.5 nm to 3.5 nm, and the thickness of the third quantum well layer is in the range of 2 nm to 3 nm. It can be.

The first to third LED cells (LC1, LC2, LC3) employed in this embodiment are nitride cells having a top surface that is a (0001) plane and a side surface that is substantially perpendicular to the first surface of the first conductive semiconductor base layer (111B). It may include a single crystal stack (112, 114, 116). For example, the top surface of the second conductive semiconductor layer 116 may be a (0001) plane. The sides of the nitride single crystal stacks 112, 114, and 116 may have substantially vertical sides obtained by removing edge regions causing leakage current through an etching process (see FIGS. 6E and 6F). For example, the angle of the side surfaces 112, 114, and 116 of the nitride single crystal stack may be in the range of 85° to 95°.

In this embodiment, the partition structure 111P that separates the subpixels SP1, SP2, and SP3 is composed of a semiconductor layer 111 with light transparency, thereby preventing optical interference between the subpixels SP1, SP2, and SP3. To prevent this, a partition reflective layer 170 may be introduced on the surface.

The partition wall reflective layer 170 employed in this embodiment may be formed on the top surface and side walls of the partition wall structure 111P. The barrier rib reflective layer 170 employed in this embodiment may include a first barrier rib insulating film 172, a reflective metal film 174, and a second barrier rib insulating film 176 that are sequentially stacked. The first barrier rib insulating layer 172 and the second barrier rib insulating layer 176 may include at least one of an insulating material, for example, SiO ₂ , SiN, SiCN, SiOC, SiON, and SiOCN. The reflective metal film 174 may include at least one of reflective metals, such as silver (Ag), nickel (Ni), and aluminum (Al). The reflective metal film 174 is formed on the inner sidewalls of the plurality of subpixel spaces, but is not formed on the bottom surfaces thereof. Through this arrangement, light emitted from each LED cell LC1, LC2, and LC3 can be emitted from the bottom surface of the plurality of subpixel spaces. A transparent resin portion 160 may be formed in each of the subpixel spaces surrounded by the partition reflective layer 170. In this embodiment, the transparent resin portion 160 may not contain wavelength conversion materials such as phosphors and/or quantum dots, and each subpixel (SP1) is directly connected to the first to third LED cells (LC1, LC2, LC3). , SP2, SP3), light of the required wavelength (e.g., R, G, B) can be emitted. In some embodiments, the transparent resin portion 160 may further include a light scattering material.

As shown in FIG. 3, the first conductive semiconductor base layer 111B is a common layer shared by the first to third LED cells LC1, LC2, and LC3 of all pixels PX. can be provided. The thickness T1 of the first conductive semiconductor base layer 111B may be, for example, about 0.1 ㎛ or more. In some embodiments, the thickness T1 of the first conductive semiconductor base layer 111B may range from about 0.1 μm to about 1.0 μm. The first conductive semiconductor base layer 111B may be disposed to extend from the display area DA to the connection area CR and the pad areas PAD, that is, a portion of the peripheral area PA. The first conductive semiconductor base layer 111B may be provided as an area for forming a common electrode for all or part of the first to third LED cells LC1, LC2, and LC3 (e.g., the same row or column). there is.

Referring to FIGS. 3 and 4A, the passivation layer 120 covers the side and top surfaces of the first to third LED cells LC1, LC2, and LC3 and the first surface of the first conductive semiconductor base layer 111B. It can be formed as follows. On the first side of the first conductive semiconductor base layer 111B, the passivation layer 120 may extend into the peripheral area PA. The passivation layer 120 may be disposed to cover the lower surface of the first conductive semiconductor layer 112 in the connection region CR and pad regions PAD, that is, in the peripheral area PA. The passivation layer 120 may include at least one of an insulating material, for example, SiO ₂ , SiN, SiCN, SiOC, SiON, SiOCN, SiOCN, HfO _x , AlO _x , ZrO _x , and AlN.

The first electrode 130 may be connected to the first conductive semiconductor base layer 111B. Specifically, the first electrode 130 may be disposed to be electrically insulated from the first to third LED cells LC1, LC2, and LC3 by the passivation layer 120. The first electrode 130 may extend into the peripheral area (PA). The first electrode 130 extending to the peripheral area PA may be connected in areas between adjacent first to third LED cells LC1, LC2, and LC3 and arranged as a single layer. The first electrode 130 may include a reflective metal material. For example, the first electrode 130 is made of silver (Ag), nickel (Ni), aluminum (Al), chromium (Cr), rhodium (Rh), iridium (Ir), palladium (Pd), and ruthenium (Ru). , magnesium (Mg), zinc (Zn), platinum (Pt), gold (Au), copper (Cu), titanium (Ti), tantalum (Ta), and tungsten (W). In some embodiments, the first electrode 130 may include a compound thereof such as TaN, TiN, or a transparent electrode material such as ITO, IZO, or GAZO. It may include at least one of: In some embodiments, the first electrode 130 may include a single-layer or multi-layer structure of a conductive material.

The first electrode 130 may be provided as a reflective electrode (also referred to as “first reflective electrode”). For example, the first electrode 130 may have an inverted U-shaped cross section between adjacent LED cells LC1, LC2, and LC3. The first electrode 130 is a grid including lines extending in the ) or may have a mesh shape. Ends of the first electrode 130 may be connected to the common electrode 145. As shown in FIG. 3 , the outermost portions of the first electrode 130 may be connected to the common electrode 145 .

In some embodiments, the first electrode 130 extends to the peripheral area PA, that is, the connection area CR, located outside the pixels PX, and is connected to the first conductive semiconductor base layer 111B. , may be physically and electrically connected to the common electrode 145. As in this embodiment, the first electrode 130 may be electrically connected to the first conductive semiconductor base layer 111B in the area between adjacent LED cells LC1, LC2, and LC3.

The contact layers 155 and the second electrodes 150 may be sequentially disposed on the lower surfaces of the second conductive semiconductor layers 116 and connected to the second conductive semiconductor layers 116 . In this embodiment, the contact layers 155 may be arranged to cover almost the entire lower surface of the second conductive semiconductor layer 116. The second electrodes 150 may include a reflective metal material similar to the first electrode 130 . For example, the second electrode 150 is made of silver (Ag), nickel (Ni), aluminum (Al), chromium (Cr), rhodium (Rh), iridium (Ir), palladium (Pd), and ruthenium (Ru). , magnesium (Mg), zinc (Zn), platinum (Pt), and gold (Au), copper (Cu), titanium (Ti), tantalum (Ta), and tungsten (W). In some embodiments, the second electrode 150 may include a compound thereof such as TaN, TiN, or a transparent electrode material such as ITO, IZO, or GAZO. In some embodiments, the second electrode 150 may include a single-layer or multi-layer structure of a conductive material.

The second electrode 150 (also referred to as “second reflective electrode”), which is a reflective electrode, may be disposed under each LED cell 110 to overlap the LED cells 110 along the Z direction. The second electrode 150 may be disposed below the contact layer 155 and connected to the contact layer 155 . The length of the second electrode 150 along the In some embodiments, the second electrodes 150 may be omitted, in which case the contact layers 155 may be directly connected to the first bonding electrodes 198 below.

The contact layers 155 and the second electrodes 150 may include a highly reflective metal, for example, silver (Ag), nickel (Ni), aluminum (Al), or chromium (Cr). ), rhodium (Rh), iridium (Ir), palladium (Pd), ruthenium (Ru), magnesium (Mg), zinc (Zn), platinum (Pt), and gold (Au). .

The pixel array 100 employed in this embodiment includes a planarization layer 182, a first pad electrode 147, and a partition wall structure 111P filled with the transparent resin portion 160 and a semiconductor layer 111. 1 may further include a wiring insulating layer 195, a first bonding insulating layer 190, first bonding electrodes 198, and a second pad electrode 199.

As described above, the semiconductor layer 111 may include an area integrated with the first conductivity type semiconductor layer 111B or a continuous area. As shown in FIG. 3, the semiconductor layer 111 in the peripheral area (PA) may have a layer structure other than the partition structure 111P, and the common electrode 145 may have a layer structure other than the partition structure 111P, and the common electrode 145 may have a layer structure other than the partition structure 111P. ) can be extended over the area. Additionally, a through hole OP may be formed in the peripheral area PA, particularly in the pad areas PAD, where a portion of the semiconductor layer 111 is removed.

The planarization layer 182 may be a transparent layer formed on the semiconductor layer 111 and the partition wall structure 111P filled with the transparent resin portion 160. In addition, the micro lenses 185 are arranged to correspond to the first to third subpixels SP1, SP2, and SP3 on the planarization layer 182, and are connected to the first to third LED cells LC1, LC2, and LC3. The emitted light can be condensed. For example, the micro lenses 185 may have a diameter larger than the width of the LED cells LC1, LC2, and LC3 in the X and Y directions. The micro lenses 185 may be formed of, for example, a transparent photoresist material or a transparent thermosetting resin film.

The common electrode 145 and the first pad electrode 147 may be disposed in the connection region CR and the pad regions PAD, respectively. The common electrode 145 may be disposed on the lower surface of the first reflective electrode 130 extending from the pixel PX to connect the first reflective electrode 130 to the first bonding electrode 198. The common electrode 145 and the first reflective electrode 130 may form a common electrode structure. The common electrode 145 may be arranged in a square ring shape or a ring shape to surround the entire pixels PX in a plan view, and may be connected to ends of the first reflective electrode 130. However, the arrangement of the common electrode 145 is not limited to this and may vary in various embodiments. The first pad electrode 147 may be disposed below the second pad electrode 199 in the pad areas PAD to connect the second pad electrode 199 and the first bonding electrode 198. The common electrode 145 and the first pad electrode 147 are made of a conductive material, such as silver (Ag), nickel (Ni), aluminum (Al), chromium (Cr), rhodium (Rh), and iridium (Ir). , palladium (Pd), ruthenium (Ru), magnesium (Mg), zinc (Zn), platinum (Pt), and gold (Au).

The first bonding electrodes 198 may connect the second reflective electrodes 150, the common electrode 145, and the first pad electrode 147 with the second bonding electrodes 298 of the circuit board 200. there is. The first bonding electrodes 198 are connected to the second electrodes 150 below the second electrodes 150 in the pixel PX, and are connected to the common electrode 145 in the connection region CR. The pad areas PAD may be connected to the first pad electrode 147. In this specification, the bonding electrodes located on the common electrode 145 and the first pad electrode 147 among the first bonding electrodes 198 are respectively referred to as “third bonding electrode” and “fourth bonding electrode”. can do. The first electrode 130 may be connected to the first bonding electrodes 198 through the common electrode 145, and the second electrodes 150 may be directly connected to the first bonding electrodes 198.

The first bonding electrodes 198 may be disposed to penetrate the first wire insulating layer 195 and the second bonding insulating layer 290. The first bonding electrodes 198 may have a pillar shape, such as a cylinder. In some embodiments, the first bonding electrodes 198 may have inclined sidewalls so that the upper surface is smaller than the lower surface. The first bonding electrodes 198 may include copper (Cu), for example. The first bonding electrodes 198 may further include a barrier metal layer, for example, a tantalum (Ta) layer and/or a tantalum nitride (TaN) layer on the top surface and side surfaces. For example, the first bonding insulating layer 190 may include at least one of SiO ₂ , SiN, SiCN, SiOC, SiON, SiCN, and SiOCN.

The first wire insulating layer 195 may be disposed under the LED cells LC1, LC2, and LC3 and the semiconductor layer 111 along with the first bonding insulating layer 190. For example, the first wire insulating layer 195 may include at least one of SiO ₂ , SiN, SiCN, and SiON. In some embodiments, the first wiring insulating layer 195 is made of TetraEthyl Ortho Silicate (TEOS), Undoped Silicate Glass (USG), PhosphoSilicate Glass (PSG), Borosilicate Glass (BSG), BoroPhosphoSilicate Glass (BPSG), and Fluoride Silicate (FSG). Glass), SOG (Spin On Glass), TOSZ (Tonen SilaZene), or a combination thereof.

The semiconductor substrate 201 may include impurity regions including source/drain regions 205 . The semiconductor substrate 201 may include, for example, a semiconductor such as silicon (Si) or germanium (Ge), or a compound semiconductor such as SiGe, SiC, GaAs, InAs, or InP. The semiconductor substrate 201 may further include through electrodes 250 such as through silicon via (TSV) connected to the driving circuit, and first and second substrate wiring lines 261 and 262 connected to the through electrodes 250. You can.

The driving circuit may include a circuit for controlling driving of pixels, particularly sub-pixels. The source region 205 of the TFT cells may be electrically connected to one electrode of the LED cells 110 through the interconnection portion 230, the wiring layer 240, and the first bonding electrode 298. For example, the drain region 205 of the TFT cells may be connected to the first wiring line 261 through the through electrode 250, and the first wiring line 261 may be connected to the data line. Gate electrodes of the TFT cells may be connected to the second wiring line 262 through the through electrode 250, and the second wiring line 262 may be connected to the gate line. This circuit configuration and operation will be described in more detail with reference to FIG. 5 below.

The top surfaces of the second bonding electrodes 298 and the top surfaces of the second bonding insulating layer 290 may form the top surface of the circuit board 200 . The second bonding electrodes 298 may be bonded to the first bonding electrodes 198 of the pixel array 100 to provide an electrical connection path. The second bonding electrodes 298 may include a conductive material, for example, copper (Cu). The second bonding insulating layer 290 may be bonded to the first bonding insulating layer 190 of the pixel array 100. For example, the second bonding insulating layer 290 may include at least one of SiO ₂ , SiN, SiCN, SiOC, SiON, SiCN, and SiOCN.

The lower surfaces of the second bonding insulating layer 290 may be arranged to form the lower surface of the pixel array 100 together with the lower surfaces of the second bonding electrodes 198 . The second bonding insulating layer 290 may form dielectric-dielectric bonding with the first bonding insulating layer 190. The circuit board 200 and the pixel array 100 include bonding of the first bonding electrodes 198 and the second bonding electrodes 298 and the first bonding insulating layer 190 and the second bonding insulating layer 290. It can be bonded by joining. The bonding of the first bonding electrodes 198 and the second bonding electrodes 298 may be, for example, copper (Cu)-copper (Cu) bonding, and the first bonding insulating layer 190 and the second bonding may be formed. Bonding of the insulating layer 290 may be, for example, dielectric-dielectric bonding, such as SiCN-SiCN bonding. The circuit board 200 and the pixel array 100 may be bonded by hybrid bonding including copper (Cu)-copper (Cu) bonding and dielectric-dielectric bonding, and can be bonded without a separate adhesive layer.

The display device 10 according to this embodiment is miniaturized by optimizing the arrangement of the electrode structure including the first electrode 130 and bonding the circuit board 200 and the pixel array 100 using hybrid bonding. High-resolution devices can be implemented.

The second pad electrode 199 may be disposed on the first pad electrode 147 in the pad areas PAD. The second pad electrode 199 may be disposed so that at least its upper surface is exposed upward by a penetrating structure (OP) that penetrates the semiconductor layer 111 and the first conductivity type semiconductor layer 112. The second pad electrode 199 may be connected to an external device, such as an external circuit (External IC) that can apply an electrical signal to the circuit board 200, by wire bonding or anisotropic conductive film (AFC) bonding. You can. The second pad electrode 199 may electrically connect the driving circuits of the circuit board 200 and the external device. The second pad electrode 199 may include a metal, such as gold (Au), silver (Ag), or nickel (Ni).

Figure 5 is a driving circuit implemented in a display device according to an embodiment of the present invention.

Referring to FIG. 5, a circuit diagram of a display device 10 in which n×n subpixels are arranged is illustrated. The first to third subpixels SP1, SP2, and SP3 may each receive data signals through data lines D1-Dn, which are vertical paths, for example, column directions. The first to third subpixels SP1, SP2, and SP3 may receive a control signal, that is, a gate signal, through the gate lines G1-Gn, which are horizontal paths, for example, in the row direction.

A plurality of pixels (PX) including the first to third sub-pixels (SP1, SP2, SP3) provide a display area (DA), and this display area (DA) serves as an active area and is a display area for the user. provided. The inactive area (NA) (or peripheral area (PA)) may be formed along one or more edges of the display area (DA). The non-active area (NA) may extend along the outer periphery of the panel of the display device 10.

The first and second driver circuits 12 and 13 may be employed to control the operation of the pixels PX, that is, the first to third subpixels SP1, SP2, and SP3. Some or all of the first and second driver circuits 12 and 13 may be implemented on the circuit board 200. The first and second driver circuits 12 and 13 may be formed of integrated circuits, thin film transistor panel circuits, or other suitable circuits, and may be disposed in the non-active area (NA) of the display device 10. The first and second driver circuits 12 and 13 may include a microprocessor, memory such as storage, processing circuitry, and communication circuitry.

In order to display an image by pixels PX, the first driver circuit 12 supplies image data to the data lines D1-Dn and provides a clock signal to the second driver circuit 13, which is a gate driver circuit. and other control signals. The second driver circuit 13 may be implemented using an integrated circuit and/or a thin film transistor circuit. A gate signal for controlling the first to third subpixels SP1, SP2, and SP3 arranged in the row direction may be transmitted through the gate lines G1-Gn of the display device 10.

FIGS. 6A to 6F are cross-sectional views of each main process for explaining the manufacturing method of the LED module according to an embodiment of the present invention, and FIG. 7 is a plan view showing the LED module of FIG. 6F.

The method of manufacturing an LED module according to this embodiment can be understood as a process of manufacturing an LED module (see FIGS. 4A and 4B) corresponding to one pixel in a pixel array of a display.

Referring to FIG. 6A, an under semiconductor layer 111 may be formed on the growth substrate 101, and a mask pattern 105 may be formed on the under semiconductor layer 111.

The upper region of the under semiconductor layer 111 used in this embodiment may include a first conductivity type semiconductor base layer 111B. In some embodiments, the lower region of the under semiconductor layer 111 may be a first conductivity type semiconductor layer or an undoped semiconductor layer, or may include a stack of a first conductivity type semiconductor layer and an undoped semiconductor layer.

The mask pattern 105 has first to third openings O1, O2, and O3 that open regions of the first conductive semiconductor base layer 111B. Regions of the first conductive semiconductor base layer 111B may be provided as regions for forming each of the first to third LED cells. The first opening (O1), the second opening (O2), and the third opening (O3) are arranged at the same pitch (P1=P2). Here, each pitch (P1, P2) may be defined as the distance between the centers of adjacent openings.

Additionally, in this embodiment, the first to third openings O1, O2, and O3 have different widths W1', W2', and W3'. Specifically, the width W'1 of the first opening O1 is greater than the width W2' of the second opening O2, and the width W2' of the second opening O2 is greater than the width W2' of the second opening O2. 3 It is larger than the width W3' of the opening O3. Due to the conditions of the same pitch and different width, the pattern spacing (d1≠d2≠d3) of each opening (O1, O2, O3) may be different.

In this way, since the areas of the growth regions provided by the first to third openings O1, O2, and O3 are different, the active layer ( That is, even if the quantum well layer) is grown simultaneously, active layers that emit light of different wavelengths can be formed.

Next, referring to FIG. 6B, the first conductivity type semiconductor cap layer 112 is formed on the regions of the first conductivity type semiconductor base layer 111B opened by the first to third openings O1, O2, and O3. ) can be formed.

The first conductivity type semiconductor cap layer 112 is n-type In _x Al _y Ga _1-xy N (0≤x<1, 0≤y<1, 0≤x+) similar to the first conductivity type semiconductor base layer (111B). It may be a nitride single crystal with a composition of y<1). For example, the first conductive semiconductor base layer 111B and the first conductive semiconductor cap layer 112 are made of n-type gallium nitride (n-) doped with silicon (Si), germanium (Ge), or carbon (C). It may be a GaN) layer. This process can be omitted, but can be added to grow the active layers to be grown in the subsequent process on a high-quality crystal surface. In some embodiments, the first conductive semiconductor cap layer 112 may be grown as a nitride single crystal having a c-plane, that is, a (0001) plane, and an edge region adjacent to the mask pattern 105 may have an inclined side. You can.

Next, referring to FIG. 6C, active layers 114a, 114b, and 114c are formed on the first conductive semiconductor cap layer 112, and second conductive layers are formed on each of the active layers 114a, 114b, and 114c. Semiconductor layers 116 are grown.

The growth process in each opening (O1, O2, O3) can be performed simultaneously using a single growth process. Through this process, first to third light emitting laminates LC1', LC2', and LC3' may be formed in the first to third openings O1, O2, and O3, respectively.

As described above, even if grown through the same process, due to the difference in area of the openings O1, O2, and O3, the first to third light emitting laminates LC1', LC2', and LC3' each have different wavelengths. It may have first to third active layers 114a, 114b, and 114c that emit light. The first active layer 114a may include a first quantum well layer configured to emit blue light, for example, light with a wavelength of 440 nm to 480 nm. The second active layer 114b may include a second quantum well layer configured to emit green light, for example, light with a wavelength of 510 nm to 550 nm. Additionally, the third active layer 114c may include a third quantum well layer configured to emit red light, for example, light with a wavelength of 610 nm to 650 nm.

Specifically, the first to third active layers 114a, 114b, and 114c may have first to third quantum well layers expressed as In _x Ga _1-x N (0<x≤1). The first to third quantum well layers may have different indium contents (x). For example, the indium content of the first quantum well layer may range from 0.15 to 0.2, the indium content of the second quantum well layer may range from 0.25 to 0.3, and the indium content of the third quantum well layer may range from 0.3 to 0.35. .

In some embodiments, the thickness of the first active layer 114a may be greater than the thickness of the second active layer 114b, and the thickness of the second active layer 114b may be greater than the thickness of the third active layer 114c. Specifically, the thickness of the first quantum well layer may be greater than the thickness of the second quantum well layer, and the thickness of the second quantum well layer may be greater than the thickness of the third quantum well layer.

In this way, the first to third quantum well layers are formed simultaneously in the same growth process, but a difference in indium content is induced by adjusting the area of the growth region for the first to third LED cells (LC1, LC2, LC3). As a result, the first to third light emitting laminates LC1', LC2', and LC3' may be configured to emit light of different wavelengths.

The first to third active layers 114a, 114b, and 114c may have a single (SQW) or multiple quantum well (MQW) structure in which quantum barrier layers and quantum well layers are alternately arranged. For example, the quantum barrier layer may be GaN or AlGaN. Since the first to third active layers 114a, 114b, and 114c are formed simultaneously through the same growth process, they may include layers corresponding to each other. The first to third active layers 114a, 114b, and 114c may include the same number of quantum barrier layers and quantum well layers.

Subsequently, the second conductive semiconductor layers 116 may be simultaneously formed on the first to third active layers 114a, 114b, and 114c, respectively. The second conductive semiconductor layer 116 may be a nitride semiconductor layer having a composition of p-type In _x Al _y Ga _1-xy N (0≤x<1, 0≤y<1, 0≤x+y<1). . For example, the second conductive semiconductor layer 116 may be a p-type gallium nitride (p-GaN) layer doped with magnesium (Mg) or zinc (Zn).

Next, referring to FIG. 6D, the mask pattern 105 can be removed from the first conductive semiconductor base layer 111B.

After removing the mask pattern 105, the first to third light emitting stacks LC1', LC2', and LC3' may remain on the first conductive semiconductor base layer 111B. As previously described, the first to third light-emitting stacks LC1', LC2', and LC3' include a nitride single crystal having a (0001) upper surface, and edge regions DL1, DL2, and slanted side surfaces. DL3) may be included. The edge regions DL1, DL2, and DL3 may be crystal damage regions that generate non-radiative recombination or leakage current. Therefore, a process to remove these edge areas is performed. Additionally, in this embodiment, the shape and size (or width) of the first to third light emitting laminates LC1', LC2', and LC3' remaining in the edge region removal process can be controlled.

The widths of the edge regions DL1, DL2, and DL3 to be removed can be set differently so that the remaining first to third light emitting laminates LC1, LC2, and LC3 have the same width (W1=W2, W3). . This edge region removal process may be performed by dry etching, wet etching, or a combination of dry/wet etching. As shown in FIG. 7 , from a plan view, the edge regions DL1, DL2, and DL3 to be removed may be positioned to surround the first to third light emitting stacks LC1, LC2, and LC3, respectively.

Next, referring to FIG. 6E, after removing the edge regions DL1, DL2, and DL3, the first to third light emitting laminates LC1, LC2, and LC3 having the same width (W1 = W2 = W3) are obtained. You can lose.

In this specification, the remaining first to third light emitting laminates are also referred to as first to third LED cells LC1, LC2, and LC3, respectively. The first to third LED cells LC1, LC2, and LC3 may serve as light sources for the first to third subpixels, respectively. The first to third LED cells LC1, LC2, and LC3 may be maintained at the same pitch (P1=P2). In this embodiment, the first to third LED cells LC1, LC2, and LC3 may have different spacings (d1>d2).

As described above, the first to third LED cells LC1, LC2, and LC3 may have a top surface that is a (0001) plane and a side surface that is substantially perpendicular to the top surface of the first conductive semiconductor base layer 111B. For example, the side angles of the first to third LED cells LC1, LC2, and LC3 may be in the range of 85° to 95°.

Next, the LED module 100A shown in FIG. 6E can be additionally processed to be manufactured into a pixel array substrate (see '100' in FIG. 3) for a display. The pixel array substrate manufacturing process may be performed by the processes of FIGS. 15A to 15E.

For example, the passivation layer 120 may be formed on the top surface of the first conductive semiconductor base layer 111B and the side and top surfaces of the first to third LED cells LC1, LC2, and LC3. Next, first electrodes 155, which are individual electrodes, are formed on the upper surfaces of the first to third LED cells LC1, LC2, and LC3 to be connected to the second conductive semiconductor layers 116, and the first electrodes 155 are formed as individual electrodes. A second electrode 130, which is a common electrode connected to the conductive semiconductor base layer 111B, can be formed.

In the process of removing the edge area of the light-emitting laminate, the shape and size of the LED cells can be controlled in various ways. As another example, the sizes (or widths) of the first to third LED cells may be set to vary. This embodiment is described with reference to FIGS. 8A, 8B, and 9.

FIGS. 8A and 8B are cross-sectional views of each main process for explaining the manufacturing method of the LED module according to an embodiment of the present invention, and FIG. 9 is a plan view showing the LED module of FIG. 8B.

Referring to FIG. 8A , first to third light emitting stacks LC1', LC2', and LC3 disposed on the under semiconductor layer 111 are shown. The first to third light emitting laminates LC1', LC2', and LC3' may be understood as results obtained after performing the processes of FIGS. 6A and 6B of the previous embodiment.

As previously described, the first to third light emitting stacks LC1', LC2', and LC3' include a nitride single crystal having an upper surface that is a (0001) plane, and include an edge region DL having an inclined side surface. can do. In this embodiment, after removing the edge region DL, the first to third light emitting laminates, that is, the first to third LED cells LC1, LC2, and LC3, have different widths (Wa>Wb>Wc). You can have For example, considering the efficiency depending on the wavelength of light, the width (or area) of the LED cell with relatively low efficiency can be formed to be large.

In this embodiment, the width (Wa) of the first LED cell (LC1) for blue light is greater than the width (Wb) of the second LED cell (LC2) for green light, and the width of the second LED cell (LC2) is (Wb) may be larger than the width (Wc) of the third LED cell LC3 for red light. The spacing (da=db) of adjacent LED cells may be the same or different, but the first to third LED cells (LC1, LC2, LC3) may still be arranged with the same pitch (P1=P2).

In some embodiments, as shown in FIG. 9, the edge area DL surrounding each of the first to third LED cells LC1, LC2, and LC3 in plan view has a sufficient width so that the damaged area can be removed. (Wd) can be eliminated. The width (Wd) of the edge area DL removed from the first to third LED cells LC1, LC2, and LC3 may be substantially the same.

As such, the LED module 100B manufactured in this embodiment includes first to third LED cells arranged at the same pitch (P1=P2) and having different widths (Wa≠Wb≠Wc) and spacing (da≠db). It may include (LC1, LC2, LC3).

The LED modules 100A and 100B corresponding to one pixel are illustrated as including first to third LED cells arranged in one direction, but may vary depending on the arrangement of subpixels. For example, the LED module 100C shown in Figure 10 has four LED cells (LC1, LC2a, LC2b, LC3) arranged at the same pitch (Pa = Pb = Pc), similar to a Bayer pattern (R-G-G-B). It includes four LED cells, a blue LED cell (L1) and a red LED cell (L3) arranged in a first diagonal line, and a first green LED cell (LC2a) and a second green LED cell (LC2a) arranged in a second diagonal line. LC2b). In FIG. 10 , the dotted lines represent the outer lines of the light emitting stacks before the openings or edge regions DL1, DL2, and DL3 of the mask pattern are removed. Four LED cells (LC1, LC2a, LC2b, LC3) can be formed in apertures with different widths. In this embodiment, the four LED cells (LC1, LC2a, LC2b, LC3) may have the same size (W1=W2=W3) after removing the edge area. It is not limited to this, and as explained in FIG. 9, the width of the edge regions (DL1, DL2, and DL3) to be removed can be adjusted to have different sizes depending on the wavelength of each LED cell (LC1, LC2a, LC2b, and LC3). You can.

In the above-described embodiments, only the form in which the first to third LED cells emitting light of different wavelengths, for example, blue, green, and red LED cells, are all simultaneously formed, but can be modified and implemented in various forms. It can be.

According to one embodiment, in one pixel unit, only the first and second LED cells that emit light of different colors are formed simultaneously, and the third LED cell that emits light of the remaining colors is formed in a separate process. (see FIGS. 11A to 11F). According to another embodiment, in one pixel unit, two LED cells that emit light of one color (e.g., blue) and one LED cell that emits light of a different color (e.g., green) are simultaneously formed. , the wavelength converter can be applied to one LED cell among the two LED cells (see FIGS. 12A to 12D).

Figures 11A to 11F are cross-sectional views for each main process to explain some processes in the method of manufacturing a display device according to an embodiment of the present invention.

Referring to FIG. 11A, an under semiconductor layer 111 having a first conductive semiconductor base layer 111B is formed on the growth substrate 101, and a first mask is applied on the first conductive semiconductor base layer 111B. A pattern 105a is formed.

The first mask pattern 105a has a first opening (O1) and a second opening (O2) having different widths (W1'≠W2'), and the first opening (O1) and the second opening (O2) are It may be arranged in a first pitch (P1). Here, the width W1' of the first opening O1 may be larger than the width W2' of the second opening O2. For example, the deviation of the widths W1' and W2' of the first and second openings O1 and O2 may be set so that active layers for blue and green are formed in the first and second openings, respectively, in the same process. You can. The first mask pattern 105a may have a portion 105a' that covers an area for forming a third LED cell in a subsequent process.

Next, referring to FIG. 11B, a first conductive semiconductor cap layer 112 is formed in each of the regions of the first conductive semiconductor base layer 111B opened by the first and second openings O1 and O2. , the first and second active layers 114a and 114b can be grown simultaneously.

The first and second active layers 114a and 114b may include first and second quantum well layers that emit first light (e.g., blue) and second light (green) of different wavelengths, respectively. . The indium content of the first quantum well layer may be in the range of 0.15 to 0.2, and the indium content of the second quantum well layer may be in the range of 0.25 to 0.3. The first quantum well layer may be configured to emit light with a wavelength of 440 nm to 480 nm, and the second quantum well layer may be configured to emit light with a wavelength of 510 nm to 550 nm. In some embodiments, the thickness t1 of the first active layer 114a is greater than the thickness t2 of the second active layer 114b, and the thickness t2 of the second active layer 114b is greater than the thickness t2 of the third active layer 114c. It may be larger than the thickness (t3) of.

Next, referring to FIG. 11C, it has a third opening (O3') that covers the first and second openings (O1, O2) and opens another area of the first conductive semiconductor base layer (111B). A second mask pattern 105b is formed.

This process may be performed by forming a dielectric layer for the second mask pattern 105b to cover the first and second openings O1 and O2 and opening the third opening O3'.

The third opening O3' is arranged as an adjacent opening among the first and second openings, that is, the second opening O2 and the second pitch P2, and the second pitch P2 is the first pitch P1. ) may be the same as The width W3 of the third opening O3 may be set arbitrarily. For process convenience, the width W3 of the third opening O3 may be substantially equal to the width W1 or W2 of the first or second openings O1 and O2.

Next, referring to FIG. 11D, a first conductive semiconductor cap layer 112' and a third active layer 114c are formed in another area of the first conductive semiconductor base layer 111B opened by the third opening O3'. ') is formed.

The first conductivity type semiconductor cap layer 112' of the third opening O3' may be the same nitride layer as the first conductivity type cap layer 112 of the other openings O1 and O2. The third active layer 114c' may include a third quantum well layer that emits third light (eg, red) with a wavelength different from the wavelength of the first and second lights. The third quantum well layer can emit light with a wavelength of 610 nm to 650 nm.

As such, in this embodiment, the third active layer 114c' may be formed by a growth process different from the growth process of the first and second active layers 114a and 114b. In some embodiments, the first and second active layers 114a and 114b are formed simultaneously and thus have different corresponding layer structures (the same number of quantum barrier layers and quantum well layers), but the third active layer 114c' is formed simultaneously. It may have a different layer structure from the first and second active layers 114a and 114b.

Next, referring to FIG. 11E, fourth and fifth openings O1' and O2' are formed in the second mask pattern 105b to open the first and second active layers 114a and 114b, respectively. , second conductive semiconductor layers 116 may be grown on the first to third active layers 114a, 114b, and 114c, respectively. As a result, the first to third light emitting laminates LC1', LC2', and LC3' arranged at the same pitch (P1=P2) can be formed.

Next, referring to FIG. 11F, the first and second mask patterns 105a and 105b are removed from the first conductive semiconductor base layer 111B, and the first to third light emitting laminates LC1' and LC2 are removed. ',LC3') Remove each edge area.

After removing the entire mask pattern 105, the first to third light emitting stacks LC1', LC2', and LC3' may remain on the first conductive semiconductor base layer 111B. As described above, the first to third light emitting stacks LC1', LC2', and LC3' may include damaged edge regions. In this embodiment, the first to third light emitting laminates LC1, LC2, and LC3 having the same width (W1=W2=W3) can be obtained after removing the edge regions DL1, DL2, and DL3. The first to third LED cells LC1, LC2, and LC3 may serve as light sources for the first to third subpixels, respectively. The first to third LED cells LC1, LC2, and LC3 may be maintained at the same pitch (P1=P2).

Figures 12A to 12D are cross-sectional views for each main process to explain some processes in the method of manufacturing a display device according to an embodiment of the present invention.

Referring to FIG. 12A, an under semiconductor layer 111 having a first conductivity type semiconductor base layer 111B is formed on a growth substrate 101, and a first conductivity type semiconductor base layer 111B is formed on the growth substrate 101. A mask pattern having through third openings O1, O2, and O1' may be formed.

The first to third openings (O1, O2, O1') are arranged at the same pitch (P1 = P2), and the width (W1) of the first opening (O1) is the width (W2) of the second opening (O2). ) may be large and may be equal to the width (W1') of the third opening (O1').

Next, referring to FIG. 12B, a first conductive semiconductor cap layer is formed in each of the regions of the first conductive semiconductor base layer 111B opened by the first to third openings O1, O2, and O1'. (112), the first to third active layers 114a, 114b, and 114a' and the second conductive semiconductor layers 116 may be grown.

First to third light emitting laminates LC1', LC2', and LC1' may be formed in the first to third openings O1, O2, and O1', respectively. Since the first and third active layers 114a and 114a' are formed in the openings O1 and O1' of the same width, the first and third quantum well layers emit light (e.g., blue light) of the same wavelength. may include. Since the second active layer 114b is formed in the relatively small width openings O2, it may include second quantum well layers that emit light of a relatively long wavelength (eg, green light). Each of the first and third quantum well layers may be configured to emit light with a wavelength of 440 nm to 480 nm, and the second quantum well layer may be configured to emit light with a wavelength of 510 nm to 550 nm.

Next, referring to FIG. 12C, the mask pattern 105 is removed from the first conductive semiconductor base layer 111B, and then, referring to FIG. 12D, the first to third light emitting laminates LC1', LC2', LC1') and remove each edge area (DL1, DL2, DL1).

After removing the mask pattern 105, two first light-emitting stacks LC1' and one second light-emitting stack LC2' between them remain on the first conductive semiconductor base layer 111B. can do. As described above, the first and third light emitting laminates LC1' and LC2' may each include damaged edge regions. In this embodiment, two first LED cells LC1 and one second LED cell LC2 having the same width (W1=W2=W3) can be obtained after removing the edge areas DL1 and DL2. . The three LED cells (LC1, LC2, LC1) are maintained at the same pitch (P1 = P2) and can each serve as a light source for the first to third subpixels.

The LED module 100E provided as one pixel includes first and second LED cells LC1, LC2, and LC1, where the two first LED cells LC1 display a first color (e.g., blue). The second LED cells LC2 may be configured to emit light of a second color (eg, green). In this embodiment, one of the two LED cells LC1 may form a wavelength converter (see '160R' in FIG. 13) that emits light of a third color (eg, red).

FIG. 13 is a schematic cross-sectional view of a display device according to an embodiment of the present invention, and can be understood as a cross-section corresponding to the cross-section corresponding to FIG. 3.

Referring to FIG. 13, the display device 10A according to the present embodiment is similar to that of FIGS. 3 and 3 except that the LED module obtained from the process of FIG. 12D is employed and the partition wall structure 170P is formed of a separate material. It can be understood as similar to the display device 10 shown in FIG. 4. Additionally, unless otherwise stated, the components of this embodiment may be understood by referring to the description of the same or similar components of the display device 10 shown in FIGS. 1 to 4.

In this embodiment, after polishing the under semiconductor layer to leave a partial region including the first conductive semiconductor base layer 111B, a partition structure 170P may be disposed on the polished surface of the remaining region. The partition wall structure 170P employed in this embodiment may include a separate structure formed of another material (eg, a light blocking material or a reflective material). For example, the partition wall structure 170P may include a reflective metal material. The partition wall structure 170P may provide a partition that prevents light interference between the subpixels SP1, SP2, and SP3, respectively.

The LED module 100E employed in the pixel array 100 employed in this embodiment can be manufactured from the processes of FIGS. 12A to 12D. The LED module 100E provided as one pixel may include two first LED cells LC1 and one second LED cell LC2. Here, one of the two first LED cells LC1 is configured to emit light of a first color (eg, blue), and the second LED cells LC2 are configured to emit light of a second color (eg, green). It can be. A transparent resin layer 160 may be disposed in each subpixel space corresponding to the first LED cell LC1 for blue and the second LED cells LC2 for green. In this embodiment, one of the two LED cells LC1 may form a wavelength converter 160R that emits light of a third color (eg, red). The wavelength conversion unit 160R employed in this embodiment may include a resin layer mixed with red phosphor or red quantum dots.

The above-described display device is illustrated in a form that introduces a partition structure that separates subpixels, but may also be implemented without a partition structure. 14A and 14B are cross-sectional views of a display device according to various embodiments of the present invention, illustrating a form without a partition structure.

First, referring to FIG. 14A, the display device 10B according to the present embodiment does not introduce a partition structure, and each LED cell LC1, LC2, and LC3 is formed on the upper surface of the first conductive semiconductor base layer 111B. ) is shown in Figures 3 and 4, except that it includes a transparent electrode layer 130' as the common electrode and that the reflection function is reinforced by forming the second electrode 150' in a bell-shaped structure. It can be understood as similar to the displayed display device 10. Additionally, unless otherwise stated, the components of this embodiment may be understood by referring to the description of the same or similar components of the display device 10 shown in FIGS. 1 to 4.

In this embodiment, after polishing the under semiconductor layer to leave a partial region including the first conductive semiconductor base layer 111B, the transparent electrode layer 130 may be disposed on the polished surface of the remaining region. The remaining first conductive semiconductor base layer 111B may have a sufficiently thin thickness to prevent light leakage between subpixels. For example, the thickness T1' of the remaining first conductive semiconductor base layer 111B may be 500 nm or less.

A transparent electrode layer 130' may be formed on the upper surface (polished surface) of the remaining first conductive semiconductor base layer 111B. For example, the transparent electrode layer 130' may include transparent conductive oxide (TCO) such as ITO, IZO, or GAZO. In this embodiment, the transparent electrode layer 130' may serve as a common electrode of the LED cells LC1, LC2, and LC3. The transparent electrode layer 130' extends to the peripheral area PA, that is, the connection area CR, located outside the pixels PX, and the extended portion of the transparent electrode layer 130' is connected to the first common electrode pad 145P1. ) to the second common electrode pad 145P2 on the other side, and may be connected to the circuit board 200 through the first bonding electrode 198.

The second electrode 150' employed in this embodiment may have a vertical structure made of a reflective electrode material. After forming the base insulating layer 191 relatively conformally on the passivation layer 120, a second electrode 130' electrically connected to the LED cell is formed on the base insulating layer 191. The second electrode 150' may have a vertical structure surrounding the upper and side regions of each of the LED cells LC1, LC2, and LC3 along the surface of the base insulating layer 191. The second electrode 150' has a reflective structure and can improve the luminance of each subpixel SP1, SP2, and SP3. The base insulating layer 191 may help the second electrode 150' have rounded corners. In some embodiments, the base insulating layer 191 may be omitted when present in the passivation layer 120. The base insulating layer 191 may include the same or similar material as the wiring insulating layer 195 formed to cover the second electrode 150'.

Referring to FIG. 14B, the display device 10C according to this embodiment is similar to the display device 10B shown in FIG. 14A except that it further includes a grid-shaped electrode layer along with the transparent electrode layer 130'. I can understand. Additionally, unless otherwise stated, the components of this embodiment may be understood by referring to the description of the same or similar components of the display device 10B shown in FIG. 14A.

In this embodiment, after polishing the under semiconductor layer to leave a partial region including the first conductive semiconductor base layer 111B, the transparent electrode layer 130 may be disposed on the polished surface of the remaining region. In this embodiment, the reflective electrode layer 175 may be introduced on the area between the LED cells LC1, LC2, and LC3 in the remaining first conductive semiconductor base layer 111B and overlapping the area. From a plan view, the overlapping area has a grid shape, and the reflective electrode layer 175 may also have a grid shape. In this embodiment, light leakage between subpixels can be more effectively prevented by forming the reflective electrode layer 175 after removing at least a portion of the overlapping area of the remaining first conductive semiconductor base layer 111B.

Additionally, the reflective electrode layer 175 may be connected to the transparent electrode layer 130' and used as part of the common electrode structure of the LED cells LC1, LC2, and LC3. As such, in this embodiment, the grid-shaped reflective electrode layer 175 can uniformly supply current to all subpixels in the entire area of the display. In this embodiment, the reflective electrode layer 175 extends to the peripheral area (PA) located outside the pixels PX, that is, the connection area (CR), and the extended portion of the reflective electrode layer 175 is the first common electrode. It is connected to the second common electrode pad 145P2 on the other side by the pad 145P1 and can be connected to the circuit board 200 through the first bonding electrode 198.

15A to 15F are cross-sectional views of each main process for explaining some processes (manufacturing of the pixel array substrate and bonding of the pixel array substrate and the circuit board) of the manufacturing method of the display device according to an embodiment of the present invention; It can be understood as a manufacturing method for the display device of 3.

Referring to FIG. 15A, an under semiconductor layer 111 having a first conductive semiconductor base layer 111b, a first conductive semiconductor cap layer 112, and first to third active layers ( 114a, 114b, 114c), and the second conductive semiconductor layer 116 may be formed sequentially, and the contact layer 155 may be formed.

The growth substrate 101 may be for growing a nitride single crystal, and may include, for example, at least one of sapphire, Si, SiC, MgAl ₂ O ₄ , MgO, LiAlO ₂ , LiGaO ₂ , and GaN. In some embodiments, in order to improve the crystallinity and light extraction efficiency of the semiconductor layers, the growth substrate 101 may have a convex-convex structure on at least a portion of the upper surface. In this case, irregularities may also be formed in the layers grown on top.

The under semiconductor layer 111, the first conductivity type base semiconductor layer 111b, the first to third active layers 114a, 114b, and 114c, and the second conductivity type semiconductor layer 116 are formed, for example, by organic metal chemistry. It can be formed using metal organic chemical vapor deposition (MOCVD), hydrogen vapor phase epitaxy (HVPE), or molecular beam epitaxy (MBE) processes.

The under semiconductor layer 111 may include a first conductive semiconductor base layer 111B and a first conductive semiconductor layer or an undoped semiconductor layer below it. In some embodiments, the under semiconductor layer 111 may include a buffer layer and an undoped nitride layer (eg, GaN). In this case, the buffer layer is for alleviating lattice defects of the first conductive semiconductor cap layer 112, and may include an undoped nitride semiconductor such as undoped GaN, undoped AlN, and undoped InGaN. The first conductive semiconductor base layer 111B and the first conductive semiconductor cap layer 112 may be an n-type nitride semiconductor layer such as n-type GaN, and the second conductive semiconductor layer 116 may be a p-type GaN/p-type. It may be a p-type nitride semiconductor layer such as AlGaN. The first to third active layers 114a, 114b, and 114c may have a single quantum well structure such as InGaN/GaN or a multiple quantum well structure. The contact layer 155 may be formed on the second conductive semiconductor layer 116. For example, the contact layer 155 may be a highly reflective ohmic contact layer.

Next, referring to FIG. 15b, a passivation layer 120 is formed on the first to third LED cells LC1, LC2, and LC3, and a portion of the under semiconductor layer 111 is removed from the outer area ISO. You can.

The passivation layer 120 may be formed on the upper surface of the stacked structure to a uniform thickness and then removed from some areas, areas where the first reflective electrode 130 (see FIG. 3) is to be formed. For example, the passivation layer 120 may include at least one of SiO ₂ , SiN, SiCN, SiOC, SiON, SiOCN, HfO _x , AlO _x , ZrO _x , and AlN. The passivation layer 120 may be formed conformally, and thus may have a substantially uniform thickness. Openings for the first reflective electrode 130 and the common electrode 145 to be formed in a subsequent process may be formed.

In the outer area (ISO), the under semiconductor layer 111 may be removed to a predetermined depth. The outer area (ISO) is an area that is cut in a subsequent process and may be an area for separating modules. Accordingly, in order to prevent cracks from occurring during the cutting or dicing process, part of the under semiconductor layer 111 may be removed in this step.

Next, referring to FIG. 15C, the first electrode 130, the common electrode 145, and the first pad electrode 147 can be formed.

First, the first reflective electrode 130 may be formed on the passivation layer 120 and the first conductive semiconductor layer 112. The first electrode 130 may have a substantially uniform thickness. The first electrode 130 may be formed in the area where the pixels PX of FIG. 3 are arranged and the connection area (CR in FIG. 3).

Next, the common electrode 145 and the first pad electrode 147 may be formed in the connection region CR and the pad regions PAD of FIG. 3, respectively. The common electrode 145 may be formed on the first reflective electrode 130 and the first pad electrode 147 may be formed on the passivation layer 120 . The common electrode 145 and the first pad electrode 147 may be formed together through the same process. The first electrode 130, the common electrode 145, and the first pad electrode 147 may include a conductive material, for example, a metal.

Next, referring to FIG. 15D , a wiring insulating layer 195 may be formed, and second electrodes 150 connected to the contact layers 155 may be formed.

The wiring insulating layer 195 is formed to cover all of the structures formed in the previous steps, including the first electrode 130, and is then subjected to a planarization process such as a chemical mechanical polishing (CMP) process or an etch-back process. A process of planarizing the first wiring insulating layer 195 may be performed using an etch-back process. For example, the first wire insulating layer 195 may be a low dielectric material such as silicon oxide.

A first wire insulating layer 195 is additionally formed, contact holes are formed through the first wire insulating layer 195 and the passivation layer 120 to expose the contact layers 155, and a conductive material is placed in the contact holes. is filled to form contact layers 155. A portion of the contact layers 155 may extend to the top surface of the first wire insulating layer 195.

Referring to FIG. 15E , a first bonding insulating layer 190 may be formed on the second electrodes 150 and first bonding electrodes 198 may be formed.

The first bonding insulating layer 190 may include the same or different material from the first wiring insulating layer 195. Additionally, the first bonding insulating layer 190 may include a material different from that of the first wiring insulating layer 195. The first bonding electrodes 198 can be formed by forming via holes penetrating the first bonding insulating layer 190 and the first wire insulating layer 195 and then filling the via holes with a conductive material. The first bonding electrodes 198 may be formed to be connected to the second electrodes 150, the common electrode 145, and the first pad electrode 147.

Referring to FIG. 15F , a pixel array structure including first to third LED cells LC1, LC2, and LC3 may be bonded to the circuit board 200.

The circuit board 200 may be prepared through a separate process. The pixel array structure and circuit board 200 may be bonded at the wafer level by a wafer bonding method, such as hybrid bonding described above. The second bonding electrodes 298 may be bonded to the first bonding electrodes 198, and the second bonding insulating layer 290 may be bonded to the first bonding insulating layer 190. As a result, the structure including the LED cells 110 and the circuit board 200 can be bonded without a separate adhesive layer.

FIGS. 16A to 16D are cross-sectional views of each main process to explain some other processes in the method of manufacturing a display device according to an embodiment of the present invention, and can be understood as processes following the process of FIG. 15F.

Referring to FIG. 16A, the growth substrate 101 may be removed from the under semiconductor layer 111, and a portion of the under semiconductor layer 111 may be removed. In the following drawings, to facilitate understanding, the pixel array structure including the first to third LED cells LC1, LC2, and LC3 is shown as being bonded to the circuit board 200.

The growth substrate 101 may be removed by various processes such as laser lift-off, mechanical polishing or mechanical chemical polishing, or an etching process. The under semiconductor layer 111 may be partially removed to reduce the thickness to a predetermined thickness using, for example, a polishing process such as CMP. The under semiconductor layer 111 may be removed so that it does not remain in the peripheral area (ISO in FIG. 3).

Next, referring to FIG. 16B, a partition wall structure 111P defining the subpixel spaces OP1, OP2, and OP3 can be formed using the under semiconductor layer 111.

The partition structure 111P may be formed using an etching process to form openings in the under semiconductor layer 111 in areas corresponding to the first to third LED cells LC1, LC2, and LC3. Each opening may provide first to third subpixels (SP1, SP2, and SP3 in FIG. 3) into corresponding first to third subpixel spaces (OP1, OP2, and OP3).

In this embodiment, the first conductive semiconductor base layer 111B may be shared by the first to third LED cells LC1, LC2, and LC3. That is, the first to third LED cells LC1, LC2, and LC3 can be connected to each other by the first conductive semiconductor base layer 111B.

Next, referring to FIG. 16C, a partition reflection layer 170 may be formed on the partition wall structure 111P.

After forming the first partition insulating film 172 and the reflective metal film 174 and removing the reflective metal film 174 from the bottom surfaces of the first to third subpixel spaces OP1, OP2, and OP3, 2 The partition reflective layer 170 can be formed by forming the partition insulating film 176.

Next, referring to FIG. 16D, transparent resin parts 160 and a planarization layer 182 are formed in the first to third subpixel spaces OP1, OP2, and OP3, and a micro lens is formed on the planarization layer 182. Fields 185 may be formed.

A transparent resin portion 160 made of transparent resin may be formed on the first to third subpixel spaces OP3. The transparent resin used in this process may include, for example, a transparent resin such as a silicone resin or an epoxy resin.

Additionally, an opening may be formed by removing the under semiconductor layer 111 and the first conductivity type semiconductor layer 112 on the first pad electrode 147. The opening may be formed to expose the passivation layer 120 on the first pad electrode 147 in the pad areas PAD of FIG. 3 . Next, after partially removing the passivation layer 120 exposed through the opening OT, the second pad electrode 199 is formed, and adjacent modules are diced in the outer area ISO, thereby finally forming the display device. (10) can be prepared (see Figure 3).

Figure 17 is a conceptual diagram of an electronic device including a display device according to an embodiment of the present invention.

Referring to FIG. 17, the electronic device 1000 according to this embodiment may be a glasses-type display, which is a wearable device. The electronic device 1000 may include a pair of temples 1100, a pair of optical coupling lenses 1200, and a bridge 1300. The electronic device 1000 may further include a display device 10 including an image generator.

The electronic device 1000 is a head-mounted, glasses-type, or goggle-type virtual reality (VR) device that can provide virtual reality or provide both a virtual image and an actual external scenery, or an augmented reality (VR) device. It may be a reality (AR) device, or a mixed reality (MR) device.

Temples 1100 may extend in one direction. The temples 1100 may be spaced apart from each other and extend in parallel. The temples 1100 may be folded toward the bridge 1300. The bridge 1300 may be provided between the light coupling lenses 1200 to connect the light coupling lenses 1200 to each other. Light coupling lenses 1200 may include a light guide plate. The display device 10 may be disposed on each of the temples 1100 and may generate images on the light coupling lenses 1200 . The display device 10 may be a display device according to the above-described embodiments.

The present invention is not limited by the above-described embodiments and attached drawings, but is intended to be limited by the appended claims. Accordingly, various forms of substitution, modification, and change may be made by those skilled in the art without departing from the technical spirit of the present invention as set forth in the claims, and this also falls within the scope of the present invention. something to do.

10: Display device 100: Pixel array
110: Semiconductor laminate 111: Base semiconductor layer
111B: First conductive base semiconductor layer 111P: Barrier structure
110: Semiconductor laminate 112: First conductive semiconductor layer
114a, 114b, 114c: first to third active layers
116: Second conductive semiconductor layer LC1, LC2, LC3: First to third light emitting cells
120: Passivation layer 130: First reflective electrode (or first electrode)
145: common electrode 147: first pad electrode
150: second reflective electrode (or second electrode)
155: contact layer 160B: wavelength conversion unit
170: Bulkhead reflective layer 185: Micro lens
199: second pad electrode 200: circuit board

Claims (20)

Forming a first conductive semiconductor base layer on a growth substrate;
Forming a mask pattern on the first conductive semiconductor base layer - the mask pattern has a first opening, a second opening, and a third opening having different widths, and the first opening, the second opening, and the third openings are arranged at the same pitch;
By growing first to third active layers in each of the regions of the first conductivity type semiconductor base layer opened by the first to third openings and second conductivity type semiconductor layers thereon, forming first to third light emitting laminates respectively within the three openings;
removing a mask pattern from the first conductive semiconductor base layer; and
A step of removing edge regions of each of the first to third light emitting laminates,
The step of forming the first to third light emitting laminates is performed by the same growth process, and the first to third active layers are LEDs having first to third quantum well layers each emitting light of different wavelengths. Manufacturing method of module.
According to paragraph 1,
The first opening has a width greater than the width of the second opening, and the second opening has a width greater than the width of the third opening.
According to paragraph 2,
The first quantum well layer emits light with a wavelength of 440 nm to 480 nm, the second quantum well layer emits light with a wavelength of 510 nm to 550 nm, and the third quantum well layer emits light with a wavelength of 610 nm to 550 nm. A method of manufacturing an LED module that emits light with a wavelength of 650 nm.
According to paragraph 1,
The first to third light emitting laminates include a nitride single crystal laminate,
The first to third quantum well layers each include a nitride single crystal layer satisfying In _x Ga _1-x N and having different indium contents (x).
According to clause 4,
The first opening has a larger area than the second opening, and the second opening has a larger area than the third opening,
Manufacturing an LED module in which the indium content of the first quantum well layer is in the range of 0.15 to 0.2, the indium content of the second quantum well layer is in the range of 0.25 to 0.3, and the indium content of the third quantum well layer is in the range of 0.3 to 0.35. method.
According to clause 5,
A method of manufacturing an LED module in which the thickness of the first quantum well layer is greater than the thickness of the second quantum well layer, and the thickness of the second quantum well layer is greater than the thickness of the third quantum well layer.
According to paragraph 1,
The step of forming the first to third light emitting laminates includes,
A method of manufacturing an LED module comprising growing first conductive semiconductor cap layers in each of the regions of the first conductive semiconductor base layer before growing the first to third active layers.
According to paragraph 1,
The first to third light emitting laminates include a nitride single crystal laminate having an upper surface that is a (0001) plane,
An LED module manufacturing method wherein each edge region of the first to third light emitting laminates includes an inclined side region.
According to paragraph 1,
The step of removing the edge area is,
A method of manufacturing an LED module comprising the step of removing edge regions of different widths from the first to third light emitting laminates so that the first to third light emitting laminates have the same width after removal of the edge regions. .
According to paragraph 1,
After removing the edge region, the first to third light emitting laminates have different widths.
According to paragraph 1,
forming first to third electrode layers on the upper surfaces of the first to third light emitting laminates to be connected to the second conductive semiconductor layers;
An LED module manufacturing method further comprising forming a common electrode connected to the first conductive semiconductor base layer.
Forming a first conductive semiconductor base layer on a growth substrate;
Forming a first mask pattern on the first conductive semiconductor base layer - the first mask pattern has first openings and second openings having different widths, and the first opening and the second opening are Arranged in 1st pitch -;
Simultaneously growing first and second active layers in each of the regions of the first conductive semiconductor base layer opened by the first and second openings, wherein the first and second active layers each have different wavelengths. comprising first and second quantum well layers emitting first and second light;
Forming a second mask pattern having a third opening that covers the first and second openings and opens another region of the first conductive semiconductor base layer, wherein the third opening is connected to the first and second openings. arranged at a second pitch with adjacent openings, and the second pitch is the same as the first pitch;
Forming a third active layer in another area of the first conductivity type semiconductor base layer opened by the third opening - a third quantum well emitting third light having a wavelength different from the wavelength of the first and second light. Contains layers -;
forming fourth and fifth openings in the second mask pattern to open the first and second active layers, respectively;
forming first to third light emitting laminates by growing second conductive semiconductor layers on the first to third active layers, respectively;
removing first and second mask patterns from the first conductive semiconductor base layer; and
A method of manufacturing an LED module comprising: removing an edge region of each of the first to third light emitting laminates.
According to clause 12,
A method of manufacturing an LED module wherein the first opening has an area larger than that of the second opening.
According to clause 13,
An LED module manufacturing method wherein the indium content of the first quantum well layer is in the range of 0.15 to 0.2, and the indium content of the second quantum well layer is in the range of 0.25 to 0.3.
According to clause 13,
An LED module manufacturing method wherein the third opening has an area equal to that of the first or second opening.
According to clause 12,
The first quantum well layer emits light with a wavelength of 440 nm to 480 nm, the second quantum well layer emits light with a wavelength of 510 nm to 550 nm, and the third quantum well layer emits light with a wavelength of 610 nm to 550 nm. A method of manufacturing an LED module that emits light with a wavelength of 650 nm.
Forming a first conductive semiconductor base layer on a growth substrate;
Forming a mask pattern having first to third openings arranged at the same pitch on the first conductive semiconductor base layer, wherein the first opening is larger than the width of the second opening and is equal to the width of the third opening. has the same width -;
The first to third openings are formed by growing first to third active layers and second conductivity type semiconductor layers in each of the regions of the first conductivity type semiconductor base layer opened by the first to third openings. forming first to third light emitting laminates respectively;
removing a mask pattern from the first conductive semiconductor base layer; and
A step of removing edge regions of each of the first to third light emitting laminates,
The step of forming the first to third light emitting laminates is performed by the same growth process, and the first and third active layers include first and third quantum well layers each emitting light of the same wavelength, The second active layer is a method of manufacturing an LED module including a second quantum well layer that emits light of a different wavelength from the first and third quantum well layers.
According to clause 17,
An LED module manufacturing method further comprising forming a wavelength converter for converting light emitted from the third quantum well layer on the third light-emitting laminate.
A first conductive semiconductor base layer; and
It includes a plurality of first to third LED cells arranged at the same pitch on a first conductive semiconductor base layer and composed of corresponding semiconductor layers,
The plurality of first to third LED cells each include a nitride single crystal laminate in which a first conductive cap layer, an active layer, and a second conductive semiconductor layer are sequentially stacked, and the upper surface of the nitride single crystal laminate is a (0001) plane. And has a side perpendicular to the first conductive semiconductor base layer,
The active layer of the plurality of first LED cells includes a first quantum well layer that emits light with a wavelength of 440 nm to 480 nm, and the active layer of the plurality of second LED cells includes a wavelength of 510 nm to 550 nm. It includes a second quantum well layer that emits light, wherein the active layer of the plurality of third LED cells emits light with a wavelength of 610 nm to 650 nm nm, and the first to third quantum well layers each An LED module including a third quantum well layer including a nitride single crystal satisfying In _x Ga _1-x N with different indium contents (x).
A circuit board having a driving circuit; and
A pixel array disposed on the circuit board, in which pixel units each composed of first to third subpixels are arranged,
The pixel array is,
a first conductive semiconductor base layer having a first surface facing the circuit board and a second surface located opposite to the first surface;
A first conductive semiconductor cap layer, an active layer, and a second conductive semiconductor are arranged to correspond to the first to third subpixels on the first surface of the first conductive semiconductor base layer, respectively, and are sequentially stacked, respectively. a plurality of first to third LED cells comprising a layer;
a light blocking barrier structure disposed on a second surface of the first conductive semiconductor base layer and having light emission windows corresponding to each of the first to third subpixels;
a passivation layer disposed on a first surface of the first conductive semiconductor base layer and side surfaces and top surfaces of the plurality of first to third LED cells;
a first electrode disposed on the passivation layer and electrically connected to the first conductive semiconductor base layer of each of the plurality of LED cells; and
Second electrodes disposed on the passivation layer and electrically connected to the second conductive semiconductor layer of each of the plurality of first to third LED cells,
A display device wherein the plurality of first to third LED cells have a top surface that is a (0001) plane and a side surface that is perpendicular to the first surface of the first conductive semiconductor base layer.

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