CN117410304A - LED display device - Google Patents

LED display device Download PDF

Info

Publication number
CN117410304A
CN117410304A CN202310865459.7A CN202310865459A CN117410304A CN 117410304 A CN117410304 A CN 117410304A CN 202310865459 A CN202310865459 A CN 202310865459A CN 117410304 A CN117410304 A CN 117410304A
Authority
CN
China
Prior art keywords
light emitting
emitting diode
bonding
diode unit
insulating layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN202310865459.7A
Other languages
Chinese (zh)
Inventor
姜三默
金美贤
成汉圭
延智慧
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Samsung Electronics Co Ltd
Original Assignee
Samsung Electronics Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from KR1020230013740A external-priority patent/KR20240010386A/en
Application filed by Samsung Electronics Co Ltd filed Critical Samsung Electronics Co Ltd
Publication of CN117410304A publication Critical patent/CN117410304A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/15—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components having potential barriers, specially adapted for light emission
    • H01L27/153—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components having potential barriers, specially adapted for light emission in a repetitive configuration, e.g. LED bars
    • H01L27/156—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components having potential barriers, specially adapted for light emission in a repetitive configuration, e.g. LED bars two-dimensional arrays
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1218—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or structure of the substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/08—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a plurality of light emitting regions, e.g. laterally discontinuous light emitting layer or photoluminescent region integrated within the semiconductor body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/36—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes
    • H01L33/38—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes with a particular shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/50—Wavelength conversion elements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/58—Optical field-shaping elements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/62—Arrangements for conducting electric current to or from the semiconductor body, e.g. lead-frames, wire-bonds or solder balls

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Led Device Packages (AREA)

Abstract

A display device includes: a circuit board including a driver circuit; and a pixel array including a plurality of pixels on the circuit board, wherein each of the plurality of pixels includes a first subpixel, a second subpixel, and a third subpixel, and wherein the pixel array includes a lower light emitting structure including: a first lower Light Emitting Diode (LED) unit, a second lower LED unit, and a third lower LED unit corresponding to the first sub-pixel, the second sub-pixel, and the third sub-pixel, respectively, each of the first lower LED unit, the second lower LED unit, and the third lower LED unit including a first semiconductor laminate configured to emit a first light of a first wavelength; and a base insulating layer on lower surfaces of the first, second and third lower LED units and including inter-unit insulating portions extending to regions between the first, second and third lower LED units.

Description

LED display device
Cross Reference to Related Applications
The present application claims the priority of korean patent application No.10-2023-0013740 filed in the korean intellectual property office at 1-2-2023 and korean patent application No.10-2022-0087470 filed in 15-7-2022, the disclosures of which are incorporated herein by reference in their entireties.
Technical Field
Example embodiments of the present disclosure relate to a Light Emitting Diode (LED) display device.
Background
Semiconductor Light Emitting Diodes (LEDs) may be used as light sources for lighting devices as well as various electronic products. In addition, the LED may be widely used as a light source for various display devices such as Televisions (TVs), mobile phones, personal Computers (PCs), notebook PCs, personal Digital Assistants (PDAs), and the like.
A general display device may mainly include a display panel having a Liquid Crystal Display (LCD) and a backlight, but recently, an LED display panel using LED elements (e.g., micro LEDs) as light sources of pixels (sub-pixels) has been developed. Such a display device can have a compact size, and a high-luminance display device having excellent light efficiency compared with an LCD can also be implemented.
The inventors have known or inferred the information disclosed in this background section prior to or during the course of implementing the embodiments of the present application or the information disclosed in this background section is technical information obtained during the course of implementing the embodiments. It may thus contain information that does not constitute prior art known to the public.
Disclosure of Invention
A Light Emitting Diode (LED) display device with high efficiency, which can be formed through a simplified alignment process, is provided.
Additional aspects will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the presented embodiments.
According to an aspect of an example embodiment, a display device may include: a circuit board including a driver circuit; and a pixel array including a plurality of pixels on the circuit board, wherein each of the plurality of pixels may include a first subpixel, a second subpixel, and a third subpixel, wherein the pixel array may include: a lower light emitting structure, comprising: a first lower Light Emitting Diode (LED) unit, a second lower LED unit, and a third lower LED unit corresponding to the first subpixel, the second subpixel, and the third subpixel, respectively, each of the first lower LED unit, the second lower LED unit, and the third lower LED unit including a first semiconductor laminate configured to emit a first light of a first wavelength, and a base insulating layer on a lower surface of the first lower LED unit, the second lower LED unit, and the third lower LED unit and including an inter-unit insulating portion extending to a region between the first lower LED unit, the second lower LED unit, and the third lower LED unit; an upper light emitting structure on the lower light emitting structure, the upper light emitting structure comprising: a transparent insulating portion on the first lower LED unit, an upper LED unit on the second lower LED unit and including a second semiconductor laminate configured to emit second light of a second wavelength, a wavelength converter on the third lower LED unit and configured to convert the first light into third light of a third wavelength, and a light blocking spacer disposed between the transparent insulating portion, the upper LED unit, and the wavelength converter, the light blocking spacer optically isolating the transparent insulating portion, the upper LED unit, and the wavelength converter from each other; a first engagement structure, comprising: a first bonding insulating layer on an upper surface of the lower light emitting structure, and a first bonding electrode at least partially surrounded by the first bonding insulating layer and connected to each of the first, second and third lower LED units; and a second engagement structure comprising: and a second bonding insulating layer on the lower surface of the upper light emitting structure and bonded to the first bonding insulating layer, and a second bonding electrode at least partially surrounded by the second bonding insulating layer, connected to at least the upper LED unit, and bonded to the first bonding electrode.
According to an aspect of an example embodiment, a display device may include: a circuit board including a driver circuit; and a pixel array on the circuit board and including a plurality of pixels, wherein each of the plurality of pixels may include a first subpixel, a second subpixel, and a third subpixel, wherein the pixel array may further include: a lower light emitting structure including first, second and third lower LED units corresponding to the first, second and third sub-pixels, respectively, and configured to emit blue light; an upper light emitting structure, comprising: a transparent insulating portion on the first lower LED unit, an upper LED unit on the second lower LED unit and configured to emit green light, and a wavelength converter on the third lower LED unit and configured to convert blue light into red light; a first engagement structure, comprising: a first bonding insulating layer on an upper surface of the lower light emitting structure, and a first bonding electrode at least partially surrounded by the first bonding insulating layer and connected to each of the first lower LED unit, the second lower LED unit, and the third lower LED unit; and a second engagement structure comprising: and a second bonding insulating layer on the lower surface of the upper light emitting structure and bonded to the first bonding insulating layer, and a second bonding electrode at least partially surrounded by the second bonding insulating layer, connected to the upper LED unit, and bonded to the first bonding electrode.
According to an aspect of an example embodiment, a display device may include: a circuit board including a driver circuit; and a pixel array including a plurality of pixels on an upper surface of the circuit board, each of the plurality of pixels including a first subpixel, a second subpixel, and a third subpixel, wherein the pixel array may further include: a lower light emitting structure including first, second and third lower LED units each including a first semiconductor laminate configured to emit blue light; an upper light emitting structure on the lower light emitting structure, the upper light emitting structure comprising: a transparent insulating portion on the first lower LED unit, an upper LED unit on the second lower LED unit and including a second semiconductor laminate configured to generate green light, and a wavelength converter on the third lower LED unit and configured to convert blue light to red light; a first engagement structure, comprising: a first bonding insulating layer on an upper surface of the lower light emitting structure, and a first bonding electrode at least partially surrounded by the first bonding insulating layer and connected to each of the first lower LED unit, the second lower LED unit, and the third lower LED unit; and a second bonding structure on a lower surface of the upper light emitting structure, the second bonding structure including: and a second bonding insulating layer bonded to the first bonding insulating layer, and a second bonding electrode at least partially surrounded by the second bonding insulating layer, connected to the upper LED unit, and bonded to the first bonding electrode, wherein the first subpixel is configured to emit blue light generated by the first lower LED unit from the transparent insulating portion, the second subpixel is configured to emit green light generated by the upper LED unit, the second lower LED unit is provided as a passive unit that is not driven, and the third subpixel is configured to convert at least a portion of the blue light generated by the third lower LED unit into red light through the wavelength converter, and emit red light.
Drawings
The above and other aspects, features and advantages of certain exemplary embodiments of the present disclosure will become more apparent from the following description when taken in conjunction with the accompanying drawings in which:
fig. 1 is a diagram illustrating a Light Emitting Diode (LED) display device according to an example embodiment of the present disclosure;
FIG. 2 is an enlarged plan view illustrating a portion "A1" in FIG. 1 according to an example embodiment;
fig. 3 is a diagram illustrating a pixel cell according to an example embodiment;
FIG. 4 is a cross-sectional view taken along line I-I' in FIG. 3, as seen from the side, according to an example embodiment;
fig. 5 illustrates a driving circuit showing an LED display device according to an example embodiment of the present disclosure;
fig. 6A, 6B, 6C, and 6D are cross-sectional views illustrating a part of a process of a method of manufacturing an LED display device according to an example embodiment of the present disclosure;
FIG. 7 is a plan view of the first and second engagement structures shown in FIG. 6B according to an example embodiment;
FIG. 8 is a perspective view of the bonding process shown in FIG. 6C according to an example embodiment;
fig. 9A, 9B, and 9C are cross-sectional views illustrating a part of processes (a process of forming a lower light emitting structure and an electrode) of a method of manufacturing an LED display device according to an example embodiment of the present disclosure;
Fig. 10A, 10B, and 10C are plan views illustrating the results of the processes of fig. 9A, 9B, and 9C, respectively, according to example embodiments;
fig. 11A, 11B, 11C, and 11D are cross-sectional views illustrating a part of processes (a process of bonding a circuit board and forming an upper light emitting structure) of a method of manufacturing an LED display device according to an example embodiment of the present disclosure;
fig. 12 is a diagram illustrating a process of bonding circuit boards in fig. 11A according to an example embodiment;
fig. 13 is a diagram illustrating the result of fig. 11C according to an example embodiment;
fig. 14 is a plan view illustrating a portion of a display device according to an example embodiment of the present disclosure;
fig. 15 is a plan view illustrating a pixel unit employed in the display device in fig. 14 according to an example embodiment;
fig. 16 is a plan view illustrating a pixel unit employed in a display device according to an example embodiment of the present disclosure; and
fig. 17 illustrates an electronic apparatus including a display device according to an example embodiment of the present disclosure.
Detailed Description
Hereinafter, example embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. The same reference numerals are used for the same components in the drawings, and repetitive descriptions thereof will be omitted. The embodiments described herein are example embodiments, and thus, the present disclosure is not limited thereto but may be implemented in various other forms.
As used herein, when an expression such as "at least one of … …" is located after a column of elements, it modifies the entire column of elements without modifying individual elements in the column. For example, the expression "at least one of a, b and c" should be understood to include a alone, b alone, c alone, both a and b, both a and c, both b and c, or all of a, b and c.
Fig. 1 is a perspective view illustrating a Light Emitting Diode (LED) display device according to an example embodiment. Fig. 2 is an enlarged plan view illustrating a portion "A1" in fig. 1 according to an example embodiment.
Referring to fig. 1 and 2, a display apparatus 10 (also referred to herein as a display panel) according to an example embodiment may include a circuit board 200 having a driver circuit and a pixel array 100 (also referred to as an LED module for a display or a variant thereof) disposed on the circuit board 200 and having a plurality of pixels PX disposed thereon. In addition, the display apparatus 10 may further include a frame 11 surrounding the circuit board 200 and the pixel array 100.
The plurality of pixels PX in the example embodiment may include first to third sub-pixels SP1, SP2, and SP3 configured to emit light of a specific wavelength (e.g., color) to provide a color image. For example, the first to third sub-pixels SP1, SP2 and SP3 may be configured to emit blue light, green light and red light, respectively. In each pixel, the first to third sub-pixels SP1, SP2 and SP3 may be disposed in a bayer pattern. Specifically, each of the plurality of pixels PX may include a first subpixel SP1 and a third subpixel SP3 disposed in a first diagonal direction and two subpixels SP2 disposed in a second diagonal direction crossing the first diagonal direction. In the example embodiment, in the pixel PX, the first to third sub-pixels SP1, SP2, and SP3 may be disposed in a 2×2 bayer pattern, but the example embodiment thereof is not limited thereto. In other example embodiments, each pixel PX may be configured in a different arrangement of 1×3, 3×3, or 4×4, and a portion of the sub-pixels may be configured to emit light of a different color (e.g., yellow) than the example colors R, G and B.
As shown in fig. 1, the pixel arrays in the example embodiment may be arranged in a 15 x 15 array, but the number of rows and columns may be implemented in any suitable number (e.g., 1024 x 768). The pixel array may have different arrangements depending on the desired resolution.
The frame 11 may be provided as a guide disposed around the pixel array 100 and defining an arrangement space of the array of pixels PX. The frame 11 may include at least one of a polymer, a ceramic, a semiconductor, and a metal, for example. In a specific example, the frame 11 may include a black matrix. The frame 11 is not limited to a black matrix, and a white matrix or another color structure may be used according to the purpose of the product. For example, the white matrix may comprise a reflective material or a scattering material.
The display device 10 in the example embodiment may have a rectangular planar structure, or may have a structure of another shape. In an example embodiment, the circuit board 200 may be implemented as a driver circuit board including a Thin Film Transistor (TFT) unit. In an example embodiment, the circuit board 200 may include only a portion of a driver circuit for a display device, and may include another driving apparatus. In an example embodiment, the circuit board 200 may be formed using a flexible substrate, thereby implementing a display device having a curved profile.
A specific configuration of a display device according to an example embodiment will be described with reference to fig. 3 and 4. Fig. 3 illustrates a structure of a pixel of the display device illustrated in fig. 1 and 2 according to an example embodiment, and fig. 4 is a cross-sectional view taken along a line I-I' in fig. 3, as seen from a side.
Referring to fig. 3 and 4, the display apparatus 10 according to an example embodiment may include a circuit board 200 and a pixel array 100 disposed on the circuit board 200.
The pixel array 100 may include a lower light emitting structure 100A having first to third lower LED units LC1a, LC1b, and LC1c. The pixel array 100 may include an upper light emitting structure 100B, the upper light emitting structure 100B including a transparent insulating portion 160 on the first lower LED unit LC1a, an upper LED unit LC2 on the second lower LED unit LC1B, and a wavelength converter 180 on the third lower LED unit LC1c. The pixel array 100 may include a first bonding structure BS1 disposed on an upper surface of the lower light emitting structure 100A and a second bonding structure BS2 disposed on a lower surface of the upper light emitting structure 100B. The lower and upper light emitting structures 100A and 100B may form the pixel array 100 by bonding the first and second bonding structures BS1 and BS2.
In the lower light emitting structure 100A, the first to third lower LED units LC1a, LC1b, and LC1c may be disposed in regions corresponding to the first to third sub-pixels SP1, SP2, and SP3, respectively, and may include first semiconductor laminates SL1 each configured to emit light of a first wavelength (e.g., blue light). The first to third lower LED units LC1a, LC1b, and LC1c may be obtained by dividing the first semiconductor laminate SL1 (see fig. 9A).
The first semiconductor laminate SL1 may include a first conductive semiconductor layer 122, an active layer 125, and a second conductive semiconductor layer 127. In example embodiments, the first semiconductor laminate SL1 may include a nitride semiconductor. For example, the first conductive semiconductor layer 122 may include a material satisfying n-type In x Al y Ga 1-x-y N (0.ltoreq.x < 1, 0.ltoreq.y < 1, 0.ltoreq.x+y < 1), and the N-type impurity may include Si, ge, se or Te. The active layer 125 may have a Multiple Quantum Well (MQW) structure in which quantum well layers and quantum barrier layers are alternately stacked. For example, the quantum well layer and the quantum barrier layer may be In having different compositions x Al y Ga 1-x-y N (x is more than or equal to 0 and less than or equal to 1, y is more than or equal to 0 and less than or equal to 1, and x+y is more than or equal to 0 and less than or equal to 1). In a particular example, the quantum well layer may be In x Ga 1-x N (0 < x.ltoreq.1), and the quantum barrier layer may be GaN or AlGaN. For example, as described above, the active layer 125 may be configured to emit blue light (e.g., 435nm to 460 nm). The second conductive semiconductor layer 127 may include a material satisfying p-type In x Al y Ga 1-x-y N (0.ltoreq.x < 1, 0.ltoreq.y < 1, 0.ltoreq.x+y < 1), whereinThe p-type impurity may include Mg, zn, or Be.
The lower light emitting structure 100A may further include a base insulating layer 110 disposed on lower surfaces of the first to third lower LED units LC1a, LC1b, and LC1 c. The base insulating layer 110 may have an inter-cell insulating portion 110E extending to a region between the first to third lower LED units LC1a, LC1b, and LC1 c. In this way, the first to third lower LED units LC1a, LC1b and LC1c may be isolated from each other by the inter-unit insulating portion 110E.
In an example embodiment, the base insulating layer 110 may include a light reflecting structure. For example, before the base insulating layer 110 is formed, an insulating film may be conformally formed on the lower surfaces and side surfaces of the first to third lower LED units LC1a, LC1b, and LC1c, a reflective metal film may be formed on the insulating film, and the base insulating layer 110 for filling may be formed on the reflective metal film. In another example embodiment, the base insulating layer 110 may include a black matrix or a white matrix, or may include a dielectric Distributed Bragg Reflector (DBR) layer and a filler insulating material. For example, the dielectric DBR layer may be obtained by alternately stacking a first dielectric layer and a second dielectric layer having different refractive indexes.
In the upper light emitting structure 100B, the transparent insulating portion 160, the upper LED unit LC2, and the wavelength converter 180 may be disposed in regions corresponding to the first to third sub-pixels SP1, SP2, and SP3, respectively.
The transparent insulating portion 160 disposed in the first subpixel SP1 may include an insulating material having light transmittance. For example, the transparent insulating portion 160 may include a transparent resin such as silicone resin or epoxy resin, or a transparent resin such as SiO 2 Is a silicon oxide of (a). The transparent insulating portion 160 may form an upper region of the first subpixel SP1 and may have a shape corresponding to that of the first lower LED unit LC1a in a plan view. In this way, the first subpixel SP1 may be configured such that light of a first wavelength (e.g., blue light) generated by the first lower LED unit LC1a may be emitted as it is through the transparent insulating portion 160.
The upper LED unit LC2 disposed in the second subpixel SP2 may have a light (e.g., green light) configured to emit light of a second wavelengthThe second semiconductor laminate SL2. Similar to the first semiconductor laminate SL1, the second semiconductor laminate SL2 may include a first conductive semiconductor layer 142, an active layer 145, and a second conductive semiconductor layer 147. In an example embodiment, the second semiconductor laminate SL2 may include a nitride semiconductor. For example, the first conductive semiconductor layer 142 may include a material satisfying n-type In x Al y Ga 1-x-y N (0.ltoreq.x < 1, 0.ltoreq.y < 1, 0.ltoreq.x+y < 1), wherein the N-type impurity may include Si, ge, se or Te. The active layer 145 may have an MQW structure in which quantum well layers and quantum barrier layers are alternately stacked. For example, the quantum well layer and the quantum barrier layer may be In having different compositions x Al y Ga 1-x-y N (x is more than or equal to 0 and less than or equal to 1, y is more than or equal to 0 and less than or equal to 1, and x+y is more than or equal to 0 and less than or equal to 1). In a particular example, the quantum well layer may be In x Ga 1-x N (0 < x.ltoreq.1), and the quantum barrier layer may be GaN or AlGaN. For example, as described above, the active layer 145 may be configured to emit green light (e.g., 480nm to 530 nm). The second conductive semiconductor layer 147 may include a material satisfying p-type In x Al y Ga 1-x-y N (0.ltoreq.x < 1, 0.ltoreq.y < 1, 0.ltoreq.x+y < 1), wherein the p-type impurity may include Mg, zn or Be.
The second subpixel SP2 in the example embodiment may be configured to emit light (e.g., green light) of a second wavelength generated by the upper LED unit LC 2. The second lower LED unit LC1b disposed below the upper LED unit LC2 may be set as a passive unit that does not emit light because the unit LC1b is not driven.
The wavelength converter 180 disposed in the third subpixel SP3 may include a wavelength converting material (e.g., a phosphor or a quantum dot) converting light of a first wavelength (e.g., blue light) into light of a third wavelength (e.g., red light). For example, the wavelength converter 180 may include a transparent resin or a phosphor film containing a wavelength conversion material. For example, the transparent resin may include silicone resin or epoxy resin. The wavelength converter 180 may form an upper region of the third subpixel SP3 and may have a shape corresponding to that of the third lower LED unit LC1c in a plan view. In this way, the third subpixel SP3 may convert at least a portion of the light of the first wavelength (e.g., blue light) generated by the third lower LED unit LC1c into light of the third wavelength (e.g., red light) through the wavelength converter 180, and may emit light.
The upper light emitting structure 100B may further include a light blocking spacer 170 disposed between the transparent insulating portion 160, the upper LED unit LC2, and the wavelength converter 180. The light blocking spacer 170 may be included as a structure for preventing light interference between the first to third sub-pixels SP1, SP2 and SP3 in the upper light emitting structure 100B.
The light blocking spacer 170 may include an insulating material for blocking light. In an example embodiment, as the light blocking spacer 170, a material such as a black matrix or a white matrix or a structure of another color may be used. For example, the white matrix may comprise a reflective material or a scattering material. In an example embodiment, the light blocking spacer 170 may include a DBR layer.
In an example embodiment, the lower and upper light emitting structures 100A and 100B may be bonded by bonding the first and second bonding structures BS1 and BS 2.
The first bonding structure BS1 may include a first bonding insulating layer 131a disposed on an upper surface of the lower light emitting structure 100A and a first bonding electrode 135a surrounded by the first bonding insulating layer 131 a. The first bonding electrode 135a may be configured to be electrically connected to each of the first to third lower LED units LC1a, LC1b, and LC1 c. In an example embodiment, the first bonding electrode 135a may be connected to the corner region C1 of the neighboring lower LED units along the boundaries of the first to third lower LED units LC1a, LC1b, and LC1C on the upper surface of the lower light emitting structure 100A. For example, the first bonding electrode 135a may have a grid shape in a plan view (see fig. 2 and 3).
The second bonding structure BS2 may include a second bonding insulating layer 131B disposed on the lower surface of the upper light emitting structure 100B and a second bonding electrode 135B surrounded by the second bonding insulating layer 131B. The second bonding electrode 135b may be electrically connected to each of the upper LED units LC 2. In an example embodiment, the second bonding electrode 135b may have a shape corresponding to that of the first bonding electrode 135a in a plan view. The first bonding electrode 135a and the second bonding electrode 135b can ensure a sufficient bonding area. For example, the second bonding electrode 135b may have the same/similar grid shape as the first bonding electrode 135a in a plan view (see fig. 2 and 3). The second bonding electrode 135B may extend along the boundary of the transparent insulating portion 160, the upper LED unit LC2, and the wavelength converter 180 on the lower surface of the upper light emitting structure 100B, and may be formed to be electrically connected to the corner region C2 of the upper LED unit LC 2.
As described above, the lower light emitting structure 100A and the upper light emitting structure 100B may be combined by the bonding of the first bonding structure BS1 and the second bonding structure BS2, and the pixel array 100 may be formed. To achieve strong bonding, the first bonding electrode 135a may have an upper surface substantially coplanar with an upper surface of the first bonding insulating layer 131 a. Similarly, the second bonding electrode 135b may have an upper surface substantially coplanar with an upper surface of the second bonding insulating layer 131 b.
The directly bonded first bonding electrode 135a and second bonding electrode 135b may be bonded by interdiffusion between metals (e.g., copper) through a high temperature annealing process. The metal included in the first and second bonding electrodes 135a and 135b may not be limited to copper (Cu) and may include other metal materials (e.g., au) that may be bonded under similar conditions. The bond between the metals ensures an electrical connection and a strong bond. In an example embodiment, the first and second bonding electrodes 135a and 135b metal-bonded in the first and second bonding structures BS1 and BS2 may also be set as the common electrode 135 for the light sources of the first to third sub-pixels SP1, SP2 and SP 3. Specifically, the common electrode 135 may be connected to the first and third lower LED units LC1a and LC1c of each of the first and third sub-pixels SP1 and SP3 and the upper LED unit LC2 of the second sub-pixel SP 2. In an example embodiment, the common electrode 135 may also have a grid shape in a plan view.
The first and second bonding insulating layers 131a and 131b may include a light-transmitting dielectric material. Light (e.g., blue light) emitted from the first and third lower LED units LC1a and LC1c may be transmitted through the first and second bonding insulating layers 131a and 131b, respectively, and may be emitted through the transparent insulating part 160 (e.g., transparent resin part) and the wavelength converter 180. For example, the first and second bonding insulating layers 131a and 131b may include silicon oxide (SiO 2 ). The first bonding insulating layer 131a and the second bonding insulating layer 131b may include bonding between dielectrics through covalent bonds during a high temperature bonding process. In example embodiments, the first and second bonding insulating layers 131a and 131b may further include another insulating film such as SiCN, siON, or SiCO.
The first and second bonding structures BS1 and BS2 may form a bond between dielectrics of the first and second bonding insulating layers 131a and 131b and a bond between metals of the first and second bonding electrodes 135a and 135 b. Such joining may also be referred to as "hybrid joining.
The pixel array 100 according to an example embodiment may include first to third individual electrodes 150a, 150b, and 150c as electrodes (first electrodes) on one sides of the light sources of the first to third sub-pixels SP1, SP2, and SP 3.
The first individual electrode 150a may be disposed on the lower surface of the first lower LED unit LC1a and may be electrically connected to the first conductive semiconductor layer 122 of the first lower LED unit LC1 a. Similarly, the third individual electrode 150c may be disposed on the lower surface of the third lower LED unit LC1c and may be electrically connected to the first conductive semiconductor layer 122 of the third lower LED unit LC1 c. The first and third individual electrodes 150a and 150c may be buried in the base insulating layer 110 to expose the contact region. The contact regions of the first and third individual electrodes 150a and 150c may have surfaces substantially coplanar with the lower surface of the base insulating layer 110.
The second individual electrode 150b may penetrate the second lower LED unit LC1b, the first and second bonding insulating layers 131a and 131b, and a portion of the upper LED unit LC2, and may be electrically connected to the first conductive semiconductor layer 142 of the upper LED unit LC 2. The second individual electrode 150b may include a feedthrough 155 extending from the lower surface of the second lower LED unit LC1b to the second conductive semiconductor layer 147 of the upper LED unit LC2, and a sidewall insulating film 151 surrounding sidewalls of the feedthrough 155. The sidewall insulating film 151 may electrically insulate the second individual electrode 150b from the second lower LED unit LC1 b. In an example embodiment, since the second lower LED unit LC1b insulated by the second individual electrode 150b is not connected to one side electrode, the unit may be a passive LED unit that is not actually driven.
The pixel array 100 according to an example embodiment may include a common electrode 135 as another electrode (second electrode) of the light sources of the first to third sub-pixels SP1, SP2 and SP 3. As described above, the common electrode 135 may be provided by the first and second bonding electrodes 135a and 135b being bonded.
As described above, each of the first and second semiconductor laminates SL1 and SL2 may include the first conductive semiconductor layers 122 and 142, the active layers 125 and 145, and the second conductive semiconductor layers 127 and 147, and the first and second semiconductor laminates SL1 and SL2 may be disposed such that the second conductive semiconductor layers 127 and 147 may be opposite to each other. Accordingly, the first and second bonding electrodes 135a and 135b may be electrically connected to the second conductive semiconductor layers 127 and 147 of the first and second semiconductor laminates SL1 and SL2, respectively, and the common electrode 135 in the example embodiment may be used as the second electrode.
In the first to third lower LED units LC1a, LC1b and LC1c, an ohmic contact layer may be disposed on each of the upper surface of the second conductive semiconductor layer 127 and the lower surface of the upper LED unit LC 2. The first and second bonding electrodes 135a and 135b may be connected to the second conductive semiconductor layers 127 and 147 through ohmic contact layers, respectively. The ohmic contact layers formed on the upper surfaces of the first to third lower LED units LC1a, LC1b and LC1c may include a light-transmitting ohmic contact layer. For example, the light-transmitting ohmic contact layer may include ITO, ZITO, ZIO, GIO, ZTO, FTO, AZO, GZO, in 4 Sn 3 O 12 Or Zn (1-x) Mg x O (0.ltoreq.x.ltoreq.1). In an example embodiment, a high reflective ohmic contact layer such as Ag and/or Ni/Au may be disposed on the upper surface of the upper LED unit LC 2.
In addition, in example embodiments, each of the first to third lower LED units LC1a, LC1B and LC1c may have a side surface inclined such that the width of each of the first to third lower LED units increases toward the upper light emitting structure 100B, and the upper LED unit LC2 may have a side surface inclined such that the width of the upper LED unit increases toward the lower light emitting structure 100A. The inclined side surface may be defined in a direction in which the etching process (see fig. 9A and 11C) is performed.
As described above, in the upper light emitting structure 100B, the first to third sub-pixels SP1, SP2 and SP3 may be optically isolated by the light blocking spacer 170. In an example embodiment, the light blocking spacer 170 may be disposed to overlap the second bonding electrode 135b (i.e., the common electrode 135) in a direction (Z direction) perpendicular to the upper surface of the circuit board. In an example embodiment, the common electrode 135 having a grid shape may be provided as an optical isolation structure for the first to third sub-pixels SP1, SP2 and SP3 together with the light blocking spacer 170. In an example embodiment, as described above, the base insulating layer 110 may include a reflective element such that the common electrode 135 and the light blocking spacer 170 may be provided as an optical isolation structure for the first to third sub-pixels SP1, SP2 and SP3 together with the inter-cell insulating portion 110E. In example embodiments, the light blocking spacer 170 may have a cross-sectional shape in which the width of the lower end is smaller than the width of the upper end, but example embodiments thereof are not limited thereto, and the light blocking spacer 170 may vary according to a process sequence for the upper light emitting structure 100B.
As such, the pixel array 100 according to the example embodiment may use the first and third lower LED units LC1a and LC1c disposed at the first level and including the first semiconductor laminate SL1 and the upper LED unit LC2 disposed at the second level and including the second semiconductor laminate SL2 as light sources. The pixel array 100 may include a wavelength converter 180 for the third lower LED unit LC1c at the second level such that light of different colors B, G and R may be emitted from the first to third sub-pixels SP1, SP2 and SP 3. In addition, the light source (i.e., the first, upper, and third lower LED units LC1a, LC2, and LC1 c) of each of the sub-pixels SP1, SP2, and SP3 and the common electrode 135 may be selectively driven by applying voltages through the first to third individual electrodes 150a, 150b, and 150 c.
The circuit board 200 in the example embodiment may include a wiring connection layer 280 and a device layer 250 in which a driver circuit including a plurality of TFT units 245 is implemented. The device layer 250 may include the semiconductor substrate 210, a driver circuit including a TFT unit 245 formed on the semiconductor substrate 210, an interconnection portion 242 electrically connected to the TFT unit 245, and an interlayer insulating film 241 disposed on the semiconductor substrate 210 and covering the driver circuit and the interconnection portion 242. For example, the semiconductor substrate 210 may include a semiconductor such as Si or Ge, or a compound semiconductor such as SiGe, siC, gaAs, inAs or InP.
The wiring connection layer 280 may include a dielectric layer 281 provided on the interlayer insulating film 241 and a metal wiring 285 provided on the dielectric layer 281 and connected to the interconnection portion 242. The metal wiring 285 may be electrically connected to the driver circuit through the interconnection portion 242.
The metal wiring 285 may have a bonding pad 285P exposed to the upper surface of the dielectric layer 281. The bond pad 285P may have a surface substantially coplanar with the upper surface of the dielectric layer 281. The coplanar upper surface of the dielectric layer 281 may be bonded to the coplanar lower surface of the base insulating layer 110, and the bonding pad 285P may be bonded to the first to third individual electrodes 150a, 150b, and 150c. The feedthrough connected to the common electrode 135 on one side of the pixel array 100 may be connected to another bond pad 285P.
The driver circuit including the plurality of TFT units 245 implemented on the circuit board 200 may be a driver circuit for controlling driving of pixels (specifically, sub-pixels). The semiconductor substrate 210 may include a through electrode 263, such as a Through Silicon Via (TSV), connected to a driver circuit, and first and second wirings 261 and 262 connected to the through electrode 263. For example, the drain regions of the plurality of TFT units 245 may be connected to the first wiring 261 through the through electrode 263, and the first wiring 261 may be connected to a data line.
Fig. 5 illustrates a driving circuit showing an LED display device according to an example embodiment.
In fig. 5, a circuit diagram of the display panel 10 in which n×n sub-pixels are provided is shown. First to third sub-pixels SP1,SP2 and SP3 may pass through data line D as a vertical (row direction) path 1 To D n A data signal is received. The first to third sub-pixels SP1, SP2 and SP3 may pass through the gate line G as a horizontal (column direction) path 1 To G n A control signal (gate signal) is received.
The plurality of pixels PX including the first to third sub-pixels SP1, SP2, and SP3 may provide an active area DA for display, and the active area DA may be set as a display area for a user. The inactive area NA of the display panel 10 may be formed along one or more edges of the active area DA. The inactive area NA may have no pixels PX along the outer circumference of the display panel 10, and may correspond to the frame 11 of the display panel 10.
The first driver circuit 12 and the second driver circuit 13 may be used to control the operation of the pixels PX (i.e., the plurality of sub-pixels SP1, SP2, SP 3). Part or all of the first driver circuit 12 and the second driver circuit 13 may be implemented on the device layer 250 of the circuit board 200. The first and second driver circuits 12 and 13 may be formed as integrated circuits, thin film transistor panel circuits, or other suitable circuits, and may be disposed in the inactive area NA of the display panel 10. The first driver circuit 12 and the second driver circuit 13 may include a microprocessor, a memory such as a storage section, a processing circuit, and a communication circuit. During operation, the system control circuit may supply image information to be displayed on the display panel 10 to the first driver circuit 12 and the second driver circuit 13.
In order to display an image on the pixels PX, the first driver circuit 12 may supply image data to the data lines D 1 To D n And sends a clock signal and other control signals to the second driver circuit 13 (also referred to as a gate driver circuit). The second driver circuit 13 may be implemented with an integrated circuit and/or a thin film transistor circuit. Gate signals for controlling the first to third sub-pixels SP1, SP2 and SP3 arranged in the column direction may pass through the gate line G of the display device 1 To G n And (5) transmission.
As such, the LED display apparatus 10 according to the example embodiment may have a two-layer light source structure having a lower LED unit and an upper LED unit emitting light of different wavelengths, and the LED display apparatus 10 may implement desired pixels by partially including a light conversion structure on an upper layer.
Fig. 6A, 6B, 6C, and 6D are cross-sectional views illustrating a part of a process of a method of manufacturing an LED display device according to an example embodiment of the present disclosure. Fig. 6A-6D illustrate a process of forming and bonding a first semiconductor laminate and a second semiconductor laminate.
Referring to fig. 6A, a first semiconductor laminate SL1 may be formed on a first growth substrate 101A, and similarly, a second semiconductor laminate SL2 may be formed on a second growth substrate 101B.
The first growth substrate 101A and the second growth substrate 101B may include an insulating material, a conductive material, or a semiconductor material, such as sapphire, si, siC, mgAl 2 O 4 、MgO、LiAlO 2 、LiGaO 2 GaN, etc. The first semiconductor laminate SL1 may include a first conductive semiconductor layer 122, an active layer 125 generating light of a first wavelength, and a second conductive semiconductor layer 127 sequentially formed on the first growth substrate 101A. The second semiconductor laminate SL2 may include a first conductive semiconductor layer 142, an active layer 145 generating light of a second wavelength, and a second conductive semiconductor layer 147 sequentially formed on the second growth substrate 101B. Light of a first wavelength and light of a second wavelength (e.g., blue light and green light) may be used for the first subpixel and the third subpixel, respectively.
As described above, each of the layers of the first and second semiconductor laminates SL1 and SL2 may be a nitride semiconductor layer, and may be grown using processes such as Metal Organic Chemical Vapor Deposition (MOCVD), hydride Vapor Phase Epitaxy (HVPE), and Molecular Beam Epitaxy (MBE). Before forming the first and second semiconductor laminates SL1 and SL2, a buffer layer and an undoped semiconductor layer (e.g., undoped GaN) may be additionally formed on the upper surfaces of the first and second growth substrates 101A and 101B. In example embodiments, as described above, an ohmic contact layer may be formed on the second conductive semiconductor layers 127 and 147.
Thereafter, referring to fig. 6B, a first bonding structure BS1 having a first bonding electrode 135a and a first bonding insulating layer 131a may be formed on the first semiconductor laminate SL1, and similarly, a second bonding structure BS2 including a second bonding electrode 135B and a second bonding insulating layer 131B may be formed on the second semiconductor laminate SL 2.
Forming the first and second bonding structures BS1 and BS2 may include the following processes: forming a first bonding insulating layer 131a and a second bonding insulating layer 131b on the first semiconductor laminate SL1 and the second semiconductor laminate SL2, respectively, forming first openings and second openings defining the first bonding electrodes 135a and the second bonding electrodes 135b in the first bonding insulating layer 131a and the second bonding insulating layer 131b, and depositing a metal such that the first openings and the second openings are filled and planarized. For example, the first and second bonding electrodes 135a and 135b may include copper (Cu), but example embodiments thereof are not limited thereto, and may include other bondable metal materials (e.g., au). In addition, the first and second bonding insulating layers 131a and 131b may include the same dielectric material, for example, silicon oxide (SiO 2 )。
The first and second openings may be formed along a boundary region between the first and second sub-pixel regions. The widths of the first and second openings, i.e., the widths of the first and second bonding electrodes 135a and 135b, may be greater than the width for dividing the first semiconductor laminate SL 1. Specifically, the first and second openings for the first and second bonding electrodes 135a and 135b may be defined to overlap each corner region of the first to third lower LED units and the corner region of the upper LED unit in a subsequent process. The first bonding electrode and the second bonding electrode may have shapes corresponding to each other at corresponding positions.
Fig. 7 is a plan view of the first and second engagement structures shown in fig. 6B. As shown in fig. 7, the first and second bonding electrodes 135a and 135b may have a grid shape dividing sub-pixels.
The first bonding electrode 135a may have an upper surface substantially coplanar with an upper surface of the first bonding insulating layer 131a through a planarization process. Similarly, the second bonding electrode 135b may have an upper surface substantially coplanar with an upper surface of the second bonding insulating layer 131 b.
Thereafter, referring to fig. 6C and 8, the first and second semiconductor laminates SL1 and SL2 may be coupled to each other using the first and second bonding structures BS1 and BS 2.
In a state where the first bonding structure BS1 and the second bonding structure BS2 are bonded, the first bonding structure BS1 and the second bonding structure BS2 may be hybrid bonded by a high temperature annealing process.
Fig. 8 is a perspective view of a bonding process for bonding the first and second bonding structures shown in fig. 6C on a wafer level according to an example embodiment. The hybrid bonding performed in this process may include metal-to-Metal Bonding (MB) of the first and second bonding electrodes 135a and 135B and Dielectric Bonding (DB) of the first and second bonding insulating layers 131A and 131B, and the first semiconductor laminate SL1 on the first growth substrate 101A and the second semiconductor laminate SL2 on the second growth substrate 101B may be firmly coupled to each other. In addition, the first and second bonding electrodes 135a and 135b may be provided as an integrated common electrode 135 by metal-to-Metal Bonding (MB). Thereafter, as shown in fig. 6D, the first growth substrate 101A may be removed from the first semiconductor laminate SL 1.
Fig. 9A, 9B, and 9C are cross-sectional views illustrating a part of processes (a process of forming a lower light emitting structure and an electrode) in a method of manufacturing an LED display device according to an example embodiment. Fig. 10A, 10B, and 10C are plan views illustrating the process results of fig. 9A, 9B, and 9C according to example embodiments.
Referring to fig. 9A and 10A, a first etching process of dividing the first semiconductor laminate SL1 into sub-pixel regions and a second etching process of forming the through holes TH in the second lower LED unit LC1b may be performed.
The first to third lower LED units LC1a, LC1b, and LC1c respectively corresponding to the sub-pixel regions may be formed by dividing the first semiconductor laminate SL1 through a first etching process. As shown in fig. 10A, each of the first to third lower LED units LC1a, LC1b, and LC1c may have a rectangular shape in a plan view, and may form a bayer pattern. The first lower LED unit LC1a and the third lower LED unit LC1c may be disposed in a first diagonal direction, and the two second lower LED units LC1b may be disposed in a second diagonal direction. As described above, the width of the cell isolation space ISO may be smaller than the width of the first bonding electrode 135 a. Accordingly, the first bonding electrode 135a may overlap the corner regions of the first to third lower LED units LC1a, LC1b, and LC1c, and may be electrically connected to the corner regions of the first to third lower LED units LC1a, LC1b, and LC1c. In example embodiments, the width of the cell isolation space ISO may decrease downward, and the first to third lower LED units LC1a, LC1b, and LC1c may have inclined side surfaces.
The through holes TH for the second individual electrodes (150 b in fig. 9C) may be formed through a second etching process. The through holes TH may penetrate the first and second bonding insulating layers 131a and 131b and a portion of the second semiconductor laminate SL2 from the second lower LED unit LC1b, and may be connected to the first conductive semiconductor layer 142 of the second semiconductor laminate SL 2. The region of the second semiconductor laminate SL2 in which the through holes TH extend may be set as the upper LED unit LC2 in a subsequent process. In an example embodiment, when configuring the bayer pattern, as shown in fig. 10A, through holes may be respectively formed in the second lower LED units LC1b disposed in the second diagonal direction.
Each of the first etching process and the second etching process may be performed through a selective etching process using a photoresist pattern, and the order is not limited. For example, the second etching process and the first etching process may be sequentially performed, and after forming the via holes to the same depth in the first etching process, the second etching process may be performed to etch additional depths.
Thereafter, referring to fig. 9B and 10B, a base insulating layer 110 may be formed on the first to third lower LED units LC1a, LC1B, and LC1c so that the cell isolation space ISO may be filled.
The base insulating layer 110 may include an inter-cell insulating portion 110E isolating the first to third lower LED cells LC1a, LC1b, and LC1 c. The base insulating layer 110 mayComprising SiO 2 At least one of SiN, siCN, siOC, siON and SiOCN. In this process or another process, a sidewall insulating film 151 may be formed on sidewalls of the through holes TH to be exposed on bottom surfaces of the through holes TH.
In an example embodiment, the base insulating layer 110 may be configured to include a reflective element. In this case, first, the insulating film can be formed relatively conformally. In this process, the sidewall insulating films 151 may be formed together. Thereafter, the reflective layer may be formed in a region other than the region in which the first to third individual electrodes are to be formed. For example, the reflective layer may include a reflective metal such as Ag, ni, or Al. Thereafter, the base insulating layer 110 may be formed to fill the insulating portion. For example, the base insulating layer 110 may include silicon oxide or a silicon oxide-based insulating material. In example embodiments, the reflective layer may be implemented as a DBR layer or an omni-directional reflector (ODR) layer. When the DBR layer is included as the reflective layer, an insulating film may not be provided.
Thereafter, referring to fig. 9C and 10C, the first and third individual electrodes 150a and 150C connected to the first conductive semiconductor layer 122 of the first and third lower LED units LC1a and LC1C, respectively, may be formed, and the second individual electrode 150b connected to the first conductive semiconductor layer 142 of the second semiconductor laminate SL2 may be formed by filling the through holes TH.
The first to third individual electrodes 150a, 150b and 150c may be formed by forming openings for opening a part of regions of the first and third lower LED units LC1a and LC1c (a part of regions of the first conductive semiconductor layer) in the base insulating layer, and forming a metal material filling the openings and the through holes TH. For example, the first to third individual electrodes 150a, 150b and 150c may include copper or copper-containing alloy, and may be formed using a dual damascene process.
Fig. 11A, 11B, 11C, and 11D are cross-sectional views illustrating a part of processes (a process of bonding a circuit board and forming an upper light emitting structure) of a method of manufacturing an LED display device according to an example embodiment.
Referring to fig. 11A, the circuit board 200 may be bonded on the result in fig. 10C (i.e., bonded on the resulting structure in fig. 10C).
In the bonding process, the first to third individual electrodes 150A, 150b and 150c of the lower light emitting structure 100A may be metal-bonded to the driver circuit (bonding pad 285P). In addition, surfaces of the dielectric layer 281 and the base insulating layer 110 opposite to each other may have coplanar surfaces and may be bonded between dielectrics. In addition, the pixel array 100 may include a through electrode connected to the common electrode 135 at a periphery thereof, and the through electrode may be bonded to the bonding pad 285P similarly to the other individual electrodes 150a, 150b, and 150c.
Fig. 12 illustrates a process of bonding the circuit board in fig. 11A according to an example embodiment. As shown in fig. 12, the bonding process between the circuit board 200 and the pixel array 100 may be performed at a wafer level.
Thereafter, referring to fig. 11B, the second growth substrate 101B may be removed from the second semiconductor laminate SL 2.
Fig. 13 shows the process result of fig. 11C according to an example embodiment. Referring to fig. 11C and 13, the first and second grooves RS1 and RS2 may be formed by removing a partial region of the second semiconductor laminate SL2 to expose the first and third lower LED units LC1a and LC1C corresponding to the first and third sub-pixels, respectively.
The second growth substrate 101B may be removed using a process similar to that for removing the first growth substrate 101A (e.g., a laser lift-off or polishing process). Similar to the previous process of dividing the first semiconductor laminate SL1, forming the first groove RS1 and the second groove RS2 may be performed through an etching process using a photoresist pattern.
The first and third lower LED units LC1a and LC1c may be exposed through the first and second grooves RS1 and RS2. In a plan view, as shown in fig. 13, a part of the region of the second bonding electrode 135b may be exposed around the first and second grooves RS1 and RS2, and in a region overlapping with these regions, the first bonding electrode 135a may be connected to corner regions C1 of the first and third lower LED units LC1a and LC1C. In addition, the corner region C2 of the remaining upper LED unit LC2 may be electrically connected to the second bonding electrode 135b.
Thereafter, referring to fig. 11D, the transparent insulating portion 160 and the wavelength converter 180 may be formed in the first groove RS1 and the second groove RS2, respectively, and the light blocking spacer 170 may be formed.
The transparent insulating portion 160 may be formed in the first groove RS1 for the first subpixel SP1, and the wavelength converter 180 may be formed in the second groove RS2 for the third subpixel SP 3. For example, the transparent insulating portion 160 may be made of a transparent resin such as silicone resin or epoxy resin or a material such as SiO 2 Is formed of silicon oxide. The wavelength converter 180 may include a transparent resin mixed with a wavelength conversion material that converts light of a first wavelength (e.g., blue light) into light of a third wavelength (e.g., red light).
In the upper light emitting structure 100B, a sub-pixel isolation region (i.e., a region between the transparent insulating portion 160, the upper LED unit LC2, and the wavelength converter 180) may be opened, and the light blocking spacer 170 may be formed by filling a light blocking material. The light blocking spacer 170 may have a grid structure formed to overlap the common electrode 135 in a vertical direction.
In an example embodiment, in the first subpixel SP1, blue light generated by the first lower LED unit LC1a may be emitted as it is through the first and second bonding insulating layers 131a and 131b and the transparent insulating portion 160, and in the third subpixel SP3, blue light generated by the third lower LED unit LC1c may pass through the first and second bonding insulating layers 131a and 131b, may be converted into red light through the wavelength converter 180, and the red light may be emitted. In the second subpixel SP2, green light may be emitted from the upper LED unit LC 2. During the driving process, the second lower LED unit LC2c may be a passive LED unit and may not emit light.
Fig. 14 is a plan view illustrating a portion of a display device according to an example embodiment. Fig. 15 is a plan view illustrating a pixel unit employed in the display device in fig. 14 according to an example embodiment.
Referring to fig. 14 and 15, the LED display device 10A according to the example embodiment may include features similar to those of the LED display device 10 shown in fig. 1 to 4, except for a configuration in which the common electrode 135' bonded to the first and second bonding electrodes may extend along the adjacent sub-pixels SP1, SP2, and SP3 in the column direction. Unless otherwise indicated, the components in the example embodiments may be understood with reference to descriptions of the same or similar components of the LED display device 10 shown in fig. 1 to 4, and duplicate descriptions may be omitted.
The common electrode 135' in example embodiments may not have a grid shape, but may have a plurality of line shapes connected to the light sources of the adjacent sub-pixels SP1, SP2, and SP3 in the column direction. A plurality of lines may be integrally connected around the pixel array 100. The common electrode 135' in example embodiments may be configured to be connected to light sources opposite to each other in a column direction. In an example embodiment, the common electrode may be connected to only sub-pixel LED units arranged in one row. The common electrode selectively drives the sub-pixels (G in FIG. 5) 1 、G 2 、……、G n ). The connection of the sub-pixels of the common electrode to the light source may be implemented in various ways.
Fig. 16 is a plan view illustrating a pixel unit employed in a display device according to an example embodiment.
Referring to fig. 16, the display panel 10B according to an example embodiment may include features similar to those in the LED display device 10 shown in fig. 1 to 4, except that the display panel 10B may include three sub-pixels SP1, SP2, and SP3 for each pixel. Unless otherwise indicated, the components in the example embodiments may be understood with reference to descriptions of the same or similar components of the LED display device 10 shown in fig. 1 to 4, and duplicate descriptions may be omitted.
Each of the plurality of pixels may include a first subpixel SP1, a second subpixel SP2, and a third subpixel SP3 disposed side by side in the horizontal direction. Each of the first, second, and third sub-pixels SP1, SP2, and SP3 may have the same rectangle.
Similar to the previous example embodiment, the first subpixel SP1 may be configured to emit blue light generated by the first lower LED unit LC1a from the transparent insulating portion 160, and the third subpixel SP3 may be configured to convert at least a portion of the blue light generated by the third lower LED unit LC1c into red light through the wavelength converter 180 and emit red light. The second subpixel SP2 may be configured to emit green light generated by the upper LED unit LC2, and the second lower LED unit LC1b disposed therebelow may be configured as a passive unit that is not driven.
Specifically, the lower light emitting structure 100A and the upper light emitting structure 100B may form the pixel array 100 by bonding the first bonding structure BS 1 and the second bonding structure BS 2. The first bonding electrode and the second bonding electrode may be bonded and a common electrode may be provided.
Fig. 17 shows an electronic apparatus including a display device according to an example embodiment.
Referring to fig. 17, an electronic device 1000 according to an example embodiment may be a glasses type display as a wearable device. The electronic device 1000 can include a pair of temples 1100, a pair of photocoupling lenses 1200, and a nosepiece 1300. The electronic apparatus 1000 may further comprise a display device 10 with an image generator.
The electronic device 1000 may be implemented as a head-mounted, glasses-type, or goggle-type Virtual Reality (VR) device, an Augmented Reality (AR) device, or a Mixed Reality (MR) device for providing a virtual reality or together providing a virtual image and an external real scene.
The temple 1100 may extend in one direction. The temples 1100 may be spaced apart from each other and may extend in parallel. The temple 1100 can be folded toward the nosepiece 1300. The bridge 1300 may be disposed between the light coupling lenses 1200 and may connect the light coupling lenses 1200 to each other. The optical coupling lens 1200 may include a light guide plate. The display device 10 may be disposed on each of the temples 1100 and may generate an image on the optical coupling lens 1200. The display device 10 may be implemented as the display device according to the above-described exemplary embodiments.
According to the above-described exemplary embodiments, an LED display device having high efficiency is provided, which can easily couple a light source for a sub-pixel to a driving substrate through a bonding process at a wafer level.
Each of the embodiments provided in the above description does not exclude the association of one or more features with another example or another embodiment also provided herein or not provided herein but consistent with the present disclosure.
While the present disclosure has been particularly shown and described with reference to embodiments thereof, it will be understood that various changes in form and details may be made therein without departing from the spirit and scope of the appended claims.

Claims (20)

1. A display device, comprising:
a circuit board including a driver circuit; and
a pixel array including a plurality of pixels on the circuit board, wherein each of the plurality of pixels includes a first subpixel, a second subpixel, and a third subpixel,
wherein the pixel array further comprises:
a lower light emitting structure, comprising:
a first lower light emitting diode unit, a second lower light emitting diode unit, and a third lower light emitting diode unit corresponding to the first sub-pixel, the second sub-pixel, and the third sub-pixel, respectively, each of the first lower light emitting diode unit, the second lower light emitting diode unit, and the third lower light emitting diode unit including a first semiconductor laminate configured to emit a first light of a first wavelength, and
A base insulating layer on lower surfaces of the first, second and third lower light emitting diode units and including an inter-unit insulating portion extending to a region between the first, second and third lower light emitting diode units;
an upper light emitting structure on the lower light emitting structure, the upper light emitting structure including:
a transparent insulating portion on the first lower light emitting diode unit,
an upper light emitting diode unit on the second lower light emitting diode unit and comprising a second semiconductor laminate configured to emit a second light of a second wavelength,
a wavelength converter on the third lower light emitting diode unit and configured to convert the first light into a third light of a third wavelength, and
a light blocking spacer disposed between the transparent insulating portion, the upper light emitting diode unit, and the wavelength converter, the light blocking spacer optically isolating the transparent insulating portion, the upper light emitting diode unit, and the wavelength converter from each other;
A first engagement structure, comprising:
a first bonding insulating layer on the upper surface of the lower light emitting structure, an
A first bonding electrode at least partially surrounded by the first bonding insulating layer and connected to each of the first, second and third lower light emitting diode units; and
a second engagement structure, comprising:
a second bonding insulating layer on the lower surface of the upper light emitting structure and bonded to the first bonding insulating layer, an
And a second bonding electrode at least partially surrounded by the second bonding insulating layer, connected to the upper light emitting diode unit, and bonded to the first bonding electrode.
2. The display device according to claim 1, wherein each of the first semiconductor laminate and the second semiconductor laminate includes a first conductive semiconductor layer, an active layer, and a second conductive semiconductor layer, and
wherein the lower light emitting structure and the upper light emitting structure are arranged such that the second conductive semiconductor layer of the first semiconductor laminate and the second conductive semiconductor layer of the second semiconductor laminate face each other.
3. The display device according to claim 2, wherein the first bonding electrode and the second bonding electrode are connected to the second conductive semiconductor layer of the first semiconductor laminate and the second conductive semiconductor layer of the second semiconductor laminate, respectively.
4. The display device of claim 2, wherein the pixel array further comprises:
a first individual electrode on a lower surface of the first lower light emitting diode unit and connected to the first conductive semiconductor layer of the first lower light emitting diode unit;
a second individual electrode penetrating the second lower light emitting diode unit, the first bonding insulating layer, the second bonding insulating layer, and a portion of the upper light emitting diode unit, and connected to the first conductive semiconductor layer of the upper light emitting diode unit; and
and a third individual electrode on a lower surface of the third lower light emitting diode unit and connected to the first conductive semiconductor layer of the third lower light emitting diode unit.
5. The display device of claim 4, wherein the second individual electrode comprises:
a feedthrough extending from a lower surface of the second lower light emitting diode unit to the first conductive semiconductor layer of the upper light emitting diode unit; and
A sidewall insulating film at least partially surrounding a side surface of the feedthrough.
6. The display device according to claim 1, wherein the first bonding electrode and the second bonding electrode include shapes corresponding to each other in a plan view.
7. The display device according to claim 6, wherein the first bonding electrode and the second bonding electrode include a grid shape in a plan view.
8. The display device according to claim 6, wherein the first bonding electrode and the second bonding electrode include a plurality of lines in a plan view.
9. The display device according to claim 1, wherein the first bonding electrode includes an upper surface substantially coplanar with an upper surface of the first bonding insulating layer, and
wherein the second bonding electrode includes a lower surface substantially coplanar with a lower surface of the second bonding insulating layer.
10. The display device according to claim 1, wherein each of the first bonding insulating layer and the second bonding insulating layer comprises a transparent insulating material.
11. The display device according to claim 1, wherein the first bonding electrode includes a grid shape in a plan view, and
Wherein the inter-cell insulating portion at least partially overlaps the first bonding electrode in a direction substantially perpendicular to an upper surface of the circuit board.
12. The display device of claim 1, wherein the base insulating layer comprises SiO 2 At least one of SiN, siCN, siOC, siON and SiOCN.
13. The display apparatus of claim 1, wherein each of the first, second, and third lower light emitting diode units includes a side surface that is inclined such that a width of each of the first, second, and third lower light emitting diode units increases as approaching the upper light emitting structure, and
wherein the upper light emitting diode unit includes a side surface inclined such that a width of the upper light emitting diode unit increases as approaching the lower light emitting structure.
14. The display device according to claim 1, wherein the light blocking spacer at least partially overlaps the second bonding electrode in a direction substantially perpendicular to an upper surface of the circuit board.
15. The display device of claim 1, wherein the first semiconductor laminate is configured to emit blue light,
wherein the second semiconductor laminate is configured to emit green light, and
wherein the wavelength converter is configured to convert at least a portion of the blue light to red light.
16. The display device according to claim 1, wherein the first sub-pixel, the second sub-pixel, and the third sub-pixel are arranged side by side in one direction in a plan view.
17. A display device, comprising:
a circuit board including a driver circuit; and
a pixel array on the circuit board and including a plurality of pixels, wherein each of the plurality of pixels includes a first sub-pixel, a second sub-pixel, and a third sub-pixel,
wherein the pixel array further comprises:
a lower light emitting structure including first, second and third lower light emitting diode units corresponding to the first, second and third sub-pixels, respectively, and configured to emit blue light,
an upper light emitting structure, comprising:
a transparent insulating portion on the first lower light emitting diode unit,
An upper light emitting diode unit on the second lower light emitting diode unit and configured to emit green light, an
A wavelength converter on the third lower light emitting diode unit and configured to convert blue light into red light,
a first engagement structure, comprising:
a first bonding insulating layer on the upper surface of the lower light emitting structure, an
A first bonding electrode at least partially surrounded by the first bonding insulating layer and connected to each of the first, second and third lower light emitting diode units, and
a second engagement structure, comprising:
a second bonding insulating layer on the lower surface of the upper light emitting structure and bonded to the first bonding insulating layer, an
And a second bonding electrode at least partially surrounded by the second bonding insulating layer, connected to the upper light emitting diode unit, and bonded to the first bonding electrode.
18. The display device of claim 17, wherein the first bonding electrode comprises a grid shape connected to each of the first, second, and third lower light emitting diode units along a boundary of the first, second, and third lower light emitting diode units.
19. The display device of claim 17, wherein the second lower light emitting diode unit is set to a passive light emitting diode unit that is not driven.
20. A display device, comprising:
a circuit board including a driver circuit; and
a pixel array including a plurality of pixels on an upper surface of the circuit board, each of the plurality of pixels including a first sub-pixel, a second sub-pixel, and a third sub-pixel,
wherein the pixel array further comprises:
a lower light emitting structure including first, second, and third lower light emitting diode units each including a first semiconductor laminate configured to emit blue light;
an upper light emitting structure on the lower light emitting structure, the upper light emitting structure including:
a transparent insulating portion on the first lower light emitting diode unit,
an upper light emitting diode unit on the second lower light emitting diode unit and comprising a second semiconductor laminate configured to generate green light, and a wavelength converter on the third lower light emitting diode unit and configured to convert blue light to red light;
A first engagement structure, comprising:
a first bonding insulating layer on the upper surface of the lower light emitting structure, an
A first bonding electrode at least partially surrounded by the first bonding insulating layer and connected to each of the first, second and third lower light emitting diode units; and
a second bonding structure on a lower surface of the upper light emitting structure, the second bonding structure comprising:
a second bonding insulating layer bonded to the first bonding insulating layer, an
A second bonding electrode at least partially surrounded by the second bonding insulating layer, connected to the upper light emitting diode unit, and bonded to the first bonding electrode,
wherein the first subpixel is configured to emit blue light generated by the first lower light emitting diode unit from the transparent insulating portion,
wherein the second sub-pixel is configured to emit green light generated by the upper light emitting diode unit, the second lower light emitting diode unit is set as a passive unit that is not driven, and
wherein the third sub-pixel is configured to convert at least a portion of blue light generated by the third lower light emitting diode unit into red light by the wavelength converter and to emit red light.
CN202310865459.7A 2022-07-15 2023-07-14 LED display device Pending CN117410304A (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
KR10-2022-0087470 2022-07-15
KR1020230013740A KR20240010386A (en) 2022-07-15 2023-02-01 Led display apparatus
KR10-2023-0013740 2023-02-01

Publications (1)

Publication Number Publication Date
CN117410304A true CN117410304A (en) 2024-01-16

Family

ID=89496838

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202310865459.7A Pending CN117410304A (en) 2022-07-15 2023-07-14 LED display device

Country Status (1)

Country Link
CN (1) CN117410304A (en)

Similar Documents

Publication Publication Date Title
US11527519B2 (en) LED unit for display and display apparatus having the same
US10797040B2 (en) Method of manufacturing display module using LED
US10770631B2 (en) Display apparatus using semi-conductor light-emitting device
KR101968592B1 (en) Integrated colour led micro-display
US20220139999A1 (en) Led display apparatus
CN112186078A (en) Method of manufacturing light emitting device package and method of manufacturing display panel using the same
US20210366981A1 (en) Led display apparatus
US11646300B2 (en) Double color micro LED display panel
JP7463662B2 (en) Image display device manufacturing method and image display device
KR20210052626A (en) Led module and method of fabricating the led module
US11935911B2 (en) Double color micro LED display panel
US20210043678A1 (en) Led display panel and led display apparatus having the same
KR20240040698A (en) Display device and method of manufacturing the same
US11476296B2 (en) Double color micro LED display panel
US20240021589A1 (en) Led display apparatus
CN117410304A (en) LED display device
KR20230020236A (en) Display apparatus
KR20240010386A (en) Led display apparatus
US20240030210A1 (en) Display apparatus
US11437353B2 (en) Light emitting device for display and display apparatus having the same
US11756940B2 (en) Light emitting device for display and display apparatus having the same
US20230215856A1 (en) Display apparatus
US20240021751A1 (en) Led module, method of manufacturing the same, and led display apparatus
CN117410391A (en) LED module, manufacturing method thereof and LED display device
KR20240010389A (en) Led module, method of fabricating the same, and led display apparatus

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication