CN117410244A - Package and packaging method thereof - Google Patents
Package and packaging method thereof Download PDFInfo
- Publication number
- CN117410244A CN117410244A CN202311196867.4A CN202311196867A CN117410244A CN 117410244 A CN117410244 A CN 117410244A CN 202311196867 A CN202311196867 A CN 202311196867A CN 117410244 A CN117410244 A CN 117410244A
- Authority
- CN
- China
- Prior art keywords
- chip
- layer
- substrate
- conductive
- pad
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000000034 method Methods 0.000 title claims abstract description 41
- 238000004806 packaging method and process Methods 0.000 title claims abstract description 24
- 239000000758 substrate Substances 0.000 claims abstract description 78
- 238000007789 sealing Methods 0.000 claims abstract description 56
- 239000010410 layer Substances 0.000 claims description 233
- 229910000679 solder Inorganic materials 0.000 claims description 74
- 230000008054 signal transmission Effects 0.000 claims description 51
- 239000011241 protective layer Substances 0.000 claims description 16
- 239000004065 semiconductor Substances 0.000 claims description 4
- 238000005538 encapsulation Methods 0.000 abstract 1
- 239000000463 material Substances 0.000 description 11
- 238000010586 diagram Methods 0.000 description 10
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 8
- 238000002360 preparation method Methods 0.000 description 7
- 238000000576 coating method Methods 0.000 description 6
- 238000009713 electroplating Methods 0.000 description 6
- 238000005530 etching Methods 0.000 description 6
- 230000010354 integration Effects 0.000 description 6
- 229910052751 metal Inorganic materials 0.000 description 6
- 239000002184 metal Substances 0.000 description 6
- 229920002120 photoresistant polymer Polymers 0.000 description 6
- 239000011248 coating agent Substances 0.000 description 5
- 239000010949 copper Substances 0.000 description 5
- 239000004642 Polyimide Substances 0.000 description 4
- 229910052802 copper Inorganic materials 0.000 description 4
- 229920001721 polyimide Polymers 0.000 description 4
- 238000004544 sputter deposition Methods 0.000 description 4
- 229910001316 Ag alloy Inorganic materials 0.000 description 3
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 3
- QCEUXSAXTBNJGO-UHFFFAOYSA-N [Ag].[Sn] Chemical compound [Ag].[Sn] QCEUXSAXTBNJGO-UHFFFAOYSA-N 0.000 description 3
- 238000004026 adhesive bonding Methods 0.000 description 3
- 229910045601 alloy Inorganic materials 0.000 description 3
- 239000000956 alloy Substances 0.000 description 3
- 238000001312 dry etching Methods 0.000 description 3
- 230000017525 heat dissipation Effects 0.000 description 3
- 239000007769 metal material Substances 0.000 description 3
- 229910001174 tin-lead alloy Inorganic materials 0.000 description 3
- 229910004298 SiO 2 Inorganic materials 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 239000000853 adhesive Substances 0.000 description 2
- 230000001070 adhesive effect Effects 0.000 description 2
- 230000005540 biological transmission Effects 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 239000004020 conductor Substances 0.000 description 2
- 238000005520 cutting process Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 230000005686 electrostatic field Effects 0.000 description 2
- 239000003292 glue Substances 0.000 description 2
- 239000010931 gold Substances 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- 239000004033 plastic Substances 0.000 description 2
- 238000007747 plating Methods 0.000 description 2
- 238000007639 printing Methods 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 230000007797 corrosion Effects 0.000 description 1
- 238000005260 corrosion Methods 0.000 description 1
- 238000005553 drilling Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 238000011221 initial treatment Methods 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 238000012536 packaging technology Methods 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 238000005476 soldering Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Chemical compound O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3157—Partial encapsulation or coating
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
The application provides a package and a packaging method thereof, wherein the package comprises a substrate, a chip, a sealing layer and a conductive layer; the chip is positioned on one side of the substrate, the nonfunctional surface of the chip faces the substrate, a first groove is formed in the nonfunctional surface of the chip, and the first groove extends from the nonfunctional surface of the chip to a first grounding pad on the functional surface of the chip; the sealing layer and the chip are arranged on the same side of the substrate, and the sealing layer is arranged around the chip; the conductive layer is positioned between the substrate and the chip and extends partially into the first groove to electrically connect the first ground pad with the second ground pad on the substrate, while the conductive layer extends from the non-functional surface of the chip to the sealing layer. The design that extends to the sealing layer from the non-functional face of chip through the conducting layer in this application for the orthographic projection of conducting layer on the base plate is greater than the orthographic projection of chip on the base plate, makes this encapsulation body can be applicable to high-power device.
Description
Technical Field
The application belongs to the field of semiconductors, and particularly relates to a packaging body and a packaging method thereof.
Background
The integrated circuit package not only plays a role in electrically connecting bonding points in the integrated circuit chip with the outside, but also provides a stable and reliable working environment for the integrated circuit chip and plays a role in protecting the integrated circuit chip mechanically or environmentally, so that the integrated circuit chip can play a normal function and has high stability and reliability.
Specifically, the package is to put the integrated circuit die on a substrate which plays a bearing role, lead out the pins, and then fix and package the die into a whole. The package not only can place, fix, seal and protect the chip and enhance the electrothermal performance, but also is a bridge for communicating the world inside the chip with external circuits, so that the packaging technology is a very critical ring for many integrated circuit products, and has important influence on the performance and exertion of the chip.
In summary, the quality of the package of the integrated circuit has a great relationship with the overall performance of the integrated circuit. Therefore, the package should have strong mechanical properties, good electrical properties, heat dissipation properties and chemical stability. The current packaging quality and packaging integration level can be further improved.
Disclosure of Invention
The application provides a package and a packaging method thereof, which can improve the packaging quality and the packaging integration level.
In order to solve the technical problems, one technical scheme adopted by the application is as follows: the application provides a package body, which comprises a substrate, a chip, a sealing layer and a conductive layer; the chip is positioned on one side of the substrate, the nonfunctional surface of the chip faces the substrate, a first groove is formed in the nonfunctional surface of the chip, and the first groove extends from the nonfunctional surface of the chip to a first grounding pad on the functional surface of the chip; the sealing layer and the chip are arranged on the same side of the substrate, and the sealing layer is arranged around the chip; the conductive layer is positioned between the substrate and the chip and extends partially into the first groove to electrically connect the first ground pad and the second ground pad on the substrate, and extends from the nonfunctional surface of the chip into the orthographic projection of the sealing layer on the substrate.
The other technical scheme adopted by the application is as follows: there is provided a packaging method, the method comprising: placing a chip on a temporary carrier plate, wherein the functional surface of the chip faces the temporary carrier plate; forming a sealing layer at the periphery of the chip; a first groove is formed in the nonfunctional surface of the chip, and extends from the nonfunctional surface of the chip to a first grounding pad on the functional surface of the chip; forming a conductive layer on the nonfunctional side of the chip, wherein a portion of the conductive layer extends into the first recess and a portion extends from the nonfunctional side of the chip onto the sealing layer; removing the temporary carrier plate; the conductive layer is electrically connected to a second ground pad on the substrate such that the first ground pad is electrically connected to the second ground pad through the conductive layer.
The beneficial effects of this application are: the conducting layer extends from the nonfunctional surface of the chip to the sealing layer, so that orthographic projection of the conducting layer on the substrate is larger than orthographic projection of the chip on the substrate, anti-interference and anti-electrostatic field impact performance of the chip are improved, the risk that the chip is broken down by an electrostatic field is reduced, the packaging body can be suitable for high-power devices, and meanwhile, the packaging body has the advantage of high integration level and wide application range.
Drawings
For a clearer description of the technical solutions in the embodiments of the present application, the drawings that are needed in the description of the embodiments will be briefly introduced below, it being obvious that the drawings in the following description are only some embodiments of the present application, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art, wherein:
FIG. 1 is a schematic diagram of an embodiment of a package of the present application;
FIG. 2 is a schematic flow chart of a method of manufacturing a package in the present application;
FIG. 3 is a schematic structural diagram of an embodiment of the step S1 in FIG. 2;
FIG. 4 is a schematic diagram of an embodiment of steps S2-S5 in FIG. 2;
fig. 5 is a schematic flow chart corresponding to step S6 in fig. 2;
FIG. 6 is a schematic diagram illustrating an embodiment of the steps shown in FIG. 5;
FIG. 7 is a schematic diagram of an embodiment of the step S7 in FIG. 2;
FIG. 8 is a schematic flow chart of step S8 in FIG. 2;
FIG. 9 is a schematic diagram illustrating an embodiment of the steps shown in FIG. 8;
FIG. 10 is a schematic flow chart of step S9 in FIG. 2;
FIG. 11 is a schematic diagram illustrating an embodiment of the steps shown in FIG. 10;
FIG. 12 is a schematic diagram of an embodiment corresponding to the step S10 in FIG. 2;
fig. 13 is a schematic flow chart of step S11 in fig. 2;
FIG. 14 is a schematic diagram illustrating an embodiment of the steps shown in FIG. 13;
FIG. 15 is a schematic diagram of an embodiment of the step S12 in FIG. 2;
reference numerals illustrate: 1, a substrate; 11 second ground pads; a second signal transmission pad 12; 13 first solder balls; 14 first underfill; 2, a chip; 21 a nonfunctional surface; 22 functional surfaces; 23 a first groove; 24 first ground pads; 25 first signal transmission pads; 26 second solder balls; 261 second solder; 27 a second insulating layer; 28 a second opening; 29 conductive blocks; 3, sealing layers; 31 through grooves; 32 conductive posts; 4 a conductive layer; 5 a first insulating layer; 51 a first opening; 6, a solder layer; 7, rewiring layers; 8, temporary carrier plates; 81 a protective layer; 82 slides; and 9, second underfill.
Detailed Description
The following description of the technical solutions in the embodiments of the present application will be made clearly and completely with reference to the accompanying drawings in the embodiments of the present application, and it is apparent that the described embodiments are only some embodiments of the present application, not all embodiments. All other embodiments, which can be made by one of ordinary skill in the art without undue burden from the present disclosure, are within the scope of the present disclosure.
Referring to fig. 1, the present application provides a package, which includes a substrate 1, a chip 2, a sealing layer 3, and a conductive layer 4; wherein, the chip 2 is located on one side of the substrate 1, the non-functional surface 21 of the chip 2 faces the substrate 1, the non-functional surface 21 of the chip 2 is provided with a first groove 23, and the first groove 23 extends from the non-functional surface 21 of the chip 2 to a first grounding pad 24 on the functional surface 22 of the chip 2; the sealing layer 3 is arranged on the same side of the substrate 1 as the chip 2, and the sealing layer 3 is arranged around the chip 2; the conductive layer 4 is located between the substrate 1 and the chip 2 and extends partly into the first recess 23 to electrically connect the first ground pad 24 with the second ground pad 11 on the substrate 1, while the conductive layer 4 extends from the non-functional surface 21 of the chip 2 into the orthographic projection of the sealing layer 3 on the substrate 1.
Specifically, the substrate 1 can provide the effects of electrical connection, protection, support, heat dissipation, assembly, etc. for the chip 2, so as to achieve the purposes of various connection modes, reduced volume of packaged products, and improved electrical performance and heat dissipation performance.
The chip 2 is located on the side of the substrate 1, the non-functional surface 21 of the chip 2 faces the substrate 1 such that the functional surface 22 of the chip 2 faces away from the substrate 1, the non-functional surface 21 of the chip 2 is provided with a first recess 23, and the first recess 23 extends from the non-functional surface 21 of the chip 2 to a first ground pad 24 on the functional surface 22 of the chip 2. That is, the first ground pad 24 is exposed in the first groove 23.
The sealing layer 3 and the chip 2 are both positioned on the same side of the substrate 1, and the sealing layer 3 surrounds the chip 2, so that the sealing layer 3 can protect the chip 2, prevent water vapor from entering and damaging the chip 2, and ensure the overall performance of the packaging body. The sealing layer 3 also provides support for the design of the conductive layer 4, and the conductive layer 4 is electrically connected between the substrate 1 and the chip 2, specifically, the conductive layer 4 is arranged between the substrate 1 and the chip 2 and extends into the first groove 23 to be connected with the first grounding pad 24 of the chip 2, and the other part is connected with the second grounding pad 11 on the substrate 1 to play a role of conducting a connection path between the first grounding pad 24 and the second grounding pad 11. In addition, the conducting layer 4 extends from the non-functional surface 21 of the chip 2 to the orthographic projection of the sealing layer 3 on the substrate 1, so that the orthographic projection of the conducting layer 4 on the substrate 1 is larger than the orthographic projection of the chip 2 on the substrate 1, the grounding area of the chip 2 can be increased, the anti-interference and anti-electrostatic field impact performance of the chip can be improved, the risk of the chip being broken down by an electrostatic field can be reduced, the package can be suitable for high-power devices, and meanwhile, the package has the advantage of high integration level and wide application range.
With continued reference to fig. 1, the conductive layer 4 fills the first recess 23, that is, the first recess 23 is filled with the conductive layer 4, which can reduce the transmission resistance of the conductive layer 4 and ensure the transmission safety. Of course, in other embodiments, the conductive layer 4 may not fill the first groove 23, for example, in this case, the conductive layer 4 is formed on a wall of the first groove 23, so long as the conductive layer 4 extends into the first groove 23 and is electrically connected to the first ground pad 24.
With continued reference to fig. 1, in one embodiment, the package further includes a first insulating layer 5, the first insulating layer 5 is located between the conductive layer 4 and the chip 2, and is provided with a first opening 51 communicating with the first recess 23, and the conductive layer 4 extends from the first opening 51 into the first recess 23. Wherein the first insulating layer 5 may be used to ensure insulating properties between the chip 2 and the conductive layer 4 at both side positions thereof, while the first opening 51 provided in the first insulating layer 5 may allow the conductive layer 4 to extend into the first recess 23. Wherein the size of the first opening 51 may be matched to the size of the first recess 23.
With continued reference to fig. 1, in one embodiment, the package further includes a solder layer 6, the solder layer 6 being located between the conductive layer 4 and the substrate 1 for electrically connecting the conductive layer 4 and a second ground pad 11 on the substrate 1. That is, the solder layer 6 is used to solder the conductive layer 4 and the second ground pad 11 on the substrate 1 together. The orthographic projection of the solder layer 6 on the substrate 1 may coincide with the second ground pad 11, however, in other embodiments, the orthographic projection of the solder layer 6 on the substrate 1 may be larger than the area of the second ground pad 11 or smaller than the area of the second ground pad 11. Wherein the solder layer 6 is made of an electrically conductive material.
In an embodiment, the orthographic projection of the second ground pad 11 on the substrate 1 is larger than the orthographic projection of the first ground pad 24 on the substrate 1, by which the electrical signal of the first ground pad 24 in the chip 2 can be effectively transmitted through the second ground pad 11, and the area of the second ground pad 11 is larger, so that the ground area of the chip 2 can be increased, and the anti-interference and anti-electrostatic field impact performance of the chip 2 is improved.
With continued reference to fig. 1, the sealing layer 3 is provided with a through groove 31, and the package further includes a rewiring layer 7 and a conductive post 32, wherein the rewiring layer 7 is located on one side of the chip 2 and the sealing layer 3 away from the substrate 1, and is electrically connected with the first signal transmission pad 25 on the functional surface 22 of the chip 2; the conductive posts 32 are disposed in the through grooves 31, and the first ends of the conductive posts 32 are electrically connected to the rewiring layer 7 and the second ends are electrically connected to the second signal transmission pads 12 on the substrate 1.
Specifically, the rewiring layer 7 is electrically connected to the first signal transmission pad 25 on the functional surface 22 of the chip 2, so that the rewiring layer 7 can lead out an electrical signal on the first signal transmission pad 25 on the chip 2. The combination of the rewiring layer 7 and the conductive columns 32 realizes electric signal conduction between the first signal transmission bonding pad 25 and the second signal transmission bonding pad 12, so that the Fan-out design is realized, the wire bonding mode in the prior art is replaced by the rewiring layer 7 and the conductive columns 32, the process is simple, and the area of the package body can be reduced.
With continued reference to fig. 1, in one embodiment, the second end of the conductive post 32 is provided with a first solder ball 13, and the first solder ball 13 electrically connects the conductive post 32 with the second signal transmission pad 12. Wherein the first solder balls 13 may be formed by reflow at the time of preparation, and may serve to fixedly connect the conductive pillars 32 and the second signal transmission pads 12.
In an embodiment, the package further comprises a first underfill 14, which fills in the gap between the sealing layer 3 and the substrate 1. Specifically, the first underfill 14 filled between the sealing layer 3 and the substrate 1 surrounds the first solder balls 13, and wraps the periphery of the conductive layer 4, the first insulating layer 5 and the solder layer 6, so that effective filling of the positions between the first solder balls 13 and the conductive layer 4 is facilitated, and structural stability of the package is protected.
With continued reference to fig. 1, the first signal transmission pad 25 of the chip 2 is provided with a second solder ball 26, and the second solder ball 26 is electrically connected to the rewiring layer 7 and the first signal transmission pad 25. Specifically, the second solder balls 26 are made of a conductive material, and thus electrical signal conduction between the rewiring layer 7 and the first signal transmission pads 25 can be achieved.
With continued reference to fig. 1, in one embodiment, the package further includes a second insulating layer 27 and a conductive block 29, the second insulating layer 27 being located between the chip 2 and the rewiring layer 7, and having a second opening 28 exposing the first signal transmission pad 25; the conductive bump 29 is disposed in the second opening 28 and electrically connected to the first signal transmission pad 25, wherein the second solder ball 26 is disposed on a side surface of the conductive bump 29 facing away from the chip 2.
Specifically, the second insulating layer 27 functions to isolate the chip 2 from the rewiring layer 7 so that the circuit between the chip 2 and the rewiring layer 7 does not cross-talk. Since the second insulating layer 27 is located on the functional surface 22 side of the chip 2, by providing the second opening 28 in the second insulating layer 27 at the position of the first signal transmission pad 25 and providing the conductive block 29 in the second opening 28, the electrical signal on the first signal transmission pad 25 is transmitted to the rewiring layer 7 through the conductive block 29, which is easy to prepare, and the electrical signal on the first signal transmission pad 25 in the chip 2 can be effectively led out to the rewiring layer 7.
With continued reference to fig. 1, the package further includes a protective layer 81, where the protective layer 81 is located on a side of the rewiring layer 7 away from the substrate 1; by providing the protective layer 81 on the side of the rewiring layer 7 facing away from the substrate 1, protection of the rewiring layer 7 is facilitated.
With continued reference to fig. 1, in an embodiment, the package further includes a second underfill 9 that fills the gap between the chip 2 and the protection layer 81. Specifically, the second underfill 9 is disposed around the second solder balls 26, so as to ensure the stability of the positional relationship between the second solder balls 26 and the chip 2, and in addition, prevent moisture from invading to damage the second solder balls 26, and improve the overall structural stability of the package.
Referring to fig. 2, the present application further provides a packaging method, which includes:
s1: a rewiring layer 7 is formed on the temporary carrier plate 8.
Referring to fig. 2 and 3, as shown in fig. 3, the temporary carrier plate 8 includes a carrier sheet 82 and a protective layer 81 that are stacked, specifically, the protective layer 81 may be prepared by coating a temporary bonding adhesive on the carrier sheet 82 and then preparing the protective layer 81 on a side of the temporary bonding adhesive facing away from the carrier sheet 82, and in an embodiment, the protective layer 81 may be prepared by coating, and the protective layer 81 may be a Polyimide (PI) film layer.
The preparation of the rewiring layer 7 may be performed by sputtering a seed layer, reserving a preparation position of the rewiring layer 7 on the protective layer 81 by adopting a gluing, exposing and developing mode, preparing the rewiring layer 7 by adopting an electroplating mode, removing the residual part of the seed layer by adopting a photoresist removing, metal etching and other modes, completing the preparation of the rewiring layer 7, and preparing the rewiring layer 7, wherein the material of the rewiring layer 7 may comprise at least one of copper (Cu), aluminum (Al), nickel (Ni), gold (Au) and other metal materials, as shown in fig. 3.
S2: a second insulating layer 27 is formed on the functional surface 22 of the chip 2.
Specifically, the wafer (the material of which may be silicon or a compound semiconductor) includes a plurality of chips 2, and at the time of preparation, in the present embodiment, the second insulating layer 27 is formed on the functional surface of the wafer, thereby realizing the formation of the second insulating layer 27 on the functional surface of the chips 2.
Of course, in other embodiments, the wafer may be cut first to obtain a plurality of independent chips 2, and then the second insulating layer 27 may be formed on the functional surface 22 of the chips 2.
Wherein the material of the second insulating layer 27 may be silicon dioxide (SiO 2 ) A photopolymer glue, such as PI glue, is also possible.
The second insulating layer 27 may be formed by any method, such as a CVD (chemical vapor deposition) process, or a coating process.
S3: a second opening 28 exposing the first signal transmission pad 25 is opened in the second insulating layer 27.
As shown in fig. 4, a second opening 28, i.e., a window, is prepared in the second insulating layer 27 at a position corresponding to the first signal transmission pad 25 to expose the pad of the chip 2 for subsequent signal transmission. Specifically, when the material of the second insulating layer 27 is SiO 2 When the window is opened, the modes of gluing, photoetching and dry etching can be adopted; when the material of the second insulating layer 27 is PI, the windowing may be performed by using a photolithography and development process.
S4: a conductive bump 29 electrically connected to the first signal transmission pad 25 is formed in the second opening 28, and the second solder ball 26 is subsequently formed on the conductive bump 29.
As shown in fig. 4, a conductive block 29 is prepared in the second opening 28, and the conductive block 29 and the first signal transmission pad 25 are electrically connected. The conductive block 29 may be formed by sputtering a seed layer, coating, exposing, developing, electroplating, photoresist removing, metal etching, removing the seed layer, and the like, and the material of the conductive block 29 may include one or more of metal materials such as Cu, al, ni, au.
S5: second solder balls 26 are formed on the first signal transmission pads 25 of the chip 2, and the subsequent chip 2 is electrically connected to the rewiring layer 7 through the second solder balls 26.
As shown in fig. 4, the second solder 261 is coated on the conductive block 29, and the second solder 261 may be prepared by an electroplating process, and the second solder ball 26 is prepared by a reflow (reflow) process. The second solder balls 26 are shown in fig. 4. The solder may be tin or a tin-containing alloy, such as a tin-silver alloy, a tin-lead alloy. After the second solder balls 26 are prepared, the chip 2 and the rewiring layer 7 can be connected through the second solder balls 26.
Then, the chips 2 on the wafer are diced to obtain individual chips 2 from which the second solder balls 26 have been prepared.
S6: the chip 2 is placed on a temporary carrier plate 8 with the functional surface 22 of the chip 2 facing said temporary carrier plate 8.
Referring to fig. 5 and 6, specifically, step S6 includes:
s61: the chip 2 is placed on the side of the rewiring layer 7 facing away from the temporary carrier plate 8 and the first signal transmission pads 25 on the functional side 22 of the chip 2 are electrically connected to the rewiring layer 7.
As shown in fig. 6, the chip 2 is electrically connected to the rewiring layer 7 through the second solder balls 26. The second solder balls 26 contain tin material, and tin soldering can firmly bond the metal material, and has better conductivity and corrosion resistance. The second solder balls 26 can thus fixedly connect the chip 2 to the rewiring layer 7, so that the first signal transmission pads 25 on the functional surface 22 of the chip 2 are electrically connected to the rewiring layer 7.
S62: a second underfill 9 is filled in the gap between the chip 2 and the temporary carrier plate 8.
The second underfill 9 may be prepared by a dispensing process, specifically, as shown in fig. 6, the underfill is filled between the chip 2 and the temporary carrier 8, and cured at a high temperature, so that the second underfill 9 wraps the second solder balls 26, and the filling effect is good.
S7: a sealing layer 3 is formed at the periphery of the chip 2.
Referring to fig. 7, the sealing layer 3 may protect the chip 2 from moisture, and specifically, step S7 includes:
s71: a sealing layer 3 is formed on the periphery of the chip 2, and the orthographic projection of the sealing layer 3 on the temporary carrier plate 8 overlaps with the orthographic projection of the rewiring layer 7 on the temporary carrier plate 8.
The sealing layer 3 is located at the periphery of the chip 2 to protect the chip 2 from external moisture, while the orthographic projection of the sealing layer 3 on the temporary carrier plate 8 overlaps with the orthographic projection of the rewiring layer 7 on the temporary carrier plate 8, so that the sealing layer 3 protects at least part of the rewiring layer 7 protruding out of the chip 2.
S8: a first recess 23 is provided in the non-functional surface 21 of the chip 2, the first recess 23 extending from the non-functional surface 21 of the chip 2 to a first ground pad 24 on the functional surface 22 of the chip 2.
Referring to fig. 8 and 9, step S8 includes:
s81: a first insulating layer 5 is formed on the nonfunctional surface 21 of the chip 2.
As shown in fig. 9, a first insulating layer 5 is formed on the side of the chip 2 facing away from the temporary carrier plate 8, i.e. the first insulating layer 5 covers the non-functional surface 21 of the chip 2.
S82: a first opening 51 is formed on the first insulating layer 5 to expose the nonfunctional surface 21 of the chip 2, and a first recess 23 is formed on the exposed nonfunctional surface 21.
As shown in fig. 9, first openings 51 are formed in the first insulating layer 5 at positions corresponding to the first grounding pads 24 to expose the nonfunctional surface 21 of the chip 2, then first grooves 23 are formed on the exposed nonfunctional surface 21 of the chip 2, and the first grooves 23 extend to the first grounding pads 24.
Of course, in other embodiments, the first opening 51 and the first recess 23 may be prepared simultaneously. The first groove 23 may be formed by a process such as photoresist coating, photolithography, dry etching (deep ion reaction etching), etc., and after the first ground pad 24 is exposed, the preparation of the first groove 23 is completed, and then the material, such as photoresist, required for preparing the first groove 23 is removed.
S9: the conductive layer 4 is formed on the non-functional side 21 of the chip 2, wherein a part of the conductive layer 4 extends into the first recess 23 and a part extends from the non-functional side 21 of the chip 2 onto the sealing layer 3.
Referring to fig. 10 and 11, step S9 specifically includes:
s91: a conductive layer 4 is formed on the side of the first insulating layer 5 facing away from the chip 2.
As shown in fig. 11, the conductive layer 4 leads out the ground signal on the first ground pad 24, and part of the conductive layer 4 extends into the first groove 23 and part of the conductive layer extends from the nonfunctional surface 21 of the chip 2 to the sealing layer 3; meanwhile, the orthographic projection of the conductive layer 4 on the temporary carrier plate 8 is larger than that of the chip 2 on the temporary carrier plate 8, so that the conductive layer 4 protrudes out of the chip 2 and extends to the sealing layer 3 partially.
The conductive layer 4 may be formed by sputtering a seed layer, gluing, exposing, developing, electroplating, photoresist removing, metal etching, and the like, and the material of the conductive layer 4 may be metal, specifically, one or more of Cu, al, ni, au, and the like.
After step S9, further comprising:
s92: a through groove 31 exposing the rewiring layer 7 is formed in the sealing layer 3.
As shown in fig. 11, a through groove 31 is formed in the sealing layer 3 at a position corresponding to the rewiring layer 7 so as to expose at least a part of the rewiring layer 7. The process of forming the through groove 31 may be laser drilling, laser induced etching, dry etching, or the like, and is not limited thereto.
S93: conductive posts 32 electrically connected to the rewiring layer 7 are formed in the through grooves 31.
As shown in fig. 11, the conductive post 32 is electrically connected to the rewiring layer 7. The conductive pillars 32 may be formed by sputtering a seed layer, coating, exposing, developing, electroplating, photoresist removing, metal etching, and the like, and the material of the conductive pillars 32 may be one or more metals, such as Cu, al, ni, au.
S94: first solder balls 13 are formed on the conductive pillars 32 such that subsequent conductive pillars 32 are electrically connected to the second signal transmission pads 12 through the first solder balls 13.
As shown in fig. 11, the first solder ball 13 on the conductive post 32 may be manufactured through a printing, ball-plating or electroplating process, and a reflow process, and the solder of the first solder ball 13 may be tin or a tin-containing alloy, such as a tin-silver alloy, a tin-lead alloy, or the like. The subsequent conductive post 32 is connected with the second signal transmission pad 12 through the first solder ball 13, so as to realize electric signal transmission.
S95: forming a solder layer 6 on the side of the conductive layer 4 facing away from the chip 2;
as shown in fig. 11, the solder layer 6 is manufactured by applying solder through a printing or plating process and then through a reflow process, and the solder of the solder layer 6 may be tin or a tin-containing alloy such as a tin-silver alloy, a tin-lead alloy. So that the solder layer 6 can play a role in connection and electrical signal transmission.
In an embodiment, the first solder ball 13 and the solder layer 6 may be manufactured simultaneously using the same material and the same process, although they may be manufactured separately.
S10: the temporary carrier plate 8 is removed.
Referring to fig. 12, the temporary carrier plate 8 includes a carrier sheet 82 and a protective layer 81 that are stacked; specifically, step S10 includes:
s101: the slide 82 is removed.
The carrier 82 provides support for the fabrication of the structure in the above steps, and the volume of the package can be further reduced by removing the carrier 82. In addition, the protective layer 81 remains in the package, and can protect the rewiring layer 7 and the chip 2.
Specifically, the removal of the carrier sheet 82 may remove the carrier sheet 82 and the bonding paste by a debonding process, leaving the protective layer 81 of the temporary carrier sheet 8 in the package.
In one embodiment, after removing the carrier 82, individual encapsulated chips 2 are obtained by cutting the sealing layer 3.
S11: the conductive layer 4 is electrically connected to the second ground pad 11 on the substrate 1 such that the first ground pad 24 is electrically connected to the second ground pad 11 through the conductive layer 4.
Referring to fig. 13 and 14, specifically, step S11 includes:
s111: the solder layer 6 is electrically connected to a second ground pad 11 on the substrate 1.
As shown in fig. 14, after the solder layer 6 and the second ground pad 11 are aligned, the solder layer 6 and the second ground pad 11 may be electrically connected by a reflow process, so as to realize signal transmission.
At the same time of step S11, the method further comprises:
s112: the conductive posts 32 are electrically connected to the second signal transmission pads 12 on the substrate 1.
As shown in fig. 14, the first solder ball 13 and the second signal transmission pad 12 are aligned, and the first solder ball 13 and the second signal transmission pad 12 can be electrically connected by a reflow process, so that signal transmission is realized.
S12: the gap between the sealing layer 3 and the substrate 1 is filled with a first underfill 14.
Referring to fig. 15, a first underfill 14 is prepared, which is located at the gap between the sealing layer 3 and the substrate 1 and wraps the first solder balls 13 to protect the overall structural stability of the package. Specifically, the first underfill 14 may be filled between the chip 2 and the substrate 1 by a dispensing process, and cured at a high temperature, thereby completing the preparation of the first underfill 14.
In the package body in this application, extend to sealing layer 3 from the non-functional face 21 of chip 2 through conducting layer 4 for conducting layer 4 orthographic projection on base plate 1 is greater than the orthographic projection of chip 2 on base plate 1, therefore this package body can be applicable to high-power device, and has the advantage that the integrated level is high, and the range of application is wide. Meanwhile, the package body in the application has the advantages of high package integration level, small package volume, strong systematicness, high power density and the like, and caters to the development trend of miniaturization, complicating and integration of integrated circuits. In addition, in the packaging method in the application, by arranging the non-functional surface 21 of the chip 2 opposite to the substrate 1, cutting a single chip on the wafer after primary treatment (to prepare the second solder ball 26), and then performing plastic packaging, so that the conductive layer 4 can extend to the sealing layer 3, and the grounding area of the first grounding pad 24 in the chip 2 is enlarged; after plastic packaging, the chips 2 are cut again, after a single chip 2 is obtained, a fan-out technology is applied to lead out signals in the chips 2, and a package body which is small in size and applicable to high-power devices is prepared.
The foregoing description is only exemplary embodiments of the present application and is not intended to limit the scope of the present application, and all equivalent structures or equivalent processes using the descriptions and the drawings of the present application, or direct or indirect application in other related technical fields are included in the scope of the present application.
Claims (10)
1. A package, the package comprising:
a substrate;
the chip is positioned on one side of the substrate, the nonfunctional surface of the chip faces the substrate, a first groove is formed in the nonfunctional surface of the chip, and the first groove extends from the nonfunctional surface of the chip to a first grounding pad on the functional surface of the chip;
a sealing layer disposed on the same side of the substrate as the chip, the sealing layer being disposed around the chip;
and the conducting layer is positioned between the substrate and the chip and extends into the first groove partially so as to electrically connect the first grounding pad and the second grounding pad on the substrate, and simultaneously extends from the nonfunctional surface of the chip to the orthographic projection of the sealing layer on the substrate.
2. The package of claim 1, wherein the package is a semiconductor device,
the conductive layer fills the first groove;
preferably, the package further includes a first insulating layer located between the conductive layer and the chip, and provided with a first opening communicating with the first groove, and the conductive layer extends from the first opening into the first groove;
preferably, the package further includes a solder layer between the conductive layer and the substrate, electrically connecting the conductive layer and the second ground pad on the substrate;
preferably, the orthographic projection of the second grounding pad on the substrate is larger than the orthographic projection of the first grounding pad on the substrate.
3. The package of claim 1, wherein the package is a semiconductor device,
the sealing layer is provided with a through groove, and the packaging body further comprises:
the rewiring layer is positioned on one side of the chip and the sealing layer, which is away from the substrate, and is electrically connected with the first signal transmission bonding pad on the functional surface of the chip;
the conductive column is arranged in the through groove, the first end of the conductive column is electrically connected with the rewiring layer, and the second end of the conductive column is electrically connected with the second signal transmission bonding pad on the substrate;
preferably, a first solder ball is arranged on the second end of the conductive column, and the first solder ball is electrically connected with the conductive column and the second signal transmission pad;
preferably, the package further includes a first underfill filled at a gap between the sealing layer and the substrate.
4. The package of claim 3, wherein the package,
a second solder ball is arranged on the first signal transmission bonding pad of the chip, and the second solder ball is electrically connected with the rewiring layer and the first signal transmission bonding pad;
preferably, the package further includes:
a second insulating layer, which is positioned between the chip and the rewiring layer and is provided with a second opening exposing the first signal transmission pad;
and the conductive block is arranged in the second opening and is electrically connected with the first signal transmission pad, and the second solder ball is arranged on the conductive block.
5. The package of claim 3, wherein the package further comprises:
the protective layer is positioned on one side of the rewiring layer, which is away from the substrate;
preferably, the package further includes:
and the second underfill is filled in the gap between the chip and the protective layer.
6. A method of packaging, the method comprising:
placing a chip on a temporary carrier plate, wherein the functional surface of the chip faces the temporary carrier plate;
forming a sealing layer on the periphery of the chip;
a first groove is formed in the nonfunctional surface of the chip, and extends from the nonfunctional surface of the chip to a first grounding pad on the functional surface of the chip;
forming a conductive layer on the nonfunctional side of the chip, wherein a portion of the conductive layer extends into the first recess and a portion extends from the nonfunctional side of the chip onto the sealing layer;
removing the temporary carrier plate;
the conductive layer is electrically connected to a second ground pad on the substrate such that the first ground pad is electrically connected to the second ground pad through the conductive layer.
7. The method of packaging of claim 6, wherein the step of providing a first recess in the nonfunctional surface of the chip comprises:
forming a first insulating layer on a non-functional surface of the chip;
forming a first opening on the first insulating layer to expose the nonfunctional surface of the chip, and forming the first groove on the exposed nonfunctional surface;
the step of forming a conductive layer on the nonfunctional surface of the chip includes:
and forming the conductive layer on one side of the first insulating layer, which is away from the chip.
8. The packaging method of claim 6, further comprising, prior to said placing the chip on the temporary carrier: forming a rewiring layer on the temporary carrier plate;
the step of placing the chip on the temporary carrier plate comprises the following steps: placing the chip on one side of the rewiring layer, which is away from the temporary carrier plate, and enabling a first signal transmission bonding pad on the chip functional surface to be electrically connected with the rewiring layer;
the step of forming a sealing layer on the periphery of the chip comprises the following steps:
forming the sealing layer on the periphery of the chip, wherein the orthographic projection of the sealing layer on the temporary carrier plate overlaps with the orthographic projection of the rewiring layer on the temporary carrier plate;
after forming the conductive layer on the non-functional surface of the chip, the method further comprises:
a through groove exposing the rewiring layer is formed in the sealing layer;
forming a conductive post in the via, the conductive post being electrically connected to the rewiring layer;
preferably, after forming the conductive layer on the non-functional surface of the chip, the method further includes:
forming a first solder ball on the conductive column so that the subsequent conductive column is electrically connected with a second signal transmission pad through the first solder ball; and/or;
forming a solder layer on one side of the conductive layer away from the chip;
while the conductive layer is electrically connected with the second grounding pad on the substrate, the method further comprises:
electrically connecting the conductive posts with second signal transmission pads on the substrate;
preferably, the step of electrically connecting the conductive layer with a second ground pad on the substrate includes:
electrically connecting the solder layer with the second grounding pad on the substrate;
preferably, after the electrically connecting the conductive post with the second signal transmission pad on the substrate, the method further comprises:
and filling a first underfill at a gap between the sealing layer and the substrate.
9. The packaging method of claim 8, further comprising, prior to said placing the chip on the temporary carrier:
forming a second solder ball on the first signal transmission pad of the chip, and electrically connecting the chip with the rewiring layer through the second solder ball;
preferably, before forming the second solder balls on the first signal transmission pads of the chip, the method further comprises:
forming a second insulating layer on the functional surface of the chip;
a second opening exposing the first signal transmission pad is formed in the second insulating layer;
and forming a conductive block electrically connected with the first signal transmission pad in the second opening, wherein the second solder ball is formed on the conductive block later.
10. The packaging method of claim 8, wherein the temporary carrier plate comprises a carrier sheet and a protective layer arranged in a stacked manner;
the step of removing the temporary carrier plate comprises the following steps:
removing the slide;
preferably, after the placing the chip on the side of the rewiring layer facing away from the temporary carrier board and electrically connecting the first signal transmission pad on the functional surface of the chip with the rewiring layer, the method further includes:
and filling a second underfill in a gap between the chip and the temporary carrier plate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202311196867.4A CN117410244A (en) | 2023-09-15 | 2023-09-15 | Package and packaging method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202311196867.4A CN117410244A (en) | 2023-09-15 | 2023-09-15 | Package and packaging method thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN117410244A true CN117410244A (en) | 2024-01-16 |
Family
ID=89499078
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202311196867.4A Pending CN117410244A (en) | 2023-09-15 | 2023-09-15 | Package and packaging method thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN117410244A (en) |
-
2023
- 2023-09-15 CN CN202311196867.4A patent/CN117410244A/en active Pending
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US9165878B2 (en) | Semiconductor packages and methods of packaging semiconductor devices | |
| US7205674B2 (en) | Semiconductor package with build-up layers formed on chip and fabrication method of the semiconductor package | |
| JP5280014B2 (en) | Semiconductor device and manufacturing method thereof | |
| CN105428265A (en) | Manufacturing method for semiconductor device | |
| KR20170009674A (en) | Semiconductor device and method of manufactures | |
| CN109755188A (en) | Encapsulating structure and its manufacturing method | |
| KR20010083204A (en) | Semiconductor device and method for fabricating the same | |
| US20240006325A1 (en) | Method of fabricating a semiconductor package | |
| US20070023886A1 (en) | Method for producing a chip arrangement, a chip arrangement and a multichip device | |
| KR101532816B1 (en) | Semiconductor packages and methods of packaging semiconductor devices | |
| US8176628B1 (en) | Protruding post substrate package structure and method | |
| KR101858954B1 (en) | Semiconductor package and method of manufacturing the same | |
| KR20200018357A (en) | Emi shielding for flip chip package with exposed die backside | |
| KR102586794B1 (en) | Semiconductor package and a method for manufacturing the same | |
| US8344495B2 (en) | Integrated circuit packaging system with interconnect and method of manufacture thereof | |
| TW201543583A (en) | Integrated circuit packaging system with vialess substrate and method of manufacture thereof | |
| KR101837514B1 (en) | Semiconductor package, method of manufacturing the same and system in package | |
| CN111725146A (en) | Electronic package and manufacturing method thereof | |
| US20220344300A1 (en) | Electronic device and manufacturing method thereof | |
| JP4084737B2 (en) | Semiconductor device | |
| US20190214367A1 (en) | Stacked package and a manufacturing method of the same | |
| CN117410244A (en) | Package and packaging method thereof | |
| TWI435429B (en) | Semiconductor package with holes through holes | |
| KR19980025624A (en) | Ball Grid Array Semiconductor Package | |
| JP2002261192A (en) | Wafer level csp |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination |