CN117408199A - Hierarchical time sequence model extraction method based on HSM - Google Patents
Hierarchical time sequence model extraction method based on HSM Download PDFInfo
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Abstract
The invention provides a hierarchical time sequence model extraction method based on HSM, belongs to the field of integrated circuit chip time sequence models, and aims to solve the problems of accuracy and analysis efficiency of time sequence analysis caused by tedious data files in the chip design process. The method comprises the following steps: according to the key data of the digital integrated circuit design, identifying; generating an analysis environment of the integrated circuit according to the analysis environment; extracting parasitic parameters aiming at the digital integrated circuit and reversely marking the parasitic parameters into the digital integrated circuit; extracting a super-large-scale time sequence model; and extracting timing sequence models of the same type from the timing sequence library, and carrying out merging optimization. According to the method and the device, the module time sequence is calculated and extracted, the time sequence interfaces are divided and combined into one time sequence model file, and therefore the number of the time sequence model files is reduced. Under the hierarchical design of the chip, the running time and memory occupation of the tool can be reduced, the design integration level of the time sequence model of the wiring tool can be improved, and the design period of the digital integrated circuit can be reduced.
Description
Technical Field
The invention belongs to the field of digital chip design, and particularly relates to a hierarchical time sequence model extraction method based on HSM.
Background
In the chip manufacturing process, the difference of the electrical characteristic parameters of each wafer can lead to the difference of delay between the gate unit and the metal wire, and the deviation can lead to the difference between the theoretical value and the actual value of each parameter of the chip. Process variation can be categorized into systematic variation and non-systematic variation. Systematic deviation is derived from or chemical mechanical or optical proximity correction, and the deviation is introduced in each manufacturing link, so that the linear change relation of the process, voltage and temperature (PVT) can be accurately predicted and corrected; rather than systematic deviations occurring randomly in the various steps of fabrication, modeling cannot be easily performed because it appears statistically completely random, independent, and lacks obvious correlation. Non-systematic variations can be categorized into global variations (inter-chip variations) and local variations (intra-chip variations), where inter-chip variations are due to process variations, equipment non-uniformities, etc. in the manufacturing process. While on-chip variations result from random dopant fluctuations in process, line edge roughness, oxide thickness variations, and internal voltage drops in voltage and junction temperature variations in temperature. If the on-chip bias is ignored during the design process, a later silicon failure may be induced. The source of the bias obviously makes analysis and simulation of the digital circuit design more difficult, so the bias must be considered more accurately during timing analysis.
In summary, as the complexity and scale of chip designs increases, timing analysis becomes a critical challenge. Advanced process design improves the difficulty of back-end design, and the traditional time sequence analysis method often faces the problems of high calculation complexity and low analysis efficiency, and the time sequence problems may cause performance degradation, increased power consumption, circuit faults and the like. Therefore, in order to shorten the design cycle, improve performance, reduce power consumption, reduce circuit failures, and improve product competitiveness, an effective solution is needed to improve the accuracy and efficiency of timing analysis.
The existing hierarchical design model mainly adopts the following steps: extracting a timing model (Extracted Timing Models, ETM) technique; rapid timing model Quick Timing Model (QTM) technique; very large scale timing model (Hyperscales Models, HSM) techniques.
ETM is a block timing model that is directly extracted from a lower level block netlist (e.g., a single IP design element (Intellectual Property Design, IP design)). The model consists of the clock of the block, a set of timing arcs between the input and output pins. The model may be used in place of the complete block netlist, and the reduction coefficients (Derating) may be increased or decreased according to each ETM in accordance with its on-chip bias for analysis at the next higher level. ETM are portable and can be easily exported to other tools, so they are typically used to represent the timing of IP design elements. Since ETM consists of only timing arcs, the internal logic of the block can be kept secret. From the outside, an ETM looks like a black box, only the ports of the model can be seen. It retains information such as setup time and hold time of the input to the output path group. A library of ETM model-like elements can be populated with delay information by looking at the information of the ports and pins. Whereas specific delays inside the path group other than the input to the output are hidden. The ETM model has the advantage of fast extraction speed, but has the disadvantage of being less accurate. Compared to ETM, QTM retains much port-to-first stage register information, including all line delay information and cell information input to output, input to register, and register-to-output. QTM extraction is slower than ETM and has a higher accuracy, typically up to about 99%.
The method mainly uses the analysis at the bottom layer, and at the moment when each module of the chip is completed, the workload of the top layer is difficult to reduce, and the problem of time sequence interface between the top layer and lower layer blocks cannot be accurately processed. For large chip designs, performing planar timing analysis from the top level of the hierarchy may consume memory resources or use excessive runtime. Thus, to accommodate large designs, very large scale integrated circuit timing models (Hyperscales models, HSM) are an advanced method that use separate runs to analyze the block-level and top-level portions and accurately process the timing interface between the top-level and lower-level blocks. The technique provides accuracy of complete planar analysis, and simultaneously utilizes the hierarchical block analysis to reduce running time and memory occupation, which can help solve the problems of improving accuracy and efficiency of time sequence analysis in the chip industry.
Disclosure of Invention
In view of the above drawbacks of the prior art, the present application is applicable to the field of chip hierarchical design, and provides a hierarchical timing model extraction method based on HSM. The path delay calculation method is shown in the formula (1):
Slack ori -Derate Required_time +Derate Arrival_time -Derate CPPR ＝Slack new (1)
Where Slackori is the initial margin for no on-chip bias analysis; slacknew is the time sequence result after on-chip deviation analysis; derateRequired_time is the descaler value of the drive path, and DerateArrival_time is the descaler value of the capture path; the DerateCPPR is the pessimistic compensation value for the common path. By calculating the time delay and integrating the time delay into a time sequence library, an accurate structure block model is created for each lower-level block in the ultra-large scale flow. The model allows each block level design to be analyzed separately while taking into account the constraints and timing characteristics of the higher level designs. Interface data transfers between the top layer and block analysis runs are handled, including input delays, output delays, and cross-boundary effects such as timing anomalies, crosstalk, and CRPR. The integrated timing library provides the same high precision as the flat-level analysis, providing shorter turn-around times and lower memory usage for hierarchical analysis.
In hierarchical analysis, the extracted timing of lower layer blocks independent of the top layer analysis can be used by the top layer, and the HyperScale model is used to represent block-level designs with lower hierarchical levels. Each model includes interface logic for block boundaries, all logic required for top-level accurate timing analysis, while excluding internal logic that is not related to top-level timing analysis. Therefore, the model is as fast and compact as possible, has flat analysis precision, can reduce running time and memory occupation, and can help to solve the problem of improving the accuracy and efficiency of time sequence analysis in the chip industry.
The invention aims to provide a hierarchical time sequence model extraction method based on HSM, which extracts common types of time sequence models through a time sequence library designed at a single block level, thereby reducing the number of time sequence model files input by a wiring tool, reducing the running time and memory occupation of the tool, improving the accuracy and efficiency of static time sequence analysis of the wiring tool, improving the design integration level of the time sequence model of the wiring tool and reducing the design period of a digital integrated circuit.
The invention provides a hierarchical time sequence model extraction method based on HSM, which comprises the following steps:
a hierarchical design method is adopted in the flow design,
preferably, a hierarchical design method is adopted in the flow design, the full-chip design can be divided into a top-layer design and a plurality of block-level designs, the block-level designs can be cut and extracted, a form of a two-level block-level design is realized, and a nested structure can be cut and extracted, so that a multi-level design is realized.
According to the key data of the digital integrated circuit design, carrying out identification, and storing the information into a data file after finishing the identification of the information; extracting information (such as examples, ports, pins and the like) describing each time sequence path of the digital integrated circuit, wherein the information describes a netlist file of the connection relation between each circuit element of the digital integrated circuit, a constraint file describing the design time sequence constraint of the digital integrated circuit;
acquiring key data of the digital integrated circuit design through a script, and generating an analysis environment of the digital integrated circuit; since the wiring tool must consider whether the timing verification of the circuit design meets the user requirement In multiple stages such as Built-In Self-Test (MBIST), low-speed Test Mode (SCAN Mode), or Function Mode (FUNC). Extracting a standard parasitic parameter file describing interconnection lines in an actual circuit after the chip is laid out and wired according to the analysis environment, reversely marking the standard parasitic parameter file into the digital integrated circuit, and marking all port logics of the digital integrated circuit with labels;
extracting a super-large-scale time sequence model, and extracting a time sequence model describing a constraint or a special processing path; and generating a plurality of super-large-scale time sequence models (HSM) according to a plurality of working modes of the digital integrated circuit design. Each model contains constraint information, non-deviation information, deviation information and IO structure information.
And carrying out the same type integration on the extracted data files of the model. And (3) carrying out file information classification, merging and optimizing, wherein the extracted super-large-scale time sequence model information can be merged according to whether the extracted super-large-scale time sequence model information has the same characteristic attribute or not as a reference, and a plurality of pieces of time sequence model information can be merged into one piece of complete time sequence information. And integrating the input and output structure information, the constraint file information and the super-large-scale time sequence model information into a complete super-large-scale time sequence model according to the three kinds of information of the super-large-scale time sequence model extracted in the working mode.
Preferably, all ports of the digital integrated circuit are logically labeled, and are divided into four groups, namely an input port to a register, an input port to an output port, a register to a register and a register to an output port, so that all netlists, ports and pins affecting delay are extracted; and omitting the idealized ports, omitting the input ports with excessively high fan-out, and extracting the ultra-large scale time sequence model.
And according to the extracted ultra-large scale time sequence model, the information characteristics of the same type are provided, and fusion is carried out to form unified information. In detail, the constraint file is optimized, the time sequence constraint and the revision are carried out on the time sequence information which does not accord with the extraction in the revision constraint file, and the newly generated time sequence port is remapped.
Preferably, the extracted files are integrated in the same type, and the extracted HSM models can be divided into HSM1, HSM2 and HSM3 according to the design of three working environments, and each HSM model comprises four files, namely an SDC file, a CONTEX file, a NOCV file and an OCV file.
Preferably, the extracted 12 files are combined into 3 model files, HSM_N is used as a one-dimensional search tag, MODE is used as a two-dimensional search tag, SDC, CONTEXT, NOCV and OCV are used as three-dimensional sub-searches to be respectively combined into three files, and the combined key circuit time sequence information can be searched.
Timing verification of the digital integrated circuit design is simulated by using the very large scale timing model.
According to the hierarchical time sequence model extraction method based on the HSM, the same attributes of all the information are fused through simple classification and combination, and conversion from a large number of files to a small number of files with high integration level is achieved. With the execution of this flow, the model is made as fast and compact as possible, with reduced run time and memory footprint. And the accuracy and the efficiency of static time sequence analysis of the wiring tool are improved by the time sequence model with high integration level. The integrated time sequence model is easy to manage and convenient to use, and can reduce the design period of the digital integrated circuit. As described above, the hierarchical time sequence model extraction method based on the HSM has the following beneficial effects:
currently, most large-scale digital integrated circuits are designed, when the chip size is too large, we have to use hierarchical flow in view of the software endurance and runtime. Directly performing full-chip STAs requires not only a significant amount of analysis time, but also significant complexity of analysis. From the perspective of portability and future universality, each level carries out time sequence analysis on circuit block level design of each level, and when the time sequence verification of each block level circuit passes, the overall static time sequence analysis is carried out on the whole chip, so that the complexity of static analysis can be reduced, and excessive verification time is avoided from being consumed in parallel operation.
Compared with a standard flattening process or an old layering process, the hierarchical time sequence model extraction method based on the HSM can achieve model extraction process combination file combination as shown in fig. 1, and constraint file information, time delay information and input and output structure information are integrated into a time sequence library file taking a single super-large time sequence model as a unit when a rear-end wiring tool extracts the time sequence model.
As shown in the first figure, a complete super-large-scale time sequence library file with the sequence number of the extracted time sequence model as a label in a working mode is extracted through file integration and optimization. Combining commonly owned conditions, environments and features, highlighting different portions of the differences,
the time sequence library file is read by the wiring tool, so that the running time and memory occupation of the tool can be reduced, and the accuracy and efficiency of static time sequence analysis of the wiring tool can be improved. This has the advantage that the complexity of the static analysis can be reduced and the parallel operation avoids consuming too much verification time.
Drawings
For further explanation of the description of the present invention, the following describes the embodiments of the present invention in further detail with reference to the accompanying drawings. It is to be understood that these drawings are solely for purposes of illustration and are not intended as a definition of the limits of the invention.
Fig. 1 is a timing extraction flow chart of a hierarchical timing model extraction method based on HSM according to the embodiment of the present invention.
Fig. 2 is a diagram of a time series extraction model file in various testability modes of operation.
Fig. 3 is a diagram of a time series extraction model tag structure.
Fig. 4 is a diagram of extracting time-series file information classification merge policy.
Fig. 5 is a schematic diagram of extracting individual information groups of a time series file.
Detailed Description
In order to make the objects, technical solutions and advantageous effects of the present application more apparent, the present application will be further described in detail with reference to the accompanying drawings and examples. It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the scope of the present invention.
In order to illustrate the technical scheme of the invention, the following description is made by specific examples.
Referring to fig. 1, an embodiment of the main flow design structure of the flow method provided in the present application may generate a plurality of block level structures, where the design structure is based on a single block level design of the embodiment.
101, in the first step of the flow of the application, a hierarchical design method is adopted in the flow design, and identification is performed according to key data of the digital integrated circuit design, and after information identification is completed, the information is stored in a data file, so that the script is convenient to transfer and process the information.
102, obtaining key data of the digital integrated circuit design described in 101 through script, and generating analysis environment of the integrated circuit, wherein the analysis environment is composed of process corner and working mode arrangement and combination.
And 103, extracting parasitic parameters of the digital integrated circuit according to the analysis environment, obtaining a standard parasitic parameter file of the interconnection line in the actual circuit after the layout and the wiring, and reversely marking the obtained standard parasitic extraction file into the digital integrated circuit.
104, obtaining and identifying the anti-marked digital integrated circuit, labeling all port logic of the digital integrated circuit with instructions for classification, and extracting a special processing path in the constraint. And input ports with excessively high fan-out are omitted, idealized ports are omitted, and a super-large-scale time sequence model is extracted.
And 105, merging and optimizing the extracted time sequence models aiming at the time sequence models of the common type.
Referring to fig. 2, a timing model file diagram is extracted for each testability operation mode described in each 102.
201, a Function Mode (FUNC) in which the logic Function of the chip is tested, and the chip needs to be ensured to operate normally in the Mode. In the mode, no test circuit is added, and only one sample storage is needed for the logic function of the chip. Consistency verification is performed in the modes of operation 302 and 303.
202, a Memory build-In Self-Test (MBIST) is embedded In a circuit during design to provide a Self-Test function, so as to reduce the dependency of device Test on Automatic Test Equipment (ATE), thereby ensuring that the circuit In the current mode cannot interfere with the normal execution of functional logic when the chip verifies a testability design.
203, inserting a Scan chain (Scan mode, scan for short), and replacing a normal register with a Scan register. And driving test excitation through a scan chain, carrying out logic operation, capturing the operation result by a scan unit, and then moving out through the scan chain to be compared with an expected value. Thus, normal execution of the circuit in the current mode is ensured.
Under the three working modes, the test circuits inserted in the testability design links are different, and for the change of connection ports and pins between the top layer and the test circuit and between the time sequence module and the test circuit, the inserted test circuit has the covering or remapping condition, and a new time sequence constraint file and an input and output structure module are required to be generated for the newly generated module. The newly generated constraint files and the input and output structure modules are classified in different working modes, and each single module generates the constraint files and the input and output structure modules in a plurality of working modes.
Referring to fig. 3, a time sequence extraction model tag path diagram is shown.
The input ports In the block level design are classified into first level registers by tagging all ports with labels as described In 104, and the paths of the first level branch registers connected by standard cells on the paths are input port-to-register groups (Input to Register Group, in2 Reg) containing the input-output delay, interface timing information, on-chip variation data metrics, pessimistic compensation, etc. of the paths described In 201.
302, by labeling all the port logic as described in 104 for classification, classifying the output port in the block level design into a first stage register traced back in the block level design, and the path of the first stage branch register connected by the standard cell on the path is a register-to-output port group (Register to Output Group, reg2 Out), where the path group includes the input-output delay, interface timing information, on-chip variation data metric, pessimistic compensation, and other timing information of the path described in 302.
The input ports In the block-level design are classified by tagging all port logic as described In 104 into input port-to-output port groups (Input to Output Group, in2 Out) containing the input-output delay, interface timing information, on-chip variation data metrics, pessimistic compensation, etc. of the paths as described In 303.
304, the paths for the Special processing in the classification constraint are classified by tagging all the port logic as described in 104, and the input ports with excessively high fanout are input port to output port group (Special Handling Group, specialty) which includes the input and output delay of the paths, interface timing information, on-chip variation data metrics, pessimistic compensation, and other timing information as described in 303.
305, classifying the time sequence path from the output port to the first stage register traced in the block stage design to the output port before the first stage register traced in the block stage design into the register-to-register group (Register to Register Group, reg2 Reg) by the classification of all ports by the tagging of all ports logic as described in 104, and removing the time sequence information from the register to the register because the time sequence model does not consider the Reg2Reg path.
Please refer to fig. 4, which is a merged diagram of file information classification under each operation mode.
401, the timing model extracted under FUNC includes timing delay models of In2Reg, out2Reg, in2Out and specialty (without on-chip deviation and with on-chip deviation), and a CONTEX timing interface model of each module between the top layer and the bottom layer; under the conventional condition, the SDC file which ensures the chip to normally operate in the mode;
402, the extracted time sequence model under MBIST comprises time sequence delay models (without on-chip deviation and containing on-chip deviation) of In2Reg, out2Reg, in2Out and specialty and a CONTEX time sequence interface model of each module between the top layer and the bottom layer; under the conventional condition, the SDC file which ensures the chip to normally operate in the mode;
403, the extracted time sequence model under SCAN comprises time sequence delay models (without on-chip deviation and with on-chip deviation) of In2Reg, out2Reg, in2Out and specialty, and a CONTEX time sequence interface model of each module between the top layer and the bottom layer; under the conventional condition, the SDC file which ensures the chip to normally operate in the mode;
404, synthesizing a unified HSM model, wherein the model comprises the complete time sequence information of all integrated files 401, and independently becomes a time sequence model penetrating through the full design.
And 405, synthesizing a unified SDC file, wherein the SDC file comprises the time sequence constraint which does not accord with the extracted time sequence module in the constraint file which is required to be revised in the three working modes and is in 402, and remapping the newly generated time sequence port.
406, synthesizing a unified CONTEXT file, wherein the CONTEXT includes a part of time sequence models of the three working modes, in which the newly generated ports are connected with the top layer, in 403.
Referring to fig. 5, an information detailed diagram of a combined file of information in an HSM according to an embodiment of the present invention is shown.
501, an input-output port structure module, which internally contains the input delay of the port boundary, the output delay of the port boundary, the cross-boundary timing condition, the cross-boundary on-chip variation data, the AOCV, the POCV metric and the common path pessimistic compensation value.
502, a constraint file module, which internally contains a clock constraint part, such as a create clock (create_clock), set clock delay (set_clock_latency), and configure clock uncertainty (set_clock_uncerty); an input port constraint time section (set_input_delay); an output port constraint time section (set_output_delay); specific examples of the point-to-point timing include, for example, configuring a pseudo path (set_false_path), configuring a multi-cycle path (set_multi-cycle_path), configuring a maximum path delay (set_max_delay), and configuring a minimum path delay (set_min_delay); an input constant logic value section (set_case_analysis), an input drive strength section, such as a configuration input port resistance value (set_drive), a configuration input port drive unit (set_drive_cell); an output port load capacitance section (set_load) and a design rule constraint section, such as configuring a maximum load capacitance (set_max_capacitance) inside all input ports, configuring a minimum load capacitance (set_min_capacitance) inside all input ports, configuring a maximum fan-out number (set_max_fanout) of input ports and modules, configuring a maximum transition time (set_max_transition) of all ports and pins, configuring a fan-out load sum (set_fanout_load) of input ports and pins.
503, a timing model module including critical timing arc setup time information (setup 1) free of on-chip bias effects and critical timing arc setup time information (setup 2) free of on-chip bias effects, critical timing arc recovery time information (recovery 2) free of on-chip bias effects and critical timing arc recovery time information (recovery 2) free of on-chip bias effects, critical timing arc hold time information (hold 1) free of on-chip bias effects and critical timing arc hold time information (hold 2) free of on-chip bias effects, critical timing arc removal time information (remove 1) free of on-chip bias effects and critical timing arc removal time information (remove 2) free of on-chip bias effects, critical timing arc setup time information (clock_gap 1) free of on-chip bias effects and critical timing arc recovery time information (clock_gap 2) free of on-chip bias effects, critical timing arc hold time information (clock_gap 2) free of on-chip bias effects, combined time information (maximum delay element, clock delay time information (maximum delay time information), clock delay time information (maximum) and clock_delay time information (maximum delay time information (maximum) of clock_delay time elements (hold_delay time information) of clock_delay time (maximum) and clock_delay time (maximum time_delay time information (maximum) of clock_delay time_delay time) Minimum period limit (minimum period constraints) information.
In order to make the HSM files in these different working modes more convenient to manage and apply, the timing module of the embodiment of the present invention includes timing information of all critical paths related to the chip, the model uses serial numbers of the super-large scale timing model as a main label (e.g. HSM1, HSM2, HSM 3) and uses the working mode as a sub-label (e.g. FUNC, MBIST, SCAN). The two difference points are used as index parameters, so that a three-dimensional rapid detection time sequence model interface can be realized.
Claims (5)
1. The hierarchical time sequence model extraction method based on the HSM is characterized by comprising the following steps of:
a hierarchical design method is adopted in the flow design,
according to the key data of the digital integrated circuit design, carrying out identification, and storing the information into a data file after finishing the identification of the information;
acquiring key data of the digital integrated circuit design through a script, and generating an analysis environment of the digital integrated circuit;
extracting parasitic parameters of the digital integrated circuit according to the analysis environment, reversely marking the parasitic parameters into the digital integrated circuit, and marking all port logics of the digital integrated circuit with labels;
extracting a super-large-scale time sequence model, and extracting a time sequence model describing a constraint or a special processing path;
and carrying out the same type integration on the extracted data files of the model.
2. The HSM-based hierarchical timing model extraction method according to claim 1, wherein a hierarchical design method is adopted in the flow design, the full-chip design can be divided into a top-level design and a plurality of block-level designs, the block-level designs can be cut and extracted to realize a two-level block-level design form, and the nested structure can be cut and extracted to realize a multi-level design.
3. The HSM-based hierarchical timing model extraction method according to claim 1, wherein all ports of the digital integrated circuit are logically labeled, and are divided into four groups, i.e., input port to register, input port to output port, register to register, register to output port, to extract all netlists, ports and pins affecting delay; and omitting the idealized ports, omitting the input ports with excessively high fan-out, and extracting the ultra-large scale time sequence model.
4. The method for extracting hierarchical timing model based on HSM according to claim 1, wherein the extracted files are integrated in the same type, the extracted HSM models are divided into HSM1, HSM2 and HSM3 according to three working environments, and each HSM model comprises four files, namely an SDC file, a CONTEX file, a NOCV file and an OCV file.
5. The method for extracting hierarchical timing model based on HSM according to claim 4, wherein the extracted 12 files are combined into 3 model files, hsm_n is used as a one-dimensional search tag, MODE is used as a two-dimensional search tag, SDC, CONTEXT, NOCV & OCV are used as three-dimensional sub-searches respectively and are combined into three files, and the combined timing information of the retrievable key circuit is obtained.
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