CN105893685A - VLSI (very Large Scale integration) formalization verification platform and method - Google Patents
VLSI (very Large Scale integration) formalization verification platform and method Download PDFInfo
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- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/39—Circuit design at the physical level
- G06F30/398—Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM]
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Abstract
The invention discloses a VLSI formal verification platform and a method thereof, wherein the verification platform comprises components: the verification platform comprises a variable setting script, a Lib reading script, a DUT reading script, an Env setting script and a Report setting script, and further comprises a match/match point extraction script for processing a result output by the verification platform. According to the invention, result processing is realized by using perl, the automatic implementation of the iterative verification of the unmatch point is realized, the source code and the Lib of each module to be verified are respectively managed, and the consumption of reading time is greatly reduced.
Description
Technical field
The present invention relates to chip form chemical examination card technical field, be specifically related to a kind of super large-scale integration VLSI Formal Verification platform and method.
Background technology
Current super large-scale integration complexity is high, scale is big, level is many, there is the problems such as resource requirement is high, time overhead is big, iteration cost is high in full chip entirety checking (top-down strategy), each level, module occur not mate (unmatch) situation and are not quite similar, and increase the difficulty of debugging.
The integrated level of digital integrated electronic circuit is more and more higher, and logical complexity and algorithm are the most complicated, is ensureing sequential, on the basis of taking into account area, power consumption, synthetic operation faces the biggest challenge, before netlist flows into back end, and the equivalence of the netlist homology Code Design function after need to guaranteeing comprehensively.Formal Verification, as a kind of check process, the speed of checking, completeness, drastically influence the expansion of follow-up work.Therefore, the important role of the most efficient verification platform.Integrated circuit big for scale, that complexity is high, Formal Verification is faced with that chip level is many, submodule is many, also relate to various IP storehouse, therefore, the Formal Verification of full chip can expend substantial amounts of machine, time resource, more can promote iteration cost, can seriously hinder the research and development process of chip, institute to be in this way substantially at present unpractical.
For solving problem above, conventional bottom-up strategy, but need rationally to realize checking level and the division of submodule.The verification platform that efficient checking work progress needs efficiently and reasonably checking script is put up and the process work to result, especially occur not being responsible for during (unmatch) situation how being iterated checking.
VLSI is super large-scale integration (Very Large
Scale Integration) abbreviation, refer on several millimeters of square silicon chips integrated up to ten thousand to million transistors, live width integrated circuit below 1 micron.Owing to transistor AND gate line once completes, therefore make man-hour of several to up to a million transistor and expense is equivalent.When producing in a large number, hardware costs almost can be disregarded, and depends on design cost.
Summary of the invention
The technical problem to be solved in the present invention is: for considering modern integrated circuits scale, the developing rapidly of complexity, synthetic operation is caused to face various challenge, the present invention proposes a kind of super large-scale integration VLSI Formal Verification platform and method, excessive in view of super large-scale integration scale, use and top-down comprehensively there is the problem that resource requirement is high, time overhead is big, chip level is many simultaneously, module difference is big, use bottom-up strategy, modular realize each assembly of verification platform.
The technical solution adopted in the present invention is:
A kind of super large-scale integration VLSI Formal Verification platform, described verification platform includes assembly: variable arranges script, Lib reads in script, DUT reads in script, Env arranges script, Report arranges script, described verification platform also includes that the match/unmatch point processing verification platform output result extracts script, once detection checking is not passed through, there is unmatch point, can make what iteration worked automatically to carry out, wherein:
Variable arranges script, and the unified Lib/DUT that arranges reads in path, results output routing and to be measured arranges the macro-variables such as top layer name, has been responsible for the setting to variablees such as each DUT top layer name, source path, report path, paths, storehouse；
Lib reads in script, administrative standard cell library and the reading of various IP, individually manages each module Lib, reduces the reading time；Whole chip can use substantial amounts of various IP, and such as: interface and memory etc., and the IP used in disparate modules is inconsistent or some module will not use IP, the library unit of each integration module individually to manage, it is achieved greatly reducing of time is read in storehouse；
DUT reads in script, calls variable and arranges being correspondingly arranged in script, reads in source design RTL code, individually manages each authentication module, it is achieved when verifying different levels, disparate modules, accurately reads in corresponding RTL code；
Env ambient As script, verification tool is set for warning (alarm), undriven(without driving), blackbox(black box) etc. the processing mode of special circumstances, complete undriven signal, mismatch_message(not match information) and the setting of warning type of process mode etc.；
Match/unmatch point extracts script, is responsible for the process to unmatch output result so that it is meets platform and reads in form, checks whether match, aborted, verified situation rationally simultaneously；Process for unmatch, unverified, aborted report, comply with platform and read in form, checking it is iterated during especially in the presence of unmatch point, to export intrinsic format analysis processing is set_user_match form, checks whether the situation of unverified and aborted meets the constraint that script is arranged simultaneously；
Report arranges script, calls variable and arranges script, output analysis result, unmatch, failing(failure), aborted(stops), unverified(unverified) etc. information under assigned work catalogue；
Top.tcl file calls other in certain sequence and arranges script, carries out being managed collectively and being responsible for the startup of platform, it is achieved the unification management of whole project.
Described Env ambient As script can share by platform entirely.
Described match/unmatch point extracts script and utilizes perl to create.Checking is likely to occur hundreds and thousands of or even more unmatch point, and platform output result form is the platform environment being not directly read into, therefore, utilize the text processing capabilities that perl is powerful, create match/unmatch point and extract script, once by not there is unmatch point in detection checking, can make the carrying out of the automation that iteration works.
Perl, the computer programming language of a kind of feature richness, operate in more than on 100 kinds of computer platforms, widely applicable, from large scale computer to portable equipment, it is created to extensive expansible exploitation from rapid prototyping.
The reading order of described top.tcl file management script is followed successively by: variable arranges script, Lib reads in script, Env arranges script, DUT reads in script, platform courses order, Report script.
A kind of super large-scale integration VLSI formalization verification method, described method classifying rationally Formal Verification platform each assembly Lib reads in script, DUT reads in and arranges script, Env ambient As script, Report arranges script, and add variable script is set, the match/unmatch point processing verification platform output result extracts script, each script is managed in certain sequence by top.tcl, realize the management of the unification of whole project, make whole Formal Verification work more having levels, it is divided level or submodule can independently be verified, realize the shortening of reading time and different submodule parallelizations are carried out.
Described method is after bottom module verification completes, and according to the level divided, one-level one-level is upwards incremented by.
The invention have the benefit that
The present invention uses perl to achieve the process to result, it is achieved that the automation to the iteration checking of unmatch point is carried out, and each design under test source code, each Self management of Lib greatly reduce the consumption of reading time.
Accompanying drawing explanation
Fig. 1 is verification platform structural representation.
Detailed description of the invention
Below in conjunction with Figure of description, according to detailed description of the invention, the present invention is further described:
Embodiment 1:
As shown in Figure 1, a kind of super large-scale integration VLSI Formal Verification platform, described verification platform includes assembly: variable arranges script, Lib reads in script, DUT reads in script, Env arranges script, Report arranges script, described verification platform also includes that the match/unmatch point processing verification platform output result extracts script, once detection checking is not passed through, there is unmatch point, it is possible to make what iteration worked automatically to carry out, wherein:
Variable arranges script, and the unified Lib/DUT that arranges reads in path, results output routing and to be measured arranges the macro-variables such as top layer name, has been responsible for the setting to variablees such as each DUT top layer name, source path, report path, paths, storehouse, has had full platform compatibility；
Lib reads in script, administrative standard cell library and various IP(storage IP, PAD IP and other IP storehouses) reading, individually manage each module Lib, reduce the reading time；Whole chip can use substantial amounts of various IP, and such as: interface and memory etc., and the IP used in disparate modules is inconsistent or some module will not use IP, the library unit of each integration module individually to manage, it is achieved greatly reducing of time is read in storehouse；
DUT reads in script, calls variable and arranges being correspondingly arranged in script, reads in source design RTL code, individually manages each authentication module, it is achieved when verifying different levels, disparate modules, accurately reads in corresponding RTL code；
Env ambient As script, the instrument of being responsible for carries the setting of variable, the verification tool processing mode for special circumstances such as warning, undriven, blackbox is set, completes the setting to undriven signal, mismatch_message and warning type of process mode etc.；
Match/unmatch point extracts script, is responsible for statistical form the result and is not responsible for the point of unmatch, and is processed as the acceptable form of verification platform and feeds back to verification platform；It is responsible for the process to unmatch output result so that it is meet platform and read in form, match, aborted, verified situation is checked whether rationally simultaneously；Process for unmatch, unverified, aborted report, comply with platform and read in form, checking it is iterated during especially in the presence of unmatch point, to export intrinsic format analysis processing is set_user_match form, checks whether the situation of unverified and aborted meets the constraint that script is arranged simultaneously；
Report arranges script, calls variable and arranges script, under the output information such as analysis result, unmatch, failing, aborted, unverified to assigned work catalogue, is responsible for printing and the output of Formal Verification result；
Top.tcl calls other in certain sequence and arranges script, carries out being managed collectively and being responsible for the startup of platform, it is achieved the unification management of whole project.
LIB has two kinds, and one is static library, such as C-Runtime storehouse, have function in this LIB realizes code, is commonly used in static build, and it is to add in object module (EXE or DLL) file by the code in LIB, so after chain has connected, LIB file is not the most used.A kind of LIB and DLL with the use of, the inside does not has code, and code is in DLL, and this LIB is used on static call DLL, so role is also link effect, link completes, and LIB is the most useless.If dynamic call DLL, do not use LIB file at all.After object module (EXE or DLL) file generated, just do not need LIB file；
DUT equipment under test.
Embodiment 2
On the basis of embodiment 1, Env ambient As script described in the present embodiment can share by platform entirely.
Embodiment 3
On the basis of embodiment 1 or 2, match/unmatch point described in the present embodiment extracts script and utilizes perl to create.Checking is likely to occur hundreds and thousands of or even more unmatch point, and platform output result form is the platform environment being not directly read into, therefore, utilize the text processing capabilities that perl is powerful, create match/unmatch point and extract script, once by not there is unmatch point in detection checking, can make the carrying out of the automation that iteration works.
Perl, the computer programming language of a kind of feature richness, operate in more than on 100 kinds of computer platforms, widely applicable, from large scale computer to portable equipment, it is created to extensive expansible exploitation from rapid prototyping；It is commonly referred to as " practical form extracts language " (Practical Extraction
And Report Language), you are likely to see " perl ", and all of letter is all small letter.Typically, " Perl ", there is the P of capitalization, refer to language itself, and " perl ", the p of small letter, the interpreter that the program that refers to is run.
Embodiment 4
On the basis of embodiment 3, the reading order of top.tcl file management script described in the present embodiment is followed successively by: variable arranges script, Lib reads in script, Env arranges script, DUT reads in script, platform courses order, Report script.
Embodiment 5
A kind of super large-scale integration VLSI formalization verification method, described method classifying rationally Formal Verification platform each assembly Lib reads in script, DUT reads in and arranges script, Env ambient As script, Report arranges script, and add variable script is set, the match/unmatch point processing verification platform output result extracts script, each script is managed in certain sequence by top.tcl, realize the management of the unification of whole project, make whole Formal Verification work more having levels, it is divided level or submodule can independently be verified, realize the shortening of reading time and different submodule parallelizations are carried out.
Embodiment 6
On the basis of embodiment 5, method described in the present embodiment is after bottom module verification completes, and according to the level divided, one-level one-level is upwards incremented by.
Embodiment of above is merely to illustrate the present invention; and not limitation of the present invention; those of ordinary skill about technical field; without departing from the spirit and scope of the present invention; can also make a variety of changes and modification; the technical scheme of the most all equivalents falls within scope of the invention, and the scope of patent protection of the present invention should be defined by the claims.
Claims (6)
1. a super large-scale integration VLSI Formal Verification platform, described verification platform includes assembly: variable arranges script, Lib reads in script, DUT reads in script, Env arranges script, Report arranges script, it is characterized in that: described verification platform also includes that the match/unmatch point processing verification platform output result extracts script, wherein:
Variable arranges script, and the unified Lib/DUT that arranges reads in path, results output routing and to be measured arranges top layer name macro-variable, has been responsible for each DUT top layer name, source path, report path, the setting of storehouse path variable；
Lib reads in script, administrative standard cell library and the reading of various IP, individually manages each module Lib, reduces the reading time；
DUT reads in script, calls variable and arranges being correspondingly arranged in script, reads in source design RTL code, individually manages each authentication module；
Env ambient As script, arranges the verification tool processing mode for warning, undriven, blackbox special circumstances, completes undriven signal, the setting of mismatch_message and warning type of process mode；
Match/unmatch point extracts script, is responsible for the process to unmatch output result so that it is meets platform and reads in form, checks whether match, aborted, verified situation rationally simultaneously；Process for unmatch, unverified, aborted report so that it is meet platform and read in form；
Report arranges script, calls variable and arranges script, under output analysis result, unmatch, failing, aborted, unverified information to assigned work catalogue；
Top.tcl file calls other in certain sequence and arranges script, carries out being managed collectively and being responsible for the startup of platform, it is achieved the unification management of whole project.
A kind of super large-scale integration VLSI Formal Verification platform the most according to claim 1, it is characterised in that: the described Env full platform of ambient As script shares.
A kind of super large-scale integration VLSI Formal Verification platform the most according to claim 1 and 2, it is characterised in that: described match/unmatch point extracts script and utilizes perl to create.
A kind of super large-scale integration VLSI Formal Verification platform the most according to claim 3, it is characterised in that: the reading order of described top.tcl file management script is followed successively by: variable arranges script, Lib reads in script, Env arranges script, DUT reads in script, platform courses order, Report script.
5. a super large-scale integration VLSI formalization verification method, it is characterized in that: described method classifying rationally Formal Verification platform each assembly Lib reads in script, DUT reads in and arranges script, Env ambient As script, Report arranges script, and add variable script is set, the match/unmatch point processing verification platform output result extracts script, each script is managed in certain sequence by top.tcl, realize the management of the unification of whole project, make whole Formal Verification work more having levels, it is divided level or submodule can independently be verified, realize the shortening of reading time and different submodule parallelizations are carried out.
A kind of super large-scale integration VLSI formalization verification method the most according to claim 5, it is characterised in that: described method is after bottom module verification completes, and according to the level divided, one-level one-level is upwards incremented by.
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| CN201610219744.1A CN105893685A (en) | 2016-04-11 | 2016-04-11 | VLSI (very Large Scale integration) formalization verification platform and method |
| PCT/CN2016/109582 WO2017177705A1 (en) | 2016-04-11 | 2016-12-13 | Very-large-scale integration circuit (vlsi) formal verification platform and method |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106375658A (en) * | 2016-09-09 | 2017-02-01 | 北京控制工程研究所 | Ultra-high-precision image processing VLSI verification method |
| WO2017177705A1 (en) * | 2016-04-11 | 2017-10-19 | 浪潮电子信息产业股份有限公司 | Very-large-scale integration circuit (vlsi) formal verification platform and method |
| CN107563025A (en) * | 2017-08-18 | 2018-01-09 | 北京东土军悦科技有限公司 | A kind of verification platform management method and device |
| CN107644128A (en) * | 2017-09-08 | 2018-01-30 | 郑州云海信息技术有限公司 | The method and system that a kind of DC synthesis cooperates with Formality Formal Verifications |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1851717A (en) * | 2005-09-09 | 2006-10-25 | 深圳市海思半导体有限公司 | Special integrated circuit comprehensive system and method |
| CN102012954A (en) * | 2010-11-29 | 2011-04-13 | 杭州中天微系统有限公司 | Subsystem integration method and subsystem integration system for integration design of system-on-chip |
| CN104573261A (en) * | 2015-01-23 | 2015-04-29 | 浪潮电子信息产业股份有限公司 | VLSI (very large scale integration) integration method |
Family Cites Families (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5703788A (en) * | 1995-06-07 | 1997-12-30 | Lsi Logic Corporation | Configuration management and automated test system ASIC design software |
| US6182258B1 (en) * | 1997-06-03 | 2001-01-30 | Verisity Ltd. | Method and apparatus for test generation during circuit design |
| CN100347683C (en) * | 2005-04-15 | 2007-11-07 | 清华大学 | Structure-irrelevant micro-processor verification and evaluation method |
| CN102012957A (en) * | 2010-12-17 | 2011-04-13 | 天津曙光计算机产业有限公司 | Verification method for packet classification logic codes based on five-tuple array |
| CN105893685A (en) * | 2016-04-11 | 2016-08-24 | 浪潮电子信息产业股份有限公司 | VLSI (very Large Scale integration) formalization verification platform and method |
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1851717A (en) * | 2005-09-09 | 2006-10-25 | 深圳市海思半导体有限公司 | Special integrated circuit comprehensive system and method |
| CN102012954A (en) * | 2010-11-29 | 2011-04-13 | 杭州中天微系统有限公司 | Subsystem integration method and subsystem integration system for integration design of system-on-chip |
| CN104573261A (en) * | 2015-01-23 | 2015-04-29 | 浪潮电子信息产业股份有限公司 | VLSI (very large scale integration) integration method |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2017177705A1 (en) * | 2016-04-11 | 2017-10-19 | 浪潮电子信息产业股份有限公司 | Very-large-scale integration circuit (vlsi) formal verification platform and method |
| CN106375658A (en) * | 2016-09-09 | 2017-02-01 | 北京控制工程研究所 | Ultra-high-precision image processing VLSI verification method |
| CN106375658B (en) * | 2016-09-09 | 2019-05-24 | 北京控制工程研究所 | A kind of very high-precision image processing VLSI verification method |
| CN107563025A (en) * | 2017-08-18 | 2018-01-09 | 北京东土军悦科技有限公司 | A kind of verification platform management method and device |
| CN107563025B (en) * | 2017-08-18 | 2021-08-20 | 北京东土军悦科技有限公司 | Verification platform management method and device |
| CN107644128A (en) * | 2017-09-08 | 2018-01-30 | 郑州云海信息技术有限公司 | The method and system that a kind of DC synthesis cooperates with Formality Formal Verifications |
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