CN1851717A - Special integrated circuit comprehensive system and method - Google Patents
Special integrated circuit comprehensive system and method Download PDFInfo
- Publication number
- CN1851717A CN1851717A CN 200510102446 CN200510102446A CN1851717A CN 1851717 A CN1851717 A CN 1851717A CN 200510102446 CN200510102446 CN 200510102446 CN 200510102446 A CN200510102446 A CN 200510102446A CN 1851717 A CN1851717 A CN 1851717A
- Authority
- CN
- China
- Prior art keywords
- comprehensive
- submodule
- unit
- asic design
- constraint
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Landscapes
- Design And Manufacture Of Integrated Circuits (AREA)
- Stored Programmes (AREA)
Abstract
The present invention discloses an ASIC integrated system including plurality of submodule and method. Said integrated system includes integrated control platform unit and universal integration unit, wherein integrated control platform unit for transmitting the to be integrated submodule information to said universal integration unit, after monitoring all submodule integration being completed, transmitting said ASIC designed information and each submodule netlist to universal integration unit; universal integration unit for reading integration submodule and setting integration constraint, to proceed integration to said integration submodule and outputting said submodule netlist, and according to said ASIC designed information setting integration constraint, to proceed ASIC designed top layer integration and outputting its netlist. The present invention greatly simplifies whole integrated system framework without script relative to said ASIC designing and every submodule, reducing integration procedural complexity, and having good transplantation quality.
Description
Technical field
The present invention relates to special IC complex art field, particularly a kind of special integrated circuit comprehensive system and method.
Background technology
In the design process of special IC (ASIC), general hardware description language (Verilog), Very High Speed Integrated Circuit (VHSIC) hardware description language electric design automation (EDA) design languages such as (VHDL) of using earlier designed logical circuit, converts actual gate level circuit to by synthesis tool again.The so-called comprehensive gate level circuit that exactly designed logical circuit code is changed into corresponding certain process means.
The comprehensive strategic of ASIC design there are from top to bottom (Top Down) and (Bottom Up) dual mode from bottom to top.Top Down mode is read in synthesis tool with design exactly, and synthesis tool carries out comprehensively it, and Top Down mode is fit to the door number in other design of 100,000 gate leves because generalized time is longer; Bottom Up mode is divided into a plurality of submodules with the ASIC design, and synthesis tool carries out comprehensively each submodule in the ASIC design earlier, and then comprehensive to described ASIC design carrying out top layer.Along with the increase of ASIC design complexities and door number, the comprehensive strategic of Top Down is infeasible, and the designer generally adopts the comprehensive strategic of Bottom Up mode.
In the ASIC design, a complete design is combined by a plurality of submodules usually.In existing technical scheme, each treats the corresponding independently comprehensive script of comprehensive submodule, and each comprehensive script reads in the corresponding comprehensive submodule for the treatment of, comprehensive constraint is set, and submodule is comprehensively produced the net table, exports consolidated return then.The also corresponding comprehensive script of described ASIC design, comprehensive to realize top layer: after all submodules were comprehensively finished, this comprehensive script read in the net table of each submodule of comprehensively having finished, and comprehensive constraint is set, and carried out comprehensively exporting consolidated return then.Comprehensive in order to realize starting top layer automatically, can utilize one to monitor that script monitors whether the net table of the comprehensive output of each submodule produces, when the net table of all submodules all produces, comprehensively finishing of all submodules is described, automatically start the comprehensive script corresponding to this ASIC design, it is comprehensive to carry out top layer.
Fig. 1 has provided the framework of above-mentioned comprehensive script in the prior art, corresponding to ASIC design is divided into n submodule with 0～n-1 mark by certain way, there be n comprehensive script among Fig. 1 with 0～n-1 mark, and there is a comprehensive script corresponding to this ASIC design, each comprehensive script reads in corresponding module or net table, comprehensive constraint is set, carries out comprehensively exporting consolidated return then.
Fig. 2 has provided the comprehensive flow process of ASIC in the prior art, may further comprise the steps:
Step 101 corresponding to each treats that each comprehensive script of comprehensive submodule reads in the corresponding comprehensive submodule for the treatment of in the ASIC design, is provided with comprehensive constraint, and submodule is comprehensively produced the net table, exports consolidated return then.
Step 102 monitors that script when the net table that monitors all submodules all produces, illustrates comprehensively finishing of all submodules, starts the comprehensive script corresponding to this ASIC design automatically, and it is comprehensive to carry out top layer.Read in the net table of each submodule of comprehensively having finished corresponding to the comprehensive script of this ASIC design, comprehensive constraint is set, carry out comprehensively, export consolidated return then.
In technique scheme, described ASIC design and all corresponding separately comprehensive script of each submodule wherein, submodule in design more for a long time, need more comprehensive script, the framework of whole system ensemble is bulky complex very, no matter write or safeguard a large amount of comprehensive scripts, all can expend huge workload.In addition,, cause the transplantability of these comprehensive scripts relatively poor, can not use for other designs, and generally comprehensive unversed designer is difficult to directly use these comprehensive scripts because each comprehensive script is corresponding with a specific submodule.
Summary of the invention
In view of this, the present invention proposes a kind of ASIC system ensemble, in order to simplify the framework of whole system ensemble.
A kind of ASIC system ensemble provided by the invention, be used for comprehensively comprising the ASIC design of a plurality of submodules, this system ensemble comprises Comprehensive Control platform unit and general comprehensive unit, wherein, Comprehensive Control platform unit, be used for described ASIC design is treated that the information of comprehensive submodule sends to described general comprehensive unit, and monitor comprehensive the finishing of each submodule, monitoring after all submodules comprehensively finish, the information of described ASIC design and the net table of each submodule are sent to general comprehensive unit; General comprehensive unit, be used for reading and treat comprehensive submodule and the comprehensive constraint for the treatment of comprehensive submodule is set according to the described information for the treatment of comprehensive submodule, treat that to described comprehensive submodule carries out comprehensively and export the net table of described submodule, and according to the comprehensive constraint of the described ASIC design of the information setting of described ASIC design, the top layer that carries out described ASIC design according to the net table of the comprehensive constraint of described ASIC design and each submodule is comprehensive, and exports the net table of described ASIC design.
Preferably, described general comprehensive unit comprises and reads in design script unit, constraint script unit and comprehensive script unit are set, wherein, read in design script unit, be used for reading and treat comprehensive submodule, and the submodule that is read is sent to comprehensive script unit according to the described information for the treatment of comprehensive submodule; Constraint script unit is set, be used for treating the comprehensive constraint of comprehensive submodule and sending to comprehensive script unit according to the described information setting of comprehensive submodule for the treatment of, and according to the comprehensive constraint of the described ASIC design of the information setting of described ASIC design and send to comprehensive script unit; Comprehensive script unit, be used for treating that to described comprehensive submodule carries out comprehensively and export the net table of described submodule according to the described comprehensive constraint of comprehensive submodule for the treatment of, and it is comprehensive to carry out the top layer of described ASIC design according to the net table of the comprehensive constraint of described ASIC design and each submodule, and export the net table of described ASIC design; And, Comprehensive Control platform unit will treat that the information of comprehensive submodule sends to described input design script unit, constraint script unit and comprehensive script unit are set, and after all submodules are comprehensively finished, the information of described ASIC design sent to constraint script unit is set and the net table that each submodule is comprehensive sends to comprehensive script unit.
Preferably, described general comprehensive unit further comprises output report script unit, the net table that is used for the described submodule of basis comprehensive script unit output produces and exports the consolidated return of described submodule, and produces and export the consolidated return of described ASIC design according to the net table that the described ASIC that comprehensive script unit is exported designs.
The invention allows for a kind of ASIC integrated approach, in order to reduce the complexity of combined process.
In view of the above, the invention provides a kind of ASIC integrated approach, be used for comprehensively comprising the ASIC design of a plurality of submodules, set in advance shared general comprehensive unit, this method further may further comprise the steps:
A. the information for the treatment of comprehensive submodule in the described design is sent to general comprehensive unit;
B. general comprehensive unit reads in the described comprehensive submodule for the treatment of according to the information of receiving for the treatment of comprehensive submodule, the comprehensive constraint for the treatment of comprehensive submodule is set, and treats comprehensive submodule and carries out comprehensively, and export the net table of described submodule;
C. monitoring after all submodules comprehensively finish, the information of described ASIC design and the net table of each submodule are sent to general comprehensive unit;
D. general comprehensive unit is according to the comprehensive constraint of the described ASIC design of the information setting of described ASIC design, and the top layer that carries out described ASIC design according to the net table of the comprehensive constraint of described ASIC design and each submodule is comprehensive, and exports the net table of described ASIC design.
Preferably, further comprise after the described step B: the consolidated return that produces and export described submodule according to the net table of described submodule.
Preferably, further comprise after the described step D: the consolidated return that produces and export described ASIC design according to the net table of described ASIC design.
In the described steps A, the described information of comprehensive submodule for the treatment of is directly sent to general comprehensive unit.
Preferably, the step that described in the steps A the described information for the treatment of comprehensive submodule is sent to general comprehensive unit comprises: to corresponding document, general comprehensive unit reads the described information for the treatment of comprehensive submodule from described file with the described information stores for the treatment of comprehensive submodule.
Whether in technique scheme, the described monitoring of step C is: produce by the net table that detects all submodules and monitor comprehensively whether finishing of all submodules.
From such scheme as can be seen, because the general comprehensive unit that the invention provides Comprehensive Control platform unit and share, in combined process to an ASIC design, no longer need respectively to have simplified the framework of whole system ensemble greatly at the described ASIC design and the script of each submodule wherein.In combined process, to treat that by Comprehensive Control platform unit the information of comprehensive submodule sends to each correlation unit, and after monitoring comprehensively the finishing of each submodule, automatically the top layer that starts described ASIC design is comprehensive, realize the full-automation processing of combined process, improved overall efficiency, reduced comprehensive personnel's workload, and all comprehensively all use the general comprehensive unit of sharing, and have reduced the complexity of combined process.
And system ensemble of the present invention can be moved under any machine and catalogue, and the title of the comprehensive submodule only need be provided, even being ignorant of polytechnic designer also can use, locatees synthtic price index fast thereby be convenient to the designer.
In addition, because comprehensive framework of the present invention is simple, just constitute by Comprehensive Control platform unit and several simple comprehensive script unit of sharing, be convenient to revise and safeguard, has higher transplantability, can be used in the project of each ASIC design, can shorten the construction cycle of ASIC project so to a certain extent.
Description of drawings
Fig. 1 is the framework of comprehensive script in the prior art;
Fig. 2 is a general flow synoptic diagram of the prior art;
Fig. 3 a and 3b are the system ensemble structural representation of the embodiment of the invention;
Fig. 4 is the general flowchart of the embodiment of the invention.
Embodiment
For making the purpose, technical solutions and advantages of the present invention clearer, the present invention is described in more detail by the following examples.
With reference to Fig. 3 a, the ASIC system ensemble of present embodiment comprises Comprehensive Control platform unit and the general comprehensive unit of sharing.Wherein, Comprehensive Control platform unit, be used for the ASIC design is treated that the information of comprehensive submodule sends to described general comprehensive unit, and monitor comprehensive the finishing of all submodules, monitoring after all submodules comprehensively finish, the information of described ASIC design and the net table of each submodule are sent to general comprehensive unit; General comprehensive unit, be used for reading and treat comprehensive submodule and the comprehensive constraint for the treatment of comprehensive submodule is set according to the described information for the treatment of comprehensive submodule, treat that to described comprehensive submodule carries out comprehensively and export the net table of this submodule, and according to the comprehensive constraint of the described ASIC design of the information setting of described ASIC design, the top layer that carries out described ASIC design according to the net table of the comprehensive constraint of described ASIC design and each submodule is comprehensive, and exports the net table of described ASIC design.
As can be seen from the above description, design with wherein all corresponding separately comprehensive script of each submodule is different with ASIC in the prior art, ASIC design and all submodules are all shared above-mentioned general comprehensive unit in the present embodiment, in other words, this general comprehensive unit is not only finished comprehensive to each submodule in the ASIC design, and the top layer of also finishing this ASIC design is comprehensive.This general comprehensive unit can realize by a general comprehensive script, and described general comprehensive script has comprised the identical content of each comprehensive script in the prior art and at this ASIC design and the different content of each submodule wherein.
Continuation is with reference to Fig. 3 a, and general comprehensive unit comprises and reads in design script unit, constraint script unit, comprehensive script unit are set.Wherein, Comprehensive Control platform unit respectively with read in design script unit, constraint script unit be set, comprehensive script unit is connected, read in design script unit, constraint script unit is set is connected with comprehensive script unit respectively.In this ASIC system ensemble, Comprehensive Control platform unit is used for the ASIC design is treated that the information of comprehensive submodule sends to described input design script unit, constraint script unit and comprehensive script unit are set, and monitor comprehensive the finishing of all submodules, monitoring after all submodules comprehensively finish, the information of described ASIC design is sent to constraint script unit is being set and the comprehensive net table that produces of each submodule is sent to comprehensive script unit; Read in design script unit and be used for reading and treat comprehensive submodule, and the submodule that is read is sent to comprehensive script unit according to the described information for the treatment of comprehensive submodule; Constraint script unit is set is used for treating the comprehensive constraint of comprehensive submodule and set comprehensive constraint being sent to comprehensive script unit, and also set comprehensive constraint is sent to comprehensive script unit according to the comprehensive constraint of the described ASIC design of the information setting of described ASIC design according to the described information setting of comprehensive submodule for the treatment of; Comprehensive script unit is used for treating that to described comprehensive submodule carries out comprehensively and export the net table of this submodule according to the described comprehensive constraint of comprehensive submodule for the treatment of, and it is comprehensive to carry out the top layer of described ASIC design according to the net table of the comprehensive constraint of described ASIC design and each submodule, and export the net table of described ASIC design.
Shown in Fig. 3 b, above-mentioned ASIC system ensemble can further include the output report script unit that is connected with comprehensive script unit.This output report script unit is used for producing according to the net table of the submodule of comprehensive script unit output the consolidated return of submodule, and export the consolidated return of described submodule, and produce the consolidated return of this ASIC design, and export the consolidated return of described ASIC design according to the net table of this ASIC design of comprehensive script unit output.Correspondingly, the general comprehensive unit among Fig. 3 b further also is used for producing the also consolidated return of output sub-module according to the net table of submodule, and the consolidated return that produces and export described ASIC design according to the net table of this ASIC design.
Below with reference to Fig. 4, the general flow according to the embodiment of the invention is described.With reference to Fig. 4, the general flow that designs for an ASIC may further comprise the steps:
Wherein, the described information of comprehensive submodule for the treatment of comprises title of submodule etc.The process that described information sends can be direct transmission, also can be Comprehensive Control platform unit with information stores in certain file, then by reading in design script unit, constraint script unit being set and comprehensive script unit reads described information from this document.
Be provided with in this step and treat that the method for comprehensive submodule comprehensive constraint has multiple, here illustrate with a comparatively easy method: preserved the comprehensive constraint corresponding respectively in advance with the information of respectively treating comprehensive submodule, the information for the treatment of comprehensive submodule that sends over according to Comprehensive Control platform unit just can obtain the comprehensive constraint corresponding with it in this step, is provided with then.
Need to prove that step 202 and step 203 do not have the branch of precedence, Cai illustrate respectively with two steps for the enforcement of clearer explanation present embodiment here.
When in described ASIC system, comprising output report script unit, comprehensive script is exported to output report script unit with the net table of described submodule, output report script unit produces the consolidated return of submodule according to the net table of described submodule, and exports this consolidated return.Described consolidated return comprises size of data, sequential, channel check result etc.
In this step, whether Comprehensive Control platform unit can produce by the net table that detects each submodule and monitor and comprehensively whether finishing of each submodule when the net table that detects all submodules all produces, just draw comprehensively finishing of all submodules.
Similar to step 203, also can make the comprehensive constraint that this ASIC design is set with the following method in this step: preserved the corresponding comprehensive constraint information of information in advance with this ASIC design, the information of the ASIC design that sends over according to Comprehensive Control platform unit in this step just can obtain the comprehensive constraint that described ASIC designs, and is provided with then.
When in described ASIC system, comprising output report script unit, output report script unit is exported to the net table of described ASIC design in comprehensive script unit, output report script unit produces the consolidated return of described ASIC design according to the net table of described ASIC design, and exports this consolidated return.Described consolidated return comprises size of data, sequential, channel check result etc.
The above only is preferred embodiment of the present invention, and is in order to restriction the present invention, within the spirit and principles in the present invention not all, any modification of being done, is equal to replacement, improvement etc., all should be included within protection scope of the present invention.
Claims (9)
1, a kind of application-specific integrated circuit ASIC system ensemble is used for comprehensively comprising the ASIC design of a plurality of submodules, it is characterized in that this system ensemble comprises Comprehensive Control platform unit and general comprehensive unit,
Wherein, Comprehensive Control platform unit, be used for described ASIC design is treated that the information of comprehensive submodule sends to described general comprehensive unit, and monitor comprehensive the finishing of each submodule, monitoring after all submodules comprehensively finish, the information of described ASIC design and the net table of each submodule are sent to general comprehensive unit;
General comprehensive unit, be used for reading and treat comprehensive submodule and the comprehensive constraint for the treatment of comprehensive submodule is set according to the described information for the treatment of comprehensive submodule, treat that to described comprehensive submodule carries out comprehensively and export the net table of described submodule, and according to the comprehensive constraint of the described ASIC design of the information setting of described ASIC design, the top layer that carries out described ASIC design according to the net table of the comprehensive constraint of described ASIC design and each submodule is comprehensive, and exports the net table of described ASIC design.
2, system ensemble according to claim 1 is characterized in that, described general comprehensive unit comprises and read in design script unit, constraint script unit and comprehensive script unit are set,
Wherein, read in design script unit, be used for reading and treat comprehensive submodule, and the submodule that is read is sent to comprehensive script unit according to the described information for the treatment of comprehensive submodule;
Constraint script unit is set, be used for treating the comprehensive constraint of comprehensive submodule and sending to comprehensive script unit according to the described information setting of comprehensive submodule for the treatment of, and according to the comprehensive constraint of the described ASIC design of the information setting of described ASIC design and send to comprehensive script unit;
Comprehensive script unit, be used for treating that to described comprehensive submodule carries out comprehensively and export the net table of described submodule according to the described comprehensive constraint of comprehensive submodule for the treatment of, and it is comprehensive to carry out the top layer of described ASIC design according to the net table of the comprehensive constraint of described ASIC design and each submodule, and export the net table of described ASIC design;
And, Comprehensive Control platform unit will treat that the information of comprehensive submodule sends to described input design script unit, constraint script unit and comprehensive script unit are set, and after all submodules are comprehensively finished, the information of described ASIC design sent to constraint script unit is set and the net table that each submodule is comprehensive sends to comprehensive script unit.
3, system ensemble according to claim 2, it is characterized in that, described general comprehensive unit further comprises output report script unit, the net table that is used for the described submodule of basis comprehensive script unit output produces and exports the consolidated return of described submodule, and produces and export the consolidated return of described ASIC design according to the net table that the described ASIC that comprehensive script unit is exported designs.
4, a kind of ASIC integrated approach is used for comprehensively comprising the ASIC design of a plurality of submodules, it is characterized in that set in advance shared general comprehensive unit, this method further may further comprise the steps:
A. the information for the treatment of comprehensive submodule in the described design is sent to general comprehensive unit;
B. general comprehensive unit reads in the described comprehensive submodule for the treatment of according to the information of receiving for the treatment of comprehensive submodule, the comprehensive constraint for the treatment of comprehensive submodule is set, and treats comprehensive submodule and carries out comprehensively, and export the net table of described submodule;
C. monitoring after all submodules comprehensively finish, the information of described ASIC design and the net table of each submodule are sent to general comprehensive unit;
D. general comprehensive unit is according to the comprehensive constraint of the described ASIC design of the information setting of described ASIC design, and the top layer that carries out described ASIC design according to the net table of the comprehensive constraint of described ASIC design and each submodule is comprehensive, and exports the net table of described ASIC design.
5, method according to claim 4 is characterized in that, further comprises after the described step B: the consolidated return that produces and export described submodule according to the net table of described submodule.
6, method according to claim 4 is characterized in that, further comprises after the described step D: the consolidated return that produces and export described ASIC design according to the net table of described ASIC design.
7, method according to claim 4 is characterized in that, in the described steps A, the described information of comprehensive submodule for the treatment of is directly sent to general comprehensive unit.
8, method according to claim 4 is characterized in that, the step that described in the steps A the described information for the treatment of comprehensive submodule is sent to general comprehensive unit comprises:
To corresponding document, general comprehensive unit reads the described information for the treatment of comprehensive submodule from described file with the described information stores for the treatment of comprehensive submodule.
Whether 9, method according to claim 4 is characterized in that, the described monitoring of step C is: produce by the net table that detects all submodules and monitor comprehensively whether finishing of all submodules.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2005101024466A CN100362520C (en) | 2005-09-09 | 2005-09-09 | Special integrated circuit comprehensive system and method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2005101024466A CN100362520C (en) | 2005-09-09 | 2005-09-09 | Special integrated circuit comprehensive system and method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1851717A true CN1851717A (en) | 2006-10-25 |
| CN100362520C CN100362520C (en) | 2008-01-16 |
Family
ID=37133196
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB2005101024466A Expired - Fee Related CN100362520C (en) | 2005-09-09 | 2005-09-09 | Special integrated circuit comprehensive system and method |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN100362520C (en) |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101821737A (en) * | 2007-07-23 | 2010-09-01 | 新思公司 | Architectural physical synthesis |
| CN102012954A (en) * | 2010-11-29 | 2011-04-13 | 杭州中天微系统有限公司 | Subsystem integration method and subsystem integration system for integration design of system-on-chip |
| CN104573261A (en) * | 2015-01-23 | 2015-04-29 | 浪潮电子信息产业股份有限公司 | VLSI (very large scale integration) integration method |
| US9280632B2 (en) | 2009-01-30 | 2016-03-08 | Synopsys, Inc. | Methods and apparatuses for circuit design and optimization |
| CN105677960A (en) * | 2016-01-04 | 2016-06-15 | 中国兵器工业集团第二一四研究所苏州研发中心 | Implementing method for Auto-DC automation integrated design |
| CN105893685A (en) * | 2016-04-11 | 2016-08-24 | 浪潮电子信息产业股份有限公司 | VLSI (very Large Scale integration) formalization verification platform and method |
| US10268797B2 (en) | 2007-07-23 | 2019-04-23 | Synopsys, Inc. | Architectural physical synthesis |
Family Cites Families (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20010020290A1 (en) * | 1998-06-19 | 2001-09-06 | Sun Microsystems, Inc. | Method and system for robust distributed circuit synthesis |
| US6493648B1 (en) * | 1999-08-16 | 2002-12-10 | Sequence Design, Inc. | Method and apparatus for logic synthesis (inferring complex components) |
| US6557159B1 (en) * | 2000-05-24 | 2003-04-29 | International Business Machines Corporation | Method for preserving regularity during logic synthesis |
| JP2002312411A (en) * | 2001-04-10 | 2002-10-25 | Ricoh Co Ltd | Logic synthesizing device and method therefor |
| JP2003196333A (en) * | 2001-12-28 | 2003-07-11 | Nec Electronics Corp | Method for designing system lsi (large scale integration) and recording medium in which the same in stored |
| US6925628B2 (en) * | 2002-10-22 | 2005-08-02 | Matsushita Electric Industrial Co., Ltd. | High-level synthesis method |
-
2005
- 2005-09-09 CN CNB2005101024466A patent/CN100362520C/en not_active Expired - Fee Related
Cited By (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101821737A (en) * | 2007-07-23 | 2010-09-01 | 新思公司 | Architectural physical synthesis |
| US8819608B2 (en) | 2007-07-23 | 2014-08-26 | Synopsys, Inc. | Architectural physical synthesis |
| US8966415B2 (en) | 2007-07-23 | 2015-02-24 | Synopsys, Inc. | Architectural physical synthesis |
| US10268797B2 (en) | 2007-07-23 | 2019-04-23 | Synopsys, Inc. | Architectural physical synthesis |
| US9280632B2 (en) | 2009-01-30 | 2016-03-08 | Synopsys, Inc. | Methods and apparatuses for circuit design and optimization |
| CN102012954A (en) * | 2010-11-29 | 2011-04-13 | 杭州中天微系统有限公司 | Subsystem integration method and subsystem integration system for integration design of system-on-chip |
| CN102012954B (en) * | 2010-11-29 | 2013-01-02 | 杭州中天微系统有限公司 | Subsystem integration method and subsystem integration system for integration design of system-on-chip |
| CN104573261A (en) * | 2015-01-23 | 2015-04-29 | 浪潮电子信息产业股份有限公司 | VLSI (very large scale integration) integration method |
| CN104573261B (en) * | 2015-01-23 | 2017-10-13 | 浪潮电子信息产业股份有限公司 | VLSI (very large scale integration) integration method |
| CN105677960A (en) * | 2016-01-04 | 2016-06-15 | 中国兵器工业集团第二一四研究所苏州研发中心 | Implementing method for Auto-DC automation integrated design |
| CN105893685A (en) * | 2016-04-11 | 2016-08-24 | 浪潮电子信息产业股份有限公司 | VLSI (very Large Scale integration) formalization verification platform and method |
Also Published As
| Publication number | Publication date |
|---|---|
| CN100362520C (en) | 2008-01-16 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN1851717A (en) | Special integrated circuit comprehensive system and method | |
| CN103974081B (en) | HEVC coding method based on multi-core processor Tilera | |
| CN1197253C (en) | Data high speed compressing and stretching method and device | |
| CN1761322A (en) | Selection method of reference pictures | |
| CN1838605A (en) | Scientific and technological adjudgment courtroom system | |
| CN1932812A (en) | Method and apparatus for holding journal | |
| CN102867022A (en) | System for anonymizing set type data by partially deleting certain items | |
| CN1499403A (en) | Method and system of computer aided analyzing patent data | |
| CN1702659A (en) | IP base LSI designing system and designing method | |
| CN1949732A (en) | Method and system for network community and searching combination | |
| CN1932864A (en) | Apparatus and method for producing electronic construction files | |
| CN1265558C (en) | A schematic diagram inspection method for hardware design | |
| CN1900903A (en) | Using a graphics system to enable a multi-user computer system | |
| CN1870752A (en) | Deblock filtering method and device for video-frequency coding/decoding | |
| CN1583478A (en) | Wireless monitoring and fault diagnostic system and method for vehicle | |
| CN1492359A (en) | Automatic state machine searching and matching method of multiple key words | |
| CN1870566A (en) | Method for implementing image in exchange system | |
| CN1667617A (en) | PCB design method and system for automatically leading-in designing rules | |
| CN1258724C (en) | Update backup system for homogeneous double-system data conversion and its method | |
| CN100340979C (en) | File comparision method | |
| CN1607771A (en) | Method for improving accessibility of communication equipment | |
| CN1599369A (en) | Physical address conversion device and conversion method | |
| CN1518312A (en) | Method of multi-channel data processing | |
| CN100340094C (en) | Telephone conference boards | |
| CN1710861A (en) | Method and apparatus for seting charge strategy |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20080116 Termination date: 20180909 |
|
| CF01 | Termination of patent right due to non-payment of annual fee |