CN103974081B - HEVC coding method based on multi-core processor Tilera - Google Patents
HEVC coding method based on multi-core processor Tilera Download PDFInfo
- Publication number
- CN103974081B CN103974081B CN201410194175.0A CN201410194175A CN103974081B CN 103974081 B CN103974081 B CN 103974081B CN 201410194175 A CN201410194175 A CN 201410194175A CN 103974081 B CN103974081 B CN 103974081B
- Authority
- CN
- China
- Prior art keywords
- task
- tilera
- row
- current line
- encoding tasks
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 238000000034 method Methods 0.000 title claims abstract description 44
- 238000012545 processing Methods 0.000 claims abstract description 36
- 230000008569 process Effects 0.000 claims abstract description 20
- 238000001914 filtration Methods 0.000 claims abstract description 9
- 238000005457 optimization Methods 0.000 abstract description 5
- 238000005516 engineering process Methods 0.000 description 3
- 230000006870 function Effects 0.000 description 3
- 230000008901 benefit Effects 0.000 description 2
- 230000006835 compression Effects 0.000 description 2
- 238000007906 compression Methods 0.000 description 2
- 230000002035 prolonged effect Effects 0.000 description 2
- 241000777300 Congiopodidae Species 0.000 description 1
- 230000004913 activation Effects 0.000 description 1
- 230000006978 adaptation Effects 0.000 description 1
- 230000003044 adaptive effect Effects 0.000 description 1
- 230000000052 comparative effect Effects 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000007812 deficiency Effects 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000007670 refining Methods 0.000 description 1
- 238000012360 testing method Methods 0.000 description 1
Landscapes
- Compression Or Coding Systems Of Tv Signals (AREA)
Abstract
The invention discloses an HEVC coding method based on a multi-core processor Tilera. The HEVC coding method based on the multi-core processor Tilera comprises the steps that according to the number of cores of the multi-core processor Tilera, a top coder allocates multiple frame coder threads, and meanwhile, multiple work threads are allocated for coding and filtering; each frame coder thread issues the coding tasks and the filtering tasks of each line of a current frame to a task queue, the work threads read the task queue and process the read tasks with CTU as a unit, wavefront parallel processing is carried out on the coding tasks and the filtering tasks of all lines, and the HEVC coding of the frame is completed. According to the HEVC coding method based on the multi-core processor Tilera, the tasks in each line of each frame are divided into the coding tasks and the filtering tasks, balancing optimization of loads among cores can be achieved in a task detailed mode, the wavefront parallel processing is carried out on the coding tasks and the filtering tasks of each frame through the work threads, the parallel processing capability by the adoption of the multi-core processor Tilera is utilized fully, and the efficiency of the HEVC coding is improved greatly.
Description
Technical field
The present invention relates to HD video coding field, and in particular to a kind of HEVC based on polycaryon processor Tilera is encoded
Method.
Background technology
With the development and popularization of high-definition video technology, H.264/AVC video encoding standard cannot gradually meet and regard
The compression requirements of frequency evidence.In order to tackle such case, the Video coding integration and cooperation group (JCT- set up by MPEG and VCEG
VC the video encoding standard of a new generation, referred to as efficient video coding (HEVC) are developed：High Efficiency Video
Coding)。
HEVC on the basis of hybrid coding basic framework, has used more flexible block to divide knot compared with H.264/AVC
Structure, more accurate predictive mode and sample self adaptation skew (SAO：Sample Adaptive Offset) etc. new technique.Energy
It is enough ensure image quality with it is H.264/AVC identical while, by the half of Compression to the latter.But, along with high pressure
Shrinkage and come is high computation complexity, this causes difficulty for the application of HEVC with popularization.There is many to grind at present
The person of studying carefully proposes the optimized algorithm of HEVC, improves code efficiency.But in addition to optimizing from algorithm aspect, can also be by hard
The mode of part parallel processing accelerates coding rate.
Parallel processing typically has two class of data parallel and function parallelization.Data parallel refers to and for data to be divided into different masses, right
They carry out same operation simultaneously.Function parallelization refers to the function classification according to process, reaches parallel processing by stream treatment
Purpose.HEVC is in design, it has to be considered that the optimization method of many parallel processings, wherein has wavefront parallel than more typical
Process and the division of Tiles.In existing patent, the mode that a kind of dependence Tiles divides to carry out parallel processing by
Propose.The program is started with from parallel data processing, realizes the purpose for accelerating HEVC codings.
On the other hand, the two-dimentional bus architecture of Tilera polycaryon processors innovation, breaches the technology of traditional one-dimensional bus
Bottleneck, greatly improves the process performance of polycaryon processor.There is independent Cache between polycaryon processor Tilera each core
System and memory system, can be effectively prevented from the data access conflict of traditional shared drive mode, can give full play to each
The ability of individual core, improves program parallelization treatment effeciency.And do not occurred entering using polycaryon processor Tilera in prior art
Row HEVC is encoded, therefore needs a kind of HEVC coded methods of utilization Tilera polycaryon processors badly, improves existing HEVC codings
Efficiency.
The content of the invention
For the deficiencies in the prior art, the invention provides a kind of HEVC coding staffs based on polycaryon processor Tilera
Method.
A kind of HEVC coded methods based on polycaryon processor Tilera, including：
(1) check figure according to polycaryon processor Tilera, distributes several frame encoder threads by top layer encoder, is used for
Parallel processing different frame, while the multiple worker threads of distribution are used for being encoded and being filtered；
(2) present frame processed for each frame encoder threads, frame encoder threads are by the coding of each row in present frame
Task and filter task are distributed to task queue, and worker thread reads task queue and the task to reading in units of CTU is entered
Row is processed, and the encoding tasks of each row carry out wavefront parallel processing with filter task, completes the HEVC codings of the frame.
Top layer encoder is software upper layer module, is substantially carried out thread distribution and initialization, and encodes progress feedback etc.
Operation.
Task in each frame per a line is divided into encoding tasks and filter task by the present invention, with many suitable for Tilera
Encoding tasks in each frame and filter task are carried out wavefront by worker thread by the two-dimentional bus architecture of core processor innovation
Parallel processing, is conducive to improving the code efficiency of HEVC codings.
In step (1), the number of frame encoder threads is 1～6.
In step (1), in polycaryon processor Tilera, each core distribution obtains a worker thread.
The number of the number of frame encoder threads and worker thread is relevant with the check figure of polycaryon processor Tilera.Acquiescence feelings
Under condition, the quantity of frame encoder threads is voluntarily determined according to the check figure of polycaryon processor Tilera by top layer encoder.Work as check figure
During more than 32, distribute 6 frame encoder threads；Otherwise, when check figure is more than or equal to 16,5 frame encoder threads are distributed；It is no
Then, when check figure is more than or equal to 12,4 frame encoder threads are distributed；Otherwise, when check figure is more than or equal to 4,2 frames of distribution are compiled
Code device thread；Otherwise, only distribute 1 frame encoder threads.And each core distribution obtains a worker thread under default situations.This
Outward, it is also possible to the quantity of artificial prescribed coding device thread and worker thread based on experience value.
The encoding tasks process for processing each row in step (2) during wavefront parallel processing is as follows：
(2-1) judge whether current line is the first row, proceeded as follows according to judged result：
If a () current line is the first row, if current line completes the threshold of the CTU quantity more than or equal to setting of encoding tasks
Value, then be distributed to the encoding tasks of next line in task queue；
If b () current line is not the first row, make the following judgment：
The difference of the CTU quantity that if current line completes the CTU quantity of encoding tasks and lastrow completes encoding tasks be less than or
Equal to the threshold value of setting, then terminate the encoding tasks of current line, worker thread re-reads task queue；
If current line completes the threshold value of the CTU quantity more than or equal to setting of encoding tasks, and is not last column, then will
The encoding tasks of next line are distributed in task queue, and continue with the encoding tasks of the row；
If current line completes the threshold value of the CTU quantity more than or equal to setting of encoding tasks, and is last column, then continue
Process the encoding tasks of the row；
(2-2), after the completion of the encoding tasks of current line are processed, the line number of current line and the filter delay line number of setting are compared
Size：
If line number is deducted filtering for the line number of current line and is prolonged more than the filter delay line number of setting by the line number of current line
The filter task of the row of line number is added to task queue late, and worker thread re-reads task queue；
Otherwise, worker thread re-reads task queue.
The filter task process for processing each row in step (2) during wavefront parallel processing is as follows：
If current line completes the CTU quantity of filter task and lastrow complete filter task CTU quantity difference less than setting
Fixed threshold value, then terminate the filter task of current line, and worker thread re-reads task queue；
If current line completes the threshold value of the CTU quantity more than or equal to setting of filter task, and is not last column, then will
The filter task of next line is distributed in task queue, and continues with the filter task of the row；
If current line completes the threshold value of the CTU quantity more than or equal to setting of encoding tasks, and is last column, then continue
Process the filter task of the row.
When encoding tasks of the worker thread process per a line or filter task, it is that (Coding Tree Unit are compiled with CTU
Code tree unit) for processing unit, from first in the encoding tasks of every a line or filter task unfinished CTU start to process.
In the processing procedure of each frame, by present frame according to CTU point of row.When certain a line processing progress is more than some row of next line
When (threshold value of setting), the process task of next line can be added task queue by worker thread；Meanwhile, when certain a line processing progress
When being less than some row with lastrow difference, current line can be locked, and wait lastrow activation this journey, start again at process.
Worker thread realizes HEVC cataloged procedures according to WPP (English spelling, translator of Chinese) form by the two rules
Processed.So as to reach the purpose of parallel processing, and it is sufficiently used the superiority of Tilera polycaryon processors.Carry out
During wavefront parallel processing, frame encoder threads are first directly distributed to the encoding tasks of present frame the first row in task queue, work
Make the encoding tasks that thread performs the first row, rule is processed according to more than in the process of implementation, constantly the coding of each row is appointed
Business and filter task are added into task queue, during addition, thread each task also in ceaselessly process task queue, because
This forms software flow processing procedure, substantially increases code efficiency.
The filter delay line number is 0～2.
Preferably, the filter delay line number is 2.
The threshold value is 2～4.
The line number of delay and set threshold value size directly determine HEVC coding accuracy rate.Postpone line number and threshold value is got over
Greatly, the accuracy rate of HEVC codings is higher, but code efficiency can be caused to decline.Therefore preferably, filter delay row in the present invention
Number is 2, and the threshold value for setting also is 2.
In addition, combining processor platform, the optimisation strategy provided using Tilera, including compiling option optimization, circulating net
Network optimizes, Intrinsic optimizations, Feedback optimizations etc., further improves code efficiency.
The HEVC coded methods based on polycaryon processor Tilera of the present invention, the task in each frame per a line is divided
For encoding tasks and filter task, the balance optimizing of inter-core load is realized in the way of refining task, by worker thread to every
Encoding tasks and filter task in one frame carry out wavefront parallel processing, take full advantage of the two of the innovation of Tilera polycaryon processors
Dimension bus architecture and internuclear independent Cache and memory system, realize the HEVC codings of two-dimentional bus, the HEVC coding staffs
Method breaches traditional polycaryon processor using unidirectional bus and the technical bottleneck of shared drive, by applying polycaryon processor
The parallel processing capability of Tilera, substantially increases the code efficiency of HEVC codings.
Specific embodiment
Below in conjunction with specific embodiment, the present invention is described in detail.
The HEVC coded methods based on polycaryon processor Tilera of the present embodiment, including：
(1) check figure according to polycaryon processor Tilera, distributes several frame encoder threads by top layer encoder, is used for
Parallel processing different frame, while the multiple worker threads of distribution are used for being encoded and being filtered；
The number of frame encoder threads is 1～6, and each core distribution in polycaryon processor Tilera obtains an active line
Journey.
In the present embodiment, the check figure of polycaryon processor Tilera is 36, and top layer encoder distributes 6 frame encoder threads, often
Individual core distribution obtains a worker thread, therefore one has 36 worker threads.
(2) present frame processed for each frame encoder threads, frame encoder threads are by the coding of each row in present frame
Task and filter task are distributed to task queue, and worker thread reads task queue and the task to reading in units of CTU is entered
Row is processed, and the encoding tasks of each row carry out wavefront parallel processing with filter task, completes the HEVC codings of the frame.
The encoding tasks process for processing each row in step (2) during wavefront parallel processing is as follows：
(2-1) judge whether current line is the first row, proceeded as follows according to judged result：
If a () current line is the first row, if current line completes the threshold of the CTU quantity more than or equal to setting of encoding tasks
Value, then be distributed to the encoding tasks of next line in task queue；
If b () current line is not the first row, make the following judgment：
The difference of the CTU quantity that if current line completes the CTU quantity of encoding tasks and lastrow completes encoding tasks be less than or
Equal to the threshold value of setting, then terminate the encoding tasks of current line, worker thread re-reads task queue；
If current line completes the threshold value of the CTU quantity more than or equal to setting of encoding tasks, and is not last column, then will
The encoding tasks of next line are distributed in task queue, and continue with the encoding tasks of the row；
If current line completes the threshold value of the CTU quantity more than or equal to setting of encoding tasks, and is last column, then continue
Process the encoding tasks of the row；
(2-2), after the completion of the encoding tasks of current line are processed, the line number of current line and the filter delay line number of setting are compared
Size：
If line number is deducted filtering for the line number of current line and is prolonged more than the filter delay line number of setting by the line number of current line
The filter task of the row of line number is added to task queue late, and worker thread re-reads task queue；
Otherwise, worker thread re-reads task queue.
The filter task process for processing each row in step (2) during wavefront parallel processing is as follows：
If current line completes the CTU quantity of filter task and lastrow complete filter task CTU quantity difference less than setting
Fixed threshold value, then terminate the filter task of current line, and worker thread re-reads task queue；
If current line completes the threshold value of the CTU quantity more than or equal to setting of filter task, and is not last column, then will
The filter task of next line is distributed in task queue, and continues with the filter task of the row；
If current line completes the threshold value of the CTU quantity more than or equal to setting of encoding tasks, and is last column, then continue
Process the filter task of the row.
Wherein, filter delay line number is 0～2 (being 2 in the present embodiment).
The threshold value for setting is 2～4 (being 2 in the present embodiment).
The sequence of 5 representative different resolutions in the cycle testss that selection JCTVC is provided：
A_Traffic_2560x1600_30 (i.e. Traffic sequences), B_Kimono1_1920x1080_24 (are designated as
Kimono1 sequences), C_BasketballDrill_832x480_50 (being designated as BasketballDrill sequences), D_
RaceHorses_416x240_30 (being designated as RaceHorses sequences) and vidyo1_720p_60 (being designated as vidyo1 sequences) is surveyed
Examination, under same the encoding option (determines QP32), is compiled with TileraGX (1.2GHz) monokaryon serial codes and 36 cores parallel respectively
Code, as shown in table 1, wherein PSNR (Peak Signal to Noise Ratio) is Y-PSNR to efficiency comparative, represents and compiles
The quality of code；The ratio of frame per second when speed-up ratio is parallel and frame per second during serial.
Table 1
As it can be seen from table 1 using the present embodiment HEVC coded methods when, code check is slightly raised, and quality is declined slightly
In the case of, coding rate (frame per second) has large increase, about 10 times of average speedup.Multiframe parallel processing is mutual with WPP
It is engaged, the advantage of Tilera polycaryon processors can be fully played in the ideal case, is greatly enhanced HEVC codings
Efficiency.
Disclosed above is only the specific embodiment of the present invention, but protection scope of the present invention is not limited thereto, and is appointed
What those of ordinary skill in the art can carry out various changes and modification spirit and model without deviating from the present invention to the present invention
Enclose, should all cover within the protection domain of this practicality invention.
Claims (6)
1. a kind of HEVC coded methods based on polycaryon processor Tilera, it is characterised in that include：
(1) check figure according to polycaryon processor Tilera, distributes several frame encoder threads by top layer encoder, for parallel
Different frame is processed, while the multiple worker threads of distribution are used for being encoded and being filtered；
(2) present frame processed for each frame encoder threads, frame encoder threads are by the encoding tasks of each row in present frame
Task queue is distributed to filter task, worker thread is read at task queue the task in units of CTU to reading
Reason, and the encoding tasks of each row carry out wavefront parallel processing with filter task, complete the HEVC codings of the frame；
The encoding tasks process for processing each row in step (2) during wavefront parallel processing is as follows：
(2-1) judge whether current line is the first row, proceeded as follows according to judged result：
If a () current line is the first row, if current line completes the threshold value of the CTU quantity more than or equal to setting of encoding tasks,
Then the encoding tasks of next line are distributed in task queue；
If b () current line is not the first row, make the following judgment：
If the difference that current line completes the CTU quantity that the CTU quantity of encoding tasks and lastrow complete encoding tasks is less than or equal to
The threshold value of setting, then terminate the encoding tasks of current line, and worker thread re-reads task queue；
If current line completes the threshold value of the CTU quantity more than or equal to setting of encoding tasks, and is not last column, then will be next
Capable encoding tasks are distributed in task queue, and continue with the encoding tasks of the row；
If current line completes the threshold value of the CTU quantity more than or equal to setting of encoding tasks, and is last column, then continue with
The encoding tasks of the row；
(2-2), after the completion of the encoding tasks of current line are processed, the line number for comparing current line is big with the filter delay line number of setting
It is little：
If line number of the line number for current line is deducted filter delay row more than the filter delay line number of setting by the line number of current line
The filter task of several rows is added to task queue, and worker thread re-reads task queue；
Otherwise, worker thread re-reads task queue；
The filter task process for processing each row in step (2) during wavefront parallel processing is as follows：
If the difference that current line completes the CTU quantity that the CTU quantity of filter task and lastrow complete filter task is less than setting
Threshold value, then terminate the filter task of current line, and worker thread re-reads task queue；
If current line completes the threshold value of the CTU quantity more than or equal to setting of filter task, and is not last column, then will be next
Capable filter task is distributed in task queue, and continues with the filter task of the row；
If current line completes the threshold value of the CTU quantity more than or equal to setting of encoding tasks, and is last column, then continue with
The filter task of the row.
2. the HEVC coded methods based on polycaryon processor Tilera as claimed in claim 1, it is characterised in that the step
(1) in, the number of frame encoder threads is 1～6.
3. the HEVC coded methods based on polycaryon processor Tilera as claimed in claim 2, it is characterised in that the step
(1) in, in polycaryon processor Tilera, each core distribution obtains a worker thread.
4. the HEVC coded methods based on polycaryon processor Tilera as claimed in claim 1, it is characterised in that the filtering
It is 0～2 to postpone line number.
5. the HEVC coded methods based on polycaryon processor Tilera as claimed in claim 4, it is characterised in that the filtering
It is 2 to postpone line number.
6. HEVC coding staffs based on polycaryon processor Tilera as described in any one claim in claim 4～5
Method, it is characterised in that the threshold value is 2～4.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410194175.0A CN103974081B (en) | 2014-05-08 | 2014-05-08 | HEVC coding method based on multi-core processor Tilera |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410194175.0A CN103974081B (en) | 2014-05-08 | 2014-05-08 | HEVC coding method based on multi-core processor Tilera |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN103974081A CN103974081A (en) | 2014-08-06 |
| CN103974081B true CN103974081B (en) | 2017-03-22 |
Family
ID=51243052
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201410194175.0A Expired - Fee Related CN103974081B (en) | 2014-05-08 | 2014-05-08 | HEVC coding method based on multi-core processor Tilera |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN103974081B (en) |
Families Citing this family (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104202602B (en) * | 2014-08-18 | 2018-03-02 | 三星电子（中国）研发中心 | Perform the device and method of Video coding |
| CN104506867B (en) * | 2014-12-01 | 2017-07-21 | 北京大学 | Sample point self-adapted offset parameter method of estimation and device |
| CN104519360B (en) * | 2014-12-30 | 2019-03-01 | 中国科学院重庆绿色智能技术研究院 | A kind of compression method based on HEVC |
| CN105791829B (en) * | 2016-03-30 | 2019-05-03 | 南京邮电大学 | A kind of parallel intra-frame prediction method of HEVC based on multi-core platform |
| CN105992008B (en) * | 2016-03-30 | 2019-08-30 | 南京邮电大学 | A kind of multi-level multi-task parallel coding/decoding method in multi-core processor platform |
| CN107483950A (en) * | 2016-06-07 | 2017-12-15 | 北京大学 | Picture parallel encoding method and system |
| CN107197296B (en) * | 2017-06-22 | 2019-08-13 | 华中科技大学 | A kind of HEVC parallel encoding method and system based on COStream |
| CN108449603B (en) * | 2018-03-22 | 2019-11-22 | 南京邮电大学 | Based on the multi-level task level of multi-core platform and the parallel HEVC coding/decoding method of data level |
| CN110446043A (en) * | 2019-08-08 | 2019-11-12 | 南京邮电大学 | A kind of HEVC fine grained parallel coding method based on multi-core platform |
| CN110337002B (en) * | 2019-08-15 | 2022-03-29 | 南京邮电大学 | HEVC (high efficiency video coding) multi-level parallel decoding method on multi-core processor platform |
| CN115643403A (en) * | 2022-11-11 | 2023-01-24 | 上海哔哩哔哩科技有限公司 | AV1 filtering method and device |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102098503A (en) * | 2009-12-14 | 2011-06-15 | 中兴通讯股份有限公司 | Method and device for decoding image in parallel by multi-core processor |
| EP2445211A1 (en) * | 2009-06-18 | 2012-04-25 | ZTE Corporation | Multi-core image encoding processing device and image filtering method thereof |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2010016806A (en) * | 2008-06-04 | 2010-01-21 | Panasonic Corp | Frame coding and field coding determination method, image coding method, image coding apparatus, and program |
-
2014
- 2014-05-08 CN CN201410194175.0A patent/CN103974081B/en not_active Expired - Fee Related
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP2445211A1 (en) * | 2009-06-18 | 2012-04-25 | ZTE Corporation | Multi-core image encoding processing device and image filtering method thereof |
| CN102098503A (en) * | 2009-12-14 | 2011-06-15 | 中兴通讯股份有限公司 | Method and device for decoding image in parallel by multi-core processor |
Also Published As
| Publication number | Publication date |
|---|---|
| CN103974081A (en) | 2014-08-06 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN103974081B (en) | HEVC coding method based on multi-core processor Tilera | |
| CN105992008B (en) | A kind of multi-level multi-task parallel coding/decoding method in multi-core processor platform | |
| Das et al. | Distributed deep learning using synchronous stochastic gradient descent | |
| CN106454354B (en) | A kind of AVS2 parallel encoding processing system and method | |
| CN102547289B (en) | Fast motion estimation method realized based on GPU (Graphics Processing Unit) parallel | |
| CN102200906B (en) | Processing system and processing method of large-scale concurrent data stream | |
| CN111182239B (en) | AI video processing method and device | |
| CN102625108B (en) | Multi-core-processor-based H.264 decoding method | |
| CN101583041B (en) | Image filtering method of multi-core image encoding processing equipment and equipment | |
| CN110337002B (en) | HEVC (high efficiency video coding) multi-level parallel decoding method on multi-core processor platform | |
| CN101860752B (en) | Video code stream parallelization method for embedded multi-core system | |
| CN104869398A (en) | Parallel method of realizing CABAC in HEVC based on CPU+GPU heterogeneous platform | |
| CN104469396A (en) | Distributed transcoding system and method | |
| CN105791829B (en) | A kind of parallel intra-frame prediction method of HEVC based on multi-core platform | |
| CN1921625A (en) | Filtering method and system of deblocking effect filter | |
| CN103188521A (en) | Method and device for transcoding distribution, method and device for transcoding | |
| CN109495743A (en) | A kind of parallelization method for video coding based on isomery many places platform | |
| WO2016210177A1 (en) | Parallel intra-prediction | |
| KR20130095927A (en) | Apparatus for correcting of in-loop pixel filter using parameterized complexity measure and method of the same | |
| CN114968587A (en) | Training method for computing MOE (machine-oriented Equipment) by parallel heterogeneous platform | |
| CN1589032A (en) | Loop filter based on multistage parallel pipeline mode | |
| CN103379319A (en) | Filtering method, filter and encoder and decoder including filter | |
| CN113242433B (en) | Image compression method and image compression system based on ARM multi-core heterogeneous processor | |
| CN103763569B (en) | A kind of HEVC fine grained parallel Forecasting Methodology based on First Input First Output | |
| CN110446043A (en) | A kind of HEVC fine grained parallel coding method based on multi-core platform |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20170322 |