CN103974081A - HEVC coding method based on multi-core processor Tilera - Google Patents
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Abstract
The invention discloses an HEVC coding method based on a multi-core processor Tilera. The HEVC coding method based on the multi-core processor Tilera comprises the steps that according to the number of cores of the multi-core processor Tilera, a top coder allocates multiple frame coder threads, and meanwhile, multiple work threads are allocated for coding and filtering; each frame coder thread issues the coding tasks and the filtering tasks of each line of a current frame to a task queue, the work threads read the task queue and process the read tasks with CTU as a unit, wavefront parallel processing is carried out on the coding tasks and the filtering tasks of all lines, and the HEVC coding of the frame is completed. According to the HEVC coding method based on the multi-core processor Tilera, the tasks in each line of each frame are divided into the coding tasks and the filtering tasks, balancing optimization of loads among cores can be achieved in a task detailed mode, the wavefront parallel processing is carried out on the coding tasks and the filtering tasks of each frame through the work threads, the parallel processing capability by the adoption of the multi-core processor Tilera is utilized fully, and the efficiency of the HEVC coding is improved greatly.
Description
Technical field
The present invention relates to HD video coding field, be specifically related to a kind of HEVC coding method based on polycaryon processor Tilera.
Background technology
Along with the development of high-definition video technology is with universal, H.264/AVC video encoding standard cannot meet the compression requirements of video data gradually.In order to tackle this situation, the Video coding integration and cooperation group (JCT-VC) being set up by MPEG and VCEG has developed video encoding standard of new generation, is called efficient video coding (HEVC:High Efficiency Video Coding).
HEVC with H.264/AVC compare, on the basis of hybrid coding basic framework, used piece partition structure more flexibly, the new technologies such as more accurate predictive mode and sample self adaptation skew (SAO:SampleAdaptive Offset).Can guarantee image quality with H.264/AVC identical in, half by Compression to the latter.But, being accompanied by high compression rate and what come is high computation complexity, this has caused difficulty for the application and popularization of HEVC.At present there have been many researchers to propose the optimized algorithm of HEVC, improved code efficiency.But except from algorithm aspect is optimized, can also accelerate coding rate by the mode of hardware parallel processing.
Parallel processing generally has data parallel and function parallelization two classes.Data parallel refers to data to be divided into different masses, and they are carried out to same operation simultaneously.Function parallelization refers to, according to the Function Classification of processing, reach the object of parallel processing by stream treatment.HEVC, when design, has considered the optimization method of many parallel processings, wherein more typically has the division of wavefront parallel processing and Tiles.In existing patent, the mode that a kind of Tiles of dependence divides to carry out parallel processing is suggested.This scheme is started with from parallel data processing, has realized the object of accelerating HEVC coding.
On the other hand, the two-dimentional bus architecture of Tilera polycaryon processor innovation, has broken through the technical bottleneck of traditional unidirectional bus, has improved greatly the handling property of polycaryon processor.Between each core of polycaryon processor Tilera, there are independently Cache system and memory system, can effectively avoid the data access conflict of traditional shared drive mode, can give full play to the ability of each core, improve program parallelization treatment effeciency.And in prior art, do not occur utilizing polycaryon processor Tilera to carry out HEVC coding, and therefore need a kind of HEVC coding method of the Tilera of utilization polycaryon processor badly, improve the efficiency of existing HEVC coding.
Summary of the invention
For the deficiencies in the prior art, the invention provides a kind of HEVC coding method based on polycaryon processor Tilera.
A HEVC coding method based on polycaryon processor Tilera, comprising:
(1) according to the check figure of polycaryon processor Tilera, by top layer encoder, distribute several frame encoder threads, for parallel processing different frame, distribute a plurality of worker threads to be used for encoding and filtering simultaneously;
(2) for the present frame of each frame encoder thread process; frame encoder thread is distributed to task queue by coding task and the filter task of each row in present frame; worker thread reads task queue Bing YiCTUWei unit reading of task is processed; and the coding task of each row and filter task carry out wavefront parallel processing, completes the HEVC coding of this frame.
Top layer encoder is software upper layer module, mainly carries out thread distribution and initialization, and the operation such as coding progress feedback.
The present invention is coding task and filter task by the task division of every a line in each frame, to be applicable to the two-dimentional bus architecture of Tilera polycaryon processor innovation, by worker thread, the coding task in each frame and filter task are carried out to wavefront parallel processing, be conducive to improve the code efficiency of HEVC coding.
In described step (1), the number of frame encoder thread is 1～6.
In described step (1), in polycaryon processor Tilera, each core distribution obtains a worker thread.
The number of frame encoder thread is relevant with the check figure of polycaryon processor Tilera with the number of worker thread.Under default situations, the quantity of frame encoder thread is determined according to the check figure of polycaryon processor Tilera voluntarily by top layer encoder.When check figure is greater than 32, distribute 6 frame encoder threads; Otherwise, when check figure is more than or equal to 16, distribute 5 frame encoder threads; Otherwise, when check figure is more than or equal to 12, distribute 4 frame encoder threads; Otherwise, when check figure is more than or equal to 4, distribute 2 frame encoder threads; Otherwise, only distribute 1 frame encoder thread.And under default situations, each core distribution obtains a worker thread.In addition, also can be artificially the quantity of prescribed coding device thread and worker thread based on experience value.
The coding task process of processing each row in described step (2) in the process of wavefront parallel processing is as follows:
(2-1) judge that whether current line is the first row, proceeds as follows according to judged result:
(a), if current line is the first row, if the CTU quantity that current line completes coding task is more than or equal to the threshold value of setting, the coding task of next line is distributed in task queue;
(b) if current line is not the first row, make the following judgment:
If current line completes the threshold value that the CTU quantity of coding task and the difference of the CTU quantity that lastrow completes coding task are less than or equal to setting, stop the coding task of current line, worker thread reads task queue again;
If current line completes the threshold value that the CTU quantity of coding task is more than or equal to setting, and not last column, the coding task of next line is distributed in task queue, and continue to process the coding task of this row;
If current line completes the CTU quantity of coding task and is more than or equal to the threshold value of setting, and is last column, continue to process the coding task of this row;
(2-2), after the coding task of current line is finished dealing with, compare the size of the line number of current line and the filter delay line number of setting:
If the line number of current line is greater than the filter delay line number of setting, the filter task that the line number that is current line by line number deducts the row of filter delay line number is added into task queue, and worker thread reads task queue again;
Otherwise worker thread reads task queue again.
The filter task process of processing each row in described step (2) in the process of wavefront parallel processing is as follows:
If current line completes the threshold value that the CTU quantity of filter task and the difference of the CTU quantity that lastrow completes filter task are less than setting, stop the filter task of current line, worker thread reads task queue again;
If current line completes the threshold value that the CTU quantity of filter task is more than or equal to setting, and not last column, the filter task of next line is distributed in task queue, and continue to process the filter task of this row;
If current line completes the CTU quantity of coding task and is more than or equal to the threshold value of setting, and is last column, continue to process the filter task of this row.
When worker thread is processed the coding task of every a line or filter task, be with CTU (Coding TreeUnit, code tree unit) for processing unit, from the coding task of every a line or filter task, first uncompleted CTU starts to process.In the processing procedure of each frame, by present frame according to CTU apportion.When certain a line processing progress is greater than the some row of next line (threshold value of setting), worker thread can add task queue by the Processing tasks of next line; Meanwhile, when certain a line is processed progress and is less than some row with lastrow difference, current line can be locked, waits for lastrow activation this journey, again starts processing.
These two rules that rely on worker thread realize HEVC cataloged procedure and process according to WPP (English spelling, translator of Chinese) form.Thereby reach the object of parallel processing, and utilized fully the superiority of Tilera polycaryon processor.When carrying out wavefront parallel processing; frame encoder thread is first directly distributed to the coding task of present frame the first row in task queue; worker thread is carried out the coding task of the first row; in the process of implementation according to above processing rule; constantly the coding task of each row and filter task are added in task queue, during interpolation, thread is each task in Processing tasks queue ceaselessly also; so form software flow processing procedure, greatly improved code efficiency.
Described filter delay line number is 0～2.
As preferably, described filter delay line number is 2.
Described threshold value is 2～4.
The line number postponing and the size of establishing threshold value have directly determined the accuracy rate of HEVC coding.Postpone line number and threshold value larger, the accuracy rate of HEVC coding is higher, but can cause code efficiency to decline.Therefore as preferred, in the present invention, filter delay line number is 2, and the threshold value of setting is also 2.
In addition, associative processor platform, the optimisation strategy of using Tilera to provide, comprises compile option optimization, recirculating network optimization, Intrinsic optimization, Feedback optimization etc., further improve code efficiency.
HEVC coding method based on polycaryon processor Tilera of the present invention, by the task division of every a line in each frame, be coding task and filter task, in the mode of refinement task, realize the balance optimizing of inter-core load, by worker thread, the coding task in each frame and filter task are carried out to wavefront parallel processing, take full advantage of two-dimentional bus architecture and internuclear independently Cache and the memory system of the innovation of Tilera polycaryon processor, realized the HEVC coding of two-dimentional bus, this HEVC coding method has broken through the technical bottleneck that traditional polycaryon processor adopts unidirectional bus and shared drive, by the parallel processing capability of application polycaryon processor Tilera, greatly improved the code efficiency of HEVC coding.
Embodiment
Below in conjunction with specific embodiment, the present invention is described in detail.
The HEVC coding method based on polycaryon processor Tilera of the present embodiment, comprising:
(1) according to the check figure of polycaryon processor Tilera, by top layer encoder, distribute several frame encoder threads, for parallel processing different frame, distribute a plurality of worker threads to be used for encoding and filtering simultaneously;
The number of frame encoder thread is 1～6, and in polycaryon processor Tilera, each core distribution obtains a worker thread.
In the present embodiment, the check figure of polycaryon processor Tilera is 36, and top layer encoder distributes 6 frame encoder threads, and each core distribution obtains a worker thread, therefore one has 36 worker threads.
(2) for the present frame of each frame encoder thread process; frame encoder thread is distributed to task queue by coding task and the filter task of each row in present frame; worker thread reads task queue Bing YiCTUWei unit reading of task is processed; and the coding task of each row and filter task carry out wavefront parallel processing, completes the HEVC coding of this frame.
The coding task process of processing each row in step (2) in the process of wavefront parallel processing is as follows:
(2-1) judge that whether current line is the first row, proceeds as follows according to judged result:
(a), if current line is the first row, if the CTU quantity that current line completes coding task is more than or equal to the threshold value of setting, the coding task of next line is distributed in task queue;
(b) if current line is not the first row, make the following judgment:
If current line completes the threshold value that the CTU quantity of coding task and the difference of the CTU quantity that lastrow completes coding task are less than or equal to setting, stop the coding task of current line, worker thread reads task queue again;
If current line completes the threshold value that the CTU quantity of coding task is more than or equal to setting, and not last column, the coding task of next line is distributed in task queue, and continue to process the coding task of this row;
If current line completes the CTU quantity of coding task and is more than or equal to the threshold value of setting, and is last column, continue to process the coding task of this row;
(2-2), after the coding task of current line is finished dealing with, compare the size of the line number of current line and the filter delay line number of setting:
If the line number of current line is greater than the filter delay line number of setting, the filter task that the line number that is current line by line number deducts the row of filter delay line number is added into task queue, and worker thread reads task queue again;
Otherwise worker thread reads task queue again.
The filter task process of processing each row in step (2) in the process of wavefront parallel processing is as follows:
If current line completes the threshold value that the CTU quantity of filter task and the difference of the CTU quantity that lastrow completes filter task are less than setting, stop the filter task of current line, worker thread reads task queue again;
If current line completes the threshold value that the CTU quantity of filter task is more than or equal to setting, and not last column, the filter task of next line is distributed in task queue, and continue to process the filter task of this row;
If current line completes the CTU quantity of coding task and is more than or equal to the threshold value of setting, and is last column, continue to process the filter task of this row.
Wherein, filter delay line number is 0～2 (in the present embodiment for be 2).
The threshold value of setting is 2～4 (being 2 in the present embodiment).
Choose the sequence of 5 different resolutions representative in the cycle tests that JCTVC provides:
A_Traffic_2560x1600_30 (being Traffic sequence), B_Kimono1_1920x1080_24 (being designated as Kimono1 sequence), C_BasketballDrill_832x480_50 (being designated as BasketballDrill sequence), D_RaceHorses_416x240_30 (being designated as RaceHorses sequence) and vidyo1_720p_60 (being designated as vidyo1 sequence) test, under same the encoding option (determining QP32), use respectively TileraGX (1.2GHz) monokaryon serial code and 36 core parallel encodings, efficiency contrast is as shown in table 1, wherein PSNR (PeakSignal to Noise Ratio) is Y-PSNR, the quality of presentation code, the ratio of frame per second when frame per second when speed-up ratio is parallel and serial.
Table 1
As can be seen from Table 1, while adopting the HEVC coding method of the present embodiment, code check slightly raises, and in the situation that quality slightly declines, coding rate (frame per second) has had large increase, average speedup to be about 10 times.Multiframe parallel processing and WPP work in coordination, and can fully play in the ideal case the advantage of Tilera polycaryon processor, greatly improve the efficiency of HEVC coding.
Disclosed is above only specific embodiments of the invention; but protection scope of the present invention is not limited to this; any those of ordinary skill in the art can carry out various changes and modification and not depart from the spirit and scope of the present invention the present invention, within all should being encompassed in the protection range of this practicality invention.
Claims (8)
1. the HEVC coding method based on polycaryon processor Tilera, is characterized in that, comprising:
(1) according to the check figure of polycaryon processor Tilera, by top layer encoder, distribute several frame encoder threads, for parallel processing different frame, distribute a plurality of worker threads to be used for encoding and filtering simultaneously;
(2) for the present frame of each frame encoder thread process; frame encoder thread is distributed to task queue by coding task and the filter task of each row in present frame; worker thread reads task queue Bing YiCTUWei unit reading of task is processed; and the coding task of each row and filter task carry out wavefront parallel processing, completes the HEVC coding of this frame.
2. the HEVC coding method based on polycaryon processor Tilera as claimed in claim 1, is characterized in that, in described step (1), the number of frame encoder thread is 1～6.
3. the HEVC coding method based on polycaryon processor Tilera as claimed in claim 2, is characterized in that, in described step (1), in polycaryon processor Tilera, each core distribution obtains a worker thread.
4. the HEVC coding method based on polycaryon processor Tilera as claimed in claim 3, is characterized in that, the coding task process of processing each row in described step (2) in the process of wavefront parallel processing is as follows:
(2-1) judge that whether current line is the first row, proceeds as follows according to judged result:
(a), if current line is the first row, if the CTU quantity that current line completes coding task is more than or equal to the threshold value of setting, the coding task of next line is distributed in task queue;
(b) if current line is not the first row, make the following judgment:
If current line completes the threshold value that the CTU quantity of coding task and the difference of the CTU quantity that lastrow completes coding task are less than or equal to setting, stop the coding task of current line, worker thread reads task queue again;
If current line completes the threshold value that the CTU quantity of coding task is more than or equal to setting, and not last column, the coding task of next line is distributed in task queue, and continue to process the coding task of this row;
If current line completes the CTU quantity of coding task and is more than or equal to the threshold value of setting, and is last column, continue to process the coding task of this row;
(2-2), after the coding task of current line is finished dealing with, compare the size of the line number of current line and the filter delay line number of setting:
If the line number of current line is greater than the filter delay line number of setting, the filter task that the line number that is current line by line number deducts the row of filter delay line number is added into task queue, and worker thread reads task queue again;
Otherwise worker thread reads task queue again.
5. the HEVC coding method based on polycaryon processor Tilera as claimed in claim 4, is characterized in that, the filter task process of processing each row in described step (2) in the process of wavefront parallel processing is as follows:
If current line completes the threshold value that the CTU quantity of filter task and the difference of the CTU quantity that lastrow completes filter task are less than setting, stop the filter task of current line, worker thread reads task queue again;
If current line completes the threshold value that the CTU quantity of filter task is more than or equal to setting, and not last column, the filter task of next line is distributed in task queue, and continue to process the filter task of this row;
If current line completes the CTU quantity of coding task and is more than or equal to the threshold value of setting, and is last column, continue to process the filter task of this row.
6. the HEVC coding method based on polycaryon processor Tilera as claimed in claim 4, is characterized in that, described filter delay line number is 0～2.
7. the HEVC coding method based on polycaryon processor Tilera as claimed in claim 6, is characterized in that, described filter delay line number is 2.
8. the HEVC coding method based on polycaryon processor Tilera as described in any one claim in claim 4～7, is characterized in that, described threshold value is 2～4.
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| CN104202602A (en) * | 2014-08-18 | 2014-12-10 | 三星电子（中国）研发中心 | Device and method of executing video coding |
| CN104506867A (en) * | 2014-12-01 | 2015-04-08 | 北京大学 | Sample adaptive offset parameter estimation method and device |
| CN104519360A (en) * | 2014-12-30 | 2015-04-15 | 中国科学院重庆绿色智能技术研究院 | Compression method based on HEVC |
| CN105791829A (en) * | 2016-03-30 | 2016-07-20 | 南京邮电大学 | HEVC parallel intra-frame prediction method based on multi-core platform |
| CN105992008A (en) * | 2016-03-30 | 2016-10-05 | 南京邮电大学 | Multilevel multitask parallel decoding algorithm on multicore processor platform |
| CN107197296A (en) * | 2017-06-22 | 2017-09-22 | 华中科技大学 | A kind of HEVC parallel encoding method and systems based on COStream |
| CN107483950A (en) * | 2016-06-07 | 2017-12-15 | 北京大学 | Picture parallel encoding method and system |
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| CN107197296A (en) * | 2017-06-22 | 2017-09-22 | 华中科技大学 | A kind of HEVC parallel encoding method and systems based on COStream |
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| WO2024098821A1 (en) * | 2022-11-11 | 2024-05-16 | 上海哔哩哔哩科技有限公司 | Av1 filtering method and apparatus |
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