CN117408196A - Chip simulation method and simulator - Google Patents
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Abstract
The specification discloses a chip simulation method and a simulator. The simulator receives chip data of a chip to be simulated. Next, in response to a selection operation by the user, at least one target chip interface is determined from among the plurality of interface types of chip interfaces. And then, receiving a logic level signal sent by the target chip interface, and determining a power-on reset signal corresponding to the logic level signal. And finally, resetting the chip to be simulated based on the power-on reset signal, and simulating data communication between the chip to be simulated and the target chip interface according to the chip data after the resetting is completed. The method can determine at least one target chip interface from the chip interfaces with a plurality of interface types, simulate the data communication between the chip to be simulated and the target chip interface according to the chip data, and therefore improve the development and test efficiency of the chip with the chip interfaces with the plurality of interface types.
Description
Technical Field
The present disclosure relates to the field of computer technologies, and in particular, to a method and an emulator for chip emulation.
Background
With the continuous expansion of the application functions of chips, multi-interface chip-based solutions are being supported and generalized by many vendors. A multi-interface chip is a chip that integrates multiple different types of chip interfaces. It can simultaneously support a plurality of different communication protocols and interface standards, thereby providing greater flexibility and compatibility. The multi-interface chip can be embedded into any mobile device and is applied to the fields of payment, transportation, electronic ticketing, password service and the like.
Currently, in order to verify the correctness and feasibility of the chip design of a multi-interface chip, after the multi-interface chip is manufactured, concurrent processing functions of different types of interfaces in the multi-interface chip are tested to find defects or logic problems in the chip design of the multi-interface chip. However, this method is costly and the development cycle of the chip is long.
Therefore, how to simulate the multi-interface chip to improve the development and testing efficiency of the multi-interface chip is a problem to be solved.
Disclosure of Invention
The present specification provides a chip emulation method, an emulator, an electronic device, and a machine-readable storage medium to emulate a multi-interface chip, thereby improving the efficiency of development and testing of the multi-interface chip.
The technical scheme adopted in the specification is as follows:
the specification provides a chip simulation method, which comprises the following steps:
receiving chip data of a chip to be simulated;
determining at least one target chip interface from among the plurality of interface-type chip interfaces in response to a selection operation by a user;
receiving a logic level signal sent by the target chip interface, and determining a power-on reset signal corresponding to the logic level signal;
resetting the chip to be simulated based on the power-on reset signal, and simulating data communication between the chip to be simulated and the target chip interface according to the chip data after the resetting is completed.
Optionally, the plurality of interface types includes: 7816 interface, SWP interface, SPI interface, I2C interface.
Optionally, the power-on reset signal includes a global power-on reset signal corresponding to the at least one target chip interface;
resetting the chip to be simulated based on the power-on reset signal, and simulating data communication between the chip to be simulated and the target chip interface according to the chip data after the resetting is completed, wherein the method comprises the following steps:
if the global power-on reset signal is detected to be changed from high level to low level, hard reset is carried out on the chip to be simulated, and data communication between the chip to be simulated and the target chip interface is terminated before the hard reset is completed;
and if the global power-on reset signal is detected to be changed from low level to high level, determining that the hard reset of the chip to be simulated is completed, and simulating data communication between the chip to be simulated and the target chip interface based on the chip data after the hard reset is completed.
Optionally, the power-on reset signal further includes a local power-on reset signal corresponding to the 7816 interface, and the method further includes:
determining whether the 7816 interface is included in the target chip interface; if not, detecting the global power-on reset signal, wherein the local power-on reset signal is in a high level, performing cold reset on the chip to be simulated, and simulating data communication between the chip to be simulated and the target chip interface based on the chip data after the cold reset is completed;
if the local power-on reset signal is detected, the chip to be simulated is subjected to thermal reset, and after the thermal reset is finished, the data communication between the chip to be simulated and the target chip interface is simulated based on the chip data.
Optionally, receiving a logic level signal sent by the target chip interface includes:
receiving a logic level signal sent by the target chip interface based on a reference voltage; if the input voltage of the target chip interface is greater than the threshold value corresponding to the reference voltage, determining that the logic level signal sent by the target chip interface is at a high level; and if the input voltage of the target chip interface is not greater than the threshold value corresponding to the reference voltage, determining that the logic level signal sent by the target chip interface is low level.
Optionally, the power supply voltage signal includes a first power supply voltage and a second power supply voltage, where the first power supply voltage is used to represent a power supply voltage corresponding to an interface other than the 7816 interface, and the second power supply voltage is used to represent a power supply voltage corresponding to the 7816 interface;
receiving a logic level signal sent by the target chip interface based on a reference voltage, wherein the logic level signal comprises the following components:
determining whether the 7816 interface is included in the target chip interface, if not, taking the first power supply voltage as the reference voltage of the logic level signal, and receiving the logic level signal sent by the target chip interface based on the first power supply voltage; and if so, taking the second power supply voltage as the reference voltage of the logic level signal, and receiving the logic level signal sent by the target chip interface based on the second power supply voltage.
The present specification provides an emulator, comprising:
the chip module is used for receiving chip data of the chip to be simulated;
a selection module for determining at least one target chip interface from among the plurality of interface types of chip interfaces in response to a selection operation by a user;
the power-on module is used for receiving the logic level signal sent by the target chip interface and determining a power-on reset signal corresponding to the logic level signal;
and the reset module is used for resetting the chip to be simulated based on the power-on reset signal, and simulating data communication between the chip to be simulated and the target chip interface according to the chip data after the reset is completed.
Optionally, the plurality of interface types includes: 7816 interface, SWP interface, SPI interface, I2C interface.
Optionally, the power-on reset signal includes a global power-on reset signal corresponding to the at least one target chip interface;
the reset module is used for carrying out hard reset on the chip to be simulated if the global power-on reset signal is detected to be changed from a high level to a low level, and terminating data communication between the chip to be simulated and the target chip interface before the hard reset is completed; and if the global power-on reset signal is detected to be changed from low level to high level, determining that the hard reset of the chip to be simulated is completed, and simulating data communication between the chip to be simulated and the target chip interface based on the chip data after the hard reset is completed.
Optionally, the power-on reset signal further includes a local power-on reset signal corresponding to the 7816 interface, and the emulator further includes:
an interface control module, configured to determine whether the 7816 interface is included in the target chip interface; if not, detecting the global power-on reset signal, wherein the local power-on reset signal is in a high level, performing cold reset on the chip to be simulated, and simulating data communication between the chip to be simulated and the target chip interface based on the chip data after the cold reset is completed; if the local power-on reset signal is detected, the chip to be simulated is subjected to thermal reset, and after the thermal reset is finished, the data communication between the chip to be simulated and the target chip interface is simulated based on the chip data.
The specification provides an electronic device, which comprises a communication interface, a processor, a memory and a bus, wherein the communication interface, the processor and the memory are connected with each other through the bus;
the memory stores machine readable instructions, and the processor executes the method of chip emulation described above by invoking the machine readable instructions.
The present specification provides a machine-readable storage medium storing machine-readable instructions that, when invoked and executed by a processor, implement the method of chip emulation described above.
The above-mentioned at least one technical scheme that this specification adopted can reach following beneficial effect:
in the chip simulation method provided in the present specification, the simulator receives chip data of a chip to be simulated. Next, in response to a selection operation by the user, at least one target chip interface is determined from among the plurality of interface types of chip interfaces. And then, receiving a logic level signal sent by the target chip interface, and determining a power-on reset signal corresponding to the logic level signal. And finally, resetting the chip to be simulated based on the power-on reset signal, and simulating data communication between the chip to be simulated and the target chip interface according to the chip data after the resetting is completed. The method can determine at least one target chip interface from the chip interfaces with a plurality of interface types, simulate the data communication between the chip to be simulated and the target chip interface according to the chip data, and therefore improve the development and test efficiency of the chip with the chip interfaces with the plurality of interface types.
Drawings
The accompanying drawings, which are included to provide a further understanding of the specification, illustrate and explain the exemplary embodiments of the present specification and their description, are not intended to limit the specification unduly. Attached at
In the figure:
FIG. 1 is a flow chart illustrating a method of chip emulation in accordance with an exemplary embodiment;
FIG. 2 is a schematic diagram of an emulator shown in an exemplary embodiment;
FIG. 3 is a schematic diagram of another simulator shown in an exemplary embodiment;
FIG. 4 is a block diagram of an electronic device in which an emulator is shown in an exemplary embodiment;
FIG. 5 is a block diagram of an emulator shown in an exemplary embodiment.
Detailed Description
In order to make the technical solutions in the present specification better understood by those skilled in the art, the technical solutions in the embodiments of the present specification will be clearly and completely described below with reference to the drawings in the embodiments of the present specification, and it is obvious that the described embodiments are only some embodiments of the present specification, not all embodiments. All other embodiments, which can be made by one of ordinary skill in the art without undue burden from the present disclosure, are intended to be within the scope of the present disclosure.
It should be noted that: in other embodiments, the steps of the corresponding method are not necessarily performed in the order shown and described in this specification. In some other embodiments, the method may include more or fewer steps than described in this specification. Furthermore, individual steps described in this specification, in other embodiments, may be described as being split into multiple steps; while various steps described in this specification may be combined into a single step in other embodiments.
In order to make the technical solution in the embodiments of the present specification better understood by those skilled in the art, the related art related to the embodiments of the present specification will be briefly described below.
A multi-interface chip is a chip that integrates multiple different types of chip interfaces. It can simultaneously support a plurality of different communication protocols and interface standards, thereby providing greater flexibility and compatibility.
ISO7816 is a standardized contact smart card communication protocol for reading from and writing to contact smart cards. This protocol defines the physical characteristics of the smart card, the electrical signals, the transmission protocol, and the format and rules of the application instructions, ensuring that the data can be exchanged efficiently. The 7816 interface is a half duplex serial communication interface.
SWP (Single Wire Protocol ) is an interface protocol for transferring information between a SIM card and a Near Field Communication (NFC) chip of a cellular telephone. The SWP interface is a communication interface that implements full duplex communication on one single line.
The SPI (Serial Peripheral Interface ) bus system is a synchronous serial peripheral interface for the processing chip to exchange communications with various peripheral devices in a serial fashion. It operates in a master-slave mode, which typically has a master device and one or more slave devices, for full duplex serial data transmission.
I2C (Inter-Integrated Circuit, integrated circuit bus) is a bidirectional two-wire synchronous serial bus. It requires only two wires to transfer information between devices connected to the bus.
In practical applications, in order to verify the correctness and feasibility of the chip design of the multi-interface chip, it is generally required to manufacture the multi-interface chip based on the chip design of the multi-interface chip, and then test the concurrent functions of different types of interfaces in the multi-interface chip to find defects or logic problems in the chip design of the multi-interface chip. However, this method is costly and the development cycle of the chip is long.
Based on this, the present specification proposes a technical solution of determining at least one target chip interface from among a plurality of interface types of chip interfaces, and simulating data communication between a chip to be simulated and the target chip interface according to chip data.
The following describes in detail the technical solutions provided by the embodiments of the present specification with reference to the accompanying drawings.
FIG. 1 is a flow chart of a method of chip simulation, shown in an exemplary embodiment, specifically comprising the steps of:
s100: and receiving chip data of the chip to be simulated.
S102: at least one target chip interface is determined from among the plurality of interface-type chip interfaces in response to a selection operation by a user.
In the embodiment of the present specification, the method for chip simulation is applied to a simulator for simulating a chip mounted on an electronic device, and the execution subject may be the simulator. The physical carrier of the emulator may be an electronic device comprising: servers, server clusters, etc. For convenience of description, a method of chip simulation provided in the present specification will be described below with only an emulator as an execution subject.
In practical application, in the process of testing the concurrent processing function of the multi-interface chip, a mode of manually dialing codes or selecting jumper wires is needed to select which chip interfaces in the multi-interface chip are concurrently processed. However, manual dialing or jumper selection requires manual adjustment of the multi-interface chip by a technician during each test, which is cumbersome to operate and results in lower efficiency in testing the concurrent processing functions of the multi-interface chip.
Based on this, the emulator can determine which chip interfaces to perform concurrent processing from among the plurality of interface type chip interfaces in response to a selection operation by the user.
In the embodiment of the present specification, the emulator may receive chip data of a chip to be emulated.
The simulator may then determine at least one target chip interface from among the plurality of interface-type chip interfaces in response to a selection operation by the user.
Specifically, the emulator outputs an interface selection signal for representing at least one chip interface in response to a selection operation by a user. And determining at least one target chip interface from the chip interfaces of the plurality of interface types according to the interface selection signal.
For example, the interface management interface is presented to the user, and the user can select at least one chip interface from the interface management interface and output an interface selection signal for representing the at least one chip interface. And determining at least one target chip interface from the chip interfaces of the plurality of interface types according to the interface selection signal.
Wherein the plurality of interface types may include: 7816 interface, SWP interface, SPI interface, I2C interface, etc.
For example, the plurality of interface types may include: 7816 interface, SWP interface, SPI interface, I2C interface. The target chip interface may be any one chip interface of 7816 interface, SWP interface, SPI interface, I2C interface, or any two chip interfaces of 7816 interface, SWP interface, SPI interface, I2C interface, or any three chip interfaces of 7816 interface, SWP interface, SPI interface, I2C interface, or four chip interfaces of 7816 interface, SWP interface, SPI interface, I2C interface.
S104: and receiving a logic level signal sent by the target chip interface, and determining a power-on reset signal corresponding to the logic level signal.
In the embodiment of the present disclosure, the emulator may receive the logic level signal sent by the target chip interface, and determine a power-on reset signal corresponding to the logic level signal.
Specifically, the receiving target chip interface transmits a logic level signal based on the power supply voltage. And if the input voltage of the target chip interface is in a high level range corresponding to the power supply voltage, determining that the logic level signal sent by the target chip interface is in a high level. If the input voltage of the target chip interface is in the low level range corresponding to the power supply voltage, determining that the logic level signal sent by the target chip interface is in the low level.
It should be noted that different digital circuit standards or devices define specific ranges or level definitions of logic levels. For example, in the Transistor-Transistor Logic (TTL) standard, the high level is defined as a voltage between 2.4V and 5V, and the low level is defined as a voltage between 0V and 0.8V. In the Complementary Metal Oxide Semiconductor (CMOS) standard, a high level is defined as a voltage close to a power supply voltage, and a low level is defined as close to 0V.
For example, when the power supply voltage is 5V, the high level range may be 2.4V to 5V, and the low level range may be 0V to 0.8V. If the input voltage of the target chip interface is between 2.4V and 5V, determining that the logic level signal sent by the target chip interface is at a high level. If the input voltage of the target chip interface is between 0V and 0.8V, determining that the logic level signal sent by the target chip interface is at a low level.
In practical applications, among the multiple interface types, the power supply voltage required by the 7816 interface is different from the power supply voltages required by the SWP interface, the SPI interface, and the I2C interface, so when the 7816 interface is included in the target chip interface, the chip needs to be powered by the power supply voltage conforming to the 7816 interface. Since the power supply voltage for powering the chip varies, the high level range and the low level range correspondingly vary.
Based on this, the emulator may determine whether the 7816 interface is included in the target chip interface, thereby determining which power supply voltage to send the logic level signal based on.
In the embodiment of the present specification, the power supply voltage signal includes a first power supply voltage for representing a power supply voltage corresponding to an interface other than the 7816 interface, and a second power supply voltage for representing a power supply voltage corresponding to the 7816 interface.
And determining whether the target chip interface comprises a 7816 interface, and if not, receiving a logic level signal sent by the target chip interface based on the first power supply voltage. If so, the receiving target chip interface transmits a logic level signal based on the second power supply voltage.
S106: resetting the chip to be simulated based on the power-on reset signal, and simulating data communication between the chip to be simulated and the target chip interface according to the chip data after the resetting is completed.
In practical applications, reset is an important step in the process of simulating a chip. Reset refers to restoring the chip to an initial state when the chip is started or in an abnormal state. In the process of simulating the chip, it is determined whether the chip can correctly initialize the respective modules and registers under different reset conditions. After the reset is completed, whether the chip can enter a normal working state to perform stable operation according to an expected mode is determined, and no abnormality or error is caused. Thus, defects or logic problems associated with reset in chip design are discovered.
Based on this, the simulator can reset the chip to be simulated and simulate the data communication after the reset is completed to find defects or logic problems in the chip design.
In the embodiment of the present disclosure, the emulator may reset the chip to be emulated based on the power-on reset signal, and after the reset is completed, emulate data communication between the chip to be emulated and the target chip interface according to the chip data.
In practical applications, hard Reset (Hard Reset) is a Reset mode triggered by a physical circuit or a signal. The hard reset may reset the entire system or device to an initial state, clear all registers and memory data, and restart the device. Thus, during a hard reset, the voltage and signal instabilities within the circuit cause the circuit to be in an indeterminate state. This may result in errors, loss or corruption of data communications.
Based on this, in order to avoid errors, loss or damage to the data communication, it is generally necessary to perform the data communication after the hard reset is completed.
In this illustrative embodiment, the power-on-reset signal comprises a global power-on-reset signal corresponding to at least one target chip interface.
And if the global power-on reset signal is detected to be changed from a high level to a low level, performing hard reset on the chip to be simulated, and terminating data communication between the chip to be simulated and the target chip interface before the hard reset is completed.
If the global power-on reset signal is detected to be changed from low level to high level, determining that the hard reset for the chip to be simulated is completed, and simulating data communication between the chip to be simulated and the target chip interface based on the chip data after the hard reset is completed. Referring to fig. 2, fig. 2 is a schematic diagram of an emulator shown in an exemplary embodiment. The simulator may include: the device comprises a chip module, a selection module, a power-on module and a reset module.
In fig. 2, a chip module receives chip data of a chip to be emulated to emulate the chip. The selection module responds to the selection operation of a user, determines at least one target chip interface from the chip interfaces of the plurality of interface types, and sends a logic level signal sent by the target chip interface to the power-on module. The power-on module receives the logic level signal sent by the target chip interface, determines a power-on reset signal corresponding to the logic level signal, and sends the power-on reset signal corresponding to the logic level signal to the reset module. The reset module receives a power-on reset signal corresponding to the logic level signal, and resets the chip simulated by the chip module based on the power-on reset signal. And after the reset is finished, simulating the data communication between the chip simulated by the chip module and the target chip interface according to the chip data.
In practical applications, the cold reset signal is generally caused by a memory fault and is used for triggering cold reset, where cold reset refers to that the whole reset system and the memory need to be restored to the first power-on state, and can be performed by powering up and powering down. The hot reset signal is typically caused by a non-memory failure and is used to trigger a hot reset, which refers to resetting a portion of the modules or units during a reset of the reset system. Among the interface types, the SWP interface, the SPI interface, and the I2C interface have no cold reset and no hot reset, and only the 7816 interface has a cold reset and a hot reset. Therefore, the emulator also needs to perform a cold reset or a hot reset for the 7816 interface during the emulation of the chip.
Based on this, when it is determined that the 7816 interface is included in the target chip interface, it is determined whether to perform a cold reset or a hot reset on the chip to be emulated.
In the embodiment of the present specification, the power-on reset signal further includes a local power-on reset signal corresponding to the 7816 interface.
And determining whether the target chip interface comprises a 7816 interface, if not, determining that the local power-on reset signal is in a high level, performing cold reset in the chip to be simulated when the global power-on reset signal is detected, and performing simulation on data communication between the chip to be simulated and the target chip interface based on chip data after the cold reset is completed.
If so, when the local power-on reset signal is detected, the chip to be simulated is subjected to thermal reset, and after the thermal reset is completed, the data communication between the chip to be simulated and the target chip interface is simulated based on the chip data.
Referring to fig. 3, fig. 3 is a schematic diagram of another simulator shown in an exemplary embodiment. The simulator may further include: and an interface control module.
In fig. 3, the chip module receives chip data of a chip to be emulated to emulate the chip. The selection module responds to the selection operation of a user, determines at least one target chip interface from the chip interfaces of the plurality of interface types, and sends a logic level signal sent by the target chip interface to the power-on module. The power-on module receives the logic level signal sent by the target chip interface, determines a global power-on reset signal corresponding to the logic level signal, and sends the global power-on reset signal corresponding to the logic level signal to the reset module.
The interface control module performs data communication with a target chip interface in the selection module, determines whether the target chip interface comprises a 7816 interface, if not, determines that the local power-on reset signal is at a high level, performs cold reset on a chip simulated by the chip module when the global power-on reset signal is detected, and simulates data communication between the chip simulated by the chip module and the target chip interface based on chip data after the cold reset is completed.
If so, when the local power-on reset signal is detected, the chip simulated by the chip module is subjected to thermal reset, and after the thermal reset is finished, the data communication between the chip simulated by the chip module and the target chip interface is simulated based on the chip data.
As can be seen from the above method, the simulator receives chip data of the chip to be simulated. Next, in response to a selection operation by the user, at least one target chip interface is determined from among the plurality of interface types of chip interfaces. And then, receiving a logic level signal sent by the target chip interface, and determining a power-on reset signal corresponding to the logic level signal. And finally, resetting the chip to be simulated based on the power-on reset signal, and simulating data communication between the chip to be simulated and the target chip interface according to the chip data after the resetting is completed. The method can determine at least one target chip interface from the chip interfaces with a plurality of interface types, simulate the data communication between the chip to be simulated and the target chip interface according to the chip data, and therefore improve the development and test efficiency of the chip with the chip interfaces with the plurality of interface types.
Referring to fig. 4, fig. 4 is a block diagram of an electronic device in which an emulator is shown in an exemplary embodiment. At the hardware level, the device includes a processor 402, an internal bus 404, a network interface 406, a memory 408, and a non-volatile storage 410, although other hardware requirements are possible. One or more embodiments of the present description may be implemented in a software-based manner, such as by the processor 402 reading a corresponding computer program from the non-volatile memory 410 into the memory 408 and then running. Of course, in addition to software implementation, one or more embodiments of the present disclosure do not exclude other implementation manners, such as a logic device or a combination of software and hardware, etc., that is, the execution subject of the following processing flow is not limited to each logic unit, but may also be hardware or a logic device.
Referring to fig. 5, fig. 5 is a block diagram of an emulator shown in an exemplary embodiment. The simulator can be applied to the electronic equipment shown in fig. 4 to realize the technical scheme of the specification. Wherein the simulator may include:
the chip module 500 is configured to receive chip data of a chip to be emulated.
A selection module 502, configured to determine at least one target chip interface from the plurality of chip interfaces of interface types in response to a selection operation of a user.
The power-on module 504 is configured to receive a logic level signal sent by the target chip interface, and determine a power-on reset signal corresponding to the logic level signal.
And the reset module 506 is configured to reset the chip to be simulated based on the power-on reset signal, and simulate data communication between the chip to be simulated and the target chip interface according to the chip data after the reset is completed.
Optionally, the plurality of interface types includes: 7816 interface, SWP interface, SPI interface, I2C interface.
Optionally, the power-on reset signal includes a global power-on reset signal corresponding to the at least one target chip interface, and the reset module 506 is specifically configured to, if the global power-on reset signal is detected to change from a high level to a low level, perform a hard reset on the chip to be simulated, and terminate data communication between the chip to be simulated and the target chip interface before the hard reset is completed; and if the global power-on reset signal is detected to be changed from low level to high level, determining that the hard reset of the chip to be simulated is completed, and simulating data communication between the chip to be simulated and the target chip interface based on the chip data after the hard reset is completed.
Optionally, the power-on reset signal further includes a local power-on reset signal corresponding to the 7816 interface, and the emulator further includes:
an interface control module, configured to determine whether the 7816 interface is included in the target chip interface; if not, detecting the global power-on reset signal, wherein the local power-on reset signal is in a high level, performing cold reset on the chip to be simulated, and simulating data communication between the chip to be simulated and the target chip interface based on the chip data after the cold reset is completed; if the local power-on reset signal is detected, the chip to be simulated is subjected to thermal reset, and after the thermal reset is finished, the data communication between the chip to be simulated and the target chip interface is simulated based on the chip data.
Optionally, the power-on module 504 is specifically configured to receive a logic level signal sent by the target chip interface based on a power supply voltage; if the input voltage of the target chip interface is in a high level range corresponding to the power supply voltage, determining that a logic level signal sent by the target chip interface is in a high level; and if the input voltage of the target chip interface is in a low level range corresponding to the power supply voltage, determining that the logic level signal sent by the target chip interface is in a low level.
Optionally, the power supply voltage includes a first power supply voltage and a second power supply voltage, where the first power supply voltage is used to represent a power supply voltage corresponding to an interface other than the 7816 interface, the second power supply voltage is used to represent a power supply voltage corresponding to the 7816 interface, and the power-on module 504 is specifically configured to determine whether the target chip interface includes the 7816 interface, and if not, receive a logic level signal sent by the target chip interface based on the first power supply voltage; and if so, receiving a logic level signal sent by the target chip interface based on the second power supply voltage.
The implementation process of the functions and roles of each unit in the above device is specifically shown in the implementation process of the corresponding steps in the above method, and will not be described herein again.
For the device embodiments, reference is made to the description of the method embodiments for the relevant points, since they essentially correspond to the method embodiments. The apparatus embodiments described above are illustrative only, in that the elements illustrated as separate elements may or may not be physically separate, and the elements shown as elements may or may not be physical elements, may be located in one place, or may be distributed over a plurality of network elements. Some or all of the modules may be selected according to actual needs to achieve the purposes of the present description. Those of ordinary skill in the art will understand and implement the present invention without undue burden.
The system, apparatus, module or unit set forth in the above embodiments may be implemented in particular by a computer chip or entity, or by a product having a certain function. A typical implementation device is a computer, which may be in the form of a personal computer, laptop computer, cellular telephone, camera phone, smart phone, personal digital assistant, media player, navigation device, email device, game console, tablet computer, wearable device, or a combination of any of these devices.
In a typical configuration, a computer includes one or more processors (CPUs), input/output interfaces, network interfaces, and memory.
The memory may include volatile memory in a computer-readable medium, random Access Memory (RAM) and/or nonvolatile memory, such as Read Only Memory (ROM) or flash memory (flash RAM). Memory is an example of computer-readable media.
Computer readable media, including both non-transitory and non-transitory, removable and non-removable media, may implement information storage by any method or technology. The information may be computer readable instructions, data structures, modules of a program, or other data. Examples of storage media for a computer include, but are not limited to, phase change memory (PRAM), static Random Access Memory (SRAM), dynamic Random Access Memory (DRAM), other types of Random Access Memory (RAM), read Only Memory (ROM), electrically Erasable Programmable Read Only Memory (EEPROM), flash memory or other memory technology, read only compact disc read only memory (CD-ROM), digital Versatile Discs (DVD) or other optical storage, magnetic cassettes, magnetic disk storage, quantum memory, graphene-based storage or other magnetic storage devices, or any other non-transmission medium, which can be used to store information that can be accessed by the computing device. Computer-readable media, as defined herein, does not include transitory computer-readable media (transmission media), such as modulated data signals and carrier waves.
User information (including but not limited to user equipment information, user personal information, etc.) and data (including but not limited to data for analysis, stored data, presented data, etc.) referred to herein are both user-authorized or fully authorized information and data by parties, and the collection, use and processing of relevant data requires compliance with relevant laws and regulations and standards of the relevant country and region, and is provided with corresponding operation portals for user selection of authorization or denial.
It should also be noted that the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article or apparatus that comprises the element.
The foregoing describes specific embodiments of the present disclosure. Other embodiments are within the scope of the following claims. In some cases, the actions or steps recited in the claims can be performed in a different order than in the embodiments and still achieve desirable results. In addition, the processes depicted in the accompanying figures do not necessarily require the particular order shown, or sequential order, to achieve desirable results. In some embodiments, multitasking and parallel processing are also possible or may be advantageous.
The terminology used in the one or more embodiments of the specification is for the purpose of describing particular embodiments only and is not intended to be limiting of the one or more embodiments of the specification. As used in this specification, one or more embodiments and the appended claims, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It should also be understood that the term "and/or" as used herein refers to and encompasses any or all possible combinations of one or more of the associated listed items.
It should be understood that although the terms first, second, third, etc. may be used in one or more embodiments of the present description to describe various information, these information should not be limited to these terms. These terms are only used to distinguish one type of information from another. For example, first information may also be referred to as second information, and similarly, second information may also be referred to as first information, without departing from the scope of one or more embodiments of the present description. The word "if" as used herein may be interpreted as "at … …" or "at … …" or "responsive to a determination", depending on the context.
The foregoing description of the preferred embodiment(s) is (are) merely intended to illustrate the embodiment(s) of the present invention, and it is not intended to limit the embodiment(s) of the present invention to the particular embodiment(s) described.
Claims (12)
1. A method of chip emulation, comprising:
receiving chip data of a chip to be simulated;
determining at least one target chip interface from among the plurality of interface-type chip interfaces in response to a selection operation by a user;
receiving a logic level signal sent by the target chip interface, and determining a power-on reset signal corresponding to the logic level signal;
resetting the chip to be simulated based on the power-on reset signal, and simulating data communication between the chip to be simulated and the target chip interface according to the chip data after the resetting is completed.
2. The method of claim 1, wherein the plurality of interface types comprises: 7816 interface, SWP interface, SPI interface, I2C interface.
3. The method of claim 2, wherein the power-on-reset signal comprises a global power-on-reset signal corresponding to the at least one target chip interface;
resetting the chip to be simulated based on the power-on reset signal, and simulating data communication between the chip to be simulated and the target chip interface according to the chip data after the resetting is completed, wherein the method comprises the following steps:
if the global power-on reset signal is detected to be changed from high level to low level, hard reset is carried out on the chip to be simulated, and data communication between the chip to be simulated and the target chip interface is terminated before the hard reset is completed;
and if the global power-on reset signal is detected to be changed from low level to high level, determining that the hard reset of the chip to be simulated is completed, and simulating data communication between the chip to be simulated and the target chip interface based on the chip data after the hard reset is completed.
4. The method of claim 3, wherein the power-on reset signal further comprises a local power-on reset signal corresponding to a 7816 interface, the method further comprising:
determining whether the 7816 interface is included in the target chip interface; if not, determining that the local power-on reset signal is at a high level, when the global power-on reset signal is detected, performing cold reset on the chip to be simulated, and after the cold reset is completed, simulating data communication between the chip to be simulated and the target chip interface based on the chip data;
if so, when the local power-on reset signal is detected, carrying out thermal reset on the chip to be simulated, and after the thermal reset is finished, carrying out simulation on data communication between the chip to be simulated and the target chip interface based on the chip data.
5. The method of claim 2, wherein receiving the logic level signal sent by the target chip interface comprises:
receiving a logic level signal sent by the target chip interface based on a power supply voltage; if the input voltage of the target chip interface is in a high level range corresponding to the power supply voltage, determining that a logic level signal sent by the target chip interface is in a high level; and if the input voltage of the target chip interface is in a low level range corresponding to the power supply voltage, determining that the logic level signal sent by the target chip interface is in a low level.
6. The method of claim 5, wherein the power supply voltages comprise a first power supply voltage for representing a power supply voltage corresponding to an interface other than the 7816 interface, and a second power supply voltage for representing a power supply voltage corresponding to the 7816 interface;
receiving a logic level signal sent by the target chip interface based on a power supply voltage, wherein the logic level signal comprises the following components:
determining whether the 7816 interface is included in the target chip interface, and if not, receiving a logic level signal sent by the target chip interface based on the first power supply voltage; and if so, receiving a logic level signal sent by the target chip interface based on the second power supply voltage.
7. A simulator, comprising:
the chip module is used for receiving chip data of the chip to be simulated;
a selection module for determining at least one target chip interface from among the plurality of interface types of chip interfaces in response to a selection operation by a user;
the power-on module is used for receiving the logic level signal sent by the target chip interface and determining a power-on reset signal corresponding to the logic level signal;
and the reset module is used for resetting the chip to be simulated based on the power-on reset signal, and simulating data communication between the chip to be simulated and the target chip interface according to the chip data after the reset is completed.
8. The emulator of claim 7, wherein the plurality of interface types include: 7816 interface, SWP interface, SPI interface, I2C interface.
9. The emulator of claim 8, wherein the power-on reset signal includes a global power-on reset signal corresponding to the at least one target chip interface;
the reset module is used for carrying out hard reset on the chip to be simulated if the global power-on reset signal is detected to be changed from a high level to a low level, and terminating data communication between the chip to be simulated and the target chip interface before the hard reset is completed; and if the global power-on reset signal is detected to be changed from low level to high level, determining that the hard reset of the chip to be simulated is completed, and simulating data communication between the chip to be simulated and the target chip interface based on the chip data after the hard reset is completed.
10. The emulator of claim 9, wherein the power-on reset signal further comprises a local power-on reset signal corresponding to the 7816 interface, the emulator further comprising:
an interface control module, configured to determine whether the 7816 interface is included in the target chip interface; if not, detecting the global power-on reset signal, wherein the local power-on reset signal is in a high level, performing cold reset on the chip to be simulated, and simulating data communication between the chip to be simulated and the target chip interface based on the chip data after the cold reset is completed; if the local power-on reset signal is detected, the chip to be simulated is subjected to thermal reset, and after the thermal reset is finished, the data communication between the chip to be simulated and the target chip interface is simulated based on the chip data.
11. An electronic device, comprising a communication interface, a processor, a memory and a bus, wherein the communication interface, the processor and the memory are connected with each other through the bus;
the memory stores machine readable instructions, the processor executing the method of any of claims 1 to 6 by invoking the machine readable instructions.
12. A machine-readable storage medium storing machine-readable instructions which, when invoked and executed by a processor, implement the method of any one of claims 1 to 6.
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| CN202311378539.6A CN117408196A (en) | 2023-10-23 | 2023-10-23 | Chip simulation method and simulator |
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| CN202311378539.6A CN117408196A (en) | 2023-10-23 | 2023-10-23 | Chip simulation method and simulator |
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