CN117393492A - Method for forming shallow slot isolation structure - Google Patents
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- CN117393492A CN117393492A CN202311426391.9A CN202311426391A CN117393492A CN 117393492 A CN117393492 A CN 117393492A CN 202311426391 A CN202311426391 A CN 202311426391A CN 117393492 A CN117393492 A CN 117393492A
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- 238000002955 isolation Methods 0.000 title claims abstract description 61
- 238000000034 method Methods 0.000 title claims abstract description 57
- 239000000758 substrate Substances 0.000 claims abstract description 51
- 239000004065 semiconductor Substances 0.000 claims abstract description 49
- 230000007547 defect Effects 0.000 claims abstract description 18
- 238000005530 etching Methods 0.000 claims abstract description 18
- 238000005229 chemical vapour deposition Methods 0.000 claims abstract description 16
- 239000012495 reaction gas Substances 0.000 claims abstract description 15
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 8
- 238000000151 deposition Methods 0.000 claims description 8
- 239000001301 oxygen Substances 0.000 claims description 8
- 229910052760 oxygen Inorganic materials 0.000 claims description 8
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 claims description 6
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 6
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 claims description 6
- 230000008021 deposition Effects 0.000 claims description 6
- 229910000077 silane Inorganic materials 0.000 claims description 6
- 239000007789 gas Substances 0.000 claims description 4
- 229910052786 argon Inorganic materials 0.000 claims description 3
- 239000001257 hydrogen Substances 0.000 claims description 3
- 229910052739 hydrogen Inorganic materials 0.000 claims description 3
- 125000004435 hydrogen atom Chemical class [H]* 0.000 claims description 3
- 229910052757 nitrogen Inorganic materials 0.000 claims description 3
- 239000010410 layer Substances 0.000 description 58
- 238000005516 engineering process Methods 0.000 description 11
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 8
- 230000003647 oxidation Effects 0.000 description 6
- 238000007254 oxidation reaction Methods 0.000 description 6
- 229910052681 coesite Inorganic materials 0.000 description 4
- 229910052906 cristobalite Inorganic materials 0.000 description 4
- 238000010586 diagram Methods 0.000 description 4
- 239000000377 silicon dioxide Substances 0.000 description 4
- 235000012239 silicon dioxide Nutrition 0.000 description 4
- 239000000243 solution Substances 0.000 description 4
- 229910052682 stishovite Inorganic materials 0.000 description 4
- 229910052905 tridymite Inorganic materials 0.000 description 4
- 239000011800 void material Substances 0.000 description 4
- 238000005137 deposition process Methods 0.000 description 3
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 3
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 2
- VEXZGXHMUGYJMC-UHFFFAOYSA-N Hydrochloric acid Chemical compound Cl VEXZGXHMUGYJMC-UHFFFAOYSA-N 0.000 description 2
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 2
- QAOWNCQODCNURD-UHFFFAOYSA-N Sulfuric acid Chemical compound OS(O)(=O)=O QAOWNCQODCNURD-UHFFFAOYSA-N 0.000 description 2
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 2
- 230000015556 catabolic process Effects 0.000 description 2
- 238000009413 insulation Methods 0.000 description 2
- 238000005468 ion implantation Methods 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 229910021645 metal ion Inorganic materials 0.000 description 2
- 239000002245 particle Substances 0.000 description 2
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 2
- 229910010271 silicon carbide Inorganic materials 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- 239000002344 surface layer Substances 0.000 description 2
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 1
- 244000025254 Cannabis sativa Species 0.000 description 1
- MYMOFIZGZYHOMD-UHFFFAOYSA-N Dioxygen Chemical compound O=O MYMOFIZGZYHOMD-UHFFFAOYSA-N 0.000 description 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- GPXJNWSHGFTCBW-UHFFFAOYSA-N Indium phosphide Chemical compound [In]#P GPXJNWSHGFTCBW-UHFFFAOYSA-N 0.000 description 1
- GRYLNZFGIOXLOG-UHFFFAOYSA-N Nitric acid Chemical compound O[N+]([O-])=O GRYLNZFGIOXLOG-UHFFFAOYSA-N 0.000 description 1
- 239000003929 acidic solution Substances 0.000 description 1
- 125000004429 atom Chemical group 0.000 description 1
- 239000013043 chemical agent Substances 0.000 description 1
- 239000003153 chemical reaction reagent Substances 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 229910003460 diamond Inorganic materials 0.000 description 1
- 239000010432 diamond Substances 0.000 description 1
- 229910001882 dioxygen Inorganic materials 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 229910017604 nitric acid Inorganic materials 0.000 description 1
- 125000004437 phosphorous atom Chemical group 0.000 description 1
- 238000005240 physical vapour deposition Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
- H01L21/31116—Etching inorganic layers by chemical means by dry-etching
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- General Chemical & Material Sciences (AREA)
- Inorganic Chemistry (AREA)
- Element Separation (AREA)
Abstract
The embodiment of the application discloses a method for forming a shallow slot isolation structure, which comprises the steps of providing a semiconductor substrate, wherein the semiconductor substrate is provided with at least one groove; placing a semiconductor substrate in a high-density plasma chemical vapor deposition chamber; introducing reaction gas with preset flow rate into the cavity, and applying first preset power to deposit a dielectric layer on the surface of the semiconductor substrate and the inner wall of the groove; etching the dielectric layer to repair the defects of the dielectric layer; and returning to execute the step of introducing reaction gas with preset flow rate into the cavity and applying preset pressure to form a dielectric layer covering the surface of the semiconductor substrate and the inner wall of the groove until the groove is filled, so as to form the shallow groove isolation structure. The scheme can reduce the defects of the shallow slot isolation structure.
Description
Technical Field
The application relates to the technical field of semiconductors, in particular to a method for forming a shallow trench isolation structure.
Background
Shallow Trench Isolation (STI) is a method of isolating a MOS integrated circuit. The shallow trench isolation technology is a process for manufacturing the transistor active region on the substrate, and can effectively ensure that the N-type and P-type doped regions are thoroughly separated. The traditional device structure uses a local oxidation isolation technology, si is oxidized into SiO2 between N-type and P-type doped regions by an oxidation method, and the N-type and P-type doped regions are isolated by utilizing the characteristic of SiO2 insulation. The shallow trench isolation technology is to etch Si in the N-type and P-type doped regions to form a shallow trench, and then fill insulating substances into the shallow trench, thereby achieving the isolation purpose.
Compared with the traditional local isolation oxidation technology, the shallow trench isolation technology can reduce leakage current between electrodes and bear larger breakdown voltage. Currently, high density plasma chemical vapor deposition (High Density Plasma Chemical Vapor Deposition, HDP-CVD) techniques have been widely used to form shallow trench isolation structures. However, as the process is improved and the aspect ratio of the trench required by different processes is continuously increased, the gap filling capability of the conventional HDP-CVD technology is insufficient, which may cause defects such as Void (Void) in the shallow trench isolation structure.
Disclosure of Invention
The embodiment of the application provides a method for forming a shallow slot isolation structure, which can reduce defects of the shallow slot isolation structure.
The embodiment of the application provides a method for forming a shallow trench isolation structure, which comprises the following steps:
providing a semiconductor substrate, wherein the semiconductor substrate is provided with at least one groove;
placing the semiconductor substrate in a high-density plasma chemical vapor deposition chamber;
introducing reaction gas with preset flow rate into the cavity, and applying first preset power to deposit a dielectric layer on the surface of the semiconductor substrate and the inner wall of the groove;
etching the dielectric layer to repair the defects of the dielectric layer;
and returning to execute the step of introducing reaction gas with preset flow rate into the cavity and applying preset pressure to form a dielectric layer covering the surface of the semiconductor substrate and the inner wall of the groove until the groove is filled, so as to form a shallow groove isolation structure.
In the method for forming the shallow trench isolation structure provided by the embodiment of the application, the reaction gas comprises silane and oxygen.
In the method for forming a shallow trench isolation structure provided in the embodiment of the present application, the flow rate of silane is 10sccm to 500sccm, and the flow rate of oxygen is 100sccm to 300sccm.
In the method for forming a shallow trench isolation structure provided in the embodiment of the present application, the first preset power is 3000W to 5000W.
In the method for forming a shallow trench isolation structure provided in the embodiment of the present application, the reaction gas used for etching the dielectric layer includes hydrogen, nitrogen, oxygen or argon.
In the method for forming a shallow trench isolation structure provided in the embodiment of the present application, when etching the dielectric layer, a second preset power is applied to the chamber.
In the method for forming a shallow trench isolation structure provided in the embodiment of the present application, the second preset power is 2000W to 4000W.
In the method for forming the shallow trench isolation structure provided by the embodiment of the application, the time for depositing the dielectric layer each time is 5-10 s.
In the method for forming the shallow trench isolation structure provided by the embodiment of the application, the time for etching the dielectric layer each time is 5 s-10 s.
In the method for forming a shallow trench isolation structure provided in the embodiment of the present application, after forming the shallow trench isolation structure, the method further includes:
and removing the redundant dielectric layer.
In summary, the method for forming a shallow trench isolation structure provided in the embodiments of the present application includes providing a semiconductor substrate having at least one trench thereon; placing the semiconductor substrate in a high-density plasma chemical vapor deposition chamber; introducing reaction gas with preset flow rate into the cavity, and applying first preset power to deposit a dielectric layer on the surface of the semiconductor substrate and the inner wall of the groove; etching the dielectric layer to repair the defects of the dielectric layer; and returning to execute the step of introducing reaction gas with preset flow rate into the cavity and applying preset pressure to form a dielectric layer covering the surface of the semiconductor substrate and the inner wall of the groove until the groove is filled, so as to form a shallow groove isolation structure. The scheme can repeatedly repair and fill the dielectric layer in the groove by repeatedly executing the deposition-etching-deposition process in the high-density plasma chemical vapor deposition chamber, so that the defect of the formed shallow groove isolation structure is reduced.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are needed in the description of the embodiments will be briefly introduced below, it being obvious that the drawings in the following description are only some embodiments of the present application, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a schematic defect diagram of a shallow trench isolation structure formed by a conventional HDP-CVD technique.
Fig. 2 is a flow chart of a method for forming a shallow trench isolation structure according to an embodiment of the present application.
Fig. 3 is a schematic structural diagram of a semiconductor device according to an embodiment of the present application.
FIG. 4 is a cross-sectional profile of a dielectric layer deposited by conventional HDP-CVD techniques.
Fig. 5 is a cross-sectional profile view of a dielectric layer deposited by a method for forming a shallow trench isolation structure according to an embodiment of the present application.
Fig. 6 is an enlarged schematic defect view of a shallow trench isolation structure formed by a conventional HDP-CVD technique.
Fig. 7 is an enlarged schematic view of a whole grass structure formed by the method for forming a shallow trench isolation structure according to an embodiment of the present application.
Fig. 8 is a schematic structural diagram of another semiconductor device according to an embodiment of the present application.
Detailed Description
Reference will now be made in detail to exemplary embodiments, examples of which are illustrated in the accompanying drawings. When the following description refers to the accompanying drawings, the same numbers in different drawings refer to the same or similar elements, unless otherwise indicated. The implementations described in the following exemplary examples are not representative of all implementations consistent with the present application. Rather, they are merely examples of apparatus and methods consistent with some aspects of the present application as detailed in the accompanying claims.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used in the description of the present application herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. The term "and/or" as used herein includes any and all combinations of one or more of the associated listed items.
It will be understood that when an element or layer is referred to as being "on," "adjacent," "connected to," or "coupled to" another element or layer, it can be directly on, adjacent, connected, or coupled to the other element or layer, or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" another element or layer, there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. may be used herein to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present application.
Spatially relative terms, such as "under," "below," "beneath," "under," "above," "over," and the like, may be used herein for ease of description to describe one element or feature's relationship to another element or feature as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use and operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements or features described as "under" or "beneath" other elements would then be oriented "on" the other elements or features. Thus, the exemplary terms "below" and "under" may include both an upper and a lower orientation. The device may be otherwise oriented (rotated 90 degrees or other orientations) and the spatially relative descriptors used herein interpreted accordingly.
Shallow Trench Isolation (STI) is a method of isolating a MOS integrated circuit. The shallow trench isolation technology is a process for manufacturing active regions of transistors on a substrate, and can effectively ensure that N-type and P-type doped regions can be thoroughly separated. The traditional device structure uses a local oxidation isolation technology, si is oxidized into SiO2 between N-type and P-type doped regions by an oxidation method, and the N-type and P-type doped regions are isolated by utilizing the characteristic of SiO2 insulation. The shallow trench isolation technology is to etch Si in the N-type and P-type doped regions to form a shallow trench, and then fill insulating substances into the shallow trench, thereby achieving the isolation purpose.
Compared with the traditional local isolation oxidation technology, the shallow trench isolation technology can reduce leakage current between electrodes and bear larger breakdown voltage. Currently, high density plasma chemical vapor deposition (High Density Plasma Chemical Vapor Deposition, HDP-CVD) techniques have been widely used to form shallow trench isolation structures. However, as the process is improved and the aspect ratio of the trenches required for different processes is increased, the conventional HDP-CVD technique has insufficient gap filling capability, which results in the occurrence of defects such as Void (Void) phenomenon as shown in fig. 1.
Based on the above, the embodiment of the application provides a method for forming a shallow trench isolation structure. The technical solutions shown in the present application will be described in detail by specific examples. The following description of the embodiments is not intended to limit the priority of the embodiments.
Referring to fig. 2 and 3, fig. 2 is a schematic flow chart of a method for forming a shallow trench isolation structure provided in the present application, and fig. 3 is a schematic structural diagram of a semiconductor device provided in an embodiment of the present application. The specific process of forming the shallow trench isolation structure can be as follows:
101. a semiconductor substrate having at least one trench thereon is provided.
The semiconductor substrate 10 may be made of monocrystalline silicon, silicon carbide, gallium arsenide, indium phosphide, silicon germanium or the like, the semiconductor substrate 10 may be a silicon germanium substrate, a group iii-v element compound substrate, a silicon carbide substrate or a stacked structure thereof, or a silicon-on-insulator structure, or may be a diamond substrate or other semiconductor material substrate known to those skilled in the art, for example, P atoms may be implanted into monocrystalline silicon to form an N-type conductive semiconductor substrate 10, or B atoms may be implanted into monocrystalline silicon to form a P-type conductive semiconductor substrate 10.
In some embodiments, the semiconductor substrate 10 may be sequentially stacked with a buried layer and an epitaxial layer. A trench 11 is provided in the epitaxial layer. In an implementation, the buried layer may be formed by ion implantation of the first conductivity type on the upper surface layer of the semiconductor substrate 10. For example, sb ion implantation may be performed on the upper surface layer of the semiconductor substrate 10 to obtain a buried layer. There are various methods of forming the epitaxial layer, such as physical vapor deposition, chemical vapor deposition, or other suitable methods.
The surface of the semiconductor substrate 10 may have a native oxide layer, surface particles, metal ions, etc. prior to placing the semiconductor substrate 10 into the high density plasma chemical vapor deposition chamber. If the semiconductor substrate 10 is directly placed in a high-density plasma chemical vapor deposition chamber for subsequent processing, various oxides are formed on the surface of the semiconductor substrate 10, resulting in defects in the shallow trench isolation structure 12 and seriously affecting the reliability of the shallow trench isolation structure 12.
To solve the above problems, the semiconductor substrate 10 may be cleaned using a wet cleaning process before the semiconductor substrate 10 is placed in the high-density plasma chemical vapor deposition chamber. For example, the semiconductor substrate 10 is cleaned with a chemical agent to remove a natural oxide layer, surface particles, metal ions, and the like on the surface of the semiconductor substrate 10.
Wherein the chemical reagent may comprise one or more of sulfuric acid, hydrochloric acid, nitric acid, hydrofluoric acid. That is, the acidic solution may include any one of the above-mentioned various solutions, or may also include a combination of any two or more of the above-mentioned various solutions, which is not limited herein.
102. The semiconductor substrate is placed in a high density plasma chemical vapor deposition chamber.
103. And introducing a reaction gas with a preset flow rate into the chamber, and applying a first preset power to deposit a dielectric layer on the surface of the semiconductor substrate and the inner wall of the groove.
Wherein the reactive gas comprises silane and oxygen. In the embodiments herein, the silane flow rate is 10sccm to 500sccm, such as 10sccm, 20sccm, 30sccm, 50sccm, 100sccm, 200sccm, 500sccm, or the like. The flow rate of the oxygen gas is 100sccm to 300sccm, for example, 100sccm, 110sccm, 120sccm, 130sccm, 200sccm, or the like. The first preset power is 3000W to 5000W, such as 3000W, 3500W, 3600W, 3700W, 5000W, or the like.
It should be noted that, the time for depositing the dielectric layer 20 is 5s to 10s, such as 5s, 6s, 7s, 8s, 9s, or 10s.
In this embodiment of the present application, the first preset power is greater than the conventional power, the flow of the reaction gas is less than the conventional flow, the deposition time of the dielectric layer 20 is less than the conventional deposition time, so that the filling capability of the dielectric layer 20 can be increased, and the formed filling cross-sectional morphology can be compared with fig. 4 and 5 in particular due to the conventional manner.
104. And etching the dielectric layer to repair the defect of the dielectric layer.
Specifically, the dielectric layer 20 may be etched using a reactive gas such as hydrogen, nitrogen, oxygen, or argon.
It should be noted that, the etching of the dielectric layer 20 uses a second preset power, and the second preset power is 2000W to 4000W, for example, 2000W, 3500W, 3600W, 3700W, 4000W, or the like.
The time for etching the dielectric layer 20 is 5 s-10 s, such as 5s, 6s, 7s, 8s, 9s or 10s.
In this embodiment of the present application, the second preset power is greater than the conventional power, and the etching time of the dielectric layer 20 is less than the conventional etching time, so that the repairing capability of the dielectric layer 20 can be increased, and the filling cross-section morphology is further improved.
105. And returning to execute the step of introducing reaction gas with preset flow rate into the cavity and applying preset pressure to form a dielectric layer covering the surface of the semiconductor substrate and the inner wall of the groove until the groove is filled, so as to form the shallow groove isolation structure.
In the embodiment of the application, the first preset power is increased, so that the deposition rate of the dielectric layer is increased, and the filling capacity of the dielectric layer is increased; and increasing the etching rate of the dielectric layer by increasing the second preset power so as to increase the repairing capability of the dielectric layer, and finally improving the shape of the filling section. In addition, by reducing the time of deposition and etching, the number of deposition-etching-deposition processes can be increased, and fewer defects are formed by each deposition, and fewer defects are required to be repaired by etching, so that the difficulty of filling the cross-sectional morphology is reduced, the defects of the formed shallow trench isolation structure 12 are reduced, and the method is particularly compared with fig. 6 and 7.
In some embodiments, after forming the shallow trench isolation structure 12, a planarization process may be further performed on the surface of the semiconductor substrate 10 to remove the excess dielectric layer 20.
In summary, the method for forming the shallow trench isolation structure 12 according to the embodiments of the present invention includes providing a semiconductor substrate 10, wherein the semiconductor substrate 10 has at least one trench 11; placing the semiconductor substrate 10 in a high-density plasma chemical vapor deposition chamber; introducing a reaction gas with a preset flow rate into the chamber, and applying a first preset power to deposit a dielectric layer 20 on the surface of the semiconductor substrate 10 and the inner wall of the groove 11; etching the dielectric layer 20 to repair defects of the dielectric layer 20; the step of introducing a reaction gas having a predetermined flow rate into the chamber and applying a predetermined pressure to form a dielectric layer 20 covering the surface of the semiconductor substrate 10 and the inner wall of the trench 11 is performed again until the trench 11 is completely filled, thereby forming a shallow trench isolation structure 12 as shown in fig. 8. The scheme can repeatedly repair and fill the dielectric layer 20 in the trench 11 by repeatedly executing the deposition-etching-deposition process in the high-density plasma chemical vapor deposition chamber, thereby reducing the defects of the formed shallow trench isolation structure 12.
The method for forming the shallow trench isolation structure provided by the application is described in detail, and specific examples are applied in the application to illustrate the principle and the implementation of the application, and the description of the above examples is only used for helping to understand the core idea of the application; meanwhile, those skilled in the art will have variations in the specific embodiments and application scope in light of the ideas of the present application, and the present description should not be construed as limiting the present application in view of the above.
Claims (10)
1. The method for forming the shallow slot isolation structure is characterized by comprising the following steps of:
providing a semiconductor substrate, wherein the semiconductor substrate is provided with at least one groove;
placing the semiconductor substrate in a high-density plasma chemical vapor deposition chamber;
introducing reaction gas with preset flow rate into the cavity, and applying first preset power to deposit a dielectric layer on the surface of the semiconductor substrate and the inner wall of the groove;
etching the dielectric layer to repair the defects of the dielectric layer;
and returning to execute the step of introducing reaction gas with preset flow rate into the cavity and applying preset pressure to form a dielectric layer covering the surface of the semiconductor substrate and the inner wall of the groove until the groove is filled, so as to form a shallow groove isolation structure.
2. The method of claim 1, wherein the reactive gas comprises silane and oxygen.
3. The method of claim 2, wherein the silane flow rate is 10sccm to 500sccm and the oxygen flow rate is 100sccm to 300sccm.
4. The method of claim 1, wherein the first predetermined power is 3000W to 5000W.
5. The method of claim 1, wherein the reactive gas used to etch the dielectric layer comprises hydrogen, nitrogen, oxygen or argon.
6. The method of claim 1, wherein a second predetermined power is applied to the chamber while etching the dielectric layer.
7. The method of claim 6, wherein the second predetermined power is 2000W to 4000W.
8. The method of claim 1, wherein each deposition of the dielectric layer is performed for a time period of between 5s and 10s.
9. The method of claim 1, wherein each etching of the dielectric layer is performed for a time period of between 5s and 10s.
10. The method of forming a shallow trench isolation structure according to any one of claims 1 to 9, further comprising, after forming the shallow trench isolation structure:
and removing the redundant dielectric layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202311426391.9A CN117393492A (en) | 2023-10-30 | 2023-10-30 | Method for forming shallow slot isolation structure |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202311426391.9A CN117393492A (en) | 2023-10-30 | 2023-10-30 | Method for forming shallow slot isolation structure |
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| CN117393492A true CN117393492A (en) | 2024-01-12 |
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