CN117377317A - Forming method of split gate flash memory - Google Patents

Forming method of split gate flash memory Download PDF

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Publication number
CN117377317A
CN117377317A CN202311421603.4A CN202311421603A CN117377317A CN 117377317 A CN117377317 A CN 117377317A CN 202311421603 A CN202311421603 A CN 202311421603A CN 117377317 A CN117377317 A CN 117377317A
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layer
floating gate
substrate
oxide
forming
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汤志林
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Shanghai Huahong Grace Semiconductor Manufacturing Corp
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Shanghai Huahong Grace Semiconductor Manufacturing Corp
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Priority to CN202311421603.4A priority Critical patent/CN117377317A/en
Publication of CN117377317A publication Critical patent/CN117377317A/en
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
    • H10B41/35—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/401—Multistep manufacturing processes
    • H01L29/4011—Multistep manufacturing processes for data storage electrodes
    • H01L29/40114—Multistep manufacturing processes for data storage electrodes the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Non-Volatile Memory (AREA)

Abstract

The invention provides a method for forming a split gate flash memory, which comprises the following steps: providing a substrate; forming a source line, a second side wall and a first side wall which are positioned at two sides of the source line, and a floating gate dielectric layer which are positioned below the first side wall on a substrate, wherein the floating gate dielectric layer and the floating gate are sequentially positioned on the substrate; forming an oxide barrier layer on the substrate uncovered by the floating gate dielectric layer; forming a tunneling oxide layer on the surface of part of the oxide barrier layer, and covering the side walls of the first side wall, the floating gate and the floating gate dielectric layer by the tunneling oxide layer; a word line is formed on the tunnel oxide layer on the oxide barrier layer. The oxide barrier layer prevents phosphorus element from diffusing into the substrate, thereby improving the channel turn-off capability under the word line and stabilizing the turn-on voltage of the high-voltage device.

Description

Forming method of split gate flash memory
Technical Field
The invention relates to the technical field of semiconductors, in particular to a method for forming a split gate flash memory.
Background
Flash memory has become a commonly used device in semiconductors. Flash memory includes two basic structures: gate stack (gate) and split gate devices. The split-gate flash memory effectively avoids over-erasure effect of the stacked gate device in terms of erasing performance by forming a word line serving as an erasure gate on one side of the floating gate and using the word line as a selection gate, and the circuit design is relatively simple. The split gate flash memory is programmed by utilizing source end hot electron injection, has higher programming efficiency, and is widely applied to various electronic products such as smart cards, SIM cards, microcontrollers, mobile phones and the like.
In the prior art, after forming a first side wall, a second side wall, a source line and a source line, and etching a floating gate layer and a floating gate dielectric layer on the periphery of the first side wall, a tunneling oxide layer for separating a word line from the first side wall and from the floating gate layer is formed in the split gate flash memory. The tunnel oxide layer is formed by depositing silicon dioxide in a furnace tube.
However, since the source line is formed by depositing polysilicon doped with phosphorus element in the prior art, phosphorus element is very easily diffused, and phosphorus element is diffused to the surface of silicon wafer (or substrate) under the high temperature of 650 ℃ and long time. And because a plurality of silicon wafers are placed in a furnace tube together to deposit and form a tunneling oxide layer, phosphorus elements emitted by source lines of all devices can mutually influence the silicon wafers of the other side. In particular, for some reasons, when the silicon wafer remains in the environment for a longer period of time, the greater the content of phosphorus element in the environment, the greater the amount of phosphorus element penetrating into the silicon wafer through the surface of the silicon wafer. And when a word line is formed at the periphery of the first side wall, phosphorus element is contained in the silicon wafer at the bottom of the word line. Resulting in a weak channel turn-off capability under the word line, making the high voltage device turn-on voltage unstable.
Disclosure of Invention
The invention aims to provide a forming method of a split gate flash memory, which can prevent phosphorus element from diffusing into a substrate, so that the channel turn-off capability below a word line can be improved, and the turn-on voltage of a high-voltage device is more stable.
In order to achieve the above object, the present invention provides a method for forming a split gate flash memory, including:
providing a substrate;
forming a source line, a second side wall and a first side wall which are positioned at two sides of the source line, and a floating gate dielectric layer which are positioned below the first side wall on the substrate, wherein the floating gate dielectric layer and the floating gate are sequentially positioned on the substrate;
forming an oxide barrier layer on the substrate uncovered by the floating gate dielectric layer;
forming a tunneling oxide layer on the surface of part of the oxide barrier layer, and covering the side walls of the first side wall, the floating gate and the floating gate dielectric layer by the tunneling oxide layer;
a word line is formed on the tunnel oxide layer at the oxide barrier layer.
Optionally, in the forming method of the split gate flash memory, the method for forming a source line on the substrate includes: and filling the opening formed by the second side wall with polysilicon doped with phosphorus element.
Optionally, in the forming method of the split gate flash memory, the oxide barrier layer includes silicon dioxide.
Optionally, in the method for forming a split gate flash memory, the thickness of the oxide barrier layer is 5-15 angstroms.
Optionally, in the method for forming a split gate flash memory, the method for forming an oxide barrier layer on the substrate uncovered by the floating gate dielectric layer includes:
and carrying out an annealing process, and oxidizing the surface of the substrate uncovered by the floating gate dielectric layer into silicon dioxide to form the oxide barrier layer.
Optionally, in the method for forming the split gate flash memory, the temperature of the annealing process is 900 ℃ to 1000 ℃.
Optionally, in the method for forming the split gate flash memory, the annealing process is performed for 5s to 15s.
Optionally, in the method for forming a split gate flash memory, an oxide is deposited on a portion of the surface of the oxide barrier layer to form a tunneling oxide layer.
Optionally, in the method for forming the split gate flash memory, an oxide is deposited in a furnace tube to form a tunneling oxide layer.
Optionally, in the method for forming the split gate flash memory, an oxide is deposited to form a tunneling oxide layer at a temperature of 600 ℃ to 700 ℃.
The method for forming the split gate flash memory provided by the invention comprises the following steps: providing a substrate; forming a source line, a second side wall and a first side wall which are positioned at two sides of the source line, and a floating gate dielectric layer which are positioned below the first side wall on a substrate, wherein the floating gate dielectric layer and the floating gate are sequentially positioned on the substrate; forming an oxide barrier layer on the substrate uncovered by the floating gate dielectric layer; forming a tunneling oxide layer on the surface of part of the oxide barrier layer, and covering the side walls of the first side wall, the floating gate and the floating gate dielectric layer by the tunneling oxide layer; a word line is formed on the tunnel oxide layer on the oxide barrier layer. The oxide barrier layer prevents phosphorus element from diffusing into the substrate, thereby improving the channel turn-off capability under the word line, and stabilizing the turn-on voltage of the high-voltage device.
Drawings
FIG. 1 is a flow chart of a method of forming a split gate flash memory according to an embodiment of the present invention;
FIG. 2 is a schematic diagram of a split gate flash memory after forming a floating gate mask layer according to an embodiment of the present invention;
FIG. 3 is a schematic diagram of a split gate flash memory after forming a first opening according to an embodiment of the present invention;
FIG. 4 is a schematic diagram of a split gate flash memory after forming a first sidewall according to an embodiment of the present invention;
FIG. 5 is a schematic diagram of a split gate flash memory after forming a second sidewall according to an embodiment of the present invention;
FIG. 6 is a schematic diagram of a split gate flash memory after forming a source region according to an embodiment of the present invention;
FIG. 7 is a schematic diagram of a split gate flash memory after forming a drain according to an embodiment of the present invention;
FIG. 8 is a schematic diagram of a split gate flash memory after forming word lines according to an embodiment of the present invention;
in the figure: 110-substrate, 111-source region, 112-drain terminal, 120-floating gate dielectric layer, 130-floating gate layer, 140-floating gate mask layer, 140A-first opening, 150-first sidewall, 150A-second opening, 160-second sidewall, 160A-third opening, 170-source line, 180-oxide barrier layer, 190-tunneling oxide layer, 200-word line.
Detailed Description
Specific embodiments of the present invention will be described in more detail below with reference to the drawings. The advantages and features of the present invention will become more apparent from the following description. It should be noted that the drawings are in a very simplified form and are all to a non-precise scale, merely for convenience and clarity in aiding in the description of embodiments of the invention.
In the following, the terms "first," "second," and the like are used to distinguish between similar elements and are not necessarily used to describe a particular order or chronological order. It is to be understood that such terms so used are interchangeable under appropriate circumstances. Similarly, if a method described herein comprises a series of steps, and the order of the steps presented herein is not necessarily the only order in which the steps may be performed, and some of the described steps may be omitted and/or some other steps not described herein may be added to the method.
Also, it will be understood that when a layer (or film), region, pattern, or structure is referred to as being "on" a substrate, layer (or film), region, and/or pattern, it can be directly on another layer or substrate, and/or intervening layers may also be present. In addition, it will be understood that when a layer is referred to as being "under" another layer, it can be directly under the other layer and/or one or more intervening layers may also be present. In addition, references to "upper" and "lower" on the respective layers may be made based on the drawings.
Referring to fig. 1, the present invention provides a method for forming a split gate flash memory, which includes:
s11: providing a substrate;
s12: forming a source line, a second side wall and a first side wall which are positioned at two sides of the source line, and a floating gate dielectric layer which are positioned below the first side wall on a substrate, wherein the floating gate dielectric layer and the floating gate are sequentially positioned on the substrate;
s13: forming an oxide barrier layer on the substrate uncovered by the floating gate dielectric layer;
s14: forming a tunneling oxide layer on the surface of part of the oxide barrier layer, and covering the side walls of the first side wall, the floating gate and the floating gate dielectric layer by the tunneling oxide layer;
s15: a word line is formed on the tunnel oxide layer on the oxide barrier layer.
Referring to fig. 2, a substrate 110 is provided, and the substrate 110 may be a silicon substrate, for example, the substrate 110 may be a wafer according to an embodiment of the present invention. A floating gate dielectric layer 120 is formed on a substrate 110, and the material of the floating gate dielectric layer 120 may be silicon dioxide, and the floating gate dielectric layer 120 may be formed by depositing silicon dioxide. A floating gate layer 130 is formed on the floating gate dielectric layer 120, and the material of the floating gate layer 130 may be polysilicon, and the floating gate layer 130 may be formed by depositing polysilicon. A floating gate mask layer 140 is formed on the floating gate layer 130, and the material of the floating gate mask layer 140 may be silicon nitride, and the floating gate mask layer 140 may be formed by depositing silicon nitride. Referring to fig. 3, the floating gate mask layer 140 is etched to form a first opening 140A, and the surface of the floating gate layer 130 is exposed in the first opening 140A.
Next, referring to fig. 3, an isotropic etching method is used to etch a portion of the thick floating gate layer 130, so that the floating gate layer 130 is also etched in the lateral direction due to the isotropic etching, so that the remaining floating gate layer 130 forms a bowl-shaped recess. I.e. the remaining floating gate layer 130 has a slope.
Referring to fig. 4, the first opening 140A is filled with silicon oxide to form an oxide layer on the remaining floating gate layer 130, and the filled silicon oxide may cover the floating gate mask layer 140, then, the surface of the remaining floating gate layer 130 is exposed by anisotropically dry etching the silicon oxide to form a first sidewall 150, the first sidewall 150 forms a second opening 150A, the surface of the remaining floating gate layer 130 is exposed in the second opening 150A, the bottom of the first sidewall 150 is connected to the remaining floating gate layer 130, and the top of the first sidewall 150 is connected to the top of the floating gate mask layer 140.
Next, referring to fig. 4 and fig. 5, the remaining floating gate layer 130 and the floating gate dielectric layer 120 at the bottom of the second opening 150A are sequentially etched and removed by using the first sidewall 150 as a mask, so as to expose the surface of the substrate 110. Then, silicon dioxide is deposited again in the opening formed by the first side wall 150 to cover the first side wall 150 and the floating gate mask layer 140, the silicon dioxide is etched to expose the surface of the substrate 110, so as to form a symmetrical second side wall 160, the second side wall 160 forms a third opening 160A, the second side wall 160 covers the side surfaces of the first side wall 150, the floating gate layer 130 and the floating gate dielectric layer 120, the top of the second side wall 160 is connected with the first side wall 150, and the bottom of the second side wall 160 is connected with the surface of the substrate 110.
Next, referring to fig. 6, ions are implanted into the substrate through the third opening 160A, wherein the implantation angle may be perpendicular to the surface of the substrate, and the implanted ions are phosphorus ions. Arsenic may also be implanted in other embodiments of the invention. Source region 111 is formed within substrate 110 after implantation. The source region 111 diffuses within the substrate 110 to the bottom of the remaining floating gate layer 130.
Next, referring to fig. 6, the third opening 160A is filled with polysilicon doped with phosphorus. The surface of the polysilicon is then polished to remove excess polysilicon, leaving the polysilicon within the third opening 160A to form a source line 170, the source line 170 being located over the source region 111 opposite the source region 111.
Next, referring to fig. 7, the remaining floating gate mask layer 140 is removed, and the floating gate layer 130 is exposed, and phosphoric acid etching may be used because the material of the floating gate mask layer 140 is silicon nitride. And, the remaining floating gate layer 130 outside the first side wall 150 is further etched, so that the floating gate layer 130 hidden by the first side wall 150 is reserved as a floating gate, and meanwhile, when the remaining floating gate layer 130 outside the first side wall 150 is removed, the corresponding floating gate dielectric layer 120 below the remaining floating gate layer 130 is also removed for etching, so that the surface of the substrate 110 is exposed. Ion implantation is performed into the substrate 110 outside the first sidewall 150 to form drain terminals 112 located on both sides of the source region 111 and not adjacent to the source region 111.
Next, referring to fig. 8, an oxide barrier layer 180 is formed on the surface of the substrate 110 exposed outside the first sidewall 150, and the oxide barrier layer is silicon dioxide, which can be formed by directly oxidizing the surface of the substrate 110 into silicon dioxide in a thermal annealing manner. The annealing temperature is 900 to 1000 ℃, preferably 950 ℃. The annealing time is 5s to 15s, preferably 10s. Oxide barrier 180 has a thickness of 5 angstroms to 15 angstroms, preferably 10 angstroms. When a plurality of split gate flash memories are simultaneously formed on the substrate 110, all of the exposed substrate 110 may be protected at this time by the oxide barrier layer 180.
Next, referring to fig. 8, a tunnel oxide layer 190 is formed on the oxide barrier layer 180, where the tunnel oxide layer 190 covers one side of the first sidewall 150 and also covers one side of the floating gate layer 130. The tunnel oxide layer 190 may be an oxide layer that may be formed by depositing an oxide, such as silicon dioxide. Specifically, an oxide may be deposited in the furnace tube to form a tunnel oxide layer. Wherein the temperature of the deposited oxide is 600-700 ℃. Next, a word line 200 is formed on the tunnel oxide layer 190 on the substrate 110. A specific forming method may be to deposit polysilicon immediately on one side of the tunnel oxide layer to cover the portion of the tunnel oxide layer 190 on the substrate 110 and the substrate 110, and etch the polysilicon to form the word line 200. Finally, the tunnel oxide layer 190 is located between the first sidewall 150 and the word line 200, the tunnel oxide layer 190 is also located between the floating gate layer 130 and the word line 200, and the tunnel oxide layer 190 is also located between the oxide barrier layer 180 and the word line 200. Before forming the tunnel oxide layer 190, an oxide barrier layer 180 is formed to protect the surface of the substrate, and phosphorus is prevented from diffusing into the inside of the substrate 110. And if at this time other metals are diffused out, for example arsenic or the like. Diffusion into the interior of the substrate 110 may also be blocked by the oxide barrier 180. The source line 170 in the embodiment of the present invention is formed by filling polysilicon doped with phosphorus, and the temperature during forming the tunnel oxide layer 190 is high, so that phosphorus is easy to diffuse out, and the oxide barrier layer 180 blocks phosphorus from diffusing into the substrate 110, so that after forming a word line on the substrate 110, the channel-shutdown capability is not reduced. Compared with the prior art, the method improves the channel turn-off capability below the word line, so that the turn-on voltage of the high-voltage device is more stable, and finally the probability of programming failure is reduced.
With continued reference to fig. 8, an embodiment of the present invention further provides a split-gate flash memory formed by the method for forming a split-gate flash memory, including: a substrate 110; a floating gate dielectric layer 120, a floating gate layer 130 and a first sidewall 150 on the substrate 110 in this order; the second side wall 160 covers the floating gate dielectric layer 120, the floating gate layer 130 and the side wall of the first side wall 150, and a third opening is formed in the second side wall 160; a source line 170 located within the third opening; a source region 111 located within the substrate 110 and corresponding to the source line 170; an oxide barrier 180 on the substrate 110 not covered by the floating gate dielectric layer 120; drain 112 in substrate 110 is located at a distance from first sidewall 150 and around the periphery of first sidewall 150.
In summary, the method for forming the split gate flash memory provided in the embodiment of the invention includes: providing a substrate; forming a source line, a second side wall and a first side wall which are positioned at two sides of the source line, and a floating gate dielectric layer which are positioned below the first side wall on a substrate, wherein the floating gate dielectric layer and the floating gate are sequentially positioned on the substrate; forming an oxide barrier layer on the substrate uncovered by the floating gate dielectric layer; forming a tunneling oxide layer on the surface of part of the oxide barrier layer, and covering the side walls of the first side wall, the floating gate and the floating gate dielectric layer by the tunneling oxide layer; a word line is formed on the tunnel oxide layer on the oxide barrier layer. The oxide barrier layer prevents phosphorus element from diffusing into the substrate, thereby improving the channel turn-off capability under the word line, and stabilizing the turn-on voltage of the high-voltage device.
The foregoing is merely a preferred embodiment of the present invention and is not intended to limit the present invention in any way. Any person skilled in the art will make any equivalent substitution or modification to the technical solution and technical content disclosed in the invention without departing from the scope of the technical solution of the invention, and the technical solution of the invention is not departing from the scope of the invention.

Claims (10)

1. The method for forming the split gate flash memory is characterized by comprising the following steps of:
providing a substrate;
forming a source line, a second side wall and a first side wall which are positioned at two sides of the source line, and a floating gate dielectric layer which are positioned below the first side wall on the substrate, wherein the floating gate dielectric layer and the floating gate are sequentially positioned on the substrate;
forming an oxide barrier layer on the substrate uncovered by the floating gate dielectric layer;
forming a tunneling oxide layer on the surface of part of the oxide barrier layer, and covering the side walls of the first side wall, the floating gate and the floating gate dielectric layer by the tunneling oxide layer;
a word line is formed on the tunnel oxide layer at the oxide barrier layer.
2. The method of forming a split gate flash memory of claim 1, wherein the method of forming a source line on the substrate comprises: and filling the opening formed by the second side wall with polysilicon doped with phosphorus element.
3. The method of claim 1, wherein the oxide barrier layer comprises silicon dioxide.
4. The method of claim 1, wherein the oxide barrier layer has a thickness of 5 a to 15 a.
5. The method for forming the split gate flash memory according to claim 1, wherein the method for forming the oxide barrier layer on the substrate uncovered by the floating gate dielectric layer comprises:
and carrying out an annealing process, and oxidizing the surface of the substrate uncovered by the floating gate dielectric layer into silicon dioxide to form the oxide barrier layer.
6. The method of claim 5, wherein the annealing process is performed at a temperature of 900 ℃ to 1000 ℃.
7. The method of claim 5, wherein the annealing process is performed for a period of time ranging from 5s to 15s.
8. The method of claim 1, wherein an oxide is deposited on a portion of the surface of the oxide barrier layer to form a tunnel oxide layer.
9. The method of claim 8, wherein oxide is deposited in a furnace to form a tunnel oxide layer.
10. The method of claim 8, wherein the temperature of depositing oxide to form the tunnel oxide layer is 600 ℃ to 700 ℃.
CN202311421603.4A 2023-10-30 2023-10-30 Forming method of split gate flash memory Pending CN117377317A (en)

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Application Number Priority Date Filing Date Title
CN202311421603.4A CN117377317A (en) 2023-10-30 2023-10-30 Forming method of split gate flash memory

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CN117377317A true CN117377317A (en) 2024-01-09

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