CN117374078A - Chip, manufacturing method thereof and electronic equipment - Google Patents

Chip, manufacturing method thereof and electronic equipment Download PDF

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Publication number
CN117374078A
CN117374078A CN202210767391.4A CN202210767391A CN117374078A CN 117374078 A CN117374078 A CN 117374078A CN 202210767391 A CN202210767391 A CN 202210767391A CN 117374078 A CN117374078 A CN 117374078A
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China
Prior art keywords
dummy gate
chip
dielectric layer
fin
field effect
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CN202210767391.4A
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Chinese (zh)
Inventor
王涛
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Huawei Technologies Co Ltd
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Huawei Technologies Co Ltd
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Priority to CN202210767391.4A priority Critical patent/CN117374078A/en
Priority to PCT/CN2023/098518 priority patent/WO2024001689A1/en
Publication of CN117374078A publication Critical patent/CN117374078A/en
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
    • H01L27/0924—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823821—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823864—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate sidewall spacers, e.g. double spacers, particular spacer material or shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823878—Complementary field-effect transistors, e.g. CMOS isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

The application provides a chip, a manufacturing method thereof and electronic equipment, relates to the technical field of semiconductors, and can simplify the manufacturing process of the chip. The chip comprises a substrate, and a first fin field effect transistor and a second fin field effect transistor which are arranged on the substrate and are adjacently arranged. The first fin field effect transistor comprises at least one first fin structure and a first metal gate, and the second fin field effect transistor comprises at least one second fin structure and a second metal gate; the first metal gate and the second metal gate are aligned along a direction perpendicular to the fin structure. A cutting-off region is arranged between the first metal gate and the second metal gate. A first dielectric layer is arranged in the chip; the first dielectric covers two side surfaces of the first metal grid electrode and the second metal grid electrode in the first direction, and the first dielectric layer extends to cover the sections of the first metal grid electrode and the second metal grid electrode, which are located in the cutting-off area.

Description

Chip, manufacturing method thereof and electronic equipment
Technical Field
The present disclosure relates to the field of semiconductor technologies, and in particular, to a chip, a method for manufacturing the same, and an electronic device.
Background
Fin field effect transistors (fin field effect transistor, finFET) are widely used as a new cmos transistor for advanced processes of integrated circuits, such as 16nm, 10nm, and 7 nm. The metal gate (metal gate) used in the current FinFET is formed by replacing a dummy gate structure (dummy gate), i.e., the dummy gate is removed first, and then the metal gate (metal gate) is formed at the location where the dummy gate is removed.
Referring to fig. 1, in the conventional FinFET fabrication process, a fin semiconductor strip 1 (i.e., fin) for forming a fin structure F (fin) of a FinFET is generally fabricated; then, the dummy gate semiconductor stripe 2 (i.e., dummy poly line) is manufactured; next, after the dummy gate semiconductor stripe 2 is subjected to a lateral cutting (multicut) to form a cutting region B, a dummy gate structure (dummy gate) can be formed. However, in this manufacturing process, the manufacturing of the dummy gate semiconductor stripe 2 and the cutting of the dummy gate semiconductor stripe 2 are separately performed at different process stages, so that the manufacturing process is complex and the flow is long, and the problem that the dummy poly line (2) cannot be cut to cause a short circuit is also easy to occur, and various problems such as high manufacturing cost and long manufacturing period are caused.
Disclosure of Invention
The application provides a chip, a manufacturing method thereof and electronic equipment, and can simplify the manufacturing process.
The application provides a chip, which comprises a substrate and a plurality of fin field effect transistors arranged on the substrate; the plurality of fin field effect transistors comprise a first fin field effect transistor and a second fin field effect transistor which are adjacently arranged. The first fin field effect transistor includes at least one first fin structure and a first metal gate, and the second fin field effect transistor includes at least one second fin structure and a second metal gate. The direction of the first fin structure and the direction of the second fin structure are both the first direction, and the direction perpendicular to the first fin structure and the second fin structure is the second direction. The first metal gate and the second metal gate are aligned in a second direction. The chip is provided with a cutting area between the first metal grid and the second metal grid; the chip is provided with a first dielectric layer; the first dielectric covers two side surfaces of the first metal grid electrode and the second metal grid electrode in the first direction, and the first dielectric layer extends to cover the sections of the first metal grid electrode and the second metal grid electrode, which are located in the cutting-off area.
In the chip provided in this embodiment of the present application, a cutting region is provided between metal gates (i.e., a first metal gate and a second metal gate) of two transistors (i.e., a first fin field effect transistor and a second fin field effect transistor) adjacent in a vertical fin direction (i.e., a second direction), and a first dielectric layer is disposed in the chip to cover a side surface of the metal gate to form a sidewall (spacer), and extends to cover a section of the metal gate in the cutting region. In this case, it can be understood that, for the fabrication of the chip, before the first dielectric layer is formed, the cutting area is formed first to complete the fabrication of the dummy gate structure (the dummy gate structure is replaced by the metal gate later), and the cutting process is performed before the first dielectric layer is formed, so that the difficulty of the cutting process is reduced, and the effective cutting between two adjacent dummy gate structures can be ensured, thereby simplifying the fabrication process. In addition, after the cutting area is formed, the first dielectric layer is formed, and the cutting area can be directly filled through the first dielectric layer without independently filling the cutting area, so that the process flow is shortened.
In some possible implementations, the chip has isolation regions on both sides of the first metal gate and the second metal gate in the first direction; the first dielectric layer extends to the isolation region; the chip is also provided with a second dielectric layer; the second dielectric layer is filled in the spacer region and is positioned on one side of the first dielectric layer away from the substrate.
In some possible implementations, the second dielectric layer extends into the cut-out region. In some implementations, since the formed cut-off region has a larger width, the formed first dielectric layer may not fill the cut-off region, that is, the first dielectric layer covers the sections of the two dummy gate structures in the cut-off region, and a certain gap is left between the sections, and the subsequently formed second dielectric layer may fill the gap to fill the entire cut-off region.
In some possible implementations, the second dielectric layer includes SiO 2 。
In some possible implementations, the first dielectric layer includes at least one of SiN, siON, siCON, siCN.
In some possible implementations, the first fin field effect transistor includes a plurality of first fin structures disposed in parallel; the second fin field effect transistor includes a plurality of second fin structures disposed in parallel.
The embodiment of the application also provides a manufacturing method of the chip, which comprises the following steps: a plurality of first semiconductor strips disposed in parallel are formed on a substrate for forming fin structures of a plurality of fin field effect transistors. Forming a second semiconductor layer, and performing one-time etching on the second semiconductor layer to form a plurality of dummy gate structures of a plurality of fin field effect transistors; the plurality of dummy gate structures comprise a first dummy gate structure and a second dummy gate structure, the first dummy gate structure and the second dummy gate structure are aligned in the direction perpendicular to the fin structure, and a cutting region is arranged between the first dummy gate structure and the second dummy gate structure. Sequentially forming a first dielectric layer and a second dielectric layer, and exposing the tops of the multiple dummy gate structures through a grinding process; the first dielectric layer at least covers the side surfaces of the plurality of dummy gate structures and the section positioned in the cutting-off area, and the second dielectric layer is filled in the two side areas of the plurality of dummy gate structures. And removing the plurality of dummy gate structures, and forming a metal gate in the region where the plurality of dummy gate structures are removed.
According to the chip manufacturing method provided by the embodiment of the application, before the first dielectric layer and the second dielectric layer are formed, the second semiconductor layer can be subjected to one-time etching technology to form the dummy gate structure (namely, the cutting of the dummy gate structure is completed), so that the difficulty of the cutting technology is reduced, and effective cutting between two adjacent dummy gate structures can be ensured. In addition, the manufacturing method of the first dielectric layer and the second dielectric layer are formed after the dummy gate structure is completed, the cutting area can be directly filled, independent filling of the cutting area is not needed, and the process flow is shortened. Meanwhile, the manufacturing method only needs to adopt one grinding process after the first dielectric layer and the second dielectric layer are formed, so that the gate height loss (gatehight loss) is reduced, and gate height control (gatehight control) is facilitated.
In some possible implementations, the forming the second semiconductor layer and etching the second semiconductor layer once to form a plurality of dummy gate structures of a plurality of fin field effect transistors may include: a second semiconductor layer is formed. A plurality of hard mask strips perpendicular to the first semiconductor strips are formed on the surface of the second semiconductor layer, and the plurality of hard mask strips are cut to form mask patterns. And etching the second semiconductor layer once to form a plurality of dummy gate structures of the fin field effect transistors.
In some possible implementations, forming a plurality of hard mask stripes perpendicular to the first semiconductor stripes on a surface of the second semiconductor layer includes: a plurality of hard mask stripes perpendicular to the first semiconductor stripes are formed on the surface of the second semiconductor layer using a self-aligned secondary patterning process (selfalign double patterning, SADP).
In some possible implementations, the second dielectric layer fills the cut-out region.
The embodiment of the application also provides an electronic device, which comprises a circuit board and a chip provided in any one of the possible implementation manners, wherein the chip is electrically connected with the circuit board.
Drawings
FIG. 1 is a schematic diagram of a chip in a manufacturing process according to the prior art;
FIG. 2 is a schematic diagram of a chip in the manufacturing process according to the prior art;
FIG. 3 is a schematic diagram of a chip in the manufacturing process according to the prior art;
FIG. 4 is a schematic diagram of a chip in the manufacturing process according to the prior art;
FIG. 5 is a schematic diagram of a chip in the manufacturing process according to the prior art;
fig. 6 is a schematic flow chart of a method for manufacturing a chip according to an embodiment of the present application;
fig. 7 is a schematic diagram of a chip in a manufacturing process according to an embodiment of the present application;
fig. 8 is a schematic diagram of a chip in a manufacturing process according to an embodiment of the present application;
fig. 9 is a schematic diagram of a chip in a manufacturing process according to an embodiment of the present application;
fig. 10 is a schematic diagram of a chip in a manufacturing process according to an embodiment of the present application;
FIG. 11 is a schematic diagram of a chip in a manufacturing process according to an embodiment of the present disclosure;
fig. 12 is a schematic diagram of a chip in a manufacturing process according to an embodiment of the present application;
fig. 13 is a schematic diagram of a chip in a manufacturing process according to an embodiment of the present application;
fig. 14 is a schematic diagram of a chip in a manufacturing process according to an embodiment of the present application;
fig. 15 is a schematic diagram of a chip in a manufacturing process according to an embodiment of the present application.
Detailed Description
For the purposes of making the objects, technical solutions and advantages of the present application more apparent, the technical solutions in the present application will be clearly and completely described below with reference to the drawings in the present application, and it is apparent that the described embodiments are some, but not all, embodiments of the present application. All other embodiments, which can be made by one of ordinary skill in the art without undue burden from the present disclosure, are within the scope of the present disclosure.
The terms "first," "second," and the like in the description and in the claims and drawings are used for descriptive purposes only and are not to be construed as indicating or implying a relative importance or order. "and/or" for describing the association relationship of the association object, the representation may have three relationships, for example, "a and/or B" may represent: only a, only B and both a and B are present, wherein a, B may be singular or plural. The character "/" generally indicates that the context-dependent object is an "or" relationship. "at least one" means one or more, and "a plurality" means two or more. "mounted," "connected," and the like are to be construed broadly and may be, for example, fixedly connected, detachably connected, or integrally connected; either directly or indirectly through intermediaries, or through communication between two elements. Furthermore, the terms "comprise" and "have," as well as any variations thereof, are intended to cover a non-exclusive inclusion, such as a series of steps or elements. The method, system, article, or apparatus is not necessarily limited to those explicitly listed but may include other steps or elements not explicitly listed or inherent to such process, method, article, or apparatus. "upper", "lower", "left", "right", etc. are used merely with respect to the orientation of the components in the drawings, these directional terms are relative terms, which are used for description and clarity with respect thereto, and which may vary accordingly depending on the orientation in which the components are placed in the drawings.
The embodiment of the application provides an electronic device, which comprises a printed circuit board (printed circuit board, PCB) and a chip, wherein the chip is arranged on the surface of the printed circuit board (also called as a circuit board) and is electrically connected with the printed circuit board; wherein a plurality of fin field effect transistors (finfets) are provided in the chip.
The present application is not limited to the arrangement form of the chip. The chip may illustratively be a processor, memory chip, logic chip, or the like.
The present application does not limit the setting form of the electronic device. The electronic equipment can be electronic products such as mobile phones, tablet computers, notebooks, vehicle-mounted computers, intelligent watches, intelligent bracelets and the like.
It will be appreciated that, depending on the actual functional requirements of the chip, there must be separate control of some adjacent finfets, i.e., no electrical connection between the gates (metal gates) of some adjacent finfets, among the plurality of finfets disposed inside the chip. In the process of manufacturing the chip, the gate of the FinFET is formed by replacing a dummy gate structure (dummy gate), that is, the dummy gate structure formed in the process of manufacturing the chip needs to be cut to ensure that two independent gates are formed to meet the chip requirement.
The chip manufacturing method provided in the embodiment of the present application is described below with reference to the prior art.
Fig. 2, 3, 4, and 5 are schematic diagrams illustrating a process for manufacturing a chip according to the prior art; the cross-sectional positions of fig. 2, 3, 4 may be referred to as a-a 'position and b-b' position as illustrated in fig. 1.
As shown in fig. 2, after forming the fin structure (fin), an amorphous silicon layer (poly) is formed on the surface of the fin structure (fin); then, a hard mask stripe HM is formed on the surface of the amorphous silicon layer (poly), and the amorphous silicon layer (poly) is etched to form dummy bars PL (dummypolyline). Next, as shown in fig. 3, a first dielectric layer c1 and a second dielectric layer c2 are sequentially deposited to form a spacer dielectric layer ILD (interlayerdielectric), and the top of the dummy bars PL are exposed by a grinding process (i.e., the portions within the dashed line frame in fig. 3 are removed by grinding). Next, as shown in fig. 4 (a), after the dummy gate PL is cut (multicut) by a single etching process (i.e., a second etching process) to form a cut region B, a dummy gate structure Gd (dummy gate) is formed; then, referring to fig. 4 (B) and (c) and fig. 5, the third dielectric layer c3 is filled in the formed cut region B, and the top of the dummy gate structure Gd is exposed through the grinding process (i.e., the second grinding process) (i.e., the portion within the dashed line frame in fig. 4 (B) is removed through grinding). Fig. 5 is a schematic plan view of the dummy gate structure Gd located in the cutting region B after the second polishing process.
In the above-mentioned existing manufacturing process, the process of forming the dummy gate structure Gd adopts a two-time etching process for the amorphous silicon layer (poly), the first etching first forms the dummy gate strips PL, and the second etching then cuts off the dummy gate strips PL to form the dummy gate structure Gd. The second etching process is performed after the interlayer dielectric layers ILD (c 1, c 2) are formed, that is, the dummy bars PL are cut (poly cut) after the interlayer dielectric layers ILD (c 1, c 2) are formed, so that the cutting difficulty is high, the process is complex, and meanwhile, the risk that the gate short circuit is caused by the fact that the dummy bars PL cannot be cut exists. In addition, the conventional manufacturing process also needs to separately fill the cutting region B (i.e., the third dielectric layer c 3) after the dummy gate structure Gd is formed. Meanwhile, the existing manufacturing process adopts two grinding processes to generate additional gate height loss (gatehight loss), and the difficulty of gate height control (gatehight control) is increased. That is, the existing manufacturing process has a series of problems of long process flow, complex process, high manufacturing cost, long period and the like.
In contrast, the embodiment of the application provides a new manufacturing method, wherein a dummy gate structure (dummy gate) is directly formed through one etching process, and the etching process is completed before interlayer dielectric layers (ILD) (c 1, c 2) are formed; namely, before interlayer dielectric layers ILD (c 1, c 2) are formed, the false grid PL is cut off (poly cut), so that the cutting difficulty is reduced, the effective cutting of the false grid is ensured, and the problem of grid short circuit is avoided; meanwhile, the manufacturing method only adopts one grinding process, so that the gate height loss (gatehight loss) is reduced, and the gate height control (gatehight control) is facilitated.
By adopting the manufacturing method provided by the embodiment of the application, the process flow is shortened, and the manufacturing method has the advantages of simple process, low manufacturing cost and the like. The following describes a specific method for manufacturing a chip provided in the embodiment of the present application.
As shown in fig. 6, a method for manufacturing a chip according to an embodiment of the present application may include:
in step 01, referring to fig. 7, a plurality of first semiconductor strips 11 arranged in parallel are formed on a substrate 10 for forming fin structures F (fin) of a plurality of fin field effect transistors.
In the present application, the extending direction of the first semiconductor stripe 11 is defined as a first direction XX ', that is, the direction of the fin structure F (fin) of the fin field effect transistor is defined as a first direction XX ', and the direction of the vertical fin structure F (fin) is defined as a second direction YY '.
Illustratively, in some possible implementations, referring to fig. 7, a plurality of first semiconductor strips 11 (i.e., fins) disposed in parallel may be formed on a surface of a silicon substrate (10) by etching, and the first semiconductor strips 11 may be cut (finished) by further etching to form fin structures F of a plurality of fin field effect transistors. Referring to fig. 8, after the plurality of first semiconductor stripes 11 are cut, shallow trench isolation layers STI may be formed on the surface of the silicon substrate (10) to achieve isolation between the plurality of fin field effect transistors.
Note that, in the partial plan view schematic diagram of the present application, the fin structure F after being cut is not simplified and illustrated by the first semiconductor stripe 11 which is not cut, and should not be considered as an illustration error.
In step 02, referring to fig. 9 (a) and (b), a second semiconductor layer 20 is formed, and the second semiconductor layer 20 is etched once to form a plurality of dummy gate structures 21 of a plurality of fin field effect transistors.
It will be appreciated that the plurality of dummy gate structures 21 formed in step 02 correspond to the gates of the plurality of finfet, respectively, and that the plurality of dummy gate structures 21 have been cut off (see for details the description of the foregoing).
Schematically, referring to fig. 9 (b), the plurality of dummy gate structures 21 formed in step 02 includes a first dummy gate structure 211 and a second dummy gate structure 212, where the first dummy gate structure 211 corresponds to a gate of a first fin field effect transistor and the second dummy gate structure 212 corresponds to a gate of a second fin field effect transistor; the first dummy gate structure 211 and the second dummy gate structure 212 are aligned in the second direction YY', but the first dummy gate structure 211 and the second dummy gate structure 212 have a cut-off region B therebetween; the first fin field effect transistor and the second fin field effect transistor are arranged in parallel in the second direction YY', and the two transistors adopt independent gate structures.
It is understood herein that the alignment of the first dummy gate structure 211 and the second dummy gate structure 212 in the second direction YY 'means that extension lines of the first dummy gate structure 211 and the second dummy gate structure 212 in the second direction YY' coincide, that is, the first dummy gate structure 211 and the second dummy gate structure 212 are located on the same dummy bar (not actually present in the manufacturing process of the present application).
The present application does not limit the manufacturing process of forming the plurality of dummy gate structures 21 by one etching in the above step 02. Illustratively, in some embodiments, step 02 above may include:
in step 21, referring to fig. 9 (a), a second semiconductor layer 20 is formed on the surface of the fin structure F. Illustratively, the second semiconductor layer 20 may be an amorphous silicon layer (poly).
In step 22, referring to fig. 10 and 11 (a) and (b), a plurality of hard mask stripes HM are formed on the surface of the second semiconductor layer 20 in parallel, and the plurality of hard mask stripes HM are cut to form a mask pattern 30. Wherein the hard mask stripes HM extend in a second direction YY'.
Fig. 11 is a schematic cross-sectional view of a process of forming a plurality of dummy gate structures 21, and the cross-sectional position of fig. 11 may refer to the c-c 'position and the d-d' position illustrated in fig. 9 (b).
Illustratively, in some possible implementations, a self-aligned secondary patterning process (selfalign double patterning, SADP) may be employed to form a plurality of hard mask stripes HM disposed in parallel along the second direction YY' on the surface of the second semiconductor layer 20. Then, the plurality of hard mask stripes HM are cut to form mask patterns 30.
It should be noted here that the mask pattern 30 may include a multi-layered film structure; for example, it may include a SiN layer on the lower layer and a SiO layer on the upper layer 2 A layer; in forming the mask pattern 30, the SiN layer may cover the surface of the second semiconductor layer 20 to protect the second semiconductor layer 20, only the SiO 2 Etching the layer to form a hard mask strip HM and cutting off the hard mask strip HM.
In step 23, referring to fig. 11 (c), the second semiconductor layer 20 is etched once to form a plurality of dummy gate structures 21 of a plurality of fin field effect transistors.
It will be appreciated here that the mask pattern 30 serves as a mask layer for the plurality of dummy gate structures 21, the mask pattern 30 substantially conforms to the pattern shape of the plurality of dummy gate structures 21, and the cut-off region B1 of the hard mask stripe 30 corresponds to the cut-off region B between the two dummy gate structures (211, 212) (refer to fig. 11). That is, the present application directly forms the dummy gate structure 21 through one etching process by cutting the hard mask strip HM first, without performing an additional cutting process.
In step 03, referring to fig. 12, a first dielectric layer c1 and a second dielectric layer c2 are sequentially formed, and the tops of the dummy gate structures 21 are exposed through a grinding process.
The step 03 removes the portion inside the dotted frame at the top in fig. 12 (a) through a grinding process, exposing the top of the dummy gate structure 21. Compared with the prior art that the two grinding processes are adopted in the process of manufacturing the dummy gate structure 21, the manufacturing process of the present application adopts only one grinding process in the step 03, so that the gate height loss (gatehight loss) is reduced, and the gate height control (gatehight control) is facilitated.
Fig. 13 is a schematic plan view of the cut-off region B in the dummy gate structure 21. Referring to fig. 13, after the polishing process in step 03, a first dielectric layer c1 covers at least two sides of the dummy gate structure 21 (211, 212) in the first direction XX' to form sidewalls (spacers), and the first dielectric layer c1 extends to cover the cross section of the cutting region B; that is, the first dielectric layer c1 wraps the side and the cross section of the dummy gate structure 21; the second dielectric layer c2 fills the isolation regions P on both sides of the dummy gate structures 21 in the first direction XX', i.e. the regions where the shallow trench isolation layers STI are located.
The materials forming the first dielectric layer c1 and the second dielectric layer c2 are not limited in this application. Illustratively, in some possible implementations, the first dielectric layer c1 may employ one or more of the dielectric materials SiN, siON, siCON, siCN, etc. Illustratively, in some possible implementations, the second dielectric layer c2 may be formed of SiO 2 。
Compared to the prior art (fig. 5) in which the cut-off region B needs to be filled with a separate dielectric layer (c 3), with the manufacturing method of the present application, the manufacturing of the dummy gate structure 21 is completed before the first dielectric layer c1 and the second dielectric layer c2 are formed, so that the filling of the cut-off region B can be completed in the process of forming the first dielectric layer c1 and the second dielectric layer c2, without separately filling the cut-off region B.
Here, as shown in fig. 13 and 14, the second dielectric layer c2 may or may not extend to fill the cutting region B, depending on the width of the two dummy gate structures (211, 212) in the cutting region B.
For example, in some possible implementations, as shown with reference to fig. 12 and 13, in the case where the cut-off region B between the two dummy gate structures (211, 212) has a smaller width W1, the first dielectric layer c1 formed by step 03 may directly fill the entire cut-off region B, that is, the cut-off region B is entirely the first dielectric layer c1.
For another example, in other possible implementations, as shown in fig. 14 and 15, in the case where the cut region B between the two dummy gate structures (211, 212) has a larger width W2, the first dielectric layer c1 formed by the step 03 fails to fill the cut region B, that is, the first dielectric layer c1 covers the cross sections of the two dummy gate structures (211, 212) in the cut region B, and a certain gap is left between the cross sections, and the subsequently formed second dielectric layer c2 fills the gap to fill the entire cut region B.
In addition, referring to fig. 13, the isolation region P between two adjacent dummy gate structures 21 (also referred to as two dummy gate strips) along the first direction XX' has a groove structure, and the first dielectric layer c1 formed in the above step 03 may extend to the isolation region P to cover the isolation region P; and a second dielectric layer c2 formed after the first dielectric layer c1 fills the groove structure.
Step 04, removing the plurality of dummy gate structures 21, and forming a metal gate in the area where the plurality of dummy gate structures 21 are removed.
That is, the plurality of dummy gate structures 21 are replaced with metal gates, such as High K Metal Gate (HKMG), via step 04.
In summary, compared with the prior art in which the process of forming the dummy gate structure is divided into two etching processes and two grinding processes, the chip manufacturing method provided in the embodiment of the present application, before forming the first dielectric layer c1 and the second dielectric layer c2 (step 03), the dummy gate structure 21 can be formed (i.e. the cutting of the dummy gate structure is completed) by adopting one etching process (step 02) for the second semiconductor layer 20, thereby reducing the difficulty of the cutting process and ensuring the effective cutting between two adjacent dummy gate structures 21. In addition, the first dielectric layer c1 and the second dielectric layer c2 are formed after the dummy gate structure 21, so that the cutting region B can be directly filled without independently filling the cutting region B, and the process flow is shortened. Meanwhile, the manufacturing method only needs to adopt one grinding process after the first dielectric layer c1 and the second dielectric layer c2 are formed, so that the gate height loss (gatehight loss) is reduced, and gate height control (gatehight control) is facilitated.
That is, compared with the prior art, the manufacturing method provided by the embodiment of the application shortens the process flow, and has the advantages of simple process, low manufacturing cost and the like.
It should be noted that, in the drawings of the present application, two fin structures F in a fin field effect transistor are taken as examples for illustration, but the present application is not limited thereto. For example, one fin structure F or three fin structures F or the like may be provided in the fin field effect transistor.
As will be appreciated by those skilled in the art, with the fabrication method of the present application, after the dummy gate structure 21 is replaced with the metal gate in step 04, the fin field effect transistor is formed, the first dummy gate structure 211 is replaced with a first metal gate to form a first fin field effect transistor, and the second dummy gate structure 212 is replaced with a second metal gate to form a second fin field effect transistor. In this case, in the finally formed chip, the coverage areas of the first dielectric layer c1 and the second dielectric layer c2 remain unchanged, and the first dielectric layer c1 covers the two sides of the first metal gate and the second metal gate in the first direction XX' and extends to cover the cross section, and the coverage manner of the first dielectric layer c1 and the second dielectric layer c2 on the first dummy gate structure 211 and the second dummy gate structure 212 may be referred to as the foregoing.
Other relevant arrangements of the first dielectric layer c1 and the second dielectric layer c2 may refer to the relevant descriptions above, and will not be repeated here.
The foregoing is merely specific embodiments of the present application, but the scope of the present application is not limited thereto, and any person skilled in the art can easily think about changes or substitutions within the technical scope of the present application, and the changes and substitutions are intended to be covered by the scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.

Claims (11)

1. A chip, comprising a substrate and a plurality of fin field effect transistors arranged on the substrate;
the fin field effect transistors comprise a first fin field effect transistor and a second fin field effect transistor which are adjacently arranged;
the first fin field effect transistor comprises at least one first fin structure and a first metal gate, and the second fin field effect transistor comprises at least one second fin structure and a second metal gate; the direction of the first fin structure and the direction of the second fin structure are both a first direction, and the direction perpendicular to the first fin structure and the second fin structure is a second direction; the first metal gate and the second metal gate are aligned in the second direction;
the chip is provided with a cutting area between the first metal grid electrode and the second metal grid electrode;
a first dielectric layer is arranged in the chip;
the first dielectric covers two side surfaces of the first metal grid electrode and the second metal grid electrode in the first direction, and the first dielectric layer extends to cover the sections of the first metal grid electrode and the second metal grid electrode, which are located in the cutting area.
2. The chip of claim 1, wherein the chip comprises a plurality of chips,
the chip is provided with isolation areas at two sides of the first metal grid electrode and the second metal grid electrode along the first direction; the first dielectric layer extends to the isolation region;
a second dielectric layer is also arranged in the chip; the second dielectric layer is filled in the interval region and is positioned on one side of the first dielectric layer away from the substrate.
3. The chip of claim 2, wherein the chip comprises a plurality of chips,
the second dielectric layer extends into the cut-out region.
4. A chip according to claim 2 or 3, which isCharacterized in that the second dielectric layer comprises SiO 2 。
5. The chip of any one of claims 1-4, wherein the first dielectric layer comprises at least one of SiN, siON, siCON, siCN.
6. The chip according to any one of claim 1 to 5, wherein,
the first fin field effect transistor comprises a plurality of first fin structures which are arranged in parallel;
the second fin field effect transistor includes a plurality of second fin structures arranged in parallel.
7. A method of manufacturing a chip, comprising:
forming a plurality of first semiconductor strips arranged in parallel on a substrate for forming fin structures of a plurality of fin field effect transistors;
forming a second semiconductor layer, and performing one-time etching on the second semiconductor layer to form a plurality of dummy gate structures of the fin field effect transistors; the plurality of dummy gate structures comprise a first dummy gate structure and a second dummy gate structure, the first dummy gate structure and the second dummy gate structure are aligned in a direction perpendicular to the fin structure, and a cutting area is arranged between the first dummy gate structure and the second dummy gate structure;
sequentially forming a first dielectric layer and a second dielectric layer, and exposing the tops of the plurality of dummy gate structures through a grinding process; the first dielectric layer at least covers the side surfaces of the plurality of dummy gate structures and the section of the cutting area, and the second dielectric layer is filled in the two side areas of the plurality of dummy gate structures;
and removing the plurality of dummy gate structures, and forming a metal gate in a region where the plurality of dummy gate structures are removed.
8. The method of manufacturing a chip according to claim 7, wherein,
the forming a second semiconductor layer, and etching the second semiconductor layer once to form a plurality of dummy gate structures of the fin field effect transistors, including:
forming a second semiconductor layer;
forming a plurality of hard mask strips perpendicular to the first semiconductor strips on the surface of the second semiconductor layer, and cutting the plurality of hard mask strips to form mask patterns;
and etching the second semiconductor layer once to form a plurality of dummy gate structures of the fin field effect transistors.
9. The method for manufacturing a chip according to claim 7 or 8, wherein,
forming a plurality of hard mask strips perpendicular to the first semiconductor strips on the surface of the second semiconductor layer, wherein the hard mask strips comprise:
and forming a plurality of hard mask strips perpendicular to the first semiconductor strips on the surface of the second semiconductor layer by adopting a self-aligned secondary patterning process.
10. The method for manufacturing a chip according to any one of claims 7 to 9, wherein,
and the second dielectric layer is filled in the cutting-off area.
11. An electronic device comprising a circuit board and a chip as claimed in any one of claims 1-6, said chip being electrically connected to said circuit board.
CN202210767391.4A 2022-07-01 2022-07-01 Chip, manufacturing method thereof and electronic equipment Pending CN117374078A (en)

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US9553171B2 (en) * 2014-02-14 2017-01-24 Taiwan Semiconductor Manufacturing Co., Ltd. Fin field effect transistor (FinFET) device and method for forming the same
US9147730B2 (en) * 2014-03-03 2015-09-29 Globalfoundries Inc. Methods of forming fins for FinFET semiconductor devices and selectively removing some of the fins by performing a cyclical fin cutting process
US9754792B1 (en) * 2016-02-29 2017-09-05 Globalfoundries Inc. Fin cutting process for manufacturing FinFET semiconductor devices
KR102553778B1 (en) * 2018-05-23 2023-07-10 삼성전자주식회사 A semiconductor device
US10818556B2 (en) * 2018-12-17 2020-10-27 United Microelectronics Corp. Method for forming a semiconductor structure

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