CN117372567B - Layout generation method, device, equipment and medium - Google Patents
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- 238000005259 measurement Methods 0.000 claims abstract description 144
- 238000005070 sampling Methods 0.000 claims abstract description 91
- 238000010586 diagram Methods 0.000 claims abstract description 45
- 238000004590 computer program Methods 0.000 claims description 9
- 238000012545 processing Methods 0.000 abstract description 6
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- G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
- G06T11/00—2D [Two Dimensional] image generation
- G06T11/20—Drawing from basic elements, e.g. lines or circles
- G06T11/203—Drawing of straight lines or curves
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- G—PHYSICS
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- G06T2207/30108—Industrial image inspection
- G06T2207/30148—Semiconductor; IC; Wafer
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Abstract
The invention relates to the field of semiconductor lithography, in particular to a layout generation method, a device, equipment and a medium, wherein a measurement gray level diagram and key size data of a measurement path on the measurement gray level diagram are obtained; determining a path gray scale graph according to the measurement path and the measurement gray scale graph; determining an edge gray threshold according to the path gray graph and the critical dimension data; determining a pattern edge graph on the measurement gray level graph according to the edge gray level value; determining a set of sampling points on the pattern edge graph; and connecting sampling points in the sampling point set in sequence by using straight lines to obtain a closed polygonal target layout. The method scans the existing wafer to obtain the corresponding wafer edge in the measurement gray level diagram, then takes a plurality of sampling points on the pattern edge diagram, and connects the sampling points to obtain the polygonal wafer layout, thereby being quick and direct, high in processing efficiency, low in occupation calculation force and high in reduction degree of the existing wafer.
Description
Technical Field
The present invention relates to the field of semiconductor lithography, and in particular, to a layout generating method, apparatus, device, and medium.
Background
In the current work flow of a wafer factory, if a wafer with a specific structure is desired, a worker is usually required to follow a specific design rule, manually design a layout by means of corresponding software, and then deliver the layout to a machine for production.
That is, in the prior art, if a layout of a specific structure is required, starting from defining a design rule and defining a design size, a layout tool is used to generate a required test layout for a series of processes such as subsequent OPC (optical proximity correction, optical proximity correction effect) development, process development, yield diagnosis and the like. However, in some actual scenes, there are existing wafer images, but there are no layout design tools and specific design rules, if a worker is required to perform back-pushing according to a real semiconductor device, thinking is performed and the semiconductor layout is gradually reconstructed according to the above-mentioned process, the production efficiency is greatly reduced, and the production cost is increased.
Therefore, how to quickly and efficiently obtain the corresponding wafer layout from the existing wafer image becomes a problem to be solved by those skilled in the art.
Disclosure of Invention
The invention aims to provide a layout generation method, device, equipment and medium, which are used for solving the problem that the corresponding wafer layout cannot be obtained from the existing wafer image rapidly and efficiently in the prior art.
In order to solve the technical problems, the invention provides a layout generation method, which comprises the following steps:
acquiring a measurement gray scale image and critical dimension data of a measurement path on the measurement gray scale image;
determining a path gray scale graph according to the measurement path and the measurement gray scale graph;
determining an edge gray threshold according to the path gray graph and the critical dimension data;
determining a pattern edge graph on the measurement gray level graph according to the edge gray level value;
determining a set of sampling points on the pattern edge graph;
and connecting sampling points in the sampling point set in sequence by using straight lines to obtain a closed polygonal target layout.
Optionally, in the layout generating method, the obtaining the measurement gray scale map and the critical dimension data of the measurement path on the measurement gray scale map includes:
and acquiring a measurement gray scale image and critical dimension data of a measurement path on the measurement gray scale image by a critical dimension scanning electron microscope.
Optionally, in the layout generating method, determining a path gray scale graph according to the measurement path and the measurement gray scale graph includes:
acquiring path gray scale information corresponding to the measurement path according to the measurement gray scale map;
normalizing the path gray information to obtain standard gray information;
and determining a path gray scale curve graph according to the measurement path and the standard gray scale information.
Optionally, in the layout generating method, the determining the set of sampling points on the pattern edge graph includes:
and determining a sampling point on the pattern edge graph every first number of scanning points to obtain a sampling point set.
Optionally, in the layout generating method, the determining the set of sampling points on the pattern edge graph includes:
rasterizing the pattern edge graph;
and determining an intersection point of the pattern edge graph and the grid edge, and taking the intersection point as a sampling point to obtain a sampling point set.
Optionally, in the layout generating method, the rasterizing the pattern edge graph includes:
and rasterizing the pattern edge graph by taking a scanning point at the lower left corner of the pattern edge graph as a coordinate zero point.
Optionally, in the layout generating method, the side length of the grid ranges from 1 nm to 10 nm, including the end point value.
A layout generating device, comprising:
the acquisition module is used for acquiring the measurement gray level diagram and the critical dimension data of the measurement path on the measurement gray level diagram;
the curve module is used for determining a path gray scale graph according to the measurement path and the measurement gray scale graph;
the gray scale module is used for determining an edge gray scale threshold according to the path gray scale graph and the critical dimension data;
an edge module for determining a pattern edge pattern on the measurement gray scale map according to the edge gray scale value;
the sampling module is used for determining a sampling point set on the pattern edge graph;
and the connecting module is used for sequentially connecting the sampling points in the sampling point set by utilizing the straight line to obtain a closed polygonal target layout.
A layout generating device, comprising:
a memory for storing a computer program;
and a processor for implementing the steps of the layout generation method as described in any one of the above when executing the computer program.
A computer readable storage medium having stored thereon a computer program which when executed by a processor performs the steps of the layout generation method as described in any of the preceding claims.
The layout generation method provided by the invention is characterized in that the key dimension data of the measurement gray level diagram and the measurement path on the measurement gray level diagram are obtained; determining a path gray scale graph according to the measurement path and the measurement gray scale graph; determining an edge gray threshold according to the path gray graph and the critical dimension data; determining a pattern edge graph on the measurement gray level graph according to the edge gray level value; determining a set of sampling points on the pattern edge graph; and connecting sampling points in the sampling point set in sequence by using straight lines to obtain a closed polygonal target layout.
The method scans the existing wafer to obtain the measurement gray level diagram, combines the critical dimension data obtained in measurement to obtain the corresponding wafer edge (namely the pattern edge diagram) in the measurement gray level diagram, then takes a plurality of sampling points on the pattern edge diagram, and connects the sampling points to obtain the polygonal wafer layout (namely the polygonal target layout). The invention also provides a layout generating device, equipment and medium with the beneficial effects.
Drawings
For a clearer description of embodiments of the invention or of the prior art, the drawings that are used in the description of the embodiments or of the prior art will be briefly described, it being apparent that the drawings in the description below are only some embodiments of the invention, and that other drawings can be obtained from them without inventive effort for a person skilled in the art.
FIG. 1 is a schematic flow chart of a specific embodiment of a layout generation method provided by the invention;
FIG. 2 is a measurement gray scale of an embodiment of the layout generation method provided by the present invention;
FIG. 3 is a schematic flow chart of another embodiment of the layout generation method provided by the present invention;
fig. 4 is a schematic structural diagram of an embodiment of the layout generating device provided by the invention.
In the drawing, it includes: 100-acquisition module, 200-curve module, 300-gray scale module, 400-edge module, 500-sampling module, 600-connection module.
Detailed Description
In order to better understand the aspects of the present invention, the present invention will be described in further detail with reference to the accompanying drawings and detailed description. It will be apparent that the described embodiments are only some, but not all, embodiments of the invention. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
The core of the present invention is to provide a layout generating method, a flow diagram of one specific embodiment of which is shown in fig. 1, which is called as a specific embodiment one, including:
s101: and acquiring the critical dimension data of the measurement path on the measurement gray scale map.
Currently, some cd measurement devices exist, which can scan a wafer and provide a scanned gray scale image of the wafer, and measure the cd, where the cd measurement can be manually set, which belongs to known information.
The method comprises the following steps:
and acquiring a measurement gray scale image and critical dimension data of a measurement path on the measurement gray scale image by a critical dimension scanning electron microscope.
The critical dimension scanning electron microscope (CD SEM, full scale Critical Dimension Scanning Electron Microscope) can measure the critical dimension in the scanning process, and the steps of generating the measurement gray scale image, acquiring the critical dimension data and marking the measurement path on the image can be completed at one time, so that the processing efficiency is greatly improved, the subsequent process is convenient, and of course, the measurement gray scale image, the critical dimension data and the measurement path can also be acquired in batches or simultaneously on other devices.
S102: and determining a path gray scale graph according to the measurement path and the measurement gray scale graph.
Referring to fig. 2, fig. 2 is a measurement gray scale map corresponding to the measurement path, where the measurement gray scale map refers to that each scanning point on the measurement path is arranged on a horizontal axis, and a vertical axis height corresponding to each scanning point refers to a corresponding gray scale value.
Specifically, a preferred embodiment of this step includes:
a1: and obtaining path gray level information corresponding to the measurement path according to the measurement gray level diagram.
Namely, the gray value corresponding to each scanning point on the measuring path is obtained.
A2: and carrying out normalization processing on the path gray information to obtain standard gray information.
A number between 0 and 1 is used to refer to a gray value from black to white.
A3: and determining a path gray scale curve graph according to the measurement path and the standard gray scale information.
I.e. the vertical axis of the path gray scale graph is set to 0 to 1. In the preferred embodiment, the gray values on the measurement path are normalized, and the data after normalization is more representative, so that cross-image comparison can be performed, and the universality and expansibility of the scheme provided by the invention are greatly widened.
S103: and determining an edge gray level threshold according to the path gray level curve graph and the critical dimension data.
Since the horizontal axis of the path gray scale graph is compared with the corresponding scanning point, after knowing the critical dimension data, the critical dimension data can be reflected in the path gray scale graph, specifically, the length of the critical dimension data is cut out in the horizontal axis direction, and a position where the distance between the two ends of the curve in the path gray scale graph on the horizontal axis is equal to the critical dimension data (marked d in fig. 2) is found, and the gray value corresponding to the position is the gray value corresponding to the semiconductor edge measured by the device, that is, the edge gray threshold (denoted by Ti in fig. 2).
S104: and determining a pattern edge graph on the measurement gray level graph according to the edge gray level value.
Finding points on the measured gray level image, the gray level value of which is equal to the edge gray level threshold value, and fitting the points to obtain the pattern edge graph, wherein the pattern edge graph represents the shape of the scanned semiconductor device.
S105: a set of sampling points on the pattern edge graph is determined.
And taking a plurality of points on the pattern edge graph as sampling points, wherein all the sampling points are the sampling point set, and naturally, the rule for extracting the sampling points can be formulated according to actual conditions, and the invention is not limited in this description.
The following provides a specific embodiment, where determining the set of sampling points on the pattern edge graph includes:
and determining a sampling point on the pattern edge graph every first number of scanning points to obtain a sampling point set.
The pattern edge graph is formed by combining and arranging a plurality of scanning points (can be understood as pixel points), in this specific embodiment, one sampling point is determined every a certain number of scanning points, and of course, the pattern edge graph is required to be taken out a circle until the number of the scanning points, which are separated from the starting point by the last sampling point, is equal to or smaller than the first number, so that the pattern edge graph can be quickly replaced by a polygon which can be used for the operation of a photoetching machine table, and the processing efficiency is high.
Of course, the first number of ranges may be selected automatically according to practical situations, and preferably, the first number of ranges from 2 to 20, including any of the end point values, such as 2.0, 15.0 or 20.0.
S106: and connecting sampling points in the sampling point set in sequence by using straight lines to obtain a closed polygonal target layout.
The layout generation method provided by the invention is characterized in that the key dimension data of the measurement gray level diagram and the measurement path on the measurement gray level diagram are obtained; determining a path gray scale graph according to the measurement path and the measurement gray scale graph; determining an edge gray threshold according to the path gray graph and the critical dimension data; determining a pattern edge graph on the measurement gray level graph according to the edge gray level value; determining a set of sampling points on the pattern edge graph; and connecting sampling points in the sampling point set in sequence by using straight lines to obtain a closed polygonal target layout. The method scans the existing wafer to obtain the measurement gray level diagram, combines the critical dimension data obtained in measurement to obtain the corresponding wafer edge (namely the pattern edge diagram) in the measurement gray level diagram, then takes a plurality of sampling points on the pattern edge diagram, and connects the sampling points to obtain the polygonal wafer layout (namely the polygonal target layout).
On the basis of the first embodiment, the obtaining process of the sampling point is further limited, so as to obtain a second embodiment, and a corresponding flow diagram is shown in fig. 3, including:
s201: and acquiring the critical dimension data of the measurement path on the measurement gray scale map.
S202: and determining a path gray scale graph according to the measurement path and the measurement gray scale graph.
S203: and determining an edge gray level threshold according to the path gray level curve graph and the critical dimension data.
S204: and determining a pattern edge graph on the measurement gray level graph according to the edge gray level value.
S205: and rasterizing the pattern edge graph.
As a preferred embodiment, the rasterizing the pattern edge pattern includes:
and rasterizing the pattern edge graph by taking a scanning point at the lower left corner of the pattern edge graph as a coordinate zero point.
The scanning point at the lower left corner is the leftmost and bottommost scanning point of the whole pattern edge graph, and the point is used as a coordinate zero point, so that the pattern edge graph can be completely positioned in the first quadrant, subsequent calculation is convenient, and the processing efficiency is improved. Of course, other scan points may be selected as the coordinate zero point according to technical conditions, and the present invention is not limited herein.
S206: and determining an intersection point of the pattern edge graph and the grid edge, and taking the intersection point as a sampling point to obtain a sampling point set.
S207: and connecting sampling points in the sampling point set in sequence by using straight lines to obtain a closed polygonal target layout.
The difference between the present embodiment and the above embodiment is that a preferred sampling point calculating method is further provided in the present embodiment, and the other steps are the same as those of the above embodiment, and are not repeated here.
In the preferred embodiment, the pattern edge graph is rasterized, that is, the pattern edge graph is placed in the grid, and only the points intersected with the grid are taken as the sampling points, so that the representation method of the relative position relation of each sampling point can be greatly simplified, the high similarity of the pattern edge graph is maintained, the operation efficiency is improved, and the polygonal target layout more similar to the measurement gray level graph is obtained.
Preferably, the grid has a side length in the range of 1 nm to 10 nm, including any of the end points, such as 1.0 nm, 5.6 nm or 10.0 nm. The smaller the side length is, the larger the calculated amount is, the higher the accuracy of the polygon target layout is, the above range is the range of the balance accuracy and calculated amount obtained after a large number of theoretical calculation and actual inspection, and of course, the invention is not limited herein, and the calculated amount can be correspondingly adjusted according to the actual situation.
The layout generating device provided by the embodiment of the invention is introduced below, and the layout generating device described below and the layout generating method described above can be referred to correspondingly.
Fig. 4 is a block diagram of a layout generating device according to an embodiment of the present invention, and referring to fig. 4, the layout generating device may include:
an obtaining module 100, configured to obtain a measurement gray scale map and critical dimension data of a measurement path on the measurement gray scale map;
a curve module 200, configured to determine a path gray scale graph according to the measurement path and the measurement gray scale graph;
the gray scale module 300 is configured to determine an edge gray scale threshold according to the path gray scale graph and the critical dimension data;
an edge module 400 for determining a pattern edge pattern on the measurement gray scale map according to the edge gray scale value;
a sampling module 500 for determining a set of sampling points on the pattern edge graph;
and the connection module 600 is used for sequentially connecting the sampling points in the sampling point set by using straight lines to obtain a closed polygonal target layout.
As a preferred embodiment, the acquisition module 100 includes:
and the SEM unit is used for acquiring the measurement gray level diagram and the critical dimension data of the measurement path on the measurement gray level diagram through a critical dimension scanning electron microscope.
As a preferred embodiment, the curve module 200 includes:
the path gray level unit is used for acquiring path gray level information corresponding to the measurement path according to the measurement gray level image;
the normalization unit is used for carrying out normalization processing on the path gray information to obtain standard gray information;
and the gray scale curve unit is used for determining a path gray scale curve chart according to the measuring path and the standard gray scale information.
As a preferred embodiment, the sampling module 500 includes:
and the interval sampling unit is used for determining a sampling point every first number of scanning points on the pattern edge graph to obtain a sampling point set.
As a preferred embodiment, the sampling module 500 includes:
a rasterizing unit for rasterizing the pattern edge graph;
and the intersection point unit is used for determining the intersection point of the pattern edge graph and the grid edge, and taking the intersection point as a sampling point to obtain a sampling point set.
As a preferred embodiment, the sampling module 500 includes:
and the lower left rasterization unit is used for rasterizing the pattern edge graph by taking a scanning point at the lower left corner of the pattern edge graph as a coordinate zero point.
The layout generating device provided by the invention is used for acquiring the measurement gray level diagram and the critical dimension data of the measurement path on the measurement gray level diagram through the acquisition module 100; a curve module 200, configured to determine a path gray scale graph according to the measurement path and the measurement gray scale graph; the gray scale module 300 is configured to determine an edge gray scale threshold according to the path gray scale graph and the critical dimension data; an edge module 400 for determining a pattern edge pattern on the measurement gray scale map according to the edge gray scale value; a sampling module 500 for determining a set of sampling points on the pattern edge graph; and the connection module 600 is used for sequentially connecting the sampling points in the sampling point set by using straight lines to obtain a closed polygonal target layout. The method scans the existing wafer to obtain the measurement gray level diagram, combines the critical dimension data obtained in measurement to obtain the corresponding wafer edge (namely the pattern edge diagram) in the measurement gray level diagram, then takes a plurality of sampling points on the pattern edge diagram, and connects the sampling points to obtain the polygonal wafer layout (namely the polygonal target layout).
The layout generating device of this embodiment is used to implement the foregoing layout generating method, so that the specific implementation in the layout generating device may be found in the foregoing embodiment parts of the layout generating method, for example, the obtaining module 100, the curve module 200, the gray scale module 300, the edge module 400, the sampling module 500, and the connecting module 600 are respectively used to implement steps S101, S102, S103, S104, S105, and S106 in the foregoing layout generating method, so that the specific implementation thereof may refer to the description of the corresponding embodiment parts and will not be repeated herein.
The invention also provides layout generating equipment, which comprises:
a memory for storing a computer program;
and a processor for implementing the steps of the layout generation method as described in any one of the above when executing the computer program. The layout generation method provided by the invention is characterized in that the key dimension data of the measurement gray level diagram and the measurement path on the measurement gray level diagram are obtained; determining a path gray scale graph according to the measurement path and the measurement gray scale graph; determining an edge gray threshold according to the path gray graph and the critical dimension data; determining a pattern edge graph on the measurement gray level graph according to the edge gray level value; determining a set of sampling points on the pattern edge graph; and connecting sampling points in the sampling point set in sequence by using straight lines to obtain a closed polygonal target layout. The method scans the existing wafer to obtain the measurement gray level diagram, combines the critical dimension data obtained in measurement to obtain the corresponding wafer edge (namely the pattern edge diagram) in the measurement gray level diagram, then takes a plurality of sampling points on the pattern edge diagram, and connects the sampling points to obtain the polygonal wafer layout (namely the polygonal target layout).
The present invention also provides a computer readable storage medium having stored thereon a computer program which when executed by a processor implements the steps of the layout generation method as described in any of the above. The layout generation method provided by the invention is characterized in that the key dimension data of the measurement gray level diagram and the measurement path on the measurement gray level diagram are obtained; determining a path gray scale graph according to the measurement path and the measurement gray scale graph; determining an edge gray threshold according to the path gray graph and the critical dimension data; determining a pattern edge graph on the measurement gray level graph according to the edge gray level value; determining a set of sampling points on the pattern edge graph; and connecting sampling points in the sampling point set in sequence by using straight lines to obtain a closed polygonal target layout. The method scans the existing wafer to obtain the measurement gray level diagram, combines the critical dimension data obtained in measurement to obtain the corresponding wafer edge (namely the pattern edge diagram) in the measurement gray level diagram, then takes a plurality of sampling points on the pattern edge diagram, and connects the sampling points to obtain the polygonal wafer layout (namely the polygonal target layout).
In this specification, each embodiment is described in a progressive manner, and each embodiment is mainly described in a different point from other embodiments, so that the same or similar parts between the embodiments are referred to each other. For the device disclosed in the embodiment, since it corresponds to the method disclosed in the embodiment, the description is relatively simple, and the relevant points refer to the description of the method section.
It should be noted that in this specification, relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element.
Those of skill would further appreciate that the various illustrative elements and algorithm steps described in connection with the embodiments disclosed herein may be implemented as electronic hardware, computer software, or combinations of both, and that the various illustrative elements and steps are described above generally in terms of functionality in order to clearly illustrate the interchangeability of hardware and software. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the solution. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present invention.
The steps of a method or algorithm described in connection with the embodiments disclosed herein may be embodied directly in hardware, in a software module executed by a processor, or in a combination of the two. The software modules may be disposed in Random Access Memory (RAM), memory, read Only Memory (ROM), electrically programmable ROM, electrically erasable programmable ROM, registers, hard disk, a removable disk, a CD-ROM, or any other form of storage medium known in the art.
The layout generation method, the device, the equipment and the medium provided by the invention are described in detail. The principles and embodiments of the present invention have been described herein with reference to specific examples, the description of which is intended only to facilitate an understanding of the method of the present invention and its core ideas. It should be noted that it will be apparent to those skilled in the art that various modifications and adaptations of the invention can be made without departing from the principles of the invention and these modifications and adaptations are intended to be within the scope of the invention as defined in the following claims.
Claims (10)
1. A layout generation method is characterized by comprising the following steps:
acquiring a measurement gray scale image and critical dimension data of a measurement path on the measurement gray scale image;
determining a path gray scale graph according to the measurement path and the measurement gray scale graph;
determining an edge gray threshold according to the path gray graph and the critical dimension data;
determining a pattern edge graph on the measurement gray scale graph according to the edge gray scale value;
determining a set of sampling points on the pattern edge graph;
connecting sampling points in the sampling point set in sequence by using straight lines to obtain a closed polygonal target layout;
the point on the horizontal axis of the path gray scale graph corresponds to each scanning point on the measuring path, and the vertical axis height corresponding to each point is the gray scale value of the corresponding scanning point;
the determining an edge gray threshold according to the path gray scale graph and the critical dimension data comprises:
intercepting the length of the critical dimension data in the horizontal axis direction of the path gray scale graph, searching a position, which is the distance between two ends of the curve in the path gray scale graph on the horizontal axis and is equal to the critical dimension data, and taking a gray value corresponding to the position as the edge gray scale threshold;
the determining the pattern edge graph on the measurement gray graph according to the edge gray value comprises the following steps:
and searching for a point with the gray value equal to the edge gray threshold value on the measurement gray map, and fitting the point with the gray value equal to the edge gray threshold value on the measurement gray map to obtain the pattern edge graph.
2. The layout generating method according to claim 1, wherein the obtaining the measurement gray scale map and the critical dimension data of the measurement path on the measurement gray scale map comprises:
and acquiring a measurement gray scale image and critical dimension data of a measurement path on the measurement gray scale image by a critical dimension scanning electron microscope.
3. The layout generation method according to claim 1, wherein determining a path gray scale map from the measurement path and the measurement gray scale map comprises:
acquiring path gray scale information corresponding to the measurement path according to the measurement gray scale map;
normalizing the path gray information to obtain standard gray information;
and determining a path gray scale curve graph according to the measurement path and the standard gray scale information.
4. The layout generation method according to claim 1, wherein the determining the set of sampling points on the pattern edge graph comprises:
and determining a sampling point on the pattern edge graph every first number of scanning points to obtain a sampling point set.
5. The layout generation method according to claim 1, wherein the determining the set of sampling points on the pattern edge graph comprises:
rasterizing the pattern edge graph;
and determining an intersection point of the pattern edge graph and the grid edge, and taking the intersection point as a sampling point to obtain a sampling point set.
6. The layout generation method according to claim 5, wherein rasterizing the pattern edge graphic comprises:
and rasterizing the pattern edge graph by taking a scanning point at the lower left corner of the pattern edge graph as a coordinate zero point.
7. The layout generation method of claim 5, wherein the grid has a side length ranging from 1 nm to 10 nm, inclusive.
8. A layout generating apparatus, comprising:
the acquisition module is used for acquiring the measurement gray level diagram and the critical dimension data of the measurement path on the measurement gray level diagram;
the curve module is used for determining a path gray scale graph according to the measurement path and the measurement gray scale graph;
the gray scale module is used for determining an edge gray scale threshold according to the path gray scale graph and the critical dimension data;
the edge module is used for determining a pattern edge graph on the measurement gray level graph according to the edge gray level value;
the sampling module is used for determining a sampling point set on the pattern edge graph;
the connecting module is used for sequentially connecting the sampling points in the sampling point set by utilizing straight lines to obtain a closed polygonal target layout;
the point on the horizontal axis of the path gray scale graph corresponds to each scanning point on the measuring path, and the vertical axis height corresponding to each point is the gray scale value of the corresponding scanning point;
the determining an edge gray threshold according to the path gray scale graph and the critical dimension data comprises:
intercepting the length of the critical dimension data in the horizontal axis direction of the path gray scale graph, searching a position, which is the distance between two ends of the curve in the path gray scale graph on the horizontal axis and is equal to the critical dimension data, and taking a gray value corresponding to the position as the edge gray scale threshold;
the determining the pattern edge graph on the measurement gray graph according to the edge gray value comprises the following steps:
and searching for a point with the gray value equal to the edge gray threshold value on the measurement gray map, and fitting the point with the gray value equal to the edge gray threshold value on the measurement gray map to obtain the pattern edge graph.
9. A layout generating apparatus, comprising:
a memory for storing a computer program;
a processor for implementing the steps of the layout generating method according to any of claims 1 to 7 when executing said computer program.
10. A computer readable storage medium, characterized in that the computer readable storage medium has stored thereon a computer program which, when executed by a processor, implements the steps of the layout generation method according to any of claims 1 to 7.
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