WO2023070597A1 - Method and apparatus for retargeting layout graphic, device, medium, and program product - Google Patents

Abstract

The present disclosure relates to a method and apparatus for retargeting a layout graphic, a device, a medium, and a program product. The method comprises: determining a plurality of mask graphics corresponding to a layout graphic in a circuit layout, the plurality of mask graphics having different sizes. The method further comprises: determining, by means of lithography imaging simulation, the sizes of a plurality of wafer graphics formed on the basis of the plurality of mask graphics. The method comprises: for each of the plurality of wafer graphics, determining a simulation value of a process parameter used for evaluating a process window or imaging quality. The method comprises: determining a target size from the sizes of the plurality of wafer graphics at least on the basis of the simulation value of the process parameter. The method further comprises: configuring the layout graphic in the circuit layout to have the target size. In this way, retargeting of the layout graphic with higher accuracy and wider coverage can be achieved.

Description

Method, device, device, medium and program product for redefining layout graphics technical field

Embodiments of the present disclosure generally relate to the field of integrated circuits. More specifically, the embodiments of the present disclosure relate to a method, apparatus, device, computer-readable storage medium and computer program product for redefining layout graphics.

Background technique

The photolithography process is one of the important processes that dominate the line width of integrated circuits. In advanced semiconductor process nodes, due to light diffraction, interference effects, and limitations in light source design, the lithography process cannot achieve sufficient lithography process windows or lithography imaging quality at certain specific size or pitch patterns. Difference. In the layout, the graphics with the above phenomena are called hot spots, which seriously affect the yield of the overall photolithography process.

In order to solve the above-mentioned problems, there are two solutions. One solution improves overall process yield by adding sub-resolution assist patterning (SRAF). Another solution is to improve the overall process yield by retargeting the pattern line width target value. However, in partial positive tone processes, SRAF offers limited improvement and tends to generate additional imaging on the wafer. Therefore, the scheme of redefining the target value of the line width of the target pattern is adopted in the photolithography process of most layout layers.

Contents of the invention

Embodiments of the present disclosure provide a solution for redefining layout graphics.

In a first aspect of the present disclosure, a method for redefining layout graphics is provided. The method includes: determining a plurality of mask patterns corresponding to layout patterns in the circuit layout, where the plurality of mask patterns have different sizes. The method also includes: determining the dimensions of the plurality of wafer patterns formed based on the plurality of mask patterns through lithographic imaging simulation. The method includes determining, for each wafer pattern of a plurality of wafer patterns, simulated values of process parameters for evaluating process window or imaging quality. The method includes determining target dimensions from dimensions of a plurality of wafer patterns based at least on simulated values of process parameters. The method further includes: setting the layout pattern in the circuit layout to have a target size.

In the embodiment of the present disclosure, there is no need to collect and organize a large amount of wafer data, so the time cost and material cost of redefining the target pattern are reduced, thereby reducing the time in the development process of lithography and optical proximity correction (OPC) process cost and material cost. In addition, in the embodiments of the present disclosure, the redefinition operation can be directly performed on all graphics in the entire layout very quickly and intelligently, and the influence of the surrounding layout environment of each graphics can be fully simulated. In this way, higher accuracy and wider coverage can be achieved, and the limitations and errors brought about by the rule-based target graph redefinition scheme are greatly improved.

In an implementation manner of the first aspect, determining a plurality of mask patterns includes: in each iteration of multiple rounds of iterations, determining a plurality of A subset of mask patterns. The method also includes: in each round of iteration, determining an intermediate value for the target size based on a subset of the plurality of mask patterns; and setting the size of the layout pattern in the circuit layout as the intermediate value for the next round of iteration.

In this implementation, the use of parallel optimization algorithms can greatly improve computational efficiency. In addition, at the beginning of each iteration except the first iteration, the surrounding environment of the layout graphics is the environment after the previous round of redefinition. As the number of iterations increases, the degree of overall redefinition will become smaller and smaller until convergence. In this way, simulation accuracy can be improved.

In yet another implementation of the first aspect, the method further includes: selecting a predetermined number of mask patterns from the first subset based on simulated values of process parameters corresponding to the first subset of the plurality of mask patterns , the first subset is determined in the first round of iterations; and based on the size of the predetermined number of mask patterns, determine the sampling range for the second round of iterations to be used to determine the mask patterns in the second round The second subset of iterations, the second iteration immediately following the first iteration. In this implementation manner, the sampling range of the next round is determined based on the size of the preferred mask pattern in the previous round. In this way, the convergence speed can be accelerated.

In yet another implementation manner of the first aspect, setting the layout pattern in the circuit layout to have a target size includes: obtaining constraints related to design rules for the layout pattern; An offset pattern corresponding to the target size is added to at least one of one side or a second side, the second side being opposite to the first side. In this way, the redefined layout can be enabled to pass design rule checking.

In yet another implementation of the first aspect, determining the target size from the sizes of the plurality of wafer patterns based at least on the simulated values of the process parameters includes: for each of the plurality of wafer patterns, determining to be set The layout pattern with the size of the wafer pattern satisfies the constraint, and the constraint is related to the design rule for the layout pattern; and based on the simulation value and the satisfaction degree of the process parameter, the target size is determined from the dimensions of the plurality of wafer patterns.

In yet another implementation of the first aspect, determining the target size from the dimensions of the plurality of wafer patterns based at least on the simulated value of the process parameter includes: determining to form a corresponding The imaging cost of the wafer pattern; and determining the size of the wafer pattern with the lowest imaging cost as the target size. In this implementation, taking the design rule check into consideration in determining the target size can efficiently determine the target size and avoid reselecting the target size due to failure of the design rule check. In this way, the efficiency of graph redefinition is improved.

In yet another implementation of the first aspect, the method further includes: detecting a predetermined type of defect in the circuit layout in response to the layout pattern being set to have a target size; and adding an offset pattern at the detected defect In order to make the graphics at the detected defects flush with the surrounding graphics. In this way, defects can be repaired to avoid negative impacts on subsequent OPC operations.

In yet another implementation manner of the first aspect, the method further includes: identifying the type of the graphic in the circuit layout; and based on the identified type and the relative position of the graphic and the surrounding graphic, dividing the graphic into a pattern including the layout graphic Multiple layout graphics. Since the environment of different parts of the same graph may not be exactly the same, it is necessary to use the segmentation operation to divide the originally larger graph in the layout into smaller layout graphs, and then perform redefinition operations on these layout graphs respectively. In this way, the accuracy of graph redefinition can be improved.

In a second aspect of the present disclosure, an apparatus for redefining layout graphics is provided. The device includes: a mask pattern determining unit configured to determine a plurality of mask patterns corresponding to layout patterns in the circuit layout, the plurality of mask patterns having different sizes. The device includes: a wafer pattern determination unit configured to determine the dimensions of a plurality of wafer patterns formed based on a plurality of mask patterns through lithographic imaging simulation. The apparatus includes: a process parameter determination unit configured to determine, for each wafer pattern among the plurality of wafer patterns, simulated values of process parameters for evaluating a process window or imaging quality. The apparatus includes: a target size determination unit configured to determine the target size from dimensions of a plurality of wafer patterns based at least on simulated values of process parameters. The apparatus further includes: a redefinition unit configured to set the layout pattern in the circuit layout to have a target size.

In an implementation manner of the second aspect, the mask pattern determination unit is further configured to: in each iteration of multiple iterations, by changing the size of the mask pattern within the sampling range for the iteration, determine A subset of multiple mask patterns. The target size determining unit is further configured to determine an intermediate value for the target size based on a subset of the plurality of mask patterns in each iteration. The redefinition unit is further configured to set the size of the layout pattern in the circuit layout to an intermediate value for the next iteration.

In yet another implementation manner of the second aspect, the device further includes: a mask pattern selection unit configured to select from the first A predetermined number of mask patterns are selected in the subset, the first subset is determined in the first round of iteration; and the sampling range determination unit is configured to determine the size of the mask pattern for the second round of iteration based on the size of the predetermined number of mask patterns A sampling range for determining a second subset of the plurality of mask patterns in a second iteration immediately after the first iteration.

In yet another implementation manner of the second aspect, the redefinition unit is further configured to: acquire constraints related to design rules for the layout pattern; and selectively add to the first or second side of the layout pattern based on the constraints Add an offset graphic corresponding to the target size on at least one side of the , and the second side is opposite the first side.

In yet another implementation of the second aspect, the target size determination unit is further configured to: for each wafer pattern in the plurality of wafer patterns, determine the layout pattern pair constraints set to have the size of the wafer pattern The degree of satisfaction of the constraint is related to the design rules for the layout pattern; and the target size is determined from the dimensions of the plurality of wafer patterns based on the simulated values of the process parameters and the degree of satisfaction.

In yet another implementation of the second aspect, the target size determination unit is further configured to: determine the imaging cost for forming the corresponding wafer pattern based on the threshold value, the target value and the simulated value for the process parameters; and minimize the imaging cost The size of the wafer pattern is determined as the target size.

In yet another implementation of the second aspect, the apparatus further includes: a defect detection unit configured to detect a predetermined type of defect in the circuit layout in response to the layout pattern being set to have a target size; and a defect repair unit, It is configured to add an offset pattern at the detected defect so that the pattern at the detected defect is flush with the surrounding pattern.

In yet another implementation manner of the second aspect, the apparatus further includes: a pattern classification unit configured to identify the type of the pattern in the circuit layout; and a pattern segmentation unit configured to identify the pattern based on the identified type and pattern The relative position of the surrounding graphics divides the graphics into multiple layout graphics including the layout graphics.

In a third aspect of the present disclosure, there is provided an electronic device comprising: at least one processor; at least one memory coupled to the at least one processor and storing instructions for execution by the at least one processor. When the instructions are executed by at least one processor, the electronic device executes the method in any one implementation manner of the first aspect.

In a fourth aspect of the present disclosure, a computer-readable storage medium is provided, on which a computer program is stored, and when the program is executed by a processor, the method in any one of the implementation manners of the first aspect is implemented.

In a fifth aspect of the present disclosure, there is provided a computer program product, which is characterized by comprising computer-executable instructions, wherein the computer-executable instructions implement the method in any one of the implementation manners of the first aspect when executed by a processor .

It can be understood that the apparatus of the second aspect, the electronic device of the third aspect, the computer storage medium of the fourth aspect, or the computer program product of the fifth aspect provided above are all used to execute the method provided in the first aspect. Therefore, the explanations or illustrations about the first aspect are also applicable to the second aspect, the third aspect, the fourth aspect and the fifth aspect. In addition, for the beneficial effects achieved by the second aspect, the third aspect, the fourth aspect and the fifth aspect, reference may be made to the beneficial effects in the corresponding methods, which will not be repeated here.

It should be understood that what is described in the Summary of the Invention is not intended to limit the key or important features of the embodiments of the present disclosure, nor is it intended to limit the scope of the present disclosure. Other features of the present disclosure will be readily understood through the following description.

Description of drawings

The above and other features, advantages and aspects of the various embodiments of the present disclosure will become more apparent with reference to the following detailed description when taken in conjunction with the accompanying drawings. In the drawings, identical or similar reference numerals denote identical or similar elements, wherein:

Figure 1 shows the test pattern used in the rule-based target pattern redefinition scheme;

Figure 2 shows a simplified schematic diagram of rule-based target graph redefinition;

3 shows a block diagram of an example system for model-based object graph redefinition according to an embodiment of the present disclosure;

Figure 4 shows an example of graph classification according to some embodiments of the present disclosure;

FIG. 5 shows a schematic diagram of layout graphics and measurement marks according to some embodiments of the present disclosure;

FIG. 6 shows a schematic diagram of simulating critical dimensions of a wafer according to some embodiments of the present disclosure;

Figure 7 shows an example of an analysis process window according to some embodiments of the present disclosure;

FIG. 8A shows an example of an adjustment function for determining imaging costs according to some embodiments of the present disclosure;

FIG. 8B illustrates another example of an adjustment function for determining imaging costs according to some embodiments of the present disclosure;

Fig. 9 shows a schematic diagram of sampling ranges in multiple rounds of iterations according to some embodiments of the present disclosure;

FIG. 10 shows a schematic diagram of a part of a redefined layout according to some embodiments of the present disclosure;

Figure 11A shows a schematic diagram of repairing an example defect according to some embodiments of the present disclosure;

FIG. 11B shows a schematic diagram of repairing another example defect according to some embodiments of the present disclosure;

Figure 12 shows an example of constraints related to design rules according to some embodiments of the present disclosure;

Figure 13 shows an example of a checked and repaired layout according to some embodiments of the present disclosure;

FIG. 14 shows a flowchart of an example method of redefining a layout graph according to some embodiments of the present disclosure;

FIG. 15 shows a schematic block diagram of an apparatus for redefining layout graphics according to some embodiments of the present disclosure; and

Figure 16 shows a block diagram of a computing device capable of implementing various embodiments of the present disclosure.

Detailed ways

Embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. Although certain embodiments of the present disclosure are shown in the drawings, it should be understood that the disclosure may be embodied in various forms and should not be construed as limited to the embodiments set forth herein; A more thorough and complete understanding of the present disclosure. It should be understood that the drawings and embodiments of the present disclosure are for exemplary purposes only, and are not intended to limit the protection scope of the present disclosure.

In the description of the embodiments of the present disclosure, the term "comprising" and its similar expressions should be interpreted as an open inclusion, that is, "including but not limited to". The term "based on" should be understood as "based at least in part on". The term "one embodiment" or "the embodiment" should be read as "at least one embodiment". The terms "first", "second", etc. may refer to different or the same object. The term "and/or" means at least one of the two items associated with it. For example "A and/or B" means A, B, or A and B. Other definitions, both express and implied, may also be included below.

In embodiments of the present disclosure, the term "critical dimension" refers to a physical feature dimension in a layout, on a mask or on a wafer, which is a form of dimension. In this document, the terms "critical dimension" and "dimension" are used interchangeably.

As mentioned above, the target pattern redefinition scheme is adopted in the photolithography process of most layout layers. Traditional target graph redefinition schemes are rule-based. In this rule-based target pattern redefinition scheme, the wafer is exposed and developed using a mask defined by a test pattern with multiple line widths/spaces continuously changing, and wafer measurement data is collected. Figure 1 shows an example of a set of test patterns used in a rule-based target pattern redefinition scheme. As shown in FIG. 1 , in the spacing dimension, that is, from the test pattern 110 to the test pattern 120 , the distance between adjacent polygons in the test pattern gradually increases. In the width dimension, that is, from the test pattern 110 to the test pattern 130, the width of each polygon in the test pattern gradually increases.

Then observe the lithography process evaluation parameters such as the lithography process window and line width roughness of each group of test patterns. Taking the lithography process window as an example, the determination method is: step-scanning the depth of focus and exposure dose of the lithography machine at a certain interval to determine the lithography process conditions under various combinations, and then in each lithography process window The test patterns (for example, the test patterns shown in FIG. 1 ) are respectively exposed and developed under the process conditions. Finally, measure the photoresist line width of the pattern on the wafer, and determine whether the photoresist line width is within a predetermined range (for example, plus/minus 10%) of the target critical dimension (CD). Draw a graph with the depth of focus as the abscissa and the exposure dose as the ordinate, and the range occupied by the point where the key dimension changes within the specified range is the photolithography process window.

A table is established according to the exposure results of all test patterns (for example, a group of test patterns shown in FIG. 1 ). This form is used to mark whether the common photolithography process window of graphics under different pitches and different CDs meets the requirements. Specifically, for each type of graphics, it is necessary to establish a aforementioned table, the horizontal row is CD, and the column is spacing change.

Then, according to the aforementioned tables, a selective size adjustment table is established through relevant mathematical formulas. Similarly, each type of graphics needs to establish its corresponding SSA form, which is used to determine the offset (bias) that needs to be added to the graphics during the redefinition operation of the target graphics, and then use the relevant layout editing tools to add bias to the relevant graphics in the layout. to change the line width of the graph. Fig. 2 shows a simplified schematic diagram of rule-based target graph redefinition. As shown in FIG. 2 , the CD of the graphic 210 is 180, and the gap between the graphic 210 and the graphic 220 is 150. By consulting the SSA table 201, it can be determined that the offset is -2. Accordingly, an offset of -2 is added to graph 210 .

Although the above-mentioned traditional rule-based target pattern redefinition scheme can solve the problem of photolithography process window, it also has significant disadvantages. For example, additional exposures and collection of wafer data for evaluating the lithography process window are required, which makes time and bill of materials costly. The complete process takes a long time period and the process is cumbersome. The rule-based target graph redefinition has certain limitations and cannot be applied to all complex graphs, and with the increase of graph types, a large number of SSA tables need to be generated. In addition, the accuracy of this traditional solution is poor, and the offset is only added in the form of a lookup table, which cannot fully consider the actual layout environment where the graphics are located.

In order to at least partially solve the above problems and other potential problems, various embodiments of the present disclosure provide a solution for redefining layout graphics. In general, according to various embodiments described herein, an offset is added to a pattern of a circuit layout by simulation of a lithography model to set the pattern to a target size. Therefore, this is a model-based scheme for object graph redefinition. The redefined circuit layout can improve the photolithography process window, improve the quality of photolithography imaging, and repair dead pixels. This also makes it easier for subsequent OPC to converge, and ultimately improves the overall lithography process yield.

In the embodiment of the present disclosure, there is no need to collect and organize a large amount of wafer data, so the time cost and material cost of redefining the target pattern are greatly reduced, thereby reducing the time cost and material cost in the process of lithography and OPC process development . In addition, in the embodiments of the present disclosure, the redefinition operation can be directly performed on all graphics in the entire layout very quickly and intelligently, and the influence of the surrounding layout environment of each graphics can be fully simulated. In this way, higher accuracy and wider coverage can be achieved, and the limitations and errors brought about by the rule-based target graph redefinition scheme are greatly improved. In addition, in the embodiments of the present disclosure, the optimal target size of the pattern within a certain range can be found, which further improves the overall performance of the photolithography process.

Various example embodiments of the present disclosure are described below with reference to FIGS. 3 to 16 .

example system

FIG. 3 shows a block diagram of an example system 300 for model-based object graph redefinition according to an embodiment of the present disclosure. In general, the system 300 uses the lithographic model 302 to process the input circuit layout 301 (also referred to as “layout 301 ”) to redefine the graphics in the layout 301 and output the redefined layout 303 . The layout 301 may be provided by the designer. The lithographic model 302 may be any known or later developed model for simulating lithographic imaging, as the scope of the present disclosure is not limited in this regard.

The processing of the layout 301 by the system 300 can be divided into a preprocessing stage 310 and an optimization stage 320 . In the preprocessing stage 310 , a series of layout graphics are determined based on each graphics in the layout 301 . As used herein, "layout pattern" refers to a pattern unit considered for redefining target dimensions. The layout graphics may be the original graphics in the layout 301, or may be a part of the original graphics, that is, obtained by dividing the original graphics. Each layout pattern is inserted with metrology marks, which are used to identify the subsequent simulation of lithographic performance and the position of the wafer CD. To achieve such processing, the preprocessing stage 310 may utilize multiple modules, such as the templating module 311 , graph classification module 312 , segmentation module 313 and measurement marker insertion module 314 shown in FIG. 3 . The templating module 311 is configured to cut the complete layout 301 to divide the layout 301 into several sub-layouts. In subsequent stages, each sublayout is processed independently and in parallel to increase overall processing speed. The graphic classification module 312 is configured to identify and classify graphics in the layout 301 (eg, graphics in each sub-layout) based on predetermined rules. The segmentation module 313 is configured to determine the layout graphics to be processed separately based on the graphics classification, for example, it can divide the original larger graphics into several smaller layout graphics. The measurement mark inserting module 314 is configured to determine a measurement position of the layout pattern, and insert a measurement mark at the measurement position. The role of these modules will be detailed below.

In the optimization phase 320, the target CD of each layout pattern is determined and the layout pattern is set to have the target CD. To achieve such processing, the optimization stage 320 utilizes at least a lithography simulation module 321 and a redefinition module 322 . The lithography simulation module 321 is configured to determine the target CD of each layout pattern through lithography imaging simulation. Specifically, the lithography simulation module 321 can determine a plurality of candidate CDs through lithography imaging simulation for each layout pattern, and select the target from the plurality of candidate CDs based on the simulated values of the process parameters respectively related to the plurality of candidate CDs. cd. In some embodiments, the lithography simulation module 321 may include multiple submodules to implement the above processing, such as the process window analysis submodule 331 , the lithography performance analysis submodule 332 and the process parameter analysis submodule 333 shown in FIG. 1 .

The redefine module 322 is configured to set the layout graph to have a target CD by adding an offset to the layout graph corresponding to the target CD. In some embodiments, the optimization phase 320 may also utilize a check and repair module 323 . The check and repair module 323 is configured to make the redefined graph satisfy design rule-related constraints, and/or repair defects in the redefined graph. As shown in FIG. 3 , the operations of the lithography simulation module 321 , the redefinition module 322 and the optional inspection and repair module 323 can be performed iteratively for continuous optimization, so as to obtain the final redefined layout 303 .

It should be understood that the division of the modules and their functions of the system 300 shown in FIG. 3 is only illustrative, and is not intended to limit the scope of the present disclosure. For example, system 300 may include more or fewer modules. As another example, the functions of some modules can be combined, or the functions of some modules can be further split.

Preprocessing of layout

As described above with reference to FIG. 3 , after the preprocessing stage 301 , a plurality of layout patterns are determined from the layout 301 , and each layout pattern is inserted with a measurement mark. Specifically, the templating module 311 cuts the complete layout 301 to divide the layout 301 into several sub-layouts, for example, several sub-layouts of equal size. The size and sampling distance of the sub-layout can be customized, or can be set based on the size of the layout 301 and the processing capability of the system 300 . Different sub-layouts may or may not overlap, and the scope of the present disclosure is not limited in this respect. During the optimization phase, each sublayout can be processed independently and in parallel. In this way, the overall processing speed of the layout 301 can be significantly improved.

The graphics classification module 312 identifies and classifies graphics in the layout 301 (eg, graphics in each sub-layout) based on predetermined rules. FIG. 4 illustrates an example of graph classification according to some embodiments of the present disclosure. As shown in FIG. 4 , graphics in a portion 400 of the layout are classified into line ends, lines (eg, line 402 ), outer corners (eg, outer corner 403 ), inner corners (eg, inner corner 404 ), gaps (eg, gap 405 ) , contacts (eg, contacts 406), gap ends (eg, gap ends 407), and the like.

The graphics classification module 312 can identify and classify the graphics in the layout 301 based on the judgment rules for different types. Taking the line end as an example, the following judgment rules can be set: the side length of the line end side is greater than or equal to the minimum width and less than or equal to the maximum width, the side length of one adjacent side is greater than or equal to the minimum short side, and the length of the other adjacent side The side length is greater than or equal to the smallest long side. According to this judging rule, a line end and its adjacent sides can be identified and determined from the layout 301 or sub-layout. By reserving the side lengths of some adjacent sides, a rectangle can be determined as the line-end figure, for example, the line-end figure 401 . Similarly, different types of graphics can be determined according to their respective judgment rules, such as line graphics 402 , outer corner graphics 403 , inner corner graphics 404 , gap graphics 405 , contact graphics 406 , and gap end graphics 407 .

The graphical classification shown in FIG. 4 is exemplary only, and is not intended to limit the scope of the present disclosure. Any suitable categorization is also possible. In addition, the above judgment rules about line ends are exemplary. In the embodiments of the present disclosure, any suitable judgment rules may be adopted for different types of graphics.

The segmentation module 313 divides the graph into several smaller layout graphs based on the graph classification. Specifically, the segmentation module 313 can insert a dissection point (dissection point) into the originally larger graph, so as to divide the graph into smaller sub-graphs. For example, an originally larger rectangle can be divided into smaller rectangles as layout graphics. The segmentation operation on the graph is the preparation stage for the subsequent redefinition operation. Since the environment of different parts of the same graph may not be exactly the same, it is necessary to use the segmentation operation to divide the original larger graph into smaller layout graphs, and then perform redefinition operations on these layout graphs respectively.

FIG. 5 shows a schematic diagram of layout patterns and metrology marks according to some embodiments of the present disclosure. FIG. 5 schematically shows segmenting the graphics 510 and 520 in the layout to determine multiple layout graphics. Taking the graphic 520 as an example, the distances between the left and right parts are different, that is, the environments where they are located are inconsistent. This will result in different process windows corresponding to the left and right parts, so the graphic 520 needs to be segmented.

As an example, the segmentation module 313 may segment larger graphs as follows. For shorter graphics such as line ends, gap ends, and contacts, segment points can be inserted at the four corners of the rectangle. That is, the line-end pattern, the gap-end pattern, and the contact pattern themselves will be determined as layout patterns. For the projected area (as shown by the dotted line in FIG. 5 ) with adjacent graphics, segment points, such as segment points 530 and 535 , can be inserted for the projected positions within the projection range. Simultaneously, segment points such as segment points 531 and 532 are inserted at predetermined distances from such segment points to the left and right, respectively, along the graph boundary. For the remaining line or gap area, segment points are inserted equidistantly according to the predetermined step size.

Through the above method, the originally large graphics can be divided into several small layout graphics, and such layout graphics are determined by multiple segmentation points. For example, a polygon can be divided into rectangles determined by 4 segment points. In the example of FIG. 5 , graph 510 and graph 520 are divided into 12 layout graphs, namely layout graphs 501 - 1 to 501 - 12 , which are also collectively or individually referred to as layout graph 501 .

After the layout pattern is determined, the metrology mark inserting module 314 inserts a metrology mark for each layout pattern. The measurement mark is used to identify the measurement position of the CD in the lithography imaging simulation. For a rectangle, the inserted measurement marks are perpendicular to the side length of the rectangle, such as the measurement mark 515 and the measurement mark 525 .

As an example, for a rectangle divided by a line or gap, the measurement mark may be located on the centerline of the rectangle. For example, the measurement mark 525 of the layout pattern 501-11 is located at the centerline of the layout pattern 501-11 (which is a rectangle). For a rectangle formed by a line end or a gap end figure, the measurement mark may be at a certain distance from the line end or gap end, and the distance may be 0.9 times the length of the adjacent side or other suitable multiples. For example, the metrology mark 515 of the layout pattern 501-4 is not located at the center line of the layout pattern 501-4, but is farther away from the line edge 550 of the layout pattern 501-4. For a rectangle formed by the contact pattern, the measurement mark may be located at the center of the long side of the rectangle and on the long side.

It should be understood that the positions of the measurement marks described above are exemplary only, and are not intended to limit the scope of the present disclosure. The position of the measurement mark can be set according to actual needs.

Model-Based Lithography Simulation

In the optimization stage 320, the lithography simulation module 321 determines the target CD of each layout pattern through lithography imaging simulation. Specifically, the lithography simulation module 321 can determine a plurality of candidate CDs through lithography imaging simulation for each layout pattern, and select the target from the plurality of candidate CDs based on the simulated values of the process parameters respectively related to the plurality of candidate CDs. cd.

Simulation values of wafer CD and process parameters

The candidate CD is the CD of the pattern formed on the wafer by lithographic imaging simulation based on the layout pattern at the measurement mark. Herein, the pattern formed on the wafer based on the layout pattern is also referred to as "wafer pattern". Correspondingly, the CD of the wafer pattern is also called wafer CD. It can be understood that the wafer CD determined by lithography imaging simulation corresponds to the simulation value of the line width on the photoresist after actual exposure and development. Correspondingly, the pattern formed on the mask corresponding to the layout pattern is also called "mask pattern", and the CD of the mask pattern is also called mask CD.

FIG. 6 shows a schematic diagram of simulating wafer CDs according to some embodiments of the present disclosure. FIG. 6 shows a mask pattern 601 corresponding to a layout pattern, which has a mask CD 604. The sine wave curve 602 is the light intensity distribution at the measurement mark obtained by simulation based on the lithographic imaging model. The horizontal dotted line 603 corresponds to the light intensity threshold determined by the lithographic imaging model. The part whose light intensity is higher than the light intensity threshold can be exposed and imaged on the wafer, while the part whose light intensity is lower than the light intensity threshold cannot be exposed and imaged on the wafer. Therefore, the wafer CD 605 of the wafer pattern can be determined based on the light intensity distribution and the light intensity threshold.

Under the same lithography conditions, the light intensity distribution is constant, so that the corresponding wafer CD 605 can be determined. In an embodiment of the present disclosure, the optimal wafer CD under ideal photolithography conditions obtained through subsequent optimization steps may be determined as the target size of the layout pattern, as will be described in detail below. The ideal lithography conditions may refer to the nominal illumination conditions of the lithography machine or the set illumination conditions of the lithography machine.

The process parameters used to evaluate the lithography process window or imaging quality may include but not limited to depth of focus (DOF), exposure latitude (EL), imaging light intensity logarithmic slope (ILS), mask error enhancement factor (MEEF), etc. . A corresponding target value tar and a threshold value tol can be set for each process parameter. The target value tar reflects the ideal value of imaging, and the threshold tol reflects the minimum requirement of imaging.

In order to determine the simulated values of the above process parameters, the lithography simulation module 321 may include a process window analysis submodule 331 and a lithography performance analysis submodule 332 . The process window analysis sub-module 331 is used to determine the process window of the layout pattern, that is, the process window at the measurement mark. As an example, the process window analysis sub-module 331 may change the focus value and exposure dose with a fixed step size, and each combination of focus value and exposure dose is a lithography condition. The process window model under various lithography conditions can be built sequentially. Then, the wafer CD under the corresponding photolithography conditions can be obtained by simulation according to the process window model. Taking the wafer CD simulated under ideal lithography conditions as the ideal CD, calculating whether the variation of the wafer CD simulated under other lithography conditions is within the predetermined range (for example, +/-10%) of the ideal CD, and to mark. In this way, the size of the process window at the measurement mark can be calculated.

Figure 7 illustrates an example of an analysis process window according to some embodiments of the present disclosure. As shown in FIG. 7 , the area between the folded line 701 and the folded line 702 corresponds to a change amount of the wafer CD within a predetermined range. Accordingly, process window 703 and DOF can be determined. The process window analysis sub-module 331 can store the value of DOF as part of the process parameters. The area of the process window 703 (ie, the area of the ellipse), which is a parameter reflecting the size of the process window, may also be additionally stored.

The above-described operations of determining DOF and process window are exemplary only, and are not intended to limit the scope of the present disclosure. In embodiments of the present disclosure, any suitable method may be used to determine DOF and process window. In addition, it can be understood that in the lithography imaging simulation, the surrounding environment of the layout pattern is taken into account, that is, the positional relationship between the layout pattern and adjacent patterns.

The lithography performance analysis sub-module 332 is used to determine the simulated values of other process parameters for the layout pattern. For example, the lithography performance analysis sub-module 332 can calculate ILS, MEEF, etc. at the measurement marks, and store corresponding simulation values. The lithography performance analysis sub-module 332 may use any existing or future developed method to determine the simulated values of these process parameters, and the scope of the present disclosure is not limited in this regard.

As will be described below with reference to an optimization algorithm, the CD of the mask pattern can be varied over a sampling range to determine multiple mask CDs. Through lithographic imaging simulation, the wafer CD under ideal conditions corresponding to each mask CD can be determined. Herein, the wafer CD under ideal conditions is referred to as "ideal wafer CD" for the purpose of illustration only without any limitation. Thereby, simulation values of a plurality of ideal wafer CDs and corresponding process parameters can be determined.

Utilization of Process Parameters

The simulated values of the process parameters obtained by the process window analysis sub-module 331 and the lithography performance analysis sub-module 332 can be utilized by the process parameter analysis sub-module 333 to determine the target CD for the layout pattern. Specifically, the process parameter analysis sub-module 333 may select a target CD for a layout pattern from a plurality of ideal wafer CDs based on a plurality of simulated values for understanding the respective process parameters of the wafer CDs.

In some embodiments, the process parameter analysis sub-module 333 can determine the target CD based on the imaging cost reflected by the process parameters. For example, the process parameter analysis sub-module 333 can determine the imaging cost of forming the corresponding wafer pattern based on the simulation value of the process parameter, the target value tar and the threshold value tol, and determine the CD of the wafer pattern with the lowest imaging cost as the target CD.

The imaging cost can be represented by a cost function. Cost functions are used to evaluate simulation or optimization results. As an example, the cost function corresponding to any process parameter can be calculated by:

weight _i ×(sim _i -tar _i ) ² f(k) Formula (1)

Among them, i represents the measurement mark, weight represents the weight of the process parameter, sim represents the simulation value of the process parameter, and f(k) represents the adjustment function.

8A and 8B illustrate examples of adjustment functions for determining imaging costs according to some embodiments of the present disclosure. The adjustment function 810 shown in FIG. 8A can be used for process parameters such as DOF and ILS. Specifically, when the simulation value is smaller than the threshold tol, the value f of the adjustment function is 10; when the simulation value is greater than or equal to the threshold tol and smaller than the target value tar, the value f of the adjustment function is 1; otherwise, f is 0. The adjustment function 820 shown in FIG. 8B can be used for process parameters such as MEEF. Specifically, when the simulation value is greater than the threshold tol, the value f of the adjustment function is 10; when the simulation value is greater than or equal to the target value tar and less than the threshold tol, the value f of the adjustment function is 1; otherwise, f is 0. The tuning function f(k) for an ideal wafer CD may be a constant function, for example a constant function with a value of 1.

In the case of considering multiple process parameters, the process parameter analysis sub-module 333 can calculate the imaging cost of each process parameter (for example, DOF, ILS, MEEF, ideal wafer CD, etc.), and then calculate these process parameters. The total cost of the parameter. The process parameter analysis sub-module 333 can then select the target CD for the layout pattern from these ideal wafer CDs based on the total costs respectively determined for the plurality of ideal wafers C.

In this embodiment, the advantages and disadvantages of the process parameters can be considered comprehensively by using the imaging cost, thereby helping to select the optimal target CD. The calculation and adjustment functions of the imaging cost described above are exemplary only, and are not intended to limit the scope of the present disclosure. In embodiments of the present disclosure, any suitable method may be used to calculate the imaging cost.

In addition, it should be noted that when the initial layout pattern meets the thresholds of process parameters such as DOF, ILS, and MEEF, it should try to avoid redefining the layout pattern. For this reason, judgment conditions can be added. For example, if the wafer CD obtained by the mask CD simulation is close to the initial target CD, and the simulated value of the considered process parameter is greater than its threshold (for example, the simulated value of DOF is greater than its threshold, the simulated value of ILS is greater than its threshold, If the simulated value of MEEF is less than its threshold), the total imaging cost can be set to 0.

Alternatively, in some embodiments, the process parameter analysis sub-module 333 may use simulated values of process parameters in other ways than the imaging cost to select the target CD. As an example, the target CD may be selected based on how close the simulated value of the process parameter is to the target value tar. For example, for the selected target CD, the simulated value of the process parameter corresponding to it is closest to the target value tar.

Examples of Optimization Algorithms

As mentioned briefly above, the CD of the mask pattern can be varied over a sampling range to determine multiple mask CDs. The sampling range may eg be +/- 40nm of the original target CD. A plurality of ideal wafer CDs corresponding to the plurality of mask CDs and simulation values of corresponding process parameters can be determined through lithography imaging simulation. Based on the simulated values of the process parameters, the final target CD can be determined from multiple ideal wafer CDs. Any suitable optimization algorithm may be used to vary the CD of the mask pattern over the sampling range.

In some embodiments, serial optimization algorithms may be employed. For example, the sampling interval can be set, and then samples are taken equidistantly at the sampling interval within the sampling range from the minimum mask CD to the maximum mask CD. The sampling interval can be set to a smaller value, or set according to the accuracy requirements of graphic redefinition, the computing power of the system 300, and the like. Subsequently, the mask CD of the sampling point is set as the sample value, and the operations described above about the process window analysis sub-module 331 and the lithography performance sub-module 332 are performed to determine the ideal wafer CD corresponding to the mask CD and simulated values of process parameters. For the mask CD of all sampling points, the above operation is repeated, and the value of the mask CD traverses all the sampling values in the sampling range.

After the traversal is completed, the process parameter analysis module 333 selects the target CD from the corresponding ideal wafer CDs based on the simulated values of the respective process parameters under all the sampled mask CDs. For example, in embodiments where imaging costs are calculated, the total imaging cost per mask CD may be calculated. Then, the mask CD corresponding to the lowest total imaging cost is determined. The simulated ideal wafer CD corresponding to the mask CD is determined as the target CD for the layout pattern.

In some embodiments, parallel optimization algorithms may be employed. In such an embodiment, multiple rounds of iterative sampling may be performed for the mask CD. Each iteration is assigned its own sampling range. In the first round of iteration, the initial number of parallel samples can be set, and then samples are equidistant within the initial sampling range according to the initial number of parallel samples. In this case, the corresponding sampling interval is related to the initial parallel sample number and can be a larger value compared to the sampling interval in the serial optimization algorithm. Set mask CD to these initial sample values respectively. The operations described above for the process window analysis sub-module 331 and the lithography performance sub-module 332 are performed in parallel (for example, by different computing cores) for different initial masks CD to determine the ideal mask CDs respectively corresponding to Simulation values of wafer CD and process parameters. These initial mask CDs are then sorted based on simulated values of process parameters, for example based on the value of the total imaging cost.

According to the ranking result, a predetermined number (for example, 3) of mask CDs that are ranked higher are selected. The selected predetermined number of masks CD will be used to determine the sampling range of the next iteration. Specifically, a new sampling sub-range may be determined within a certain range on the left and right of each of the selected predetermined number of masks CD. For example, +/- 6nm of each mask CD can be selected as a new sampling sub-range. These sampling subranges form the sampling range for the next iteration. Then, according to the number of parallel samples in the next iteration, equidistant sampling is carried out in each sampling sub-range. The operations described above with respect to the process window analysis sub-module 331 and the lithography performance sub-module 332 are performed in parallel for the sampled different mask CDs to determine the ideal wafer CDs corresponding to these mask CDs and the simulation of the process parameters value. Then, based on the simulated values of the process parameters, an integrated ranking is performed with the mask CDs in the first iteration. By analogy, multiple rounds of iterations are performed until the optimal ideal wafer CD is determined based on the simulation values of the process parameters, for example, the ideal wafer CD corresponding to the lowest imaging cost. This ideal wafer CD is determined as the target CD.

FIG. 9 shows a schematic diagram of sampling ranges in multiple rounds of iterations according to some embodiments of the present disclosure. In the example of FIG. 9 , iteration 1 has an initial sampling range 910 from minimum mask CD to maximum mask CD, and the initial number of parallel samples is seven. Correspondingly, in the first round of iterations, the operations described above with respect to the process window analysis submodule 331 and the lithography performance submodule 332 are performed in parallel for the seven initial masks CDs, so as to determine the seven initial masks CDs respectively Corresponding simulated values of ideal wafer CD and process parameters. These 7 initial mask CDs are then sorted based on the simulated values of the process parameters, for example based on the value of the total imaging cost.

Based on the sorting results, the mask CD corresponding to the sampling points 911, 912 and 913 is selected to determine the sampling range of the second iteration. For the second round of iteration, based on the mask CD corresponding to the sampling points 911 , 912 and 913 , the sampling sub-ranges 921 , 922 and 923 are respectively determined. The union of sampling sub-ranges 921, 922, 923 is the sampling range of the second iteration. In the second round of iterations, the number of parallel samples (2 in the example of FIG. 9 ) is sampled at equal intervals in each of the sampling sub-ranges 921 , 922 , 923 , thereby determining 6 masks CD. For these 6 mask CDs, perform the operations described above about the process window analysis submodule 331 and the lithography performance submodule 332 in parallel to determine the ideal wafer CD and process parameters corresponding to the 6 mask CDs. simulated value. Then, based on the simulated values of the process parameters, an integrated ranking was performed with the 7 mask CDs in the first iteration. By analogy, multiple rounds of iterations are performed until the optimal ideal wafer CD is determined based on the simulation values of the process parameters, for example, the ideal wafer CD corresponding to the lowest imaging cost. This ideal wafer CD is determined as the target CD.

It should be understood that the number of parallel samples and the number of mask CDs selected in each iteration shown in FIG. 9 is exemplary only and not intended to limit the scope of the present disclosure. In the embodiments of the present disclosure, these numbers can be set according to actual needs.

Serial optimization algorithms may be employed when the computing power of system 300 is insufficient. In the case that the calculation capability of the system 300 is sufficient, the calculation efficiency can be greatly improved by using a parallel optimization algorithm.

In addition, in the embodiment of the sampling parallel optimization algorithm, in each round of iteration, the above operations are performed for each layout pattern in the layout 301 . After each round of iteration, the size of the layout pattern can be set as the optimal CD determined in this round of iteration, that is, the layout pattern can be redefined as the optimal CD of this round of iteration. In this way, at the beginning of each iteration except the first iteration, the surrounding environment of the layout graphics is the environment after the previous round of redefinition. As the number of iterations increases, the degree of overall redefinition will become smaller and smaller until convergence. Therefore, the simulation accuracy of the parallel optimization algorithm is also higher than that of the serial optimization algorithm.

Example of redefine operation

Through the operation of the lithography simulation module 321 described above, a target CD can be determined for each layout pattern. The redefine module 322 sets the layout graph to have a target CD. Specifically, the redefinition module 321 can add an offset graphic corresponding to the target CD to the layout graphic, and the offset caused by the offset graphic can be positive or negative. The set of initial graphics and added offset graphics is the target graphics.

FIG. 10 shows a schematic diagram of a portion of a redefined layout according to some embodiments of the present disclosure. Layout area 1000 includes graphics 1010 , 1020 and 1030 . These graphics are divided into several layout graphics. By adding corresponding offset graphics to these layout graphics, the redefined graphics as shown in FIG. 10 are formed.

In an embodiment employing a serial optimization algorithm, the redefinition operation is performed after the target CD is determined based on all mask CDs within the sampling range. In an embodiment using a parallel optimization algorithm, in each iteration, the redefinition operation is performed based on the median value of the target CD determined in the current round (i.e., the value of the optimal ideal wafer CD determined in the current round) . In such an embodiment, after each round of iterative redefinition operation, it is necessary to process the measurement marks of the layout pattern so as to be aligned with the boundary of the layout pattern after redefinition.

Furthermore, in some embodiments, the layout may additionally be checked and/or repaired to determine the final redefined layout 303 . In such an embodiment, it is necessary to combine the operation of the lithography simulation module 321 with inspection and/or repair, and iteratively perform the final redefinition operation.

Example of checking and repairing

defect repair

There may be defects in the redefined layout, such as notch and jog. In some embodiments, these defects can be repaired to avoid negative impact on subsequent OPC operations. For example, the inspection and repair module 323 may detect defects in the redefined layout, and each defect may have a corresponding detection standard. Offset graphics can be added at detected defects so that the graphics at the defect are flush with the surrounding graphics.

FIG. 11A shows a schematic diagram of a repair notch 1110 according to some embodiments of the present disclosure. In the example of FIG. 11A , inspection and repair module 323 detects notch 1110 because width 1112 is less than or equal to the threshold width for the notch and height 1111 is less than or equal to the threshold height for the notch. An offset graphic 1115 is added at the notch 1110 so that the graphic at the notch 1110 is flush with the surrounding graphic. In this way, notch defects are repaired.

FIG. 11B shows a schematic diagram of repair steps 1120 according to some embodiments of the present disclosure. In the example of FIG. 11B , the check and repair module 323 detects a step 1120 because the height 1121 is less than or equal to the threshold height for the step. An offset graphic 1125 is added at the step 1120 so that the graphic at the step 1120 is flush with the surrounding graphics. In this way, the cut order defect is repaired.

Furthermore, the model-based lithography simulations described above were not performed for the features at the outer corners because their process window could not be directly assessed. Correspondingly, you can use a method similar to repairing defects to add offset graphics to the outer corners to make them flush with adjacent line graphics.

The deficiencies and their fixes described above are exemplary only and are not intended to limit the scope of the present disclosure. Corresponding repair methods can be adopted for different types of defects.

design rule check

Any layer of graphics in the layout needs to satisfy constraints or restrictions related to design rules. Although design rule checking (DRC) has been performed on the layout during layout design, the redefined layout may require further DRC, such as clearance checks between adjacent polygons, correlation checks between different layers, etc.

Figure 12 illustrates an example of design rule related constraints according to some embodiments of the present disclosure. The graph 1210 and the graph 1220 will be split into different masks, so a gap check needs to be performed on the gap 1201 between the graph 1210 and the graph 1220, for example, to determine whether it satisfies the gap constraints under different masks. The graph 1210 and the graph 1230 will be split into the same mask, so a gap check needs to be performed on the gap 1202 between the graph 1220 and the graph 1230, for example, to determine whether it satisfies the gap constraint under the same mask. In addition, it is necessary to perform a correlation check on the graph 1240 and the graph 1250 representing the via, for example, to determine whether the enclosure 1203 satisfies the constraints.

In some embodiments, DRC may be implemented as a constraint on redefinition operations. If the graphics redefined according to the selected target CD do not meet the constraints related to the design rules, then the target CD will be discarded. A sub-optimal wafer CD can be selected from multiple ideal wafer CDs as a target CD to redefine the layout pattern again.

As an example, in an embodiment using a parallel optimization algorithm, after each round of iterations, the layout pattern in the layout is redefined according to the intermediate value of the target CD determined in the current round. If the redefined layout graph passes DRC, it will not affect the direction of iterative optimization. If the DRC is not passed, the mask CD selected for this round is discarded, and the rest of the mask CDs will be reordered.

In some embodiments, DRC may be implemented as a supplement to the redefinition operation. In the redefinition operation, an offset pattern corresponding to the target CD may be selectively added to at least one of both sides of the layout pattern based on constraints related to design rules. For example, if adding an offset graphic to one side does not satisfy the constraints of the DRC, you can reduce the offset added to the graphic on that side and add a larger width offset graphic to the other side to ensure the offset The total amount meets the target CD.

In some embodiments, the DRC may be combined with simulated values of process parameters to determine the target CD. It is possible to determine how well the DRC constraints are satisfied given that the layout pattern is set to have a corresponding ideal wafer CD. The target CD is then selected based on the degree of satisfaction and the simulated values of the process parameters. For example, in embodiments where imaging costs are considered, a cost item related to DRC may be added to the total cost. The greater the degree of satisfaction, that is, the less the design rules are exceeded, the smaller the cost item; on the contrary, the smaller the degree of satisfaction, that is, the more the design rules are exceeded, the greater the cost item.

FIG. 13 illustrates an example of an inspected and repaired layout according to some embodiments of the present disclosure. Layout area 1300 includes graphics 1310 , 1320 and 1330 . As shown by the arrow 1301, the offset graphics are only added on the side of the graphic 1310 away from the graphic 1320, and no offset graphics are added to the part of the graphic 1320 adjacent to the graphic 1310. In this way, the redefined layout can pass the DRC.

Example operations of the different modules are described above with reference to FIGS. 3-13 . It should be understood that operations described with respect to different embodiments may be combined. For example, in some embodiments, parallel optimization algorithms can be employed, and DRC can be implemented as a complement to the redefinition operation. As another example, in some embodiments, serial optimization algorithms may be employed, and DRC may be implemented as a complement to the redefinition operation. As another example, in some embodiments, a parallel optimization algorithm may be employed, and the DRC may be combined with simulated values of process parameters.

EXAMPLE METHODS, APPARATUS AND APPARATUS

FIG. 14 shows a flowchart of an example method 1400 of redefining a layout graph according to some embodiments of the present disclosure. Method 1400 may be implemented by any suitable computing device or computing system. It should be understood that method 1400 may also include additional actions not shown and/or illustrated actions may be omitted. The scope of the present disclosure is not limited in this respect.

At block 1410, a plurality of mask patterns corresponding to layout patterns in the circuit layout are determined. Multiple mask patterns have different sizes. For example, a parallel optimization algorithm or a serial optimization algorithm may be used to determine multiple mask patterns by changing the mask CD within the sampling range.

In some embodiments, in order to determine a plurality of mask patterns, in each iteration of multiple rounds of iterations, by changing the size of the mask patterns within the sampling range for the round of iterations, the parameters of the plurality of mask patterns can be determined. Subset. In such an embodiment, the method 1400 may further include: in each iteration, determining an intermediate value for the target size based on a subset of the plurality of mask patterns; and setting the size of the layout pattern in the circuit layout to the intermediate value , for the next iteration. For example, parallel optimization algorithms may be employed.

In some embodiments, the method 1400 may further include: selecting a predetermined number of mask patterns from the first subset based on simulated values of process parameters corresponding to the first subset of the plurality of mask patterns, the first subset is determined in the first round of iterations; and based on the size of the predetermined number of mask patterns, determine the sampling range for the second round of iterations for determining the second of the plurality of mask patterns in the second round of iterations subset, the second iteration follows immediately after the first iteration. For example, the sampling sub-ranges 921 , 922 , and 923 may be determined based on the mask CDs corresponding to the sampling points 911 , 912 , and 913 , respectively. The union of sampling sub-ranges 921, 922, 923 is the sampling range of the second iteration.

At block 1420, the dimensions of the plurality of wafer patterns formed based on the plurality of mask patterns are determined by lithographic imaging simulation. For example, using a lithographic imaging model, a plurality of ideal wafer CDs corresponding to a plurality of mask CDs can be determined. At block 1430, for each wafer pattern of the plurality of wafer patterns, simulated values for process parameters used to assess process window or imaging quality are determined. For example, simulated values of parameters such as DOF, ILS, and MEEF can be determined.

At block 1440, target dimensions are determined from the dimensions of the plurality of wafer patterns based at least on the simulated values of the process parameters. For example, the determined target CD may optimize process parameters.

In some embodiments, imaging cost may be considered in order to determine target size. The imaging cost for forming the corresponding wafer pattern can be determined based on thresholds, target values and simulated values for the process parameters. The size of the wafer pattern with the lowest imaging cost can be determined as the target size. The ideal wafer CD with the lowest total cost function can be determined as the target CD.

In some embodiments, DRC may be combined with process parameters in order to determine target dimensions. For each of the plurality of wafer patterns, a degree to which the constraint is satisfied by the layout pattern set to have the size of the wafer pattern may be determined. Constraints relate to design rules for layout patterns. The target size may be determined from the sizes of the plurality of wafer patterns based on simulated values and satisfaction levels of the process parameters. For example, a cost term related to satisfaction can be added to the total cost function.

At block 1450, layout patterns in the circuit layout are set to have target dimensions. For example, an offset graphic corresponding to the target size can be added to the layout graphic.

In some embodiments, DRC may be implemented as a supplement to the redefinition operation. For example, constraints related to design rules for the layout pattern may be obtained; and based on the constraints, selectively adding an offset pattern corresponding to the target size to at least one of the first side or the second side of the layout pattern. The second side is opposite the first side.

In some embodiments, defects may also be repaired. The method 1400 may further include: detecting a predetermined type of defect in the circuit layout in response to the layout pattern being set to have a target size; and adding an offset pattern at the detected defect such that the pattern at the detected defect is consistent with the The surrounding graphics are flush.

In some embodiments, in order to determine the target size for each layout pattern, the original pattern in the layout may be segmented. The method 1400 may also include: identifying a type of pattern in the circuit layout; and based on the identified type and the relative position of the pattern to surrounding patterns, dividing the pattern into a plurality of layout patterns including the layout pattern.

FIG. 15 shows a schematic block diagram of an apparatus 1500 for redefining layout graphics according to some embodiments of the present disclosure. Apparatus 1500 may be used to implement or be included in a computing device or computing system implementing method 1400 . As shown in FIG. 15 , the apparatus 1500 includes a mask pattern determination unit 1510 configured to determine a plurality of mask patterns corresponding to layout patterns in the circuit layout, the plurality of mask patterns having different sizes. The apparatus 1500 further includes a wafer pattern determination unit 1520 configured to determine the dimensions of the plurality of wafer patterns formed based on the plurality of mask patterns through lithographic imaging simulation. The apparatus 1500 further includes a process parameter determining unit 1530 configured to determine, for each of the plurality of wafer patterns, simulated values of process parameters for evaluating process window or imaging quality. The apparatus 1500 also includes a target size determining unit 1540 configured to determine the target size from the sizes of the plurality of wafer patterns based at least on the simulated values of the process parameters. The apparatus 1500 also includes a redefinition unit 1550 configured to set the layout pattern in the circuit layout to have a target size

In some embodiments, the mask pattern determination unit 1510 is further configured to: in each iteration of multiple rounds of iterations, determine a plurality of masks by changing the size of the mask pattern within the sampling range for the iteration A subset of graphics, and wherein the target size determination unit 1540 is further configured to determine an intermediate value for the target size based on a subset of a plurality of mask graphics in each iteration; and the redefinition unit 1550 is further configured to circuit The size of the layout graphics in the layout is set to an intermediate value for the next iteration.

In some embodiments, the apparatus 1500 further includes: a mask pattern selection unit configured to select a predetermined number of mask patterns from the first subset based on simulated values of process parameters corresponding to the first subset of mask patterns. The mask pattern, the first subset is determined in the first round of iteration; and the sampling range determination unit is configured to determine the sampling range for the second round of iteration based on the size of the predetermined number of mask patterns for A second subset of the plurality of mask patterns is determined in a second iteration immediately following the first iteration.

In some embodiments, the redefinition unit 1550 is further configured to: acquire constraints related to design rules for the layout pattern; and selectively add to at least one of the first side or the second side of the layout pattern based on constraints Add an offset graphic corresponding to the target size, with the second side opposite the first.

In some embodiments, the target size determination unit 1540 is further configured to: for each wafer pattern among the plurality of wafer patterns, determine how well the layout pattern set to have the size of the wafer pattern satisfies the constraint, the constraint Related to design rules for layout patterns; and determining target dimensions from dimensions of multiple wafer patterns based on simulated values and satisfaction levels of process parameters.

In some embodiments, the target size determining unit 1540 is further configured to: determine the imaging cost of forming the corresponding wafer pattern based on the threshold value, the target value and the simulation value for the process parameter; and determine the imaging cost of the wafer pattern with the lowest imaging cost The size is determined to be the target size.

In some embodiments, the apparatus 1500 further includes: a defect detection unit configured to detect a predetermined type of defect in the circuit layout in response to the layout pattern being set to have a target size; and a defect repair unit configured to detect Add offset graphics to detected defects so that the detected graphics are flush with the surrounding graphics.

In some embodiments, the apparatus 1500 further includes: a pattern classification unit configured to identify the type of the pattern in the circuit layout; and a pattern segmentation unit configured to, based on the identified type and the relative position of the pattern and the surrounding pattern, The pattern is divided into a plurality of layout patterns including the layout pattern.

Fig. 16 shows a schematic block diagram of a device 1600 capable of implementing multiple embodiments of the present application. The device 1600 can be used to implement the method for redefining layout graphics according to the present disclosure. As shown, the device 1600 includes a computing unit 1601 that can execute according to computer program instructions stored in a read-only memory (ROM) 1602 or loaded from a storage unit 1607 into RAM 1603 and/or ROM 1602 Various appropriate actions and treatments. In the RAM 1603 and/or the ROM 1602, various programs and data necessary for the operation of the device 1600 can also be stored. The computing unit 1601 and the RAM 1603 and/or ROM 1602 are connected to each other via a bus 1604. An input/output (I/O) interface 1605 is also connected to the bus 1604 .

Multiple components in the device 1600 are connected to the I/O interface 1605, including: an input unit 1606, such as a keyboard, a mouse, etc.; an output unit 1607, such as various types of displays, speakers, etc.; a storage unit 1608, such as a magnetic disk, an optical disk, etc. ; and a communication unit 1609, such as a network card, a modem, a wireless communication transceiver, and the like. The communication unit 1609 allows the device 1600 to exchange information/data with other devices through a computer network such as the Internet and/or various telecommunication networks.

The computing unit 1601 may be various general-purpose and/or special-purpose processing components with processing and computing capabilities. Some examples of computing units 1601 include, but are not limited to, central processing units (CPUs), graphics processing units (GPUs), various dedicated artificial intelligence (AI) computing chips, various computing units that run machine learning model algorithms, digital signal processing processor (DSP), and any suitable processor, controller, microcontroller, etc. The calculation unit 1601 executes various methods and processes described above, such as the method 1400 . For example, in some embodiments, method 1400 may be implemented as a computer software program tangibly embodied on a machine-readable medium, such as storage unit 1608 . In some embodiments, part or all of the computer program may be loaded and/or installed on the device 1600 via the RAM 1603 and/or the ROM 1602 and/or the communication unit 1609. When a computer program is loaded into RAM 1603 and/or ROM 1602 and executed by computing unit 1601, one or more steps of method 1400 described above may be performed. Alternatively, in other embodiments, the computing unit 1601 may be configured to execute the method 1400 in any other suitable manner (for example, by means of firmware).

Program codes for implementing the methods of the present application may be written in any combination of one or more programming languages. These program codes may be provided to a processor or controller of a general-purpose computer, a special purpose computer, or other programmable data processing devices, so that the program codes, when executed by the processor or controller, make the functions/functions specified in the flow diagrams and/or block diagrams Action is implemented. The program code may execute entirely on the machine, partly on the machine, as a stand-alone software package partly on the machine and partly on a remote machine or entirely on the remote machine or server.

In the context of the present application, a machine-readable medium may be a tangible medium that may contain or store a program for use by or in conjunction with an instruction execution system, apparatus, or device. A machine-readable medium may be a machine-readable signal medium or a machine-readable storage medium. A machine-readable medium may include, but is not limited to, electronic, magnetic, optical, electromagnetic, infrared, or semiconductor systems, apparatus, or devices, or any suitable combination of the foregoing. More specific examples of machine-readable storage media would include one or more wire-based electrical connections, portable computer discs, hard drives, random access memory (RAM), read only memory (ROM), erasable programmable read only memory (EPROM or flash memory), optical fiber, compact disk read only memory (CD-ROM), optical storage, magnetic storage, or any suitable combination of the foregoing.

In addition, while operations are depicted in a particular order, this should be understood to require that such operations be performed in the particular order shown, or in sequential order, or that all illustrated operations should be performed to achieve desirable results. Under certain circumstances, multitasking and parallel processing may be advantageous. Likewise, while the above discussion contains several specific implementation details, these should not be construed as limitations on the scope of the application. Certain features that are described in the context of separate embodiments can also be implemented in combination in a single implementation. Conversely, various features that are described in the context of a single implementation can also be implemented in multiple implementations separately or in any suitable subcombination.

Although the subject matter has been described in language specific to structural features and/or methodological acts, it is to be understood that the subject matter defined in the appended claims is not necessarily limited to the specific features or acts described above. Rather, the specific features and acts described above are merely example forms of implementing the claims.

Claims (19)

1. A method for redefining layout graphics, characterized in that the method comprises:

   determining a plurality of mask patterns corresponding to layout patterns in the circuit layout, where the plurality of mask patterns have different sizes;

   determining the size of a plurality of wafer patterns formed on the wafer based on the plurality of mask patterns by lithography imaging simulation;

   determining, for each wafer pattern of the plurality of wafer patterns, simulated values of process parameters used to assess process window or imaging quality;

   determining target dimensions from dimensions of the plurality of wafer patterns based at least on simulated values of the process parameters; and

   The layout pattern in the circuit layout is set to have the target size.
2. The method according to claim 1, wherein determining the plurality of mask patterns comprises:

   In each iteration of the plurality of iterations, determining a subset of the plurality of mask patterns by varying the size of the mask patterns within a sampling range for the iteration,

   And the method also includes:

   In each iteration, determining an intermediate value for the target size based on the subset of the plurality of mask patterns; and

   and setting the size of the layout pattern in the circuit layout as the intermediate value for the next round of iteration.
3. The method according to claim 2, further comprising:

   selecting a predetermined number of mask patterns from a first subset of the plurality of mask patterns based on simulated values of the process parameters corresponding to the first subset of the plurality of mask patterns, the first subset being in the first determined in round iterations; and

   Based on the size of the predetermined number of mask patterns, determining a sampling range for a second round of iterations for determining a second subset of the plurality of mask patterns in the second round of iterations, the A second round of iterations follows said first round of iterations.
4. The method according to any one of claims 1 to 3, wherein setting the layout pattern in the circuit layout to have the target size comprises:

   obtaining constraints related to design rules for the layout pattern; and

   selectively adding an offset pattern corresponding to the target size to at least one of a first side or a second side of the layout pattern, the second side being opposite to the first side, based on the constraint .
5. The method according to any one of claims 1 to 4, wherein determining the target size from the sizes of the plurality of wafer patterns based at least on the simulated value of the process parameter comprises:

   determining, for each wafer pattern of the plurality of wafer patterns, how well the layout pattern configured to have the dimensions of the wafer pattern satisfies constraints that are consistent with a design for the layout pattern rules; and

   The target size is determined from the sizes of the plurality of wafer patterns based on the simulation value of the process parameter and the degree of satisfaction.
6. The method according to any one of claims 1 to 5, wherein determining the target size from the sizes of the plurality of wafer patterns based at least on the simulated value of the process parameter comprises:

   determining an imaging cost for forming a corresponding wafer pattern based on the threshold value for the process parameter, the target value, and the simulated value; and

   The size of the wafer pattern with the lowest imaging cost is determined as the target size.
7. The method according to any one of claims 1 to 6, further comprising:

   detecting a predetermined type of defect in the circuit layout in response to the layout pattern being set to have the target size; and

   Adding an offset pattern at the detected defect to make the pattern at the detected defect flush with surrounding patterns.
8. The method according to any one of claims 1 to 7, further comprising:

   identifying the type of pattern in the circuit layout; and

   The graphic is divided into a plurality of layout graphics including the layout graphic based on the identified type and the relative position of the graphic to surrounding graphics.
9. A device for redefining layout graphics, characterized in that the device includes:

   a mask pattern determining unit configured to determine a plurality of mask patterns corresponding to layout patterns in the circuit layout, the plurality of mask patterns having different sizes;

   a wafer pattern determination unit configured to determine the size of a plurality of wafer patterns formed on the wafer based on the plurality of mask patterns through lithography imaging simulation;

   a process parameter determination unit configured to determine, for each of the plurality of wafer patterns, simulated values of process parameters for evaluating a process window or imaging quality;

   a target size determination unit configured to determine a target size from the sizes of the plurality of wafer patterns based at least on simulated values of the process parameters; and

   A redefinition unit configured to set the layout pattern in the circuit layout to have the target size.
10. The device according to claim 9, wherein the mask pattern determination unit is further configured to:

    In each iteration of the plurality of iterations, determining a subset of the plurality of mask patterns by varying the size of the mask patterns within a sampling range for the iteration,

    And wherein the target size determining unit is further configured to determine an intermediate value for the target size based on the subset of the plurality of mask patterns in each iteration; and

    The redefinition unit is further configured to set the size of the layout pattern in the circuit layout to the intermediate value for a next iteration.
11. The device according to claim 10, further comprising:

    a mask pattern selection unit configured to select a predetermined number of mask patterns from the first subset of the plurality of mask patterns based on simulated values of the process parameters corresponding to the first subset of mask patterns, said first subset is determined in a first iteration; and

    A sampling range determination unit configured to determine a sampling range for a second round of iterations based on the size of the predetermined number of mask patterns, for determining the plurality of mask patterns in the second round of iterations The second subset of , the second round of iterations is immediately after the first round of iterations.
12. The device according to any one of claims 9 to 11, wherein the redefinition unit is further configured to:

    obtaining constraints related to design rules for the layout pattern; and

    selectively adding an offset pattern corresponding to the target size to at least one of a first side or a second side of the layout pattern, the second side being opposite to the first side, based on the constraint .
13. The device according to any one of claims 9 to 12, wherein the target size determination unit is further configured to:

    determining, for each wafer pattern of the plurality of wafer patterns, how well the layout pattern configured to have the dimensions of the wafer pattern satisfies constraints that are consistent with a design for the layout pattern rules; and

    The target size is determined from the sizes of the plurality of wafer patterns based on the simulation value of the process parameter and the degree of satisfaction.
14. The device according to any one of claims 9 to 13, wherein the target size determining unit is further configured to:

    determining an imaging cost for forming a corresponding wafer pattern based on the threshold value for the process parameter, the target value, and the simulated value; and

    The size of the wafer pattern with the lowest imaging cost is determined as the target size.
15. The device according to any one of claims 9 to 14, wherein the device further comprises:

    a defect detection unit configured to detect a predetermined type of defect in the circuit layout in response to the layout pattern being set to have the target size; and

    A defect repairing unit configured to add an offset pattern to the detected defect so that the detected pattern at the defect is flush with surrounding patterns.
16. The device according to any one of claims 9 to 15, wherein the device further comprises:

    a pattern classification unit configured to identify a type of pattern in the circuit layout; and

    A graphic segmentation unit configured to divide the graphic into a plurality of layout graphics including the layout graphic based on the identified type and the relative position of the graphic to surrounding graphics.
17. An electronic device, characterized in that it comprises:

    at least one processor;

    at least one memory coupled to the at least one processor and storing instructions for execution by the at least one processor that, when executed by the at least one processor, cause the The electronic device executes the method according to any one of claims 1-8.
18. A computer-readable storage medium, characterized in that a computer program is stored thereon, and when the program is executed by a processor, the method according to any one of claims 1-8 is realized.
19. A computer program product, characterized by comprising computer-executable instructions, wherein the computer-executable instructions implement the method according to any one of claims 1-8 when executed by a processor.

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