TWI466171B - Method of selecting subset of patterns, computer program product for performing thereto and method of performing source mask optimization - Google Patents

Description

Method for selecting a subset of patterns, computer program product for performing the method, and method for performing optimization of light source mask

The present invention relates to lithography apparatus and programs, and more particularly to methods of selecting a subset of patterns for use in light source and mask optimization.

The lithography apparatus can be used, for example, in the manufacture of integrated circuits (ICs). In this case, the mask may contain a circuit pattern corresponding to the individual layers of the IC, and the pattern may be imaged onto the target portion of the substrate (the wafer) to which the radiation-sensitive material (resist) layer has been coated. (for example, containing one or more grains). In general, a single wafer will contain the entire network of adjacent target portions that are sequentially irradiated one at a time via the projection system. In one type of lithographic projection apparatus, each target portion is irradiated by exposing the entire mask pattern to a target portion at a time; this device is commonly referred to as a wafer stepper. In an alternative device (commonly referred to as a step-and-scan device), the mask pattern under the projected beam is progressively scanned parallel or anti-parallel in this direction by a predetermined reference direction ("scan" direction). The substrate stage is scanned synchronously to irradiate each target portion. In general, because the projection system will have an amplification factor of M (typically <1), the velocity V at which the substrate stage is scanned will be a factor M times the speed at which the mask is scanned. Further information regarding the lithographic devices described herein can be gathered, for example, from U.S. Patent No. 6,046,792, incorporated herein by reference.

In a fabrication process using a lithographic projection apparatus, the mask pattern is imaged onto a substrate that is at least partially covered by a layer of radiation-sensitive material (resist). Prior to this imaging step, the substrate can be subjected to various procedures such as topping, resist coating, and soft baking. After exposure, the substrate can be subjected to other procedures, such as post-exposure bake (PEB), development, hard bake, and measurement/detection of the imaged features. This program array is used as the basis for patterning individual layers of a device (eg, an IC). This patterned layer can then be subjected to various procedures such as etching, ion implantation (doping), metallization, oxidation, chemical mechanical polishing, and the like, all of which are intended to complete individual layers. If several layers are required, the entire program or its variants will have to be repeated for each new layer. Finally, an array of devices will be present on the substrate (wafer). The devices are then separated from one another by techniques such as splitting or sawing, whereby individual devices can be mounted on a carrier, attached to a pin, and the like.

For the sake of simplicity, the projection system may hereinafter be referred to as a "lens"; however, this term should be interpreted broadly to encompass various types of projection systems including, for example, refractive optical instruments, reflective optical instruments, and catadioptric systems. . The radiation system may also include components for operating, controlling, or controlling the projection of the radiation beam in accordance with any of these types of designs, and such components may also be referred to collectively or individually as "lenses" hereinafter. . Additionally, the lithography apparatus can be of the type having two or more substrate stages (and/or two or more mask stages). In such "multi-stage" devices, additional stations may be used in parallel, or preliminary steps may be performed on one or more stations while one or more other stations are used for exposure. For example, a dual stage lithography apparatus is described in U.S. Patent No. 5,969,441, incorporated herein by reference.

The photolithographic mask referred to above includes a geometric pattern corresponding to the circuit components to be integrated onto the germanium wafer. A CAD (Computer Aided Design) program is used to create a pattern for forming such masks, a procedure commonly referred to as EDA (Electronic Design Automation). Most CAD programs follow a predetermined set of design rules to form a functional mask. These rules are set by processing and design constraints. For example, design rules define the spatial tolerance between circuit devices (such as gates, capacitors, etc.) or interconnect lines to ensure that circuit devices or lines do not interact with each other in a bad manner. Design rule limits are often referred to as "critical dimensions" (CD). The critical dimension of a circuit can be defined as the minimum width of a line or hole, or the minimum space between two lines or two holes. Therefore, the CD determines the total size and density of the designed circuit. Of course, one of the goals in the fabrication of integrated circuits is to faithfully reproduce the original circuit design (via the mask) on the wafer.

As mentioned, lithography is a central step in the fabrication of semiconductor integrated circuits in which the patterns formed on the semiconductor wafer substrate define functional elements of the semiconductor device, such as microprocessors, memory chips, and the like. Similar lithography technology is also used in the formation of flat panel displays, microelectromechanical systems (MEMS) and other devices.

As semiconductor manufacturing processes continue to advance, the size of circuit components has steadily shrunk, and the amount of functional components (such as transistors) per device has steadily increased over decades, often following what is called "Moore's Law." (Moore's law) trend. In the current state of the art, a critical layer of a front edge device is fabricated using an optical lithography projection system called a scanner that projects the mask image onto the substrate using illumination from a deep ultraviolet laser source. Thereby forming individual circuit features having dimensions sufficiently below 100 nanometers (i.e., less than half the wavelength of the projected light).

This procedure, in which features having dimensions smaller than the traditional resolution limits of optical projection systems, is commonly referred to as low k ₁ lithography, which is based on the resolution formula CD = k ₁ × λ / NA, where λ is used The wavelength of the radiation (currently 248 nm or 193 nm in most cases), NA is the numerical aperture of the projection optics, CD is the "critical dimension" (usually the smallest feature size printed), and k ₁ Is an empirical resolution factor. Generally, k ₁ is smaller, it becomes more difficult as a pattern reproduced on the wafer: a pattern similar to the shape and size of the plan by the circuit designer, in order to achieve particular electrical functionality and performance. To overcome these difficulties, complex fine-tuning steps are applied to the projection system as well as the mask design. For example, such steps include, but are not limited to, optimization of NA and optical coherence settings, custom lighting schemes, use of phase shift masks, optical proximity correction in mask layouts, or generally defined as " Other methods of Resolution Enhancement Technology (RET).

As an important example, optical proximity correction (OPC, sometimes referred to as "optical and process correction") addresses the fact that the final size and placement of printed features on a wafer will not only be It is a function of the size and placement of the corresponding features on the mask. It should be noted that the terms "mask" and "proportional mask" are used interchangeably herein. For small feature sizes and high feature densities that exist on typical circuit designs, the location of a particular edge of a given feature will be affected to some extent by the presence or absence of other adjacent features. These proximity effects result from a small amount of light coupled from one feature to another. Similarly, the proximity effect can result from diffusion and other chemical effects during post-exposure bake (PEB), resist development, and etching, which are typically followed by lithography.

In order to ensure that features are generated on a semiconductor substrate according to the requirements of a given target circuit design, complex numerical models are needed to predict the proximity effect, and correction or pre-distortion needs to be applied to the mask before successful fabrication of the high-end device becomes possible. The design of the hood. The paper "Full-Chip Lithography Simulation and Design Analysis-How OPC Is Changing IC Design" (C. Spence, Proc. SPIE, Vol. 5751, pp. 1-14 (2005)) provides the current "model-based" ( A review of the optical proximity correction procedure for model-based. In a typical high-end design, almost every feature edge requires some modification in order to achieve a printed pattern that is sufficiently close to the target design. Such modifications may include shifting or offsetting of edge positions or line widths and the application of "auxiliary" features, which are not intended to print themselves, but will affect the attributes of the associated primary features.

Applying model-based OPC to a target design would require an excellent program model and considerable computing resources given the millions of features that are typically present in a wafer design. However, the application of OPC is usually not "exact science", but an empirical iterative process, which does not always resolve all possible weaknesses in a layout. Therefore, it is necessary to verify the post-OPC design by design detection (ie, intensive full-wafer simulation using a calibrated numerical program model) (ie, apply all pattern modifications by OPC and any other resolution enhancement techniques (RET)). Subsequent mask layout) to minimize the possibility of building the design into the fabrication of the mask set. This situation is driven by the huge cost of making high-end mask sets that operate over millions of dollars; and by making real masks, by redoing or repairing actual masks The effect of a turn-around time.

Both OPC and full-film RET verification can be based on numerical modeling systems and methods, such as, for example, U.S. Patent No. 7,003,758 and Y. Cao et al. entitled "Optimized Hardware and Software For Fast, Full Chip Simulation" (Proc . SPIE, Vol. 5754, 405 (2005)).

In addition to performing the aforementioned mask adjustments (eg, OPC) in an effort to optimize imaging results, it is also possible to optimize the illumination scheme for use in imaging procedures in conjunction with mask optimization or individually to improve Total lithography fidelity. Since the 1990s, many off-axis sources, such as toroids, quadrupoles, and dipoles, have been introduced and have provided more freedom to OPC designs, thereby improving imaging results. As we know, off-axis illumination is a proven way to resolve the fine structure (ie, target features) contained in the mask. However, off-axis illuminators typically provide less light intensity to aerial imagery (AI) than conventional illuminators. Therefore, it has become necessary to attempt to optimize the illuminator to achieve an optimal balance between finer resolution and reduced light intensity.

Many prior art illumination optimization methods are known to us. For example, in the paper entitled "Optimum Mask and Source Patterns to Print A Given Shape" by Rosenbluth et al. (Journal of Microlithography, Microfabrication, Microsystems 1 (1), pp. 13-20 (2002)), The light source is divided into regions, each of which corresponds to a particular region of the pupil spectrum. Next, it is assumed that the light source distribution is uniform in each light source region, and the brightness of each region is optimized for a process window. However, the uniformity of the distribution of the light source in each of the light source regions is not always valid, and as a result, the effectiveness of the method is lost. In another example described in Granik's paper entitled "Source Optimization for Image Fidelity and Throughput" (Journal of Microlithography, Microfabrication, Microsystems 3(4), pp. 509-522 (2004)), a number of reviews are reviewed. Existing light source optimization methods, and a method based on illuminator pixels, which converts the light source optimization problem into a series of non-negative least squares optimizations. Although these methods have demonstrated some success, they often require multiple complex iterations to converge. In addition, it may be difficult to determine the appropriate/optimal value of some additional parameters (such as gamma in Granik's method), which stipulates between optimizing the smoothness requirements of the source for the wafer image fidelity and the source. Choose.

For low-k1 photolithography, optimization of both the source and the mask (i.e., source and mask optimization or SMO) is required to ensure a viable program window for printing critical patterns. Existing algorithms (eg, Socha et al., Proc. SPIE, Vol. 5853, p. 180, 2005) typically discretize illumination into independent source points and discretize masks into diffraction orders in the spatial frequency domain, and are based on The cost function is formulated separately, such as the procedural window metric of the exposure latitude, which can be predicted from the source point intensity and the mask diffraction level by the optical imaging model. Next, standard optimization techniques are used to minimize the objective function.

These conventional SMO techniques are computationally expensive (especially for complex designs). Therefore, it is generally only practical to perform light source optimization for simple repetitive designs, such as Flash memory cells, DRAM devices, or SRAM cells (Flash, DRAM, and SRAM) for logic device memory design. At the same time, full wafers include other more complex designs such as logic and gates. Therefore, because SMO source optimization is based only on a limited small area of a particular design, it is difficult to ensure that the source will be suitable for designs that are not included in the SMO program. Therefore, there is still a need for a technique that optimizes the source of light for representing multiple design clips of all complex design layouts in a full wafer within a practical runtime amount.

The present invention relates to lithography apparatus and programs, and more particularly to tools for optimizing illumination sources and masks used in lithography apparatus and programs. According to a particular aspect, the present invention achieves coverage of the design or even achieves a full wafer coverage by intelligently selecting a subset of patterns from the full design, while reducing computational cost, wherein the design or one of the designs modifies the group The state is imaged onto a substrate via a lithography process. For example, the selected subset can be used in light source and mask optimization. For example, optimization can be performed only on this selected subset of patterns to obtain an optimized source. For example, the optimized light source can then be used to optimize the mask for the full wafer (eg, using OPC and manufacturability verification), or the optimized pattern can be masked. The cover is used directly in this design so that the OPC is only applied to the remainder of the design with the optimized source. In a repetitive method, the program window performance results of the mask optimized using the subset are compared to the program window performance results of the mask optimized using the full wafer. If the results are comparable to a conventional full-wafer SMO, then the process ends, otherwise, various methods for repeatedly converge to successful results are provided.

In promoting such aspects and other aspects, a method of selecting a subset of patterns associated with a design includes identifying, from the design, a set of patterns associated with a predefined representation of the design; Performing grouping and/or ranking; defining a threshold associated with the grouping and/or ranking; and selecting the subset of patterns from the set of patterns, wherein the subset includes from the threshold above or below the threshold The pattern of the pattern collection. By selecting the subset of patterns according to the method, the selected subset of patterns constitutes one of the designs resembling a predefined representation as the set of patterns. For example, this predefined representation of the design can be a diffraction order produced by the patterns of the design. These patterns can then be grouped. In the present example, the grouping may be based on a diffraction order distribution of the patterns, for example, a geometric correlation between each of the patterns may be calculated, and a classification method may be performed to group the most similar patterns in together. However, grouping according to another predefined representation of the design may also be possible. Selecting at least one pattern from each of the groups (eg, from each of the groups of diffraction stages) ensures that the design (eg, the diffraction level distribution) of the selected pattern subset It generally represents the representation of the design (such as the diffraction order distribution) that substantially corresponds to the design or the full wafer. When the pattern subset is used to perform the source and mask optimization, the optimization procedure considers the predefined representation of the design (in this case, the diffraction order distribution of the full wafer) All aspects of this full wafer design are indicated in . Alternatively, for example, the step of selecting a subset of patterns may select at least one pattern from the group of diffraction levels including the program window restriction pattern. In this embodiment, the source and mask optimization can, for example, be primarily focused on improving the imaging characteristics of the program window confinement structure. Alternatively, or alternatively, the step of selecting a subset of patterns may select at least one pattern from each of the identified sets of diffraction stages. After optimizing the source and mask using the subset of patterns, an additional design optimization or full wafer optimization is preferably performed using a source that is self-using the source of the pattern subset And the mask is optimized to be produced. Therefore, the full wafer is optimized.

The subset of patterns associated with the design may include patterns that are manually or automatically extracted from the design, or may include a particular pattern provided by, for example, the designer of the design along with the design. These particular patterns (usually also indicated as clips) are separate patterns associated with the design, in that the clips represent portions of the design: for such portions, special attention may be required, or such portions may be used The most difficult structure of the lithography program. A design or design layout (typically containing a layout in a standard digital format such as OASIS, GDSII, etc.) (for example, a lithography program will be optimized for the design or design layout) may include a memory pattern , test patterns and logic patterns. The layout is designed from this point on, identifying the initial larger pattern (usually also indicated as a clip) collection. Typically, a set of clips is extracted or provided along with the design layout. This clip collection represents a complex pattern in the design layout (a design can contain about 50 to 1000 clips, but any number of clips can be provided or extracted). Those skilled in the art will appreciate that such patterns or clips represent a small portion of the design (i.e., circuitry, units or patterns) and, in particular, such clips typically represent a small portion: for such small portions, Specific attention and / or verification.

In an embodiment of the invention, the identifying step includes identifying a clip or set of patterns associated with the design. In an embodiment of the invention, the identifying step includes automatically identifying a pattern from the design to form at least a portion of the set of patterns. This identification of the set of patterns can be automated, as the representations can be used during the recognition process to identify the patterns of the set of patterns.

In one embodiment of the invention, the step of selecting the subset of patterns includes selecting a clip from the set of patterns for a set of clips. The subset of patterns contains the selected clips. The step of selecting the subset of patterns can also include manually extracting the pattern from the design. In this case, the subset of patterns includes the manually extracted patterns. The step of selecting the subset of patterns can also include automatically extracting the pattern from the design. In this particular case, the subset of patterns includes the automatically extracted patterns. Due to the fact that there is a threshold in the selection method, the selection step can be performed by instructing a computer program product to automatically extract all of the patterns following the threshold from the set of patterns to produce the subset. For example, the threshold can be defined by a user. Thus, the entire method from a design selection pattern can be automated into an extraction algorithm that automatically extracts the pattern subset from a design. This situation is an important benefit when the source and mask optimization procedures are to be performed in a mass production environment where the variation in subset selection will be limited to improve the predictability of the optimization step. Sex, and will limit the time required to select those subsets to improve the speed at which the source and mask are optimized.

In an alternate embodiment, the predefined representation of the design includes a different pattern type (such as a gate or logic pattern) or a pattern having a particular orientation. For example, a set of patterns identified using this representation of the design can then be grouped according to spacing. In an alternate embodiment, the predefined representation of the design includes a level of complexity of the patterns in the design. In an alternate embodiment, the predefined representation includes a pattern that requires particular attention and/or verification during lithography, such as a memory unit. In another alternative embodiment, the predefined representation includes a pattern having a predefined program window performance. A definition group in the set of patterns can be selected such that a pattern subset is selected from one of the patterns of each of the groups associated with the program window performance, the pattern subset and the full wafer program window The comparison has a substantially similar program window. Thus, by performing the illumination and mask optimization to optimize the program window of the subset of patterns, the program window of the full wafer is also substantially optimized. In a further alternative embodiment, the predefined representation of the design includes sensitivity to one of the program parameter changes to the pattern. Selecting a pattern having a particular sensitivity to one of the particular program parameters as a subset for the source and mask optimization results in the source and mask optimization program having similar sensitivities to these particular program parameters, in which case This optimization program is allowed, for example, to reduce the program sensitivity of these particular program parameters.

In an additional embodiment of the invention, the subset of patterns includes hotspots that form a pattern from the set of patterns that limits the performance of the program window of the design. To identify the hotspots, a numerical modeling approach can be used to model the imaging performance of the patterns of the set of patterns for identifying such patterns that limit the performance of the program window of the design.

In one embodiment of the invention, the grouping and/or ranking of the set of patterns is performed in accordance with a parameter associated with the predefined representation of the design. For example, the parameter can be a user defined value or can be a program window parameter such as exposure latitude and depth of focus. In one embodiment of the invention, the grouping and/or ranking of the set of patterns is performed in accordance with a function associated with the predefined representation of the design. For example, the function can be a severity score function, including, for example, an edge placement error and a mask error enhancement function value to determine the deviation of the simulated contour from the target (EPE) and the masking Mask Manufacturing Error Sensitivity (MEEF). In one embodiment of the invention, the grouping and/or ranking of the set of patterns is performed in accordance with a rule associated with the predefined representation of the design. In rule-based grouping and/or ranking, the grouping may occur according to user-defined rules, such as line/space structures (eg, based on a pattern of groups of predefined W/S intervals, a particular W/S combination has Width/interval above the priority of other W/S combinations, or pattern type (eg, pattern grouped by 1D line/space, line pair end pattern, end-to-end pattern, elbow pattern, or H-shaped pattern) The specific pattern type has priority over other pattern types).

To select the subset of patterns from the set of patterns, a threshold is used. The selected patterns can be patterns above or below the threshold and can even be patterns at the threshold. In an embodiment of the invention, the threshold includes a severity score level. In this embodiment, only those patterns from the set of patterns having a severity score (eg, at a particular severity score level or above the particular severity score level) are selected to This subset of patterns. In an alternate embodiment of the invention, the threshold includes a program window parameter such as exposure latitude and depth of focus. In still another alternative embodiment of the invention, the threshold includes a number from a pattern of a predetermined number of groups identified during the step of grouping the set of patterns. The predetermined number of groups may be all identified groups, or may be only one pattern subgroup. For example, the number of patterns from each group can be at least one pattern from each group, summing up to, for example, one of 15 to 50 patterns. In a further alternative embodiment, the threshold includes a predefined number of patterns from the ranked patterns in a ranking order. In an alternate embodiment of the invention, the threshold includes a dimension of the structure in the patterns. For example, a small size pattern can be selected prior to the large size pattern. In a further alternative embodiment of the invention, the threshold value comprises a number of occurrences of the patterns in the design or in the set of patterns. For example, a high appearance pattern can be selected before the pattern appears low. In an alternate embodiment of the invention, the threshold includes a criticality for the patterns of the design. For example, a pattern for the gate or a pair of critical patterns can be selected prior to the local interconnect pattern. All such options can be relatively easily automated by instructing a computer program product to apply the threshold to the set of patterns.

In an additional aspect of the above aspects and other aspects, the present invention is directed to a method of performing light source mask optimization for imaging a design or one of the designs onto a substrate via a lithography process . The method comprises the steps of: selecting a subset of patterns from the design according to any of the preceding technical solutions; performing light source and mask optimization on the selected patterns to obtain an optimized light source configuration, wherein The light source is configured as a configuration for illuminating the design or one of the designs onto one of the illumination sources of one of the lithography tools on the substrate, and the method includes optimizing the design using the optimized source The steps. In this embodiment, the design can be a full wafer design.

In an alternate embodiment of the source mask optimization, the method of performing source mask optimization can be performed on a separate wafer layer. In this embodiment, the method can begin by, for example, selecting an initial source configuration from one of the source mask adaptations for a related program or a related design. This initial light source configuration can be used to verify the lithographic performance of the design using, for example, a simulation tool for simulating the imaging of the design using this initial light source configuration. From this lithography performance verification, one or more hotspots can be identified in the design. Hotspots are patterns or clips that have been identified as limiting a lithography parameter such as depth of focus, exposure latitude, critical dimension uniformity, or even program window size or similar parameters. Subsequently, at least one of the identified hotspots is included in the subset of patterns for re-executing the source mask optimization, but for this particular wafer design, the use of the at least one identified hotspot is now used A subset of patterns. One of the benefits of this process is that it usually only requires marginal changes compared to the original source mask optimization, which ensures typical calculation time and performance to perform this "per design" source mask optimization. The source mask optimization without initial selection of the initial source configuration is substantially less.

In an additional aspect of the above aspects and other aspects, the present invention is directed to a computer program product comprising a computer readable medium having recorded instructions for causing a computer to perform a self-design when executed The method of selecting a subset of patterns.

Embodiments of the present invention will now be described by way of example only with reference to the accompanying drawings,

The invention will be described in detail with reference to the drawings, which are to be construed as an illustrative embodiment of the invention. The following figures and examples are not intended to limit the scope of the invention to a single embodiment, and other embodiments are possible by the interchange of some or all of the elements described or illustrated. In addition, where specific components of the invention may be implemented, in part or in whole, using known components, only those components of such known components necessary to understand the invention will be described, and such known components will be omitted. The detailed description of the other parts is provided so as not to obscure the invention. It will be apparent to those skilled in the art that embodiments described as being implemented in software should not be limited to this, and may include embodiments implemented in a combination of hardware or software and hardware, and vice versa (unless this document Another explanation). In the present specification, the embodiments of the singular components are not to be construed as limiting; rather, the invention is intended to cover other embodiments including the plurality of the same components, and vice versa (unless otherwise explicitly stated herein). In addition, the Applicant does not intend to attribute any term in this specification or the scope of the claims to the rare or specific meaning (unless so explicitly stated). In addition, the present invention encompasses present and future known equivalents of the known components referred to herein by way of illustration.

Although the use of the invention in the manufacture of ICs may be specifically referenced herein, it should be expressly understood that the invention has many other possible applications. For example, the present invention can be used to fabricate integrated optical systems, guidance and detection patterns for magnetic domain memories, liquid crystal display panels, thin film magnetic heads, and the like. Those skilled in the art should understand that in the context of the content of such alternative applications, any use of the terms "proportional mask", "wafer" or "die" in this context is considered to be more generic, respectively. Replace the terms "mask", "substrate" and "target part".

In the context of the present invention, the terms "radiation" and "beam" are used to cover all types of electromagnetic radiation, including ultraviolet radiation (for example, having 365 nm, 248 nm, 193 nm, 157 nm or 126). The wavelength of the nanometer) and EUV (extreme ultraviolet radiation, for example, having a wavelength in the range of 5 nm to 20 nm).

The term "mask" as used herein may be broadly interpreted to refer to a universally patterned member that can be used to impart a patterned cross-section to an incident radiation beam corresponding to a pattern to be formed in a target portion of the substrate. The term "light valve" can also be used in the context of this content. In addition to conventional masks (transmission or reflection; binary, phase shifting, blending, etc.), examples of other such patterned components include:

● Programmable mirror array. An example of such a device is a matrix addressable surface having a viscoelastic control layer and a reflective surface. The basic principle implied by this device is, for example, that the addressed area of the reflective surface reflects incident light as diffracted light, while the unaddressed area reflects incident light as non-diffracted light. By using a suitable filter, the non-diffracted light can be filtered out of the reflected beam leaving only the diffracted light; in this manner, the beam becomes patterned according to the addressing pattern of the matrix addressable surface. The appropriate electronic components can be used to perform the required matrix addressing. Further information on such mirror arrays can be found, for example, in U.S. Patent Nos. 5,296,891 and 5,523,193, the disclosures of which are incorporated herein by reference.

● Programmable LCD array. An example of such construction is given in U.S. Patent No. 5,229,872, which is incorporated herein by reference.

Prior to discussing the present invention, a brief discussion of the general simulation and imaging procedures is provided. FIG. 1 illustrates an exemplary lithography projection system 10. The main components are: a light source 12, which may be a deep ultraviolet excimer laser source; an illumination optics that defines a partial coherence (denoted as a mean square sigma) and may include a particular source shaping optical instrument 14, 16a and 16b; a mask or proportional mask 18; and a projection optics 16c that produces an image of the proportional mask pattern onto the wafer plane 22. The adjustable filter or aperture 20 at the pupil plane can limit the range of beam angles that illuminate the wafer plane 22, where the largest possible angle defines the numerical aperture NA = sin(Θ _max ) of the projection optics.

In a lithography simulation system, as illustrated in Figure 2, such major system components can be described by, for example, separate functional modules. Referring to FIG. 2, the functional module includes: a design layout module 26 that defines a target design; a mask layout module 28 that defines a mask to be used in an imaging process; and a mask model module 30 that defines a standby a model of the mask layout during the simulation process; an optical model module 32 that defines the performance of the optical components of the lithography system; and a resist model module 34 that defines the resist for a given program efficacy. As is known to us, for example, the results of the simulation program produce a predicted contour and CD in the results module 36.

More specifically, it should be noted that the properties of the illumination and projection optics are captured in the optical model 32, which includes, but is not limited to, the NA mean squared deviation ([sigma] setting and any particular illumination source shape (eg, off-axis) Light sources, such as rings, quads and dipoles, etc.). The optical properties (i.e., refractive index, film thickness, propagation, and polarization effects) of the photoresist layer coated on the substrate can also be captured as part of the optical model 32. The mask model 30 captures the design features of the reticle, and may also include a representation of the detailed physical properties of the mask, as described, for example, in U.S. Patent No. 7,587,704. Finally, resist model 34 describes the effects of chemical processes occurring during resist exposure, PEB, and development to predict, for example, the profile of the resist features formed on the substrate wafer. The goal of the simulation is to accurately predict, for example, edge placement and CD, which can then be compared to the target design. The target design is usually defined as the OPC pre-mask layout and will be provided in a standardized digital file format such as GDSII or OASIS.

In a typical high-end design, almost every feature edge requires some modification in order to achieve a printed pattern that is sufficiently close to the target design. Such modifications may include shifting or offsetting of edge positions or line widths and the application of "auxiliary" features, which are not intended to print themselves, but will affect the attributes of the associated primary features. In addition, optimization techniques applied to illumination sources can have different effects on different edges and features. Optimization of the illumination source can include the use of an aperture to limit illumination of the source to a selected pattern of light. The present invention provides an optimized method that can be applied to both light source configuration and mask configuration.

In general, a method of performing light source and mask optimization (SMO) according to an embodiment of the present invention achieves full wafer pattern coverage by intelligently selecting a set of small critical design patterns from a full set of clips to be used in SMO. At the same time, reduce the cost of calculation. SMO is only performed for these selected patterns to obtain an optimized source. Next, an optimized source is used to optimize the mask for the full wafer (eg, using OPC and LMC) and the results are compared. If the results are comparable to a conventional full-wafer SMO, then the process ends, otherwise, various methods for repeatedly converge to successful results are provided.

An example SMO method in accordance with an embodiment of the present invention will be explained in conjunction with the flowchart of FIG. 3A. It will be apparent to those skilled in the art that the flow chart in Figure 3A may not always be used for many feedback loops during SMO optimization. For example, in SMO during program development, the best possible source and mask may require the use of several feedback loops, and for SMOs performed during the wafer production process, speed is important and typically uses a simplified SMO process, thus Most of the feedback loops as shown in Figure 3A are omitted.

Target design 300 (typically containing layouts in a standard digital format such as OASIS, GDSII, etc.) (for target design 300, a lithography program will be optimized) includes memory, test patterns, and logic. From this design 300, a set of patterns 302 associated with a predefined representation of the design is identified from the design. In a particular embodiment of the invention, the set of patterns is the extracted full set of clips 302, which represents all of the complex patterns in design 300 (typically about 50 to 1000 clips). Those skilled in the art will appreciate that such patterns or clips represent a small portion (i.e., circuit, unit or pattern) of the design, and in particular, the clips represent a small portion: for such small portions, specific Attention and / or verification.

A predefined representation of a design for identifying a collection of patterns may, for example, comprise a different pattern type (such as a gate or a logic pattern), or may, for example, comprise a pattern having a particular orientation. A predefined representation for identifying a collection of patterns may, for example, also include: a pattern containing a particular level of complexity, or a pattern that requires particular attention and/or verification during lithography, for example, following design rules (eg, 1D full) Specific pitch of through pitch, staggered full dot spacing, common design construction or primitives (eg, elbow, T, H)), reusable layout structures (eg, memory cells (eg, bricks) Wall), memory peripheral structure (eg, hook to memory unit), and patterns with imaging problems known from previous generations, and the like. The predefined representation for identifying the set of patterns may, for example, further comprise a pattern having a predefined program window performance, or, for example, a pattern comprising: sensitivity to changes in program parameters of the pattern.

As shown generally at 304, a small pattern subset 306 or a small subset of clips 306 (eg, 15 to 50 clips) are selected from the full set 302. As will be explained in more detail below, the selection of the pattern or subset of clips is preferably performed such that the program window of the selected pattern matches the program window of the set of full critical patterns as closely as possible. The effectiveness of the selection is also measured by total rotational run time (pattern selection and SMO) reduction.

At 308, SMO is performed with a selected subset of patterns (15 to 50 patterns) 306. More specifically, the illumination source is optimized for the selected subset of patterns 306. This optimization can be performed using any of a variety of known methods (e.g., the methods described in U.S. Patent Publication No. 2004/0265707), the disclosure of which is incorporated herein by reference.

At 310, the manufacturability verification of the selected pattern subset 306 is performed with the light source obtained at 308. More specifically, the verification includes performing an aerial image simulation of the selected subset of patterns 306 and optimizing the source, and verifying that the subset of patterns will be printed across a wide enough program window. This verification can be performed using any of a variety of known methods (e.g., the methods described in U.S. Patent No. 7,342,646), the disclosure of which is incorporated herein by reference.

If the verification at 310 is satisfactory (as determined at 312), then processing proceeds to full wafer optimization at 314. Otherwise, processing returns to 308 where SMO is performed again, but SMO is performed with different light sources or different subsets of patterns. For example, the program performance as estimated by the verification tool can be compared to the threshold of a particular program window parameter such as exposure latitude and depth of focus. These thresholds can be predetermined or set by the user.

In 316, after the selected subset of patterns meets the lithography performance specifications as determined in 312, the optimized source 314 will be optimized for the full wafer or full clip set.

At 318, model-based sub-resolution assisted feature placement (MB-SRAF) and optical proximity correction (OPC) are performed for all of the patterns in the full wafer or full clip set 316. This procedure can be performed using any of a variety of known methods, such as those described in U.S. Patent Nos. 5,663,893, 5,821,014, 6,541,167, and 6,670,081.

In 320, verifiability verification based on full pattern simulation is performed by using a procedure similar to step 310 to optimize the source 314 and the full wafer or full clip set 316 as corrected in 318.

At 322, the performance of the full wafer or full clip set 316 (eg, program window parameters such as exposure latitude and depth of focus) and pattern or clip subset 306 are compared. In an example embodiment, when similar (<10%) lithography performance is obtained for both selected patterns (15 to 20) 306 and all critical patterns (50 to 1000) 316, the pattern selection is considered complete and / or the light source is fully qualified for the full wafer.

Otherwise, in 324, the hotspots are extracted, and in 326, the hotspots are added to the pattern subset 306 and the program begins again. For example, the hotspots identified during verification 320 (i.e., features of the full-wafer or full-clip set 316 that limit program window performance) are used for additional source tuning or to re-run the SMO. The source is considered to converge completely when the program window of the full wafer or full clip set 316 is the same between the last run and the run before the last run of 322. In this case, the optimized source and mask can be extracted from the process, as indicated in step 328.

A variety of pattern selection methods for use in 304 have been developed, and specific non-limiting examples are detailed below.

FIG. 3B shows the overall flow of a pattern selection method for selecting a subset of patterns from design 300. The initial step 302 in the pattern selection method is to identify the pattern from the design 300. The identification of the pattern in the set of patterns is such that the pattern is related to the design via a predefined representation as indicated above. In a particular embodiment of the invention, the identified set of patterns may comprise a full set of cuts. Subsequently, the identified set of patterns is grouped and/or ranked in step 350. This grouping and/or ranking may be based on parameters associated with predefined representations, or based on functions associated with predefined representations, or according to rules associated with predefined representations. Next, a threshold is defined in step 352, which is then used in step 354 to select a subset of patterns from the set of patterns.

Beneficially, step 302 of identifying a collection of patterns and step 354 of selecting a subset of patterns may be performed in an automated program. Due to the fact that there is a threshold in the selection method, the selection step 354 can be performed by instructing the computer program product to automatically extract all of the patterns following the threshold from the set of patterns to produce the subset. For example, the threshold can be defined by the user. Again, the pattern set identification step 302 can be automated, as the pattern representing the pattern set can also be identified during the recognition process using the representation requirements. Thus, the entire method from a design or full wafer selection pattern can be automated into an extraction algorithm that automatically extracts a subset of patterns from the design or the full wafer. Ultimately, the entire method of performing light source and mask optimization can be fully automated, which can be an optimization of the implementation of light sources and masks in a mass production environment in which automated procedures are performed. Ensure speed and consistency.

In a first embodiment, the light source is optimized for the SRAM pattern in the target design, and then the hotspots in the full set of clips are identified and selected as a subset of patterns for the SMO.

For example, as shown in FIG. 4, pattern selection in accordance with this embodiment begins in S402 by selecting an SRAM pattern (eg, two SRAM patterns) from target design 300.

In step S404, the two patterns are used to perform light source optimization such as light source optimization performed in 308 to obtain an optimized light source for the SRAM pattern.

In step S406, OPC is performed on the full cut set 302 using the optimized light source from S404. The OPC program executed in this step can be similar to the procedure described above in connection with 318 of FIG.

In step S408, manufacturability verification is performed for the full cut set 302 that has been adjusted in S406. This verification can be performed similar to the verification described above in connection with 320 of FIG.

From the result of the manufacturability verification, the clip having the worst performance is selected in S410. For example, S410 includes identifying from the manufacturability verification structure five to fifteen clips having the most finite effects on the program window for the SRAM-optimized light source.

Next, the SRAM pattern and hotspots are used as a subset 306 in the example full wafer SMO process of FIG.

In the next embodiment, where the original or initial source and model are used, the hotspots are identified from the full set of clips and are selected as a subset of the pattern for the SMO.

For example, as shown in FIG. 5A, pattern selection in accordance with this embodiment begins in S502 by identifying the original or initial source and model for the lithography program. In the remainder of the description of Figures 5A and 5B, the initial source is also indicated as the initial source configuration to indicate that the illumination source used in the lithography procedure initially has a source that can be used as described in Figures 5A and 5B. The specific configuration in which the mask program is changed. For example, a ring illumination source is used as the initial source or initial source configuration. Alternatively, the original source or initial source may be caused by a previous SMO for a particular or similar lithography program or design. Use this raw or initial source as a starting point for the optimization of the current design. The model can be any model for calculating lithography procedures in lithography and aerial image simulation, and can include a Transmission Cross Coefficient (TCC) as described, for example, in U.S. Patent No. 7,342,646.

In step S504, manufacturability verification is performed using the light source and model and the full cut set 302. The verification process can be similar to the verification process described above in connection with 310 of FIG.

In step S506, the severity score is calculated using the verification structure of each of the full cut sets 302 to identify hotspots. In a non-limiting example, the severity score is calculated as:

Scoring = Normalization (+EPE) + Normalization (-EPE) + 2 × Normalized MEEF

The EPE is the edge placement error, and the MEEF is the mask error enhancement factor. However, it will be apparent to those skilled in the art that any score or value indicating whether the design conforms to a particular lithography performance can be used in this step P506 to understand the design when using this particular initial source configuration. What is the performance of the film.

In step S508, the clip having the highest score or the limit lithography parameter used is recognized as a hot spot. For example, S508 includes identifying five to fifteen clips having the highest severity score as calculated above.

These clips are then used as a subset 306 in the example full wafer SMO process of FIG. In an embodiment, two SRAM patterns from target design 300 are also included in subset 306.

Figure 5B shows this procedure in more detail. The dashed squares indicate portions of the procedure shown in Figure 5A. The process begins in step 510 where an initial source configuration or baseline source is selected, for example, from a previous source mask optimization. This previous source mask optimization can be performed for a particular lithography program, or can be performed on a design similar to the design currently under study. Next, in the step indicated by 520, the lithographic performance of the design is verified when the initial source configuration is used. In the event that lithography performance is insufficient, the hotspot is identified in step 530, after which at least some of the identified hotspots are added to the pattern selected from the set of clips (as shown in step 540) to increase pattern coverage. Subsequently, a subset of clips that now include at least some of the identified hotspots are used to perform source mask optimization in the steps indicated by element symbol 306 and substantially similar to the steps indicated by FIG. 3A. Because of the initial source configuration used since a similar lithography procedure or similar design choice, it is expected that the changes required to find the optimal source mask combination during the source mask optimization process are limited, resulting in significant reductions to achieve The calculation time for the optimization of the light source mask. Moreover, this flow makes it possible to perform source mask optimization substantially for each wafer or design. This may be required when the program window is further tightened due to the ever-increasing lithography requirements.

In the next embodiment, an analysis is performed on the full set of cuts 302, and the same clips that give the best features and spacing coverage are selected as a subset of the patterns for the SMO.

For example, as shown in FIG. 6, the pattern selection according to this embodiment is started in S602 by grouping the clips according to the feature types. For example, the clips may be grouped by the type of circuit pattern (eg, gate or logic) or by orientation or complexity, and the like.

In step S604, the clips in each group are further classified by the pitch.

In step S606, each of the clips is sampled in a small pitch region to determine the coverage that will be provided for both the type and the spacing.

In step S608, the clip having the smallest pitch and the highest cell density is selected from among the clips to be covered in S606. For example, S608 includes identifying five to fifteen clips having an optimal design coverage and from a minimum to a distance of 1.5 times the minimum spacing.

These clips are then used as a subset 306 in the example full wafer SMO process of FIG. In an embodiment, two SRAM patterns from target design 300 are also included in subset 306.

In the next embodiment, the analysis is performed on the full set of clips, and the clips having the highest sensitivity to the particular program parameters according to the original model of the program are selected as the subset of patterns for the SMO.

For example, as shown in FIG. 7, pattern selection according to this embodiment begins in S702 by identifying an original model for a lithography program. Similar to S502, the model can be any model used to calculate lithography procedures in lithography and aerial image simulation, and can include transmission crossover coefficients (TCC) as described, for example, in U.S. Patent No. 7,342,646.

In step S704, the cutting lines are placed in the pattern at the center of each of the full cut sets 302.

In step S706, the program parameter sensitivity is calculated for each of the clips using the original model. For example, the program parameters can be dose and focus, and the sensitivity can be calculated by running an aerial image simulation using the lithography simulation model identified in S702. Next, the behavior of the clip at the cut line during various program conditions is analyzed to determine its sensitivity.

In step S708, a clip having the highest sensitivity to changes in program parameters is selected. For example, S708 includes identifying five to fifteen clips having the highest sensitivity to changes in dose and focus.

Next, these clips are used as an example in the full-wafer SMO process of Figure 3. Subset 306. In an embodiment, two SRAM patterns from target design 300 are also included in subset 306.

In the next embodiment, an analysis is performed on the full set of clips, and the clips that provide the best diffraction order distribution are selected as the subset of patterns for the SMO. The diffraction pattern of the pattern is known to those skilled in the art and can be determined, for example, as described in U.S. Patent Publication No. 2004/0265707.

For example, as shown in FIG. 8, pattern selection in accordance with this embodiment begins in S802 by calculating a diffraction order behavior for each of the full set of cuts 302. A number of possible methods can be used to calculate the diffraction level behavior, for example, U.S. Patent Publication No. 2004/0265707.

In step S804, the calculated diffraction order of the full cut set is compared, and in step S806, the cut is grouped according to the diffraction order distribution of the cut. For example, geometric correlations between each of the clips can be calculated, and a classification method can be performed to group the most similar clips together.

In step S808, a clip from each of the groups is selected. For example, S806 includes forming five to fifteen clip groups, and randomly selecting one clip from each group. 9A-9O illustrate example diffraction order distributions 902A through 902O of fifteen individual clips that have been calculated from a full set of clips.

These clips are then used as a subset 306 in the example full wafer SMO process of FIG. In an embodiment, two SRAM patterns from target design 300 are also included in subset 306.

Some advantages of the diffraction-level based pattern selection method described in connection with FIG. 8 over other methods are that no starting conditions (eg, starting illumination source) are required, no resist model is needed, and no model is needed. This pattern selection method requires only the target pattern, and therefore, it is program independent.

Figure 10 is a graph comparing the performance of various pattern selection methods described above with respect to the program window performance of the conventional full wafer SMO method. It can be seen that all methods improve the original program window, where the diffraction level method gives the performance closest to the full wafer SMO.

Figure 11 is a graph comparing the processing run time performance of the various pattern selection methods described above with respect to the conventional full wafer SMO method. It can be seen that all methods improve the known run time, with the diffraction level method giving the most improvement.

FIG. 12 is a block diagram illustrating a computer system 100 that can assist in implementing the optimization methods and processes disclosed herein. The computer system 100 includes a busbar 102 or other communication mechanism for communicating information, and a processor 104 coupled to the busbar 102 for processing information. Computer system 100 also includes a main memory 106, such as a random access memory (RAM) or other dynamic storage device, coupled to bus bar 102 for storing information and instructions to be executed by processor 104. The main memory 106 can also be used to store temporary variables or other intermediate information during execution of instructions to be executed by the processor 104. Computer system 100 further includes a read only memory (ROM) 108 or other static storage device coupled to bus bar 102 for storing static information and instructions for processor 104. A storage device 110, such as a magnetic disk or optical disk, is provided and coupled to the busbar 102 for storing information and instructions.

The computer system 100 can be coupled via a busbar 102 to a display 112 for displaying information to a computer user, such as a cathode ray tube (CRT) or a flat panel display or a touch panel display. Input device 114 (including alphanumeric and other keys) is coupled to busbar 102 for communicating information and command selections to processor 104. Another type of user input device is a cursor control 116, such as a mouse, trackball or cursor direction key, for communicating direction information and command selections to the processor 104 and for controlling cursor movement on the display 112. This input device typically has two degrees of freedom on two axes (a first axis (e.g., x ) and a second axis (e.g., y )) that allow the device to specify a position in a plane. A touch panel (screen) display can also be used as an input device.

In accordance with an embodiment of the present invention, portions of the optimization program may be executed by the computer system 100 in response to the processor 104 executing one or more sequences of one or more instructions contained in the main memory 106. These instructions can be read into the main memory 106 from another computer readable medium, such as storage device 110. Execution of the sequences of instructions contained in main memory 106 causes processor 104 to perform the program steps described herein. The sequence of instructions contained in the main memory 106 can also be executed using one or more processors in a multi-processing configuration. In alternative embodiments, hard-wired circuitry may be used in place of or in combination with software instructions to implement the invention. Thus, embodiments of the invention are not limited to any specific combination of hardware circuitry and software.

The term "computer readable medium" as used herein refers to any medium that participates in providing instructions to processor 104 for execution. This medium can take many forms, including but not limited to, non-volatile media, volatile media, and transmission media. Non-volatile media includes, for example, optical or magnetic disks, such as storage device 110. Volatile media includes dynamic memory, such as main memory 106. The transmission medium includes a coaxial cable, a copper wire, and an optical fiber including a wire including the bus bar 102. The transmission medium can also take the form of sound waves or light waves, such as sound waves or light waves generated during radio frequency (RF) and infrared (IR) data communication. Common forms of computer readable media include, for example, floppy disks, flexible disks, hard disks, magnetic tape, any other magnetic media, CD-ROM, DVD, any other optical media, punch card, paper tape, aperture pattern Any other physical media, RAM, PROM and EPROM, FLASH-EPROM, any other memory chip or wafer, carrier wave as described hereinafter, or any other medium that can be read by a computer.

Various forms of computer readable media may be involved in carrying one or more sequences of one or more instructions to processor 104 for execution. For example, the instructions may initially be carried on a disk of a remote computer. The remote computer can load the instructions into its dynamic memory and use the modem to send commands via the telephone line. The data machine at the local end of the computer system 100 can receive the data on the telephone line and use an infrared transmitter to convert the data into an infrared signal. The infrared detector coupled to the bus bar 102 can receive the data carried in the infrared signal and place the data on the bus bar 102. The bus 102 carries the data to the main memory 106, and the processor 104 autonomously retrieves and executes the instructions. The instructions received by the main memory 106 may be stored on the storage device 110 before or after execution by the processor 104 as appropriate.

Computer system 100 also preferably includes a communication interface 118 that is coupled to bus bar 102. Communication interface 118 provides a two-way data communication coupling to network link 120 connected to area network 122. For example, communication interface 118 can be an integrated services digital network (ISDN) card or modem to provide a data communication connection to a corresponding type of telephone line. As another example, communication interface 118 can be a local area network (LAN) card to provide a data communication connection to a compatible LAN. A wireless link can also be implemented. In any such implementation, communication interface 118 transmits and receives electrical, electromagnetic or optical signals that carry digital data streams representing various types of information.

Network link 120 typically provides data communication to other data devices via one or more networks. For example, network link 120 can provide a connection to host computer 124 via local area network 122 or provide a connection to a data device operated by an Internet Service Provider (ISP) 126. ISP 126 provides data communication services via a global packet data communication network (now commonly referred to as "Internet" 128). Both the local area network 122 and the Internet 128 use electrical, electromagnetic or optical signals that carry digital data streams. Signals via various networks and signals over network link 120 and via communication interface 118, which carry digital data to computer system 100 and digital data from computer system 100, are exemplary carriers for conveying information.

The computer system 100 can transmit and receive data (including code) via the network, the network link 120, and the communication interface 118. In the Internet instance, server 130 may transmit the requested code for the application via Internet 128, ISP 126, regional network 122, and communication interface 118. In accordance with the present invention, one such downloaded application provides, for example, illumination optimization for this embodiment. The received code may be executed by processor 104 as it is received, and/or stored in storage device 110 or other non-volatile storage for later execution. In this manner, computer system 100 can obtain application code in the form of a carrier wave.

Figure 13 schematically depicts an exemplary lithographic projection apparatus whose illumination source can be optimized using the procedures of the present invention. The device contains:

- Radiation systems Ex, IL, which are used to supply the projected radiation beam PB. In this particular case, the radiation system also includes a radiation source LA;

a first object stage (mask stage) MT provided with a mask holder for holding a mask MA (for example, a proportional mask) and connected to accurately position the mask with respect to the item PL First positioning member;

a second object stage (substrate stage) WT having a substrate holder for holding a substrate W (for example, a resist wafer coated with a resist) and connected to accurately position the substrate PL with respect to the item PL a second positioning member of the substrate;

a projection system ("lens") PL (eg, a refractive, reflective or catadioptric optical system) for imaging the irradiated portion of the mask MA to a target portion C of the substrate W (eg, comprising one or more On the grain).

As depicted herein, the device is of the transmissive type (ie, has a transmissive mask). However, in general, it can also be, for example, a type of reflection (with a reflective mask). Alternatively, the device may use another type of patterned member as an alternative to the use of a mask; examples include a programmable mirror array or LCD matrix.

A light source LA (eg, a mercury lamp or a quasi-molecular laser) produces a beam of radiation. This beam is fed into the illumination system (illuminator) IL either directly or after having been traversed, for example, by an adjustment member of the beam expander Ex. The illuminator IL may include an adjustment member AM for setting an outer radial extent and/or an inner radial extent (commonly referred to as σ outer and σ inner, respectively) of the intensity distribution in the beam. In addition, the illuminator IL will typically include various other components such as the concentrator IN and the concentrator CO. In this way, the light beam PB illuminating the mask MA has a desired uniformity and intensity distribution in its cross section.

It should be noted with respect to FIG. 13 that the light source LA can be in the housing of the lithographic projection apparatus (in this case, usually when the light source LA is, for example, a mercury lamp), but the light source LA can also be remote from the lithographic projection apparatus, and the light source LA is generated. the radiation beam is guided to the apparatus through (e.g., by virtue of appropriate guiding mirror); typically source LA is an excimer laser (e.g., based on KrF, ArF or F ₂ laser action) of the case when this latter scenario. The present invention covers at least two such scenarios.

The light beam PB is then intercepted by the mask MA, and the mask MA is held on the mask table MT. After traversing the mask MA, the light beam PB is transmitted through the lens PL, which focuses the light beam PB onto the target portion C of the substrate W. With the second positioning member (and the interference measuring member IF), the substrate table WT can be accurately moved, for example, to position the different target portions C in the path of the light beam PB. Similarly, the first positioning member can be used to accurately position the mask MA, for example, after mechanically capturing the mask MA from the mask library or during the scan relative to the path of the beam PB. In general, the movement of the object tables MT, WT will be achieved by means of a long stroke module (rough positioning) and a short stroke module (fine positioning) not explicitly depicted in FIG. However, in the case of a wafer stepper (as opposed to a step-and-scan tool), the mask table MT may be connected only to the short-stroke actuator or may be fixed.

The depicted tool can be used in two different modes:

- In the step mode, the mask table MT is kept substantially stationary, and the entire mask image is projected once (i.e., a single "flash") onto the target portion C. Next, the substrate table WT is displaced in the x and / or y direction, so that the different target portions C can be irradiated by the light beam PB;

- In scan mode, basically the same scenario applies, except that a given target part C is not exposed in a single "flash". Instead, the mask table MT can be moved at a speed v in a given direction (so-called "scanning direction", for example, the y direction), causing the projection beam PB to scan across the mask image; at the same time, the substrate table WT is at a speed V = Mv and move simultaneously in the same or opposite directions, where M is the magnification of the lens PL (typically, M = 1/4 or 1/5). In this way, the relatively large target portion C can be exposed without impairing the resolution.

The invention may be further described in terms of the following clauses:

CLAIMS 1. A method for optimizing a lithography process for imaging a portion of a design onto a substrate, the method comprising: selecting a subset of patterns from the portion of the design; The lithography program of the subset of patterns optimizes an illumination source; and the optimized illumination source is used to optimize the portion of the design for imaging in the lithography procedure.

2. The method of clause 1, wherein the method initially performs the steps of: selecting an initial source configuration; verifying a lithography performance of the portion of the design when the initial source configuration is used, wherein verifying the lithography performance The step includes identifying hotspots in the portion of the design, the hotspots forming a pattern from the portion of the design that limits lithography parameters of the portion of the design; and wherein the subset of patterns includes the identified hotspots At least some of them.

3. The method of clause 1, wherein the portion of the design comprises a full wafer.

4. The method of clause 1, wherein the portion of the design includes a clip, and wherein the step of selecting a subset of patterns comprises: identifying a full set of clips from the design; selecting a subset of clips from the set of full cuts; The optimizing step includes optimizing an illumination source for the lithography program for imaging the selected subset of clips; and wherein the using step comprises using the optimized illumination source to optimize the full clip set for use Imaging is performed in the lithography program.

5. The method of clause 1, 2, 3 or 4, wherein the selecting step comprises: calculating a diffraction order distribution of the pattern in the portion of the design; grouping the patterns into groups based on the calculating the diffraction order distribution a plurality of groups; and selecting one or more representative patterns from each of the groups as the subset of patterns.

6. The method of clause 1, 2, 3 or 4, wherein the selecting step comprises: identifying one or more memory patterns in the portion of the design; pre-optimizing the one or more memory patterns An illumination source; the pre-optimized illumination source is used to determine potential hot spots in the portion of the design; and the subset of patterns is selected based on the determined potential hot spots.

7. The method of clause 1, 2, 3 or 4, wherein the selecting step comprises: identifying an original illumination source for the lithography procedure; using the original illumination source to determine a potential hot spot in the portion of the design; And selecting the subset of patterns based on the determined potential hot spots.

8. The method of clause 6 or 7, wherein the method further comprises the steps of: calculating a severity score for a hotspot; and selecting the hotspot having a predefined severity score, or selecting having a predefined The hot spot of one of the severity scores within the severity score.

9. The method of clause 1, 2, 3 or 4, wherein the selecting step comprises: grouping the patterns in the portion of the design into a plurality of groups by design type; each by spacing and feature type The patterns in a group are classified to determine one of the best patterns in each group; and the best pattern in each group is selected as the subset of patterns.

10. The method of clause 1, 2, 3 or 4, wherein the selecting step comprises: identifying one of the lithography program simulation models; using the model to estimate program parameter sensitivity of the pattern in the portion of the design; The subset of patterns is selected based on the estimated program parameter sensitivity.

11. The method of any one of clauses 1 to 10, further comprising: determining whether a lithography performance metric of the subset of the optimized pattern is acceptable; and if the determined metric is not acceptable , adding a clip with potential hotspots to the subset of patterns and repeating the optimization steps.

12. The method of any of clauses 1 to 11, wherein the step of optimizing the illumination source comprises simulating a lithography performance using the lithography program, the illumination source, and one of the pattern subsets. To determine if the performance is acceptable.

13. The method of any of clauses 1 to 12, wherein the step of optimizing the portion of the design comprises performing optical proximity correction on the particular pattern in the patterns based on the optimized illumination source.

14. A computer readable medium recorded with instructions that, when read by a computer, cause the computer to perform the optimization of clauses 1 through 13 for imaging a portion of a design to a A method of lithography on a wafer.

15. A lithography apparatus comprising: an illumination system configured to provide a radiation beam; a support structure configured to support a patterned member for use in the radiation beam Giving a pattern to the radiation beam in a cross section; a substrate stage configured to hold a substrate; and a projection system for projecting the patterned radiation beam onto a target portion of the substrate; The lithography apparatus further includes a processor for configuring the illumination system to generate an optimized illumination source in accordance with the method for optimizing a lithography procedure as in clauses 1 through 13.

16. A patterned member for imparting a radiation beam from an illumination system of a lithography apparatus, the lithography apparatus being configured to project the imparted beam onto a target portion of a substrate via a projection system Wherein the patterned member comprises an optimized portion of the design, wherein the optimized portion of the design is determined according to the method of optimizing a lithography procedure as in clauses 1 through 12.

According to a particular aspect, the present invention achieves full design coverage by intelligently selecting a subset of patterns from a design while reducing computational cost, wherein the design or one of the designs is modified to be configured via a lithography procedure. Imaging onto a substrate. The method of selecting the subset of patterns from a design includes identifying from the design a set of patterns associated with a predefined representation of the design. By selecting the subset of patterns according to the method, the selected subset of patterns constitutes one of the designs resembling a predefined representation as the set of patterns. This predefined representation of the design can, for example, be a diffraction level produced by the pattern of the design, or, for example, the type of pattern present in the design, or, for example, present in the design A complexity of the pattern, or, for example, a pattern that requires particular attention and/or verification, or, for example, a pattern with predefined program window performance, or, for example, a predefined sensitivity to one of the program parameter changes.

The concepts disclosed herein can simulate or mathematically model any general-purpose imaging system for imaging sub-wavelength features, and can be particularly useful for emerging imaging technologies that are capable of producing wavelengths of ever smaller size. Emerging technologies that are already in use include the ability to generate 193 nm wavelengths by using ArF lasers and even EUV (ultraviolet ultraviolet) lithograms of wavelengths of 157 nm by using a fluorine laser. In addition, EUV lithography is capable of producing wavelengths in the range of 20 nm to 5 nm, either by using a synchrotron or by striking a material (solid or plasma) with high-energy electrons to produce Photons within range. Since most materials are absorptive in this range, illumination can be produced by having a multi-stacked mirror surface of molybdenum and tantalum. The multi-stacked mirror has 40 pairs of layers of molybdenum and tantalum, each of which has a thickness of a quarter wavelength. Even smaller wavelengths can be produced by X-ray lithography. Typically, synchrotrons are used to generate X-ray wavelengths. Since most materials are absorptive at x-ray wavelengths, thin absorbing material sheets define features where they will be printed (positive resist) or not printed (negative resist).

Although the concepts disclosed herein can be used for imaging on substrates such as germanium wafers, it should be understood that the disclosed concepts can be used with any type of lithography imaging system, for example, on substrates other than germanium wafers. Imaging lithography imaging system.

The above description is intended to be illustrative, and not restrictive. Therefore, it will be apparent to those skilled in the art that the invention as described herein may be modified without departing from the scope of the appended claims.

10‧‧‧ lithography projection system

12‧‧‧Light source

14‧‧‧Special light source shaping optical instrument

16a‧‧‧Special light source shaping optical instrument

16b‧‧‧Special light source shaping optical instrument

16c‧‧‧Projection optical instruments

18‧‧‧ mask or proportional mask

20‧‧‧Adjustable filter or aperture

22‧‧‧ Wafer plane

26‧‧‧Design layout module

28‧‧‧Mask layout module

30‧‧‧Mask model module

32‧‧‧Optical model module

34‧‧‧Resist model module

36‧‧‧Result Module

100‧‧‧ computer system

102‧‧‧ busbar

104‧‧‧Processor

106‧‧‧ main memory

108‧‧‧Reading Memory (ROM)

110‧‧‧Storage device

112‧‧‧ display

114‧‧‧Input device

116‧‧‧ cursor control

118‧‧‧Communication interface

120‧‧‧Network link

122‧‧‧Regional Network

124‧‧‧Host computer

126‧‧‧ Internet Service Provider (ISP)

128‧‧‧Internet

130‧‧‧Server

300‧‧‧Target design

302‧‧‧Pattern Collection/Full Clip Collection

306‧‧‧Pattern subsets/clip subsets

314‧‧‧Optimized light source

316‧‧‧Full wafer or full clip collection/critical pattern

320‧‧‧Verification

902A‧‧‧Diffraction level distribution

902B‧‧‧Diffraction level distribution

902C‧‧‧Diffraction level distribution

902D‧‧‧Diffraction level distribution

902E‧‧‧Diffraction level distribution

902F‧‧‧diffraction level distribution

902G‧‧‧Diffraction level distribution

902H‧‧‧Diffraction level distribution

902I‧‧‧Diffraction level distribution

902J‧‧‧Diffraction level distribution

902K‧‧‧diffraction level distribution

902L‧‧‧diffraction level distribution

902M‧‧‧diffraction level distribution

902N‧‧‧Diffraction level distribution

902O‧‧‧Diffraction level distribution

C‧‧‧Target section

CO‧‧‧ concentrator

IF‧‧ Interference measuring components

IL‧‧‧radiation system/lighting system/illuminator

IN‧‧‧ concentrator

MA‧‧‧ mask

MT‧‧‧First Object Table/Mask Table

W‧‧‧Substrate

WT‧‧‧Second object table/substrate table

1 is an exemplary block diagram illustrating a typical lithography projection system; FIG. 2 is an exemplary block diagram illustrating a functional module of a lithography simulation model; and FIG. 3A is a flow chart illustrating an example SMO program in accordance with an embodiment of the present invention. FIG. 3B is a detailed flowchart illustrating a pattern selection algorithm; FIG. 4 is a flowchart illustrating an example pattern selection method that may be included in an embodiment of the SMO program according to the present invention; FIG. 5A is a description that may be included in the A flowchart of an example pattern selection method in another embodiment of the inventive SMO program; FIG. 5B is a flow chart illustrating an example of performing an SMO procedure after selecting a baseline source or initial source configuration; FIG. 6 is an illustration that may be included in A flowchart of an example pattern selection method in another embodiment of the SMO program of the present invention; FIG. 7 is a flow chart illustrating an example pattern selection method that may be included in another embodiment of the SMO program in accordance with the present invention; To illustrate a flowchart of an example pattern selection method that may be included in another embodiment of the SMO program in accordance with the present invention; FIGS. 9A-9O illustrate the implementation of the clip selected in accordance with the method of FIG. Example: Diffraction level distribution; FIG. 10 is a graph comparing program window performance of various pattern selection methods according to the present invention; FIG. 11 is a graph comparing processing time performance of various pattern selection methods according to the present invention; FIG. A block diagram of a computer system that can aid in the implementation of the simulation method of the present invention; and Figure 13 schematically depicts a lithographic projection apparatus suitable for use in the method of the present invention.

300. . . Target design

302. . . Pattern collection / full clip collection

306. . . Pattern subset/clip subset

314. . . Optimized light source

316. . . Full wafer or full clip collection / critical pattern

320. . . verification

Claims (17)

A method of selecting a subset of patterns associated with a design, wherein the design or one of the designs is modified to be imaged onto a substrate via a lithography process, and wherein the subset of patterns constitutes the design A predefined representation, the method comprising the steps of: identifying a set of patterns associated with the predefined representation of the design; grouping and/or ranking the set of patterns; defining a threshold associated with the group and/or ranking a value; and selecting the subset of patterns from the set of patterns, wherein the subset includes patterns from the set of patterns above or below the threshold. The method of claim 1, wherein the step of identifying a set of patterns comprises: identifying a set of clips associated with the design; identifying a pattern from the design to form at least a portion of the set of patterns; automatically identifying patterns from the design to Forming at least a portion of the collection of patterns. The method of claim 1, wherein the step of selecting the subset of patterns comprises: selecting a clip from the set of patterns for a set of clips, the subset of patterns comprising the selected clips; automatically extracting a pattern from the design, the pattern The subset includes the automatically extracted patterns; the pattern is manually extracted from the design, the subset of patterns comprising the manually extracted patterns. The method of claim 1, wherein the predefined representation of the design for identifying the set of patterns comprises one or more of: a diffraction level produced by a pattern of the design; present in the design One or more pattern types; the complexity of the patterns present in the design; the patterns present in the design that require specific attention and/or verification during the lithography process; Program window performance of a pattern; a predefined sensitivity to program parameter variations of the patterns present in the design. The method of claim 3, wherein the predefined representation of the design for identifying the set of patterns comprises program window performance of the pattern in the design, wherein the subset of patterns comprises the program substantially corresponding to the design A program window performance for window performance. The method of claim 3, wherein the predefined representation of the design for identifying the set of patterns comprises program window performance of the pattern in the design, wherein the subset of patterns comprises hotspots that limit the design The program window performance is derived from the pattern of the pattern set. The method of claim 5 or 6, wherein the method further comprises a numerical modeling method for identifying a program window performance of at least one of the patterns from the set of patterns. The method of claim 1, wherein the grouping and/or ranking comprises a grouping and/or ranking according to one or more of: a parameter associated with the predefined representation of the design; A function associated with the predefined representation of the design; a rule associated with the predefined representation of the design. The method of claim 1, wherein the threshold comprises one or more of: a severity score level; a program window parameter; a pattern from each of the predetermined number of pattern groups a number of patterns that are generated by the step of grouping the set of patterns; a predefined number of patterns from the ranked patterns in a ranking order; a size of the structure in the patterns a number of occurrences of the patterns in the design or in the set of patterns; a criticality with respect to the patterns of the design. The method of claim 1, wherein the step of identifying a set of patterns comprises the step of calculating a diffraction order distribution of the patterns of the design, and wherein the step of grouping and/or ranking the set of patterns comprises The diffraction level distribution is calculated to group the pattern sets into a plurality of groups, and wherein the step of selecting the pattern subset includes selecting one or more patterns from the plurality of groups as the subset. The method of claim 1, wherein the step of identifying a set of patterns comprises identifying one or more memories a body pattern, and wherein the method further comprises a step of pre-optimizing the illumination source for imaging the design to one of the lithography tools on the substrate for the one or more memory patterns, and wherein the pattern The step of grouping and/or ranking the set includes using the pre-optimized illumination source to determine potential hotspots in the design, and wherein the step of selecting the subset of patterns comprises selecting the sub-spot based on the determined potential hotspots set. The method of claim 1, wherein the method further comprises a step of identifying an initial illumination source for the lithography procedure, and wherein the step of grouping and/or ranking the set of patterns comprises using the initial illumination source A potential hot spot in the design is determined, and wherein the step of selecting the subset of patterns comprises selecting the subset based on the determined potential hotspots. The method of claim 1, wherein the step of grouping and/or ranking the set of patterns comprises: grouping the patterns in the full set of clips into a plurality of groups by design type; and by spacing and feature types And classifying the patterns in each group to determine one of the best patterns in each group; and wherein the step of selecting the pattern subset includes selecting the best pattern in each group as This subset. The method of claim 1, wherein the method further comprises identifying a simulation model of the lithography program And using the model to estimate a step of program parameter sensitivity of the patterns of the design; and wherein the step of selecting the subset of patterns comprises selecting the subset based on the estimated program parameter sensitivity. A method of performing light source mask optimization for imaging a design or one of the designs onto a substrate via a lithography process, the method comprising the steps of: self-according to any of the foregoing claims The design selects a subset of patterns; performing a light source and mask optimization on the selected patterns to obtain an optimized light source configuration configured to modify the design or one of the designs to the A configuration of one of the lithography tools on the substrate illuminates the light source; and the optimized light source is used to optimize the design. The method of claim 15, wherein the method initially performs the steps of: selecting an initial source configuration; verifying a lithography performance of the design when the initial source configuration is used, wherein the step of verifying the lithography performance comprises identifying Hotspots in the design that form a pattern from the design that limits one of the lithographic parameters of the design; and wherein the subset of patterns includes at least one identified hotspot. A computer program product comprising a computer readable medium having recorded instructions for causing a computer to perform a method of selecting a subset of patterns of any of claims 1 through 14 when executed.