CN117353678A - Ultra-wideband high-harmonic suppression ratio low-noise amplifier circuit - Google Patents
Ultra-wideband high-harmonic suppression ratio low-noise amplifier circuit Download PDFInfo
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
- H03F1/42—Modifications of amplifiers to extend the bandwidth
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
- H03F1/26—Modifications of amplifiers to reduce influence of noise generated by amplifying elements
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
- H03F1/30—Modifications of amplifiers to reduce influence of variations of temperature or supply voltage or other physical parameters
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/189—High-frequency amplifiers, e.g. radio frequency amplifiers
- H03F3/19—High-frequency amplifiers, e.g. radio frequency amplifiers with semiconductor devices only
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/68—Combinations of amplifiers, e.g. multi-channel amplifiers for stereophonics
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
- H03H7/00—Multiple-port networks comprising only passive electrical elements as network components
- H03H7/01—Frequency selective two-port networks
- H03H7/0115—Frequency selective two-port networks comprising only inductors and capacitors
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
- H03H7/00—Multiple-port networks comprising only passive electrical elements as network components
- H03H7/42—Networks for transforming balanced signals into unbalanced signals and vice versa, e.g. baluns
- H03H7/422—Networks for transforming balanced signals into unbalanced signals and vice versa, e.g. baluns comprising distributed impedance elements together with lumped impedance elements
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
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- H03F2200/451—Indexing scheme relating to amplifiers the amplifier being a radio frequency amplifier
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Abstract
The invention discloses a low-noise amplifier circuit with ultra-wideband and high harmonic rejection ratio, which relates to the technical field of radio frequency and comprises an input module, a low-noise amplifying module and an output module which are sequentially connected in series. The ultra-wideband frequency conversion method can meet ultra-wideband performance of a plurality of octaves and obviously improve the higher harmonic suppression ratio; the phase-shifting regulation unit is introduced, and the frequency divider and the combiner can improve the suppression degree of third harmonic and higher harmonic and solve the problem of gain deterioration of the cross frequency band of the combiner; the second harmonic power can be suppressed using the first low frequency balun, the first high frequency balun, the second low frequency balun, and the second Gao Pinba balun.
Description
Technical Field
The invention relates to the technical field of radio frequency, in particular to a low-noise amplifier circuit with ultra-wideband and high harmonic rejection ratio.
Background
The current key chip of the radio frequency front end is developed towards high performance and high integration level. A Low Noise Amplifier (LNA) is widely used as a core device of a radio frequency receiving link in a system such as a radar T/R module and a radio frequency front-end transceiver.
When the ultra-wideband communication system adopts a baseband pulse working mode, the ultra-wideband communication system has stronger penetrating capacity and multipath interference resistance. In general, the low noise amplifier is operated in a linear amplifying state, and the output frequency spectrum is not affected by higher harmonic power. Modern communication systems currently often require a 1dB compression point of the output of the low noise amplifier to meet a large power requirement, and require that the higher harmonic output power due to non-linear power compression must also be reduced. The addition of filters in a narrow band low noise amplifier design can very easily achieve this type of requirement, but in ultra wideband low noise amplifiers of several octaves it is not possible to add any form of filter circuit, which would significantly reduce the gain and deteriorating noise figure in the passband. Therefore, how to realize that the low-noise amplifier can meet ultra-wideband performance and can also obviously improve the higher harmonic suppression ratio is a problem which needs to be solved at present.
Disclosure of Invention
Aiming at the defects in the prior art, the low-noise amplifier circuit with the ultra-wideband high harmonic rejection ratio solves the problem that the ultra-wideband performance cannot be met in the prior art and the high harmonic rejection ratio is improved at the same time.
In order to achieve the aim of the invention, the invention adopts the following technical scheme:
the low-noise amplifier circuit with ultra-wideband high harmonic rejection ratio comprises an input module, a low-noise amplifying module and an output module which are sequentially connected in series; the input module comprises a frequency divider, a first low-frequency balun and a first high-frequency balun; the low-noise amplifying module comprises two first low-frequency low-noise amplifying units and second low-frequency low-noise amplifying units which are connected in parallel, and two first high-frequency low-noise amplifying units and second high-frequency low-noise amplifying units which are connected in parallel; the output module comprises a second low-frequency balun, a second Gao Pinba balun, a phase-shifting regulation and control unit and a combiner;
the first end of the frequency divider is used as a signal input end, the second port of the frequency divider is connected with one end of the first low-frequency balun, and the third port of the frequency divider is connected with one end of the first high-frequency balun; the positive electrode of the first low-frequency balun is connected with one end of the first low-frequency low-noise amplifying unit, and the negative electrode of the first low-frequency balun is connected with one end of the second low-frequency low-noise amplifying unit; the other end of the first low-frequency low-noise amplifying unit is connected with the anode of the second low-frequency balun; the other end of the second low-frequency low-noise amplifying unit is connected with the negative electrode of the second low-frequency balun; one end of the second low-frequency balun is connected with one end of the phase-shifting regulation and control unit; the other end of the phase-shifting regulation unit is connected with a first port of the joint circuit; the positive electrode of the first high-frequency balun is connected with one end of the first high-frequency low-noise amplifying unit, and the negative electrode of the first high-frequency balun is connected with one end of the second high-frequency low-noise amplifying unit; the other end of the first high-frequency low-noise amplifying unit is connected with the anode of the second Gao Pinba; the other end of the second high-frequency low-noise amplifying unit is connected with the negative electrode of the second Gao Pinba; one end of the second Gao Pinba is connected with a second port of the joint router; the third port of the combiner is used as a signal output end.
Further, the frequency divider and the combiner are of a differential structure and each comprises a high-pass filter and a low-pass filter; the low-pass filter comprises an inductor L1, an inductor L2, an inductor L3, an inductor L4, an inductor L5, a capacitor C1 and a capacitor C2, and the high-pass filter comprises an inductor L6, an inductor L7, an inductor L8, an inductor L9, an inductor L10, a capacitor C3 and a capacitor C4;
one end of the inductor L1 is connected with one end of the inductor L8 and is used as an input end of the frequency divider, and the other end of the inductor L1 is respectively connected with one end of the inductor L2 and one end of the inductor L4; the other end of the inductor L2 is respectively connected with one end of the inductor L3 and one end of the inductor L4; the other end of the inductor L3 is used as a low-frequency output end of the frequency divider; the other end of the inductor L4 is connected with the negative electrode of the capacitor C1; the positive electrode of the capacitor C1 is grounded; the other end of the inductor L5 is connected with the negative electrode of the capacitor C2; the positive electrode of the capacitor C2 is grounded;
the other end of the inductor L8 is connected with one end of the inductor L7 and one end of the inductor L9 respectively; the other end of the inductor L7 is connected with one end of the inductor L6 and one end of the inductor L10 respectively; the other end of the inductor L10 is used as a high-frequency output end of the frequency divider; the other end of the inductor L9 is connected with the negative electrode of the capacitor C4; the positive electrode of the capacitor C4 is grounded; the other end of the inductor L6 is connected with the negative electrode of the capacitor C3; the positive electrode of the capacitor C3 is grounded.
Further, the balun circuit employs a microstrip coupling line or an active FET die.
Further, the first low-frequency balun, the first high-frequency balun, the second low-frequency balun and the second Gao Pinba balun are of a dissimilarity structure and each comprise a single microstrip line TL1, a single microstrip line TL2, a coupling microstrip line CL1, a coupling microstrip line CL2, an inductor L1 and a capacitor C1;
one end of a single microstrip line TL1 is respectively connected with one end of a grounding inductor L1 and one end of a capacitor C1, and the other end of the single microstrip line TL1 is used as an input end of a balun; the other end of the capacitor C1 is connected with a port 2 of the coupling microstrip line CL 1; the port 1 of the coupling microstrip line CL1 is grounded, the port 3 of the coupling microstrip line CL1 is connected with the port 4 of the coupling microstrip line CL2, and the port 4 of the coupling microstrip line CL1 is connected with one end of a single microstrip line TL 2; the port 2 of the coupling microstrip line CL2 is grounded, and the port 3 of the coupling microstrip line CL2 is used as a first output end of the balun; the other end of the single microstrip line TL2 serves as a second output of the balun.
Further, the amplitudes of the differential signals output by the first low-frequency balun and the first high-frequency balun are equal and 180 degrees different.
Further, the first low-frequency low-noise amplifying unit, the second low-frequency low-noise amplifying unit, the first high-frequency low-noise amplifying unit and the second high-frequency low-noise amplifying unit are built by adopting an input matching network, a first stage FET1 die, a direct current bias circuit, an interstage matching circuit, a second stage FET2 die, an output matching network, two grid direct current bias circuits and two drain direct current bias circuits; one end of the input matching network is respectively connected with the grid electrode of the first-stage FET1 tube core and one end of the first grid electrode direct current bias circuit, and the other end of the input matching network is used as the input end of the amplifying unit; the other end of the first grid DC bias circuit is used as a DC voltage input end; the source electrode of the first-stage FET1 die is grounded, and the drain electrode of the first-stage FET1 die is respectively connected with one end of the first drain electrode direct current bias circuit and one end of the interstage matching circuit; the other end of the first drain electrode DC bias circuit is used as a DC voltage input end; the other end of the interstage matching circuit is respectively connected with one end of the second grid direct current bias circuit and the grid of the second stage FET2 die; the other end of the second grid DC bias circuit is used as a DC voltage input end; the source electrode of the second-stage FET2 die is grounded, and the drain electrode of the second-stage FET2 die is respectively connected with one end of the second drain electrode direct current bias circuit and one end of the output matching circuit; the other end of the second drain electrode DC bias circuit is used as a DC voltage input end; the other end of the output matching circuit is used as the output end of the amplifying unit.
Further, the DC operating point of the first stage FET1 die is a low noise operating point; the dc operating point of the second stage FET2 die is a class a power amplifying operating point.
Further, the phase-shifting regulation unit adopts a series microstrip line or a parallel microstrip line.
The beneficial effects of the invention are as follows: the low-noise amplifier circuit can meet ultra-wideband performance of a plurality of octaves and obviously improve the higher harmonic suppression ratio; the phase-shifting regulation unit is introduced, and the frequency divider and the combiner can improve the suppression degree of third harmonic and higher harmonic and solve the problem of gain deterioration of the cross frequency band of the combiner; the second harmonic power can be suppressed using the first low frequency balun, the first high frequency balun, the second low frequency balun, and the second Gao Pinba balun.
Drawings
FIG. 1 is a block diagram of the general circuit topology of the present invention;
FIG. 2 is a circuit diagram of a frequency divider and combiner according to the present invention;
FIG. 3 is a graph of transmission coefficients of a frequency divider and a combiner;
FIG. 4 is a graph of the output phase of the frequency divider and the combiner;
FIG. 5 is a graph showing the comparison of the present invention after the phase shift control of the input output stage;
FIG. 6 is a circuit diagram of an input stage balun and an output stage balun of the present invention;
FIG. 7 is a graph of output amplitude differences for an input stage balun and an output stage balun;
FIG. 8 is a graph of output phase difference of an input stage balun and an output stage balun;
fig. 9 is a schematic block diagram of a circuit of the low noise amplifying unit;
FIG. 10 is a gain diagram of the overall architecture of the present invention;
FIG. 11 is a graph of the noise figure of the overall architecture of the present invention;
FIG. 12 is a graph showing the comparison of the harmonic suppression of the overall architecture and the amplifying unit of the present invention.
Detailed Description
The following description of the embodiments of the present invention is provided to facilitate understanding of the present invention by those skilled in the art, but it should be understood that the present invention is not limited to the scope of the embodiments, and all the inventions which make use of the inventive concept are protected by the spirit and scope of the present invention as defined and defined in the appended claims to those skilled in the art.
As shown in fig. 1, an ultra-wideband high-harmonic rejection ratio low-noise amplifier circuit comprises an input module, a low-noise amplifying module and an output module which are sequentially connected in series; the input module comprises a frequency divider, a first low-frequency balun and a first high-frequency balun; the low-noise amplifying module comprises two first low-frequency low-noise amplifying units and second low-frequency low-noise amplifying units which are connected in parallel, and two first high-frequency low-noise amplifying units and second high-frequency low-noise amplifying units which are connected in parallel; the output module comprises a second low-frequency balun, a second Gao Pinba balun, a phase-shifting regulation and control unit and a combiner;
the first end of the frequency divider is used as a signal input end, the second port of the frequency divider is connected with one end of the first low-frequency balun, and the third port of the frequency divider is connected with one end of the first high-frequency balun; the positive electrode of the first low-frequency balun is connected with one end of the first low-frequency low-noise amplifying unit, and the negative electrode of the first low-frequency balun is connected with one end of the second low-frequency low-noise amplifying unit; the other end of the first low-frequency low-noise amplifying unit is connected with the anode of the second low-frequency balun; the other end of the second low-frequency low-noise amplifying unit is connected with the negative electrode of the second low-frequency balun; one end of the second low-frequency balun is connected with one end of the phase-shifting regulation and control unit; the other end of the phase-shifting regulation unit is connected with a first port of the joint circuit; the positive electrode of the first high-frequency balun is connected with one end of the first high-frequency low-noise amplifying unit, and the negative electrode of the first high-frequency balun is connected with one end of the second high-frequency low-noise amplifying unit; the other end of the first high-frequency low-noise amplifying unit is connected with the anode of the second Gao Pinba; the other end of the second high-frequency low-noise amplifying unit is connected with the negative electrode of the second Gao Pinba; one end of the second Gao Pinba is connected with a second port of the joint router; the third port of the combiner is used as a signal output end.
As shown in fig. 2, the frequency divider and the combiner are of a mutually different structure, and each of the frequency divider and the combiner comprises a high-pass filter and a low-pass filter; the low-pass filter comprises an inductor L1, an inductor L2, an inductor L3, an inductor L4, an inductor L5, a capacitor C1 and a capacitor C2, and the high-pass filter comprises an inductor L6, an inductor L7, an inductor L8, an inductor L9, an inductor L10, a capacitor C3 and a capacitor C4;
one end of the inductor L1 is connected with one end of the inductor L8 and is used as an input end of the frequency divider, and the other end of the inductor L1 is respectively connected with one end of the inductor L2 and one end of the inductor L4; the other end of the inductor L2 is respectively connected with one end of the inductor L3 and one end of the inductor L4; the other end of the inductor L3 is used as a low-frequency output end of the frequency divider; the other end of the inductor L4 is connected with the negative electrode of the capacitor C1; the positive electrode of the capacitor C1 is grounded; the other end of the inductor L5 is connected with the negative electrode of the capacitor C2; the positive electrode of the capacitor C2 is grounded;
the other end of the inductor L8 is connected with one end of the inductor L7 and one end of the inductor L9 respectively; the other end of the inductor L7 is connected with one end of the inductor L6 and one end of the inductor L10 respectively; the other end of the inductor L10 is used as a high-frequency output end of the frequency divider; the other end of the inductor L9 is connected with the negative electrode of the capacitor C4; the positive electrode of the capacitor C4 is grounded; the other end of the inductor L6 is connected with the negative electrode of the capacitor C3; the positive electrode of the capacitor C3 is grounded.
The balun circuit employs a microstrip coupling line or an active FET die.
As shown in fig. 6, the first low-frequency balun, the first high-frequency balun, the second low-frequency balun, and the second Gao Pinba balun are of a mutually different structure, and each of the first and second low-frequency balun, the second Gao Pinba balun includes a single microstrip line TL1, a single microstrip line TL2, a coupling microstrip line CL1, a coupling microstrip line CL2, an inductor L1, and a capacitor C1;
one end of a single microstrip line TL1 is respectively connected with one end of a grounding inductor L1 and one end of a capacitor C1, and the other end of the single microstrip line TL1 is used as an input end of a balun; the other end of the capacitor C1 is connected with a port 2 of the coupling microstrip line CL 1; the port 1 of the coupling microstrip line CL1 is grounded, the port 3 of the coupling microstrip line CL1 is connected with the port 4 of the coupling microstrip line CL2, and the port 4 of the coupling microstrip line CL1 is connected with one end of a single microstrip line TL 2; the port 2 of the coupling microstrip line CL2 is grounded, and the port 3 of the coupling microstrip line CL2 is used as a first output end of the balun; the other end of the single microstrip line TL2 serves as a second output of the balun.
The differential signals output by the first low-frequency balun and the first high-frequency balun are equal in amplitude and 180 degrees different in phase.
As shown in fig. 9, the first low-frequency low-noise amplifying unit, the second low-frequency low-noise amplifying unit, the first high-frequency low-noise amplifying unit and the second high-frequency low-noise amplifying unit are all built by adopting an input matching network, a first stage FET1 die, a direct current bias circuit, an inter-stage matching circuit, a second stage FET2 die, an output matching network, two grid direct current bias circuits and two drain direct current bias circuits; one end of the input matching network is respectively connected with the grid electrode of the first-stage FET1 tube core and one end of the first grid electrode direct current bias circuit, and the other end of the input matching network is used as the input end of the amplifying unit; the other end of the first grid DC bias circuit is used as a DC voltage input end; the source electrode of the first-stage FET1 die is grounded, and the drain electrode of the first-stage FET1 die is respectively connected with one end of the first drain electrode direct current bias circuit and one end of the interstage matching circuit; the other end of the first drain electrode DC bias circuit is used as a DC voltage input end; the other end of the interstage matching circuit is respectively connected with one end of the second grid direct current bias circuit and the grid of the second stage FET2 die; the other end of the second grid DC bias circuit is used as a DC voltage input end; the source electrode of the second-stage FET2 die is grounded, and the drain electrode of the second-stage FET2 die is respectively connected with one end of the second drain electrode direct current bias circuit and one end of the output matching circuit; the other end of the second drain electrode DC bias circuit is used as a DC voltage input end; the other end of the output matching circuit is used as the output end of the amplifying unit.
The direct current operating point of the first stage FET1 die is a low noise operating point; the dc operating point of the second stage FET2 die is a class a power amplifying operating point.
The phase-shifting regulating unit adopts a series microstrip line or a parallel microstrip line.
In one embodiment of the invention, the frequency band of the input broadband signal is 2-7 GHz, and the balun circuit adopts a microstrip coupling line. The broadband signal is input to the frequency divider, the high-frequency signal and the low-frequency signal are output by one way and two ways respectively, and the isolation degree of the cross frequency bands of the two ways of signals is slightly poor; when the frequency divider is used as a combiner, the frequency and power synthesis of the cross frequency band is deteriorated, and the gain and output power are reduced in the cross frequency band, a phase shift regulating unit is introduced to tune the phase of the cross frequency band, so as to compensate the deterioration phenomenon of the combiner. The input matching network of the low-noise amplifying unit provided by the invention matches the input impedance of the first-stage FET1 tube core with the impedance of the balun output port, and a DC blocking capacitor is added; the dc operating point of the first stage FET1 die is preferably a low noise operating point; the direct current bias circuit applies external power supply to the first stage FET1 die and suppresses radio frequency signals; the interstage matching circuit matches the first stage FET1 die output impedance with the second stage FET2 die input impedance; the DC operating point of the second stage FET2 die is preferably a class A power amplifying operating point; the output matching network matches the output impedance of the second stage FET2 die to the port impedance of the output stage balun. The low noise amplifying module in the invention can adopt any low noise amplifying unit, and is not limited to the structure of the low noise amplifying unit provided by the invention.
As shown in fig. 3 and 4, the frequency division point of the frequency divider is 3.7GHz, signals are output from the low frequency output end of the frequency divider in the frequency band of 2-3.7 GHz, and signals are output from the high frequency output end of the frequency divider in the frequency band of 3.7-7 GHz. In both fig. 3 and 4, the crossover section appears around 3.7 GHz. As shown in fig. 5, the introduced phase-shift regulating unit tunes the phase of the cross frequency band, compensates for the degradation phenomenon of the combiner, and reduces the transmission coefficient loss to within 0.5 dB.
As shown in fig. 7 and 8, the input stage balun and the output stage balun have good amplitude-phase balance, the second harmonic output power is obviously suppressed, and the suppression ratio is improved.
As shown in fig. 10, the noise figure curve amplitude is not greatly changed, and the stable transformation is within a certain range; as shown in fig. 11, the gain curve floats within a certain range; from this, it is clear that the harmonic suppression method of the present invention does not seriously deteriorate the noise figure, and the gain flatness is very flat in the cross frequency band. The gain flatness in the frequency band of 2-7 GHz is within + -0.5 dB, and the noise coefficient is below 3 dB.
As shown in fig. 12, the present invention is compared with the second and third harmonic suppression degree of the low noise amplifier. In the frequency band of 2-7 GHz, the second harmonic suppression degree and the third harmonic suppression degree of the low-noise amplifier are both below 40dBc, and the second harmonic suppression degree is 90dBc at the minimum and the third harmonic suppression degree is 70dBc at the minimum, so that the invention can obviously improve the suppression ratio of each higher harmonic.
In conclusion, the ultra-wideband performance of a plurality of octaves can be met, and the higher harmonic suppression ratio is obviously improved; the phase-shifting regulation unit is introduced, and the frequency divider and the combiner can improve the suppression degree of third harmonic and higher harmonic and solve the problem of gain deterioration of the cross frequency band of the combiner; the second harmonic power can be suppressed using the first low frequency balun, the first high frequency balun, the second low frequency balun, and the second Gao Pinba balun.
Claims (8)
1. An ultra-wideband high-harmonic rejection ratio low-noise amplifier circuit is characterized in that: the low-noise amplifier comprises an input module, a low-noise amplifying module and an output module which are sequentially connected in series; the input module comprises a frequency divider, a first low-frequency balun and a first high-frequency balun; the low-noise amplifying module comprises a first low-frequency low-noise amplifying unit and a second low-frequency low-noise amplifying unit which are connected in parallel, and a first high-frequency low-noise amplifying unit and a second high-frequency low-noise amplifying unit which are connected in parallel; the output module comprises a second low-frequency balun, a second Gao Pinba balun, a phase-shifting regulation and control unit and a combiner;
the first end of the frequency divider is used as a signal input end, the second port of the frequency divider is connected with one end of the first low-frequency balun, and the third port of the frequency divider is connected with one end of the first high-frequency balun; the positive electrode of the first low-frequency balun is connected with one end of the first low-frequency low-noise amplifying unit, and the negative electrode of the first low-frequency balun is connected with one end of the second low-frequency low-noise amplifying unit; the other end of the first low-frequency low-noise amplifying unit is connected with the anode of the second low-frequency balun; the other end of the second low-frequency low-noise amplifying unit is connected with the negative electrode of the second low-frequency balun; one end of the second low-frequency balun is connected with one end of the phase-shifting regulation and control unit; the other end of the phase-shifting regulation unit is connected with a first port of the joint circuit; the positive electrode of the first high-frequency balun is connected with one end of the first high-frequency low-noise amplifying unit, and the negative electrode of the first high-frequency balun is connected with one end of the second high-frequency low-noise amplifying unit; the other end of the first high-frequency low-noise amplifying unit is connected with the anode of the second Gao Pinba; the other end of the second high-frequency low-noise amplifying unit is connected with the negative electrode of the second Gao Pinba amplifier; one end of the second Gao Pinba is connected with a second port of the joint router; the third port of the combiner is used as a signal output end.
2. The ultra wideband high harmonic rejection ratio low noise amplifier circuit of claim 1, wherein: the frequency divider and the combiner are of a dissimilarity structure and both comprise a high-pass filter and a low-pass filter; the low-pass filter comprises an inductor L1, an inductor L2, an inductor L3, an inductor L4, an inductor L5, a capacitor C1 and a capacitor C2, and the high-pass filter comprises an inductor L6, an inductor L7, an inductor L8, an inductor L9, an inductor L10, a capacitor C3 and a capacitor C4;
one end of the inductor L1 is connected with one end of the inductor L8 and is used as an input end of the frequency divider, and the other end of the inductor L1 is respectively connected with one end of the inductor L2 and one end of the inductor L4; the other end of the inductor L2 is connected with one end of the inductor L3 and one end of the inductor L4 respectively; the other end of the inductor L3 is used as a low-frequency output end of the frequency divider; the other end of the inductor L4 is connected with the negative electrode of the capacitor C1; the positive electrode of the capacitor C1 is grounded; the other end of the inductor L5 is connected with the negative electrode of the capacitor C2; the positive electrode of the capacitor C2 is grounded;
the other end of the inductor L8 is connected with one end of the inductor L7 and one end of the inductor L9 respectively; the other end of the inductor L7 is connected with one end of the inductor L6 and one end of the inductor L10 respectively; the other end of the inductor L10 is used as a high-frequency output end of the frequency divider; the other end of the inductor L9 is connected with the negative electrode of the capacitor C4; the positive electrode of the capacitor C4 is grounded; the other end of the inductor L6 is connected with the negative electrode of the capacitor C3; the positive electrode of the capacitor C3 is grounded.
3. The ultra wideband high harmonic rejection ratio low noise amplifier circuit of claim 1, wherein: the balun circuit employs a microstrip coupling line or an active FET die.
4. A low noise amplifier circuit of ultra wideband high harmonic rejection ratio according to claim 3, wherein: the first low-frequency balun, the first high-frequency balun, the second low-frequency balun and the second Gao Pinba balun are of a dissimilarity structure and each comprise a single microstrip line TL1, a single microstrip line TL2, a coupling microstrip line CL1, a coupling microstrip line CL2, an inductor L1 and a capacitor C1;
one end of the single microstrip line TL1 is connected with one end of a grounding inductor L1 and one end of a capacitor C1 respectively, and the other end of the single microstrip line TL1 is used as an input end of the balun; the other end of the capacitor C1 is connected with a port 2 of the coupling microstrip line CL 1; the port 1 of the coupling microstrip line CL1 is grounded, the port 3 of the coupling microstrip line CL1 is connected with the port 4 of the coupling microstrip line CL2, and the port 4 of the coupling microstrip line CL1 is connected with one end of a single microstrip line TL 2; the port 2 of the coupling microstrip line CL2 is grounded, and the port 3 of the coupling microstrip line CL2 is used as a first output end of the balun; the other end of the single microstrip line TL2 serves as a second output of the balun.
5. The ultra wideband high harmonic rejection ratio low noise amplifier circuit according to claim 4, wherein: the amplitudes of the differential signals output by the first low-frequency balun and the first high-frequency balun are equal and 180-degree phase difference.
6. The ultra wideband high harmonic rejection ratio low noise amplifier circuit of claim 1, wherein: the first low-frequency low-noise amplifying unit, the second low-frequency low-noise amplifying unit, the first high-frequency low-noise amplifying unit and the second high-frequency low-noise amplifying unit are all built by adopting an input matching network, a first stage FET1 die, a direct current bias circuit, an interstage matching circuit, a second stage FET2 die, an output matching network, two grid direct current bias circuits and two drain direct current bias circuits; one end of the input matching network is respectively connected with the grid electrode of the first-stage FET1 tube core and one end of the first grid electrode direct current bias circuit, and the other end of the input matching network is used as the input end of the amplifying unit; the other end of the first grid direct current bias circuit is used as a direct current voltage input end; the source electrode of the first-stage FET1 die is grounded, and the drain electrode of the first-stage FET1 die is respectively connected with one end of the first drain electrode direct current bias circuit and one end of the interstage matching circuit; the other end of the first drain electrode direct current bias circuit is used as a direct current voltage input end; the other end of the interstage matching circuit is respectively connected with one end of the second grid direct current bias circuit and the grid of the second stage FET2 die; the other end of the second grid direct current bias circuit is used as a direct current voltage input end; the source electrode of the second-stage FET2 die is grounded, and the drain electrode of the second-stage FET2 die is respectively connected with one end of the second drain electrode direct current bias circuit and one end of the output matching circuit; the other end of the second drain electrode direct current bias circuit is used as a direct current voltage input end; the other end of the output matching circuit is used as the output end of the amplifying unit.
7. The ultra wideband high harmonic rejection ratio low noise amplifier circuit according to claim 6, wherein: the direct current working point of the first stage FET1 tube core is a low noise working point; the DC operating point of the second stage FET2 die is a class A power amplification operating point.
8. The ultra wideband high harmonic rejection ratio low noise amplifier circuit of claim 1, wherein: the phase-shifting regulation and control unit adopts a series microstrip line or a parallel microstrip line.
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| Application Number | Priority Date | Filing Date | Title |
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| CN2023112277457 | 2023-09-21 | ||
| CN202311227745 | 2023-09-21 |
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| CN202311406060.9A Pending CN117353678A (en) | 2023-09-21 | 2023-10-26 | Ultra-wideband high-harmonic suppression ratio low-noise amplifier circuit |
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