CN117352478A - Chip packaging structure and display device - Google Patents

Chip packaging structure and display device Download PDF

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Publication number
CN117352478A
CN117352478A CN202311290342.7A CN202311290342A CN117352478A CN 117352478 A CN117352478 A CN 117352478A CN 202311290342 A CN202311290342 A CN 202311290342A CN 117352478 A CN117352478 A CN 117352478A
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CN
China
Prior art keywords
lead frame
chip
lead
package structure
frame
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN202311290342.7A
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Chinese (zh)
Inventor
闫续博
杨珊珊
黄森鹏
余长治
徐宸科
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Quanzhou Sanan Semiconductor Technology Co Ltd
Original Assignee
Quanzhou Sanan Semiconductor Technology Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Quanzhou Sanan Semiconductor Technology Co Ltd filed Critical Quanzhou Sanan Semiconductor Technology Co Ltd
Priority to CN202311290342.7A priority Critical patent/CN117352478A/en
Publication of CN117352478A publication Critical patent/CN117352478A/en
Pending legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49575—Assemblies of semiconductor devices on lead frames
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49541—Geometry of the lead-frame
    • H01L23/49565—Side rails of the lead frame, e.g. with perforations, sprocket holes

Abstract

The invention provides a chip packaging structure and a display device, wherein the chip packaging structure comprises n LED chips and m lead frames, each LED chip is provided with two terminals, the two terminals are respectively connected to two lead frames in the m lead frames, and the distance between the two lead frames connected with the same LED chip is larger than or equal to 80 mu m. The distance between the lead frames is increased, the migration rate of metal ions can be slowed down, and electric leakage is prevented, so that the service life of the packaging structure is prolonged; in addition, the alloy plating layer containing Ag is formed on the surface of the lead frame, the plating layer containing Ag can increase the light extraction efficiency and brightness of the packaging structure, the rate of metal ion migration can be further slowed down by adding other metals, electric leakage is prevented, and the service life of the packaging structure is effectively prolonged.

Description

Chip packaging structure and display device
Technical Field
The invention belongs to the technical field of semiconductor manufacturing, and particularly relates to a chip packaging structure and a display device.
Background
At present, the chip is fixedly welded on the substrate and then sealed by epoxy resin, but the epoxy resin can be yellowing in the use process, so that the performance of the product is reduced, and therefore, some design packaging adhesives can use silicone resin. However, silicone has poor sealability compared with epoxy, and the package body undergoes metal ion migration phenomenon under the conditions of high humidity, continuous voltage, contact with metals such as silver, or insulators with water absorption and moisture absorption properties, so that the package body fails in leakage.
Disclosure of Invention
In view of the above-described drawbacks of the prior art, the present invention provides a chip package structure and a display device, the chip package structure includes n LED chips and m lead frames, each LED chip has two terminals connected to two lead frames of the m lead frames, respectively, and a pitch of the two lead frames connected to the same LED chip is greater than or equal to 80 μm. The distance between the lead frames is increased, the migration rate of metal ions can be slowed down, and electric leakage is prevented, so that the service life of the packaging structure is prolonged; in addition, the alloy plating layer containing Ag is formed on the surface of the lead frame, the plating layer containing Ag can increase the light extraction efficiency and brightness of the packaging structure, the rate of metal ion migration can be further slowed down by adding other metals, electric leakage is prevented, and the service life of the packaging structure is effectively prolonged.
To achieve the above and other related objects, the present invention provides a chip package structure, comprising:
n LED chips, each comprising two terminals;
a substrate to which n LED chips are fixed, m lead frames being provided on the substrate, two terminals of each LED chip being connected to two lead frames among the m lead frames, n being a natural number of 1 or more, and m=2n, respectively;
the distance between the two lead frames connected with the same LED chip is larger than or equal to 80 mu m.
The invention also provides a display device which comprises a circuit substrate and a plurality of light emitting devices, wherein the light emitting devices comprise the chip packaging structure.
The chip packaging structure and the display device provided by the invention have at least the following beneficial effects:
the chip packaging structure provided by the invention comprises n LED chips and m lead frames, wherein each LED chip is provided with two terminals which are respectively connected to two lead frames in the m lead frames, and the distance between the two lead frames connected with the same LED chip is larger than or equal to 80 mu m. The distance between the lead frames is increased, the migration rate of metal ions can be slowed down, and electric leakage is prevented, so that the service life of the packaging structure is prolonged; in addition, the alloy plating layer containing Ag is formed on the surface of the lead frame, the plating layer containing Ag can increase the light extraction efficiency and brightness of the packaging structure, the rate of metal ion migration can be further slowed down by adding other metals, electric leakage is prevented, and the service life of the packaging structure is effectively prolonged.
The display device provided by the invention comprises the chip packaging structure, so that the display device has the same beneficial effects.
Drawings
Fig. 1 is a top view of a chip package structure according to a first embodiment.
Fig. 2 is a top view of a chip package structure according to a second embodiment.
Fig. 3 is a top view of a chip package structure according to a third embodiment.
Fig. 4 is a perspective view showing a chip package structure according to a third embodiment.
Fig. 5 is a top view of a chip package structure according to a fourth embodiment.
Fig. 6 is a schematic structural diagram of a display device according to a fifth embodiment.
Description of element reference numerals
100. Substrate board
101-104 first to fourth lead frames
105. Fifth lead frame
105 a-105 c first to third portions of five lead frames
106. Sixth lead frame
106 a-106 c first to third portions of a sixth lead frame
107. Seventh lead frame
107 a-107 c first to third portions of a seventh lead frame
108. Eighth lead frame
108 a-108 c first to third portions of an eighth lead frame
109. Ninth lead frame
109 a-109 c first through third portions of a ninth lead frame
110. Tenth lead frame
110 a-110 c first through third portions of a tenth lead frame
200. Die bonding frame
20 LED chip
21. First chip
22. Second chip
23. Third chip
201. Terminal for connecting a plurality of terminals
30. Lead wire
40. Enclosure dam
50. Packaging colloid
1000. Circuit substrate
2000. Light emitting device
Detailed Description
Other advantages and effects of the present invention will become apparent to those skilled in the art from the following disclosure, which describes the embodiments of the present invention with reference to specific examples. The invention may be practiced or carried out in other embodiments that depart from the specific details, and the details of the present description may be modified or varied from the spirit and scope of the present invention.
It should be noted that, the illustrations provided in the present embodiment only illustrate the basic concept of the present invention by way of illustration, but only the components related to the present invention are shown in the illustrations, rather than being drawn according to the number, shape and size of the components in actual implementation, and the form, number, positional relationship and proportion of each component in actual implementation may be changed at will on the premise of implementing the present technical solution, and the layout of the components may be more complex.
Example 1
The present embodiment provides a chip package structure, as shown in fig. 1, including a substrate 100, and a lead frame, an LED chip 20 and a lead 30 are disposed on the substrate 100.
As shown in fig. 1, a first lead frame 101, a second lead frame 102, and a die attach frame 200 are disposed on a substrate 100. As an example, the first lead frame 101, the second lead frame 102, and the die attach frame 200 each have a flat shape, and are arranged flush with and separated from each other; in the Y-axis direction shown in fig. 1, the die attach frame 200 is disposed opposite to the first lead frame 101 and the second lead frame 102; in the X-axis direction shown in fig. 1, the first lead frame 101 and the second lead frame 102 are arranged side by side with a spacing.
As an example, the first lead frame 101, the second lead frame 102, and the die attach frame 200 are made of the same conductive material, and plating layers having a highly reflective material, which can reflect light generated from the chip, are formed on the upper surfaces of the first lead frame 101, the second lead frame 102, and the die attach frame 200, to increase light extraction efficiency and brightness. In the present embodiment, the surfaces of the first lead frame 101, the second lead frame 102 and the die attach frame 200 are formed with an alloy plating layer containing Ag, including but not limited to Ag-Pd alloy, ag-Cu alloy, ag-Ni alloy, on the one hand, ag in the alloy plating layer can reflect light generated from the chip, increasing light extraction efficiency and brightness; on the other hand, the addition of other metals can slow down the migration rate of metal ions and prevent electric leakage, so that the service life of the chip packaging structure is prolonged, and compared with the packaging structure adopting other non-alloy plating layers in the prior art, the service life of the packaging structure adopting the alloy plating layers can be prolonged by 50% -100% on average.
As shown in fig. 1, the LED chip 20 is fixed on the die attach frame 200 by conductive paste. In the present embodiment, the LED chip 20 is a green light chip or a blue light chip, which is an upper surface terminal type chip, and on a surface facing away from the die attach frame 200, the LED chip 20 has two terminals 201, one of the terminals 201 being connected to the first lead frame 101 through the lead 30, and the other terminal 201 being connected to the second lead frame 102 through the lead 30. By way of example, the spacing d between the first leadframe 101 and the second leadframe 102 is 80 μm or more, preferably 80-500 μm, e.g., in an alternative embodiment, the spacing d may be 100 μm, 150 μm, 200 μm, 250 μm, 300 μm, 350 μm, 400 μm, 450 μm, 500 μm, etc. When the surface of the lead frame is provided with an Ag-containing coating, ag ions can migrate, the migration rate of the Ag ions is related to the voltage and the electrode spacing, when the voltage is unchanged, the spacing between the first lead frame 101 and the second lead frame 102 is increased, the migration rate of metal ions between the lead frames can be slowed down, electric leakage is prevented, the service life of the packaging structure is prolonged by 50% -100% on average, and on the basis, the Ag-containing alloy coating is formed on the surfaces of the first lead frame 101, the second lead frame 102 and the die bonding frame 200, so that the service life of the packaging structure can be further prolonged to 80% -250%.
In the present embodiment, the distance d between the first lead frame 101 and the second lead frame 102 can be increased by increasing the distance between the first lead frame 101 and the second lead frame 102 in the X-axis direction, when the area of the package structure is unchanged; in other alternative embodiments, the space d between the first lead frame 101 and the second lead frame 102 may also be increased by reducing the area of the first lead frame 101 and/or the second lead frame 102, where the area of the package structure is unchanged. In practical applications, one of the two ways may be selected to increase the pitch between the lead frames according to the specific situation.
As an example, the leads 30 are used to connect the LED chip 20 with the first and second lead frames 101, 102. In the present embodiment, the lead 30 is a metal wire, for example, made of one of the materials of Al, cu, ag, au, and the metal wire has good electrical conductivity, mechanical strength, thermal stability and cost effectiveness as a lead, and is suitable for various electronic applications and manufacturing requirements.
As shown in fig. 1, the package structure further includes a dam 40 for enclosing the package region. In this embodiment, the top surface of the dam 40 is higher than the upper surface of the LED chip 20, so as to ensure that the encapsulation glue filled in the encapsulation area can effectively encapsulate the first lead frame 101, the second lead frame 102, the die attach frame 200, the LED chip 20 and the leads 30 in the subsequent steps.
As an example, the encapsulation area is filled with an encapsulation compound. In this embodiment, the encapsulant is a transparent resin body, such as a silicone resin or an epoxy resin with high resistance to light and heat, so that the service life of the package structure can be prolonged.
Example two
The present embodiment provides a chip package structure, as shown in fig. 2, including a substrate 100, and a lead frame, an LED chip 20 and a lead 30 are disposed on the substrate 100.
As shown in fig. 2, a third lead frame 103 and a fourth lead frame 104 are provided on the substrate 100. As an example, the third lead frame 103 and the fourth lead frame 104 each have a flat shape, and are arranged flush with and separated from each other; in the Y-axis direction shown in fig. 2, the third lead frame 103 and the fourth lead frame 104 are disposed at an opposite interval.
As an example, the third and fourth lead frames 103 and 104 are made of the same conductive material, and plating layers having a highly reflective material, which can reflect light generated from the chip to increase light extraction efficiency and brightness, are formed on the upper surfaces of the third and fourth lead frames 103 and 104. In the present embodiment, the surfaces of the third lead frame 103 and the fourth lead frame 104 are each formed with an alloy plating layer containing Ag, including but not limited to Ag-Pd alloy, ag-Cu alloy, ag-Ni alloy, on the one hand, ag in the alloy plating layer can reflect light generated from the chip, increasing light extraction efficiency and brightness; on the other hand, the addition of other metals can slow down the migration rate of metal ions and prevent electric leakage, so that the service life of the chip packaging structure is prolonged, and compared with the packaging structure adopting other non-alloy plating layers in the prior art, the service life of the packaging structure adopting the alloy plating layers can be prolonged by 50% -100% on average.
As shown in fig. 2, the LED chip 20 is fixed on the third lead frame 103 by a conductive adhesive. In the present embodiment, the LED chip 20 is a red light chip, the red light chip is a vertical conduction type chip, the LED chip 20 has one terminal (not shown in the drawing) soldered to the third lead frame 103 on a surface near the third lead frame 103, the LED chip 20 has one terminal 201 on a surface facing away from the third lead frame 103, and the terminal 201 is connected to the fourth lead frame 104 through the lead 30. By way of example, the spacing d between the third leadframe 103 and the fourth leadframe 104 is 80 μm or more, preferably 80-500 μm, e.g., in an alternative embodiment, the spacing d may be 100 μm, 150 μm, 200 μm, 250 μm, 300 μm, 350 μm, 400 μm, 450 μm, 500 μm, etc. When the surface of the lead frame is provided with an Ag-containing coating, ag ions can migrate, the migration rate of the Ag ions is related to the voltage and the electrode spacing, when the voltage is unchanged, the spacing between the third lead frame 103 and the fourth lead frame 104 is increased, the migration rate of metal ions between the lead frames can be slowed down, the service life of the packaging structure is prolonged by 50% -100% on average, and on the basis, an Ag-containing alloy coating is formed on the surfaces of the third lead frame 103 and the fourth lead frame 104, so that the service life of the packaging structure can be further prolonged to 80% -250%.
In the present embodiment, the distance d between the third lead frame 103 and the fourth lead frame 104 may be increased by increasing the distance between the third lead frame 103 and the fourth lead frame 104 in the Y-axis direction, when the area of the package structure is unchanged; in other alternative embodiments, the space d between the third lead frame 103 and the fourth lead frame 104 may also be increased by reducing the area of the third lead frame 103 and/or the fourth lead frame 104, where the area of the package structure is unchanged. In practical applications, one of the two ways may be selected to increase the pitch between the lead frames according to the specific situation.
As an example, the leads 30 are used to connect the LED chip 20 with the fourth lead frame 104. In the present embodiment, the lead 30 is a metal wire, for example, made of one of the materials of Al, cu, ag, au, and the metal wire has good electrical conductivity, mechanical strength, thermal stability and cost effectiveness as a lead, and is suitable for various electronic applications and manufacturing requirements.
As shown in fig. 2, the package structure further includes a dam 40 for enclosing the package region. In this embodiment, the top surface of the dam 40 is higher than the upper surface of the LED chip 20, so as to ensure that the encapsulation glue filled in the encapsulation area can effectively encapsulate the third lead frame 103, the fourth lead frame 104, the LED chip 20 and the leads 30 in the subsequent steps.
As an example, the encapsulation area is filled with an encapsulation compound. In this embodiment, the encapsulant is a transparent resin body, such as a silicone resin or an epoxy resin with high resistance to light and heat, so that the service life of the package structure can be prolonged.
Example III
The embodiment provides a chip packaging structure, as shown in fig. 3, which comprises a substrate, and a lead frame, a chip and leads are arranged on the substrate.
As shown in fig. 3, the lead frames include a fifth lead frame 105, a sixth lead frame 106, a seventh lead frame 107, an eighth lead frame 108, a ninth lead frame 109, and a tenth lead frame 110. As an example, the fifth to tenth lead frames 105 to 110 each have a flat shape and are arranged to be flush and separated from each other, and the fifth, seventh, eighth, sixth, tenth and ninth lead frames 105, 107, 108, 106, 110 and 109 are arranged in this order in the clockwise direction; in the X-axis direction shown in fig. 3, the five lead frames 105 and the sixth lead frame 106 are arranged at an opposite interval; in the Y-axis direction shown in fig. 3, the seventh lead frame 107 and the ninth lead frame 109 are symmetrically arranged on both sides of the fifth lead frame 105, respectively, and the eighth lead frame 108 and the tenth lead frame 110 are symmetrically arranged on both sides of the sixth lead frame 106, respectively.
As an example, the fifth to tenth lead frames 105 to 110 are made of the same conductive material, and plating layers having a highly reflective material, which can reflect light generated from the chip to increase light extraction efficiency and brightness, are formed on the upper surfaces of the fifth to tenth lead frames 105 to 110. In the present embodiment, the fifth to tenth lead frames 105 to 110 are each formed with an Ag-containing alloy plating layer including, but not limited to, ag-Pd alloy, ag-Cu alloy, ag-Ni alloy, on the one hand, ag in the alloy plating layer being capable of reflecting light generated from the chip, increasing light extraction efficiency and brightness; on the other hand, the addition of other metals can slow down the migration rate of metal ions and prevent electric leakage, so that the service life of the chip packaging structure is prolonged, and compared with the packaging structure adopting other non-alloy plating layers in the prior art, the service life of the packaging structure adopting the alloy plating layers can be prolonged by 50% -100% on average.
As shown in fig. 3, the fifth lead frame 105 includes a first portion 105a, a second portion 105b, and a third portion 105c that are in communication, wherein the first portion 105a is located at an edge of the package structure, the second portion 105b is used to connect the first portion 105a and the third portion 105c, and the third portion 105c has a chip mounted thereon. As an example, the chip is fixed on the third portion 105c of the fifth lead frame by conductive adhesive.
In the present embodiment, the third portion 105c has an LED chip mounted thereon, including the first chip 21, the second chip 22, and the third chip 23. The first chip 21 is a red light chip, which is a vertical conduction type chip, and on a surface near the third portion 105c of the fifth lead frame, the first chip 21 has one terminal soldered to the fifth lead frame 105, on a surface facing away from the fifth lead frame 105, the first chip 21 has the other terminal, and the terminal is connected to the sixth lead frame 106 through the lead 30; the first chip 21 is located near the sixth lead frame 106 so as to be electrically connected to the sixth lead frame 106. The second chip 22 is a green chip, which is an upper surface terminal type chip, and the second chip 22 has two terminals on a surface facing away from the fifth lead frame 105; the second chip 22 is located near the seventh lead frame 107 and the eighth lead frame 108 so as to be electrically connected to the seventh lead frame 107 and the eighth lead frame 108. The third chip 23 is a blue light chip, which is an upper surface terminal type chip, and the third chip 23 has two terminals on a surface facing away from the fifth lead frame 105; the third chip 23 is located near the ninth lead frame 109 and the tenth lead frame 110 so as to be electrically connected to the ninth lead frame 109 and the tenth lead frame 110. In an alternative embodiment, the number of light emitting chips may be smaller, or may be larger, for example, one chip emitting green light may be added, or chips emitting colors other than red, green, blue (e.g., yellow or cyan) light may be added. In another alternative embodiment, a plurality of light emitting chips mounted in one chip package structure may emit light of completely different colors from each other, or some light emitting chips may be configured to emit light of the same color, while other light emitting chips emit light of different colors, or all light emitting chips emit light of the same color.
As shown in fig. 3, the sixth lead frame 106 also includes a first portion 106a, a second portion 106b and a third portion 106c that are in communication, wherein the first portion 106a is located at an edge of the package structure, the second portion 106b is used to connect the first portion 106a and the third portion 106c, and the third portion 106c is electrically connected to the first chip 21 through the lead 30. As an example, a spacing d between the fifth lead frame 105 and the sixth lead frame 106 1 80 μm or more, specifically, in the Y-axis direction shown in FIG. 3, a distance d between the fifth lead frame 105 and the sixth lead frame third portion 106c 1 Greater than or equal to 80 μm, preferably 80-500 μm, e.g., in an alternative embodiment, the spacing d 1 May be 100 μm, 150 μm, 200 μm, 250 μm, 300 μm, 350 μm, 400 μm, 450 μm, 500 μm, etc. When the surface of the lead frame is provided with the Ag-containing coating, ag ions can migrate, the migration rate of the Ag ions is related to the voltage and the electrode spacing, and when the voltage is unchanged, the spacing between the fifth lead frame 105 and the sixth lead frame 106 is increased, so that the migration rate of metal ions between the lead frames can be further slowed down, and the service life of the chip packaging structure is prolonged.
In the present embodiment, as shown in fig. 3, the sixth lead frame second portion 106b and the third portion 106c can be increased to the fifth lead frame second portion 105b and the third portion 105cDistance in Y-axis direction to increase the distance d between the fifth lead frame 105 and the sixth lead frame 106 1 At this time, the area of the packaging structure is unchanged; in other alternative embodiments, the spacing d between the fifth leadframe 105 and the sixth leadframe 106 may also be increased by reducing the area of the fifth leadframe third portion 105c and/or the sixth leadframe third portion 106c 1 At this time, the area of the package structure is unchanged. In practical applications, one of the two ways may be selected to increase the pitch between the lead frames according to the specific situation.
As shown in fig. 3, the seventh lead frame 107 also includes a first portion 107a, a second portion 107b and a third portion 107c that are in communication, wherein the first portion 107a is located at an edge of the package structure, the second portion 107b is used to connect the first portion 107a and the third portion 107c, and the third portion 107c is connected to one terminal of the second chip 22 through the lead 30, thereby achieving an electrical connection with the second chip 22.
As shown in fig. 3, the eighth lead frame 108 also includes a first portion 108a, a second portion 108b and a third portion 108c that are in communication, wherein the first portion 108a is located at an edge of the package structure, the second portion 108b is used to connect the first portion 108a and the third portion 108c, and the third portion 108c is connected to another terminal of the second chip 22 through the lead 30, thereby achieving an electrical connection with the second chip 22.
As an example, a distance d between the seventh lead frame 107 and the eighth lead frame 108 2 80 μm or more, specifically, a distance d between the seventh lead frame third portion 107c and the eighth lead frame third portion 108c in the X-axis direction shown in FIG. 3 2 Greater than or equal to 80 μm, preferably 80-500 μm, e.g., in an alternative embodiment, the spacing d 2 May be 100 μm, 150 μm, 200 μm, 250 μm, 300 μm, 350 μm, 400 μm, 450 μm, 500 μm, etc. When the surface of the lead frame is provided with a plating layer containing Ag, ag ions can migrate, the migration rate of the Ag ions is related to the voltage and the electrode spacing, and when the voltage is unchanged, the spacing between the seventh lead frame 107 and the eighth lead frame 108 is increased, so that the metal ions in each lead frame can be further slowed downThe rate of migration between the shelves thereby extending the useful life of the chip package structure.
In the present embodiment, as shown in fig. 3, the distance d between the seventh lead frame 107 and the eighth lead frame 108 can be increased by increasing the length of the seventh lead frame second portion 107b and/or the eighth lead frame second portion 108b in the X-axis direction 2 At this time, the area of the packaging structure is unchanged; in other alternative embodiments, the spacing d between the seventh lead frame 107 and the eighth lead frame 108 may also be increased by reducing the area of the seventh lead frame third portion 107c and/or the eighth lead frame third portion 108c 2 At this time, the area of the package structure is unchanged. In practical applications, one of the two ways may be selected to increase the pitch between the lead frames according to the specific situation.
As shown in fig. 3, the ninth lead frame 109 also includes a first portion 109a, a second portion 109b and a third portion 109c that are in communication, wherein the first portion 109a is located at an edge of the package structure, the second portion 109b is used to connect the first portion 109a and the third portion 109c, and the third portion 109c is connected to one terminal of the third chip 23 through the lead 30, thereby achieving an electrical connection with the third chip 23.
As shown in fig. 3, the tenth lead frame 110 also includes a first portion 110a, a second portion 110b and a third portion 110c that are in communication, wherein the first portion 110a is located at an edge of the package structure, the second portion 110b is used to connect the first portion 110a and the third portion 110c, and the third portion 110c is connected to another terminal of the third chip 23 through the lead 30, thereby achieving an electrical connection with the third chip 23.
As an example, a spacing d between the ninth lead frame 109 and the tenth lead frame 110 3 80 μm or more, specifically, a distance d between the ninth lead frame third portion 109c and the tenth lead frame third portion 110c in the X-axis direction shown in FIG. 3 3 Greater than or equal to 80 μm, preferably 80-500 μm, e.g., in an alternative embodiment, the spacing d 3 May be 100 μm, 150 μm, 200 μm, 250 μm, 300 μm, 350 μm, 400 μm, 450 μm, 500 μm, etc. When the lead frame surface is provided withWhen the Ag plating layer is included, ag ions migrate, and the migration rate of Ag ions is related to the voltage and the electrode spacing, and when the voltage is unchanged, the spacing between the ninth lead frame 109 and the tenth lead frame 110 is increased, so that the migration rate of metal ions between the lead frames can be further slowed down, and the service life of the chip package structure is prolonged.
In the present embodiment, as shown in fig. 3, the distance d between the ninth lead frame 109 and the tenth lead frame 110 may be increased by increasing the length of the ninth lead frame second portion 109b and/or the tenth lead frame second portion 110b in the X-axis direction 3 At this time, the area of the packaging structure is unchanged; in other alternative embodiments, the spacing d between the ninth lead frame 109 and the tenth lead frame 110 may also be increased by reducing the area of the ninth lead frame third portion 109c and/or the tenth lead frame third portion 110c 3 At this time, the area of the package structure is unchanged. In practical applications, one of the two ways may be selected to increase the pitch between the lead frames according to the specific situation.
As an example, a spacing d between the fifth lead frame 105 and the sixth lead frame 106 1 A distance d between the seventh lead frame 107 and the eighth lead frame 108 2 And a distance d between the ninth lead frame 109 and the tenth lead frame 110 3 May be equal or unequal. The intervals among the lead frames are all set to be more than or equal to 80 mu m, so that the migration rate of metal ions among the lead frames can be slowed down, electric leakage is prevented, the service life of the packaging structure is prolonged by 50% -100% on average, and on the basis, an alloy plating layer containing Ag is formed on the surface of the lead frames, so that the service life of the packaging structure is further prolonged to 80% -250%.
In the present embodiment, the first chip 21, the second chip 22, and the third chip 23 are connected to lead frames different from each other, respectively, so that the outputs of the first chip 21, the second chip 22, and the third chip 23 can be controlled independently of each other, and light of any intensity and tone can be emitted from the package structure. For packages with other numbers of chips, the number of lead frames is twice the number of chips.
As an example, leads 30 are used to connect the chip with the respective lead frames. In the present embodiment, the lead 30 is a metal wire, for example, made of one of the materials of Al, cu, ag, au, and the metal wire has good electrical conductivity, mechanical strength, thermal stability and cost effectiveness as a lead, and is suitable for various electronic applications and manufacturing requirements.
As shown in fig. 3, the package structure further includes a dam 40, and the dam 40 is overlapped over the fifth lead frame second portion 105b, the sixth lead frame second portion 106b, the seventh lead frame second portion 107b, the eighth lead frame second portion 108b, the ninth lead frame second portion 109b, and the tenth lead frame second portion 110b in a direction perpendicular to the plane formed by the X-Y axes, for enclosing a package region. In this embodiment, as shown in fig. 4, the top surface of the dam 40 is higher than the upper surfaces of the first to third chips 21 to 23, so as to ensure that the encapsulant 50 filled in the packaging region can effectively encapsulate the fifth to tenth lead frames 105 to 110, the first to third chips 21 to 23 and the leads 30 in the subsequent steps.
As shown in fig. 4, the encapsulation area is filled with an encapsulant 50. In this embodiment, the encapsulant 50 is made of a transparent resin, such as a silicone or epoxy resin with high resistance to light and heat, so as to prolong the service life of the package structure.
Example IV
The embodiment also provides a chip package structure, as shown in fig. 5, which includes a substrate, and a lead frame, a chip and leads are disposed on the substrate. The lead frames include a fifth lead frame 105, a sixth lead frame 106, a seventh lead frame 107, an eighth lead frame 108, a ninth lead frame 109, and a tenth lead frame 110. The chips include a first chip 21, a second chip 22 and a third chip 23.
The chip package structure of the present embodiment is the same as that of the third embodiment, and will not be described here again. The difference is that, as shown in fig. 5, in the present embodiment, the third portion 105c of the fifth lead frame has a protrusion, and the first chip 21 is mounted on the protrusionIn the third embodiment, the area of the third portion 105c of the fifth lead frame is smaller than that of the chip package structure provided in the third embodiment, and the spacing between the protruding portion and the third portion 106c of the sixth lead frame is larger, which is helpful for increasing the spacing d between the fifth lead frame 105 and the third portion 106c of the sixth lead frame 1 The migration rate of metal ions between the lead frames is slowed down, so that the service life of the chip packaging structure is prolonged.
Example five
The present embodiment provides a display apparatus, as shown in fig. 6, including a circuit substrate 1000 and a plurality of light emitting devices 2000, the plurality of light emitting devices 2000 being disposed on the circuit substrate 1000 at intervals. As an example, the light emitting device 2000 includes the chip package structure described in the first embodiment or the second embodiment or the third embodiment or the fourth embodiment.
The above embodiments are merely illustrative of the principles of the present invention and its effectiveness, and are not intended to limit the invention. Modifications and variations may be made to the above-described embodiments by those skilled in the art without departing from the spirit and scope of the invention. Accordingly, it is intended that all equivalent modifications and variations of the invention be covered by the claims, which are within the ordinary skill of the art, be within the spirit and scope of the present disclosure.

Claims (15)

1. A chip package structure, comprising:
n LED chips, each comprising two terminals;
a substrate to which n LED chips are fixed, m lead frames being provided on the substrate, two terminals of each LED chip being connected to two lead frames among the m lead frames, n being a natural number of 1 or more, and m=2n, respectively;
the distance between the two lead frames connected with the same LED chip is larger than or equal to 80 mu m.
2. The chip package structure of claim 1, wherein the leadframe includes a first portion, a second portion, and a third portion in communication, wherein the first portion is located at an edge of the package structure, the second portion is for communicating the first portion and the third portion, and the third portion is for a lead.
3. The chip package structure according to claim 1, wherein a length of the second portion is shortened so that a pitch of two lead frames to which the same LED chip is connected is 80 μm or more.
4. The chip package structure according to claim 1, wherein an area of the third portion is reduced so that a pitch of two lead frames to which the same LED chip is connected is 80 μm or more.
5. The chip package structure according to claim 1, wherein n=1, the LED chip is a green light chip or a blue light chip, a die bonding frame is disposed on the substrate, the LED chip is fixed on the die bonding frame, the lead frame includes a first lead frame and a second lead frame disposed opposite to the die bonding frame, and the first lead frame and the second lead frame are disposed side by side at intervals.
6. The chip package structure according to claim 1, wherein n=1, the LED chip is a red light chip, the lead frame includes a third lead frame and a fourth lead frame disposed at opposite intervals, one terminal of the vertical conduction type chip is soldered to the third lead frame, and the other terminal is connected to the fourth lead frame via a wire.
7. The chip package structure according to claim 1, wherein n=3, the LED chip includes a green light chip, a blue light chip, and a red light chip, and the lead frames include a fifth lead frame, a sixth lead frame, a seventh lead frame, an eighth lead frame, a ninth lead frame, and a tenth lead frame; wherein,
the green light chip, the blue light chip and the red light chip are positioned on the fifth lead frame, the red light chip is electrically connected with the sixth lead frame through leads, the green light chip is electrically connected with the seventh lead frame and the eighth lead frame through leads respectively, and the blue light chip is electrically connected with the ninth lead frame and the tenth lead frame through leads respectively.
8. The chip package structure according to any one of claims 5 to 7, wherein an Ag-containing alloy plating layer is formed on a surface of the lead frame.
9. The chip package structure according to claim 8, wherein the alloy plating layer is one of Ag-Pd alloy, ag-Cu alloy, ag-Ni alloy.
10. The chip package structure of claim 1, further comprising a dam for enclosing the package region.
11. The chip package structure according to claim 10, wherein the package region is filled with an encapsulant, the encapsulant encapsulating the lead frame, the LED chip, and leads connecting terminals of the LED chip and the lead frame.
12. The chip package structure of claim 11, wherein the encapsulant is one of silicone and epoxy.
13. The chip package structure of claim 11, wherein the leads are made of one of the materials Al, cu, ag, au.
14. The chip package structure according to claim 1, wherein a pitch between two lead frames to which the same LED chip is connected is 80 μm to 500 μm.
15. A display device comprising a circuit substrate and a plurality of light emitting devices, wherein the light emitting devices comprise the chip package structure of any one of claims 1 to 14.
CN202311290342.7A 2023-10-08 2023-10-08 Chip packaging structure and display device Pending CN117352478A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202311290342.7A CN117352478A (en) 2023-10-08 2023-10-08 Chip packaging structure and display device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202311290342.7A CN117352478A (en) 2023-10-08 2023-10-08 Chip packaging structure and display device

Publications (1)

Publication Number Publication Date
CN117352478A true CN117352478A (en) 2024-01-05

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Family Applications (1)

Application Number Title Priority Date Filing Date
CN202311290342.7A Pending CN117352478A (en) 2023-10-08 2023-10-08 Chip packaging structure and display device

Country Status (1)

Country Link
CN (1) CN117352478A (en)

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