CN117350936A - A layout through hole defect detection method, device and automatic reinforcement method - Google Patents

Abstract

The invention discloses a method and a device for detecting defects of a layout through hole and an automatic reinforcement method, wherein the method for detecting the defects of the layout through hole comprises the following steps: acquiring metal patterns contained in a first wiring network and a second wiring network in a target layout; respectively acquiring overlapping areas of each metal pattern in the first wiring network and the second wiring network, which are overlapped with the metal patterns in the upper and lower non-adjacent metal layers, and performing space verification, generating an intermediate layer metal pattern in the area passing the space verification, and extracting each first overlapping area of the generated intermediate layer metal pattern and the metal patterns in the upper and lower adjacent metal layers; and extracting second overlapping areas of each metal pattern in the wiring network and the metal patterns in the upper and lower adjacent metal layers, performing through hole defect verification on each first and each second overlapping area, and outputting the first overlapping area and the second overlapping area with the through hole defects. The invention can be used for accurately and rapidly detecting and reinforcing the defects of the through holes in the layout.

Description

A layout through hole defect detection method, device and automatic reinforcement method

Technical field

The invention relates to the technical field of integrated circuit layout design defect inspection, and in particular to a layout through hole defect detection method, device and automatic reinforcement method.

Background technique

With the advancement of semiconductor integrated circuit manufacturing processes, the characteristic sizes of transistors are getting smaller and smaller, the integration of circuits per unit area is higher, there are more and more layers of metal connections, and the density of interconnections is getting higher and higher. According to statistics, more than 70% of the causes of product functional failure originate from interconnection line defects. When designing the internal layout of the chip, different levels of metal inside the chip are used to alternately arrange the upper and lower layers vertically and horizontally. The upper and lower metal layers are connected through different through holes to form a grid-like power line network and ground lines. Network is used to ensure the power supply inside the chip.

Defects such as no through-hole points being set at the connection points in the upper and lower metal layers or no through-holes of corresponding shapes being added at the through-hole point positions often occur. As the layout design becomes more and more complex, it is necessary to inspect the through-hole defects in the layout. It also tends to be difficult. At present, through-hole defect detection methods are mainly divided into the following three types: the first is manual inspection, which requires a large workload and has the risk of missing inspections in the inspection results; the second method is through automated tool inspection, but this method This method cannot accurately locate areas with insufficient through hole density, and the software cost is high; the third method is performance testing, which connects different levels of metal lines to test pads for performance testing. Although this method can ensure detection Accurate, but requires the use of test metal lines and test pads, which is cumbersome to operate and is not suitable for highly integrated layout designs. In layout design where multiple metal layers are connected, how to accurately and quickly verify whether the metal layers are fully connected is a technical problem that needs to be solved urgently.

Contents of the invention

This application provides a layout through hole defect detection method, device and automatic reinforcement method for accurately and quickly detecting through hole defects in the layout.

In the first aspect, this application provides a method for detecting layout through hole defects, including:

Obtain all metal graphics contained in the first wiring network and the second wiring network in the target layout;

Obtain the overlapping areas in each metal pattern and the metal patterns in the upper and lower non-adjacent metal layers in the first wiring network and the second wiring network respectively, perform spatial verification on each overlapping area, and pass the space Generate an intermediate layer metal pattern in each overlapping area of the verification, and extract each first overlapping area where the generated intermediate layer metal pattern overlaps with the metal patterns in the upper and lower adjacent metal layers;

Extract the second overlapping area where each metal pattern in the first wiring network and the second wiring network exists and the metal pattern in the upper and lower adjacent metal layers, respectively, for each first overlapping area and each second overlapping area Perform through-hole defect verification and output the first overlapping area and the second overlapping area where through-hole defects exist; wherein, when there are no through-holes in the overlapping area and there is space for placing through-holes in the overlapping area, When, it is determined that there is a through hole defect in the overlapping area.

In this way, after obtaining all the metal graphics in the target layout, further based on the positional relationship of the metal graphics, the overlapping areas in the wiring network between the metal graphics and the metal graphics in the upper and lower non-adjacent metal layers are obtained, and each overlapping area is The area is spatially verified and the middle layer metal pattern is generated in the overlapping area that passes the spatial verification, and each first overlapping area in which the middle layer metal pattern overlaps with upper and lower adjacent metal patterns is extracted. Using the middle layer metal graphics as a medium, the area where the metal graphics in the upper and lower non-adjacent metal layers overlap is converted into the first overlapping area where the metal graphics in the upper and lower adjacent metal layers overlap, reducing through-hole defect detection. difficulty. Further, obtain a second overlapping area in which each metal pattern overlaps with metal patterns in upper and lower adjacent metal layers in the wiring network, and compare the existence of the middle layer metal pattern with the metal patterns in upper and lower non-adjacent metal layers. Through-hole defects are checked one by one in the overlapping first intersection area. When there are no through-holes in the overlapping area and there is space that allows the placement of through-holes, it is determined that there are through-hole defects in the overlapping area at this time, so as to realize the target layout. Through-hole defect detection. This application provides a method for detecting through-hole defects. Based on the idea of constructing an intermediate layer metal pattern as a medium, the overlapping area of metal patterns in upper and lower non-adjacent metal layers is converted into an overlap of metal patterns in upper and lower adjacent metal layers. area, reducing the difficulty of through-hole defect detection. Furthermore, through-hole defects are directly determined in the overlapping area, without manual inspection, and there is no need to perform performance testing on the target layout to determine whether there are through-hole defects. The operation is simple and easy to implement. . And the through hole defect detection results are not affected by the through hole density, which improves the accuracy of through hole defect detection.

In one implementation, the acquisition of all metal patterns contained in the first wiring network and the second wiring network in the target layout specifically includes:

Obtain the structure file of the target layout and input the structure file into the layout verification tool;

Based on the layout verification tool, all metal patterns included in the wiring network in the target layout are obtained; wherein the first wiring network is a power line network, and the second wiring network is a ground line network.

In this way, all metal patterns in the layout can be extracted through layout verification tools commonly used in this field, eliminating the need for manual detection, reducing manual operation costs and avoiding false detections and missed detections.

In one implementation, the spatial verification is performed on each overlapping area, and the intermediate layer metal pattern is generated in each overlapping area that passes the spatial verification, which specifically includes:

Perform a first spatial check on each overlapping area, determine whether there is an intermediate metal pattern in each overlapping area one by one, and eliminate the overlapping areas where there is an intermediate metal pattern. When there is no intermediate layer in each overlapping area, The first spatial verification result is output when a metal pattern is formed; wherein, the first spatial verification result includes all overlapping areas where there is no intermediate metal pattern;

Perform a second space verification on each overlapping area in the first space verification result, and determine one by one whether there is a space that allows the placement of the intermediate layer metal graphics in each overlapping area. When the space of the middle layer metal pattern is determined, the overlapping area is determined to pass the space check.

In this way, spatial verification is performed on the overlapping area between each metal graphic and the upper and lower non-adjacent metal graphics. Each intersection is judged by whether there is an intermediate metal graphic in the overlapping area and whether there is a space that allows the intermediate metal graphic to be placed. Whether it is allowed to generate intermediate metal graphics in the stack space.

In one implementation, each first overlapping area in which the middle layer metal pattern generated by the extraction overlaps with the metal pattern in the upper and lower adjacent metal layers specifically includes:

Obtain the metal patterns in the upper and lower non-adjacent metal layers corresponding to the overlapping area where each intermediate layer metal pattern is located one by one;

Position matching is performed between the middle layer metal pattern and the metal patterns in the upper and lower non-adjacent metal layers corresponding to the overlapping area to generate a first overlapping area in which the middle layer metal pattern overlaps with the upper and lower adjacent metal patterns.

In this way, using the middle layer metal pattern as a medium, the overlapping area of the upper and lower non-adjacent metal patterns in the wiring network is converted into the first overlapping area where the upper and lower adjacent metal patterns overlap, so as to facilitate the detection of the upper and lower adjacent metal patterns. Whether there is a defect between the via position and the number of vias.

In the second aspect, this application also provides an automatic reinforcement method, including:

Use the layout through hole defect detection method as described above to detect defects in the target layout;

Collect the first overlapping area and the second overlapping area of each through-hole defect, and generate through-hole defect verification results;

Generate corresponding reinforced via patterns in each overlapping area of the via defect verification results according to the design rules of the target layout;

Summarize each generated reinforced via pattern and each intermediate layer metal pattern and generate a reinforced information file. Merge the reinforced information file with the structure file of the target layout to generate a reinforced layout file.

In this way, the generated information of each reinforced via pattern and the intermediate layer metal pattern is summarized and output as a reinforced information file. The generated reinforced information file is merged with the structure file of the target layout to form a complete reinforced information file. Strong territory document. The reinforcement layout file contains the via information that needs to be reinforced, thus realizing automatic reinforcement of the power line network and ground network in the target power supply network.

In one implementation, before summarizing the generated through hole pattern information and interlayer metal pattern information and generating the reinforcement information file, it also includes:

Perform through hole verification on the first overlapping area where each intermediate layer metal pattern is located. When it is detected that the reinforcing through hole pattern does not exist in the first overlapping area, the middle layer corresponding to the first overlapping area is eliminated. layer metal graphics.

In this way, before collecting the information of the interlayer metal pattern, a through hole check is also performed on the first overlapping area where the interlayer metal pattern is located. If there is no reinforcing through hole pattern in the first overlapping area, the first overlapping area is eliminated. The interlayer metal pattern corresponding to the overlapping area ensures that there is indeed space in the first overlapping area where the interlayer metal pattern is located to allow the generation of reinforced through hole patterns, thereby improving the accuracy of through hole defect detection.

In a third aspect, this application also provides a layout through hole defect detection device, including a graphics acquisition module, a first verification module and a second verification module;

The graphics acquisition module is used to acquire all metal graphics contained in the first wiring network and the second wiring network in the target layout;

The first verification module is used to respectively obtain the overlapping areas in each metal pattern in the first wiring network and the second wiring network and the metal patterns in the upper and lower non-adjacent metal layers, and perform a test on each overlapping area. Spatial verification, generating an intermediate layer metal pattern in each overlapping area that passes the spatial verification, and extracting each first overlapping area where the metal pattern in the generated intermediate layer metal layer overlaps;

The second verification module is used to respectively extract the second overlapping area where each metal pattern in the first wiring network and the second wiring network exists and the metal pattern in the upper and lower adjacent metal layers, and for each first overlap The through hole defect check is performed on the area and each second overlapping area, and the first overlapping area and the second overlapping area where there are through hole defects are output; where, when there is no through hole in the overlapping area and the overlap When there is space within the area that allows placement of through holes, it is determined that there is a through hole defect in the overlapping area.

In this way, after obtaining all the metal graphics in the target layout, further based on the positional relationship of the metal graphics, the overlapping areas in the wiring network between the metal graphics and the metal graphics in the upper and lower non-adjacent metal layers are obtained, and each overlapping area is The area is spatially verified and the middle layer metal pattern is generated in the overlapping area that passes the spatial verification, and each first overlapping area in which the middle layer metal pattern overlaps with the metal patterns in the upper and lower adjacent metal layers is extracted. Using the middle layer metal graphics as a medium, the area where the metal graphics in the upper and lower non-adjacent metal layers overlap is converted into the first overlapping area where the metal graphics in the upper and lower adjacent metal layers overlap, reducing through-hole defect detection. difficulty. Further, a second overlapping area is obtained in which each metal pattern overlaps with the metal patterns in the upper and lower adjacent metal layers in the wiring network, and overlaps with the metal pattern in the middle layer and the metal patterns in the upper and lower adjacent metal layers. Through-hole defects are checked one by one in the first intersection area of the overlap. When there are no through-holes in the overlapping area and there is space that allows placement of through-holes, it is determined that there are through-hole defects in the overlapping area at this time, so as to achieve the target layout. Through-hole defect detection. This application provides a through-hole defect detection device. Based on the idea of constructing an intermediate layer metal pattern as a medium, the overlapping area of metal patterns in upper and lower non-adjacent metal layers is converted into the intersection of metal patterns in upper and lower adjacent metal layers. The overlapping area reduces the difficulty of through-hole defect detection. Furthermore, through-hole defects are directly determined in the overlapping area. There is no need for manual inspection, and there is no need to perform performance testing on the target layout to determine whether there are through-hole defects. The operation is simple and easy. accomplish. And the through hole defect detection results are not affected by the through hole density, which improves the accuracy of through hole defect detection.

In one implementation, the graphics acquisition module is used to acquire all metal graphics included in the first wiring network and the second wiring network in the target layout, specifically including:

Obtain the structure file of the target layout and input the structure file into the layout verification tool;

Based on the layout verification tool, all metal patterns included in the wiring network in the target layout are obtained; wherein the first wiring network is a power line network, and the second wiring network is a ground line network.

In one implementation, the spatial verification is performed on each overlapping area, and the intermediate layer metal pattern is generated in each overlapping area that passes the spatial verification, which specifically includes:

Perform a first spatial check on each overlapping area, determine whether there is an intermediate metal pattern in each overlapping area one by one, and eliminate the overlapping areas where there is an intermediate metal pattern. When there is no intermediate layer in each overlapping area, The first spatial verification result is output when a metal pattern is formed; wherein, the first spatial verification result includes all overlapping areas where there is no intermediate metal pattern;

Perform a second space verification on each overlapping area in the first space verification result, and determine one by one whether there is a space that allows the placement of the intermediate layer metal graphics in each overlapping area. When the space of the middle layer metal pattern is determined, the overlapping area is determined to pass the space check.

In one implementation, each first overlapping area in which the middle layer metal pattern generated by the extraction overlaps with the metal pattern in the upper and lower adjacent metal layers specifically includes:

Obtain the metal patterns in the upper and lower non-adjacent metal layers corresponding to the overlapping area where each intermediate layer metal pattern is located one by one;

Matching the positions of the metal graphics in the middle layer with the metal graphics in the upper and lower non-adjacent metal layers corresponding to the overlapping area to generate a first overlapping area in which the metal graphics in the middle layer overlaps with the metal graphics in the upper and lower adjacent metal layers. .

In one implementation, the layout through hole defect detection method also includes automatically reinforcing the target layout based on the through hole defect verification results, specifically including:

Collect the first overlapping area and the second overlapping area of each through-hole defect, and generate through-hole defect verification results;

Generate corresponding reinforced via patterns in each overlapping area of the via defect verification results according to the design rules of the target layout;

Summarize each generated reinforced via pattern and each intermediate layer metal pattern to generate a reinforced information file, and merge the reinforced information file with the structure file of the target layout to generate a reinforced layout file.

In one implementation, before summarizing the generated through hole pattern information and the intermediate layer metal pattern information and generating the reinforcement information file, it also includes:

Perform through hole verification on the first overlapping area where each intermediate layer metal pattern is located. When it is detected that the reinforcing through hole pattern does not exist in the first overlapping area, the middle layer corresponding to the first overlapping area is eliminated. layer metal graphics.

Description of drawings

Figure 1 is a schematic flow chart of a layout through hole defect detection method provided by an embodiment of the present invention;

Figure 2 is a top view of a layout wiring network provided by an embodiment of the present invention;

Figure 3 is a schematic flow chart of an automatic reinforcement method provided by an embodiment of the present invention;

Figure 4 is an application flow diagram of an automatic reinforcement method provided by an embodiment of the present invention.

Detailed ways

Specific implementations of the present invention will be described in further detail below with reference to the accompanying drawings and examples. The following examples are used to illustrate the invention but are not intended to limit the scope of the invention.

The terms “first”, “second”, etc. in the description, claims, and drawings of this application are used to distinguish different objects, rather than describing a specific sequence. Furthermore, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusion. For example, a process, method, system, product or device that includes a series of steps or units is not limited to the listed steps or units, but optionally also includes steps or units that are not listed, or optionally also includes Other steps or units inherent to such processes, methods, products or devices.

Reference herein to "an embodiment" means that a particular feature, structure or characteristic described in connection with the embodiment can be included in at least one embodiment of the present application. The appearances of this phrase in various places in the specification are not necessarily all referring to the same embodiment, nor are separate or alternative embodiments mutually exclusive of other embodiments. Those skilled in the art understand, both explicitly and implicitly, that the embodiments described herein may be combined with other embodiments.

Example 1

Referring to Figure 1, Figure 1 is a schematic flowchart of a method for detecting layout through hole defects provided by an embodiment of the present invention. An embodiment of the present invention provides a method for detecting layout through hole defects, which includes steps 101 to 103. Each step is specifically as follows:

Step 101: Obtain all metal patterns contained in the first wiring network and the second wiring network in the target layout.

In one embodiment, obtaining all metal patterns contained in the first wiring network and the second wiring network in the target layout specifically includes: obtaining the structure file of the target layout and inputting the structure file into the layout verification tool; based on the The layout verification tool obtains all metal patterns included in the wiring network in the target layout; wherein the first wiring network is a power line network, and the second wiring network is a ground line network. In the embodiment of the present invention, the structure file of the target layout is converted into a GDS format file and input into the layout verification tool. GDSII is a binary file that contains the geometric shapes, text or labels of the planes in the integrated circuit layout, and is used for data conversion of the integrated circuit layout. Preferably, the embodiment of the present invention inputs the converted GDS file into the Mentor Caliber layout verification tool, and uses the verification tool to obtain all metal patterns included in the power line network and ground line network in the target layout.

Referring to Figure 2, Figure 2 is a top view of a layout wiring network provided by an embodiment of the present invention. The embodiment of the present invention provides a top view of the wiring network in the layout for auxiliary explanation. Metal 1 indicates the metal pattern located on the first layer of the layout. Metal 2, metal 3 and metal 4 are successively represented to indicate metal patterns located on different layers. . Metal patterns between different levels are connected using different through-hole patterns. Through hole 1 is used to connect metal 1 and metal 2, through hole 2 is used to connect metal 2 and metal 3, and through hole 3 is used to connect metal 3 and metal 4. It should be noted that the specific layers of metal used in the layout, the shape of the connecting holes between the metals, etc. are adjusted according to the specific application products. The top view of the wiring network in the layout provided by the embodiment of the present invention is only for Provide auxiliary explanations.

Step 102: Obtain the overlapping areas in each metal pattern and the metal patterns in the upper and lower non-adjacent metal layers in the first wiring network and the second wiring network respectively, perform spatial verification on each overlapping area, and pass An intermediate layer metal pattern is generated in each overlapping area of the spatial verification, and each first overlapping area in which the generated intermediate layer metal pattern overlaps with the graphics in upper and lower adjacent metal layers is extracted.

Obtain the areas where each metal pattern in the power line network overlaps with the metal patterns in the upper and lower non-adjacent metal layers, and the area where each metal pattern in the ground wire network overlaps with the metal patterns in the upper and lower non-adjacent metal layers. Area. In one embodiment, performing spatial verification on each overlapping area and generating an intermediate layer metal pattern in each overlapping area that passes the spatial verification specifically includes: performing a first step on each overlapping area. Spatial verification, one by one determines whether there is an intermediate metal pattern in each overlapping area and eliminates the overlapping areas where there is an intermediate metal pattern. When there is no intermediate metal pattern in each overlapping area, the first spatial verification is output. Result; wherein, the first space verification result contains all overlapping areas without intermediate layer metal graphics; perform a second space verification on each overlapping area within the first space verification result, one by one Determine whether there is space in each overlapping area that allows the placement of the intermediate metal graphics. When there is space in the overlapping area that allows the placement of the intermediate metal graphics, it is determined that the overlapping area passes the space check. Obtain overlapping areas between metal graphics and non-adjacent upper and lower metal graphics in the power line network and ground wire network respectively, and perform spatial verification on each overlapping area. The spatial verification includes a first spatial verification and a second spatial verification. During the first spatial verification, when it is detected that the middle layer metal pattern exists in the overlapping area, the overlapping area is eliminated. Determine whether there is an intermediate metal pattern in each overlapping area one by one until it is detected that there is no intermediate metal pattern in all overlapping areas, and output the first spatial verification result. The first spatial verification result includes all overlapping areas where there is no intermediate metal pattern. A second space verification is performed on each overlapping area within the first space verification result, and it is determined one by one whether there is space in each overlapping area that allows the placement of the intermediate layer metal graphics. The spatial size of each intermediate layer metal pattern is determined according to the metal pattern design of different metal layers in the specific layout. The space for placing the intermediate layer metal pattern in the overlapping area is not limited here. When the overlapping area satisfies both "there is no intermediate metal pattern" and "there is space that allows the placement of the intermediate metal pattern", it is determined that the overlapping area passes the space check. As an alternative to the embodiment of the present invention, when performing space verification, the order of the first space verification and the second space verification can be replaced. The second space verification is performed first and there is an intersection that allows the placement of the intermediate layer metal pattern. overlap the area, and then perform the first space verification.

In one embodiment, each first overlapping area where the middle layer metal pattern generated by the extraction overlaps with the metal pattern in the upper and lower adjacent metal layers specifically includes: obtaining the intersection where each middle layer metal pattern is located one by one. The metal graphics in the upper and lower non-adjacent metal layers corresponding to the overlapping area are matched; the metal graphics in the middle layer are position-matched with the metal graphics in the upper and lower non-adjacent metal layers corresponding to the overlapping area. Select the metal pattern in the adjacent metal layer that has a relationship with the middle layer metal pattern in the upper and lower adjacent metal layers, and obtain the first overlapping area in which the middle layer metal pattern overlaps with the metal pattern in the upper and lower adjacent metal layers. . When generating an interlayer metal pattern in each overlapping area that passes spatial verification, the shape of the interlayer metal pattern depends on the design requirements of the target layout. The upper and lower non-adjacent metal graphics corresponding to the overlapping area of each intermediate layer metal graphic are obtained one by one and the positions are matched to generate a first overlapping area of the intermediate layer metal graphic and the upper and lower adjacent metal graphics. In the embodiment of the present invention, the interlayer metal pattern is used as a medium to convert the overlapping area of the metal patterns in the upper and lower non-adjacent metal layers in the wiring network into the first intersection where the metal patterns in the upper and lower adjacent metal layers overlap. The overlapping area is used to detect whether there are defects in the position and number of through holes between the upper and lower adjacent metal patterns.

Step 103: Extract the second overlapping area between each metal pattern in the first wiring network and the second wiring network and the metal pattern in the upper and lower adjacent metal layers, and extract the second overlapping area for each first overlapping area and each second The overlapping area is checked for through hole defects, and the first overlapping area and the second overlapping area where through hole defects exist are output; where, when there is no through hole in the overlapping area and there is a through hole that is allowed to be placed in the overlapping area, When there is a hole space, it is determined that there is a through hole defect in the overlapping area.

In the embodiment of the present invention, the first overlapping area of the metal patterns in the upper and lower adjacent metal layers in the power network and the ground network is obtained, and the second intersection area of the metal patterns in the middle layer and the metal patterns in the upper and lower adjacent metal layers is obtained. In the overlapping area, through hole defect verification is performed on each first overlapping area and each second overlapping area. When it is detected that there is no through hole in the overlapping area and there is a space that allows the placement of through holes, it is determined that the intersection There are via defects in the stack area.

In an embodiment of the present invention, a layout via defect detection device is also provided, which includes a processor, a memory, and a computer program stored in the memory and configured to be executed by the processor. When the processor executes the computer program, the above layout is implemented. Through-hole defect detection methods.

In an embodiment of the present invention, a computer-readable storage medium is also provided. The computer-readable storage medium includes a stored computer program, wherein when the computer program is running, the device where the computer-readable storage medium is located is controlled to execute the above layout via defects. Detection method.

Exemplarily, the computer program can be divided into one or more modules, and the one or more modules are stored in the memory and executed by the processor to complete the present invention. The one or more modules may be a series of computer program instruction segments capable of completing specific functions. The instruction segments are used to describe the execution process of the computer program in the layout through hole defect detection equipment.

The layout through hole defect detection equipment can be computing equipment such as desktop computers, notebooks, handheld computers, and cloud servers. The layout via defect detection device may include, but is not limited to, a processor, a memory, and a display. Those skilled in the art can understand that the above components are only examples of layout through hole defect detection equipment and do not constitute a limitation to the layout through hole defect detection equipment. It may include more or less components than the mentioned components, or a combination of certain components. Some components, or different components, for example, the layout via defect detection device may also include input and output devices, network access devices, buses, etc.

The so-called processor can be a central processing unit (Central Processing Unit, CPU), or other general-purpose processor, digital signal processor (Digital Signal Processor, DSP), application specific integrated circuit (Application Specific Integrated Circuit, ASIC), off-the-shelf processor Programmable gate array (Field-Programmable Gate Array, FPGA) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. The general processor can be a microprocessor or the processor can be any conventional processor, etc. The processor is the control center of the layout through hole defect detection equipment and uses various interfaces and lines to connect the entire layout. Various parts of through-hole defect inspection equipment.

The memory may be used to store the computer program and/or module. The processor implements the layout by running or executing the computer program and/or module stored in the memory and calling data stored in the memory. Various functions of through hole defect inspection equipment. The memory may mainly include a storage program area and a storage data area, wherein the storage program area may store an operating system, an application program required for at least one function (such as a sound playback function, a text conversion function, etc.), etc.; the storage data area may store Data created based on the use of mobile phones (such as audio data, text message data, etc.), etc. In addition, the memory may include high-speed random access memory, and may also include non-volatile memory, such as hard disk, memory, plug-in hard disk, smart memory card (Smart Media Card, SMC), secure digital (Secure Digital, SD) card, Flash Card, at least one disk storage device, flash memory device, or other volatile solid-state storage device.

Wherein, if the integrated module of the layout through hole defect detection equipment is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the present invention can implement all or part of the processes in the methods of the above embodiments, and can also be completed by instructing relevant hardware through a computer program. The computer program can be stored in a computer-readable storage medium, and the computer program can be stored in a computer-readable storage medium. When the program is executed by the processor, the steps of each of the above method embodiments can be implemented. Wherein, the computer program includes computer program code, which may be in the form of source code, object code, executable file or some intermediate form. The computer-readable medium may include: any entity or device capable of carrying the computer program code, recording media, U disk, mobile hard disk, magnetic disk, optical disk, computer memory, read-only memory (ROM, Read-Only Memory) , Random Access Memory (RAM, Random Access Memory), electrical carrier signals, telecommunications signals, and software distribution media, etc. It should be noted that the content contained in the computer-readable medium can be appropriately added or deleted according to the requirements of legislation and patent practice in the jurisdiction. For example, in some jurisdictions, according to legislation and patent practice, the computer-readable medium Excludes electrical carrier signals and telecommunications signals. Persons of ordinary skill in the art can understand and implement the method without any creative effort.

Embodiments of the present invention provide a method for detecting layout through-hole defects. After acquiring all the metal graphics in the target layout, further based on the positional relationship of the metal graphics, the existence of the metal graphics and the metal graphics in the upper and lower non-adjacent metal layers in the wiring network is obtained. For overlapping areas, perform spatial verification on each overlapping area and generate the middle layer metal pattern in the overlapping area that passes the spatial verification. Extract the existence of the middle layer metal pattern and the metal patterns in the upper and lower adjacent metal layers. Each first overlapping area of overlap. Using the middle layer metal graphics as a medium, the area where the metal graphics in the upper and lower non-adjacent metal layers overlap is converted into the first overlapping area where the metal graphics in the upper and lower adjacent metal layers overlap, reducing through-hole defect detection. difficulty. Further, a second overlapping area is obtained in which each metal pattern overlaps with the metal patterns in the upper and lower adjacent metal layers in the wiring network, and overlaps with the metal pattern in the middle layer and the metal patterns in the upper and lower adjacent metal layers. Through-hole defects are checked one by one in the first intersection area of the overlap. When there are no through-holes in the overlapping area and there is space that allows placement of through-holes, it is determined that there are through-hole defects in the overlapping area at this time, so as to achieve the target layout. Through-hole defect detection. A through-hole defect detection method provided by an embodiment of the present invention is based on the idea of constructing an intermediate layer metal pattern as a medium to convert the overlapping area of metal patterns in upper and lower non-adjacent metal layers into metal patterns in upper and lower adjacent metal layers. The overlapping area reduces the difficulty of through-hole defect detection. Furthermore, through-hole defects are directly determined in the overlapping area without manual inspection, and there is no need to perform performance testing on the target layout to determine whether there are through-hole defects. Operation Simple and easy to implement. And the through hole defect detection results are not affected by the through hole density, which improves the accuracy of through hole defect detection.

Example 2

Refer to Figure 3, which is a schematic flowchart of an automatic reinforcement method provided by an embodiment of the present invention. The embodiment of the present invention provides an automatic reinforcement method, which includes steps 201 to 204. The specific steps are as follows:

Step 201: Use the layout through hole defect detection method as described in Embodiment 1 to perform through hole defect detection on the target layout;

Step 202: Collect the first overlapping area and the second overlapping area of each through hole defect, and generate a through hole defect verification result;

Step 203: Generate corresponding reinforced via patterns in each overlapping area of the via defect verification results according to the design rules of the target layout;

Step 204: Summarize each generated reinforced via pattern and each intermediate layer metal pattern and generate a reinforced information file. Merge the reinforced information file with the structure file of the target layout to generate a reinforced layout file. .

In the embodiment of the present invention, the structure file of the target layout is input into the layout verification tool, and the through-hole defect detection method of the target layout is performed based on the layout through-hole defect detection method described in Embodiment 1. Referring to Figure 4, Figure 4 is an application flow diagram of an automatic reinforcement method provided by an embodiment of the present invention. After the through hole defect detection is completed, each generated reinforced through hole pattern and each intermediate layer metal pattern are summarized and a reinforcement information file is generated, and the reinforcement information file is merged with the structure file of the target layout, Generate enhanced layout files. Through the layout verification tool, in accordance with the design rules of the target layout, a reinforced via pattern corresponding to the via level is automatically added in each overlapping area with via hole defects, and the generated reinforced via pattern needs to meet drc Verification requirements. Summarize the generated information of each reinforced via pattern and intermediate layer metal pattern, and output it as a reinforcement information file in GDS format. Merge the generated reinforcement information file with the GDS file of the target layout into a complete GDS file is a reinforcement layout file. The reinforcement layout file contains the via information that needs to be reinforced, realizing automatic reinforcement of the power line network and ground wire network.

As an optimization solution of the embodiment of the present invention, before aggregating the generated through hole pattern information and the interlayer metal pattern information and generating the reinforcement information file, it also includes: performing the following steps on the first overlapping area where each interlayer metal pattern is located. Through-hole verification: when it is detected that the reinforcing through-hole pattern does not exist in the first overlapping area, the intermediate layer metal pattern corresponding to the first overlapping area is eliminated. Before collecting the information of the interlayer metal pattern, it is also necessary to perform through hole verification on the first overlapping area where the interlayer metal pattern is located. If there is no reinforcing through hole pattern in the first overlapping area, the first intersection is eliminated. The interlayer metal pattern corresponding to the overlapping area is used to ensure that there is indeed space in the first overlapping area where the interlayer metal pattern is located to allow the generation of the reinforcing via pattern.

Example 3

Embodiments of the present invention provide a layout through hole defect detection device, which includes a graphics acquisition module, a first verification module and a second verification module;

The graphics acquisition module is used to acquire all metal graphics contained in the first wiring network and the second wiring network in the target layout;

The first verification module is used to respectively obtain the overlapping areas in each metal pattern and the metal patterns in the upper and lower non-adjacent metal layers in the first wiring network and the second wiring network, and perform a test on each overlapping area. Spatial verification, generate an intermediate layer metal pattern in each overlapping area that passes the spatial verification, and extract each first overlapping area in which the metal pattern in the generated intermediate layer metal layer overlaps;

The second verification module is used to respectively extract the second overlapping area where each metal pattern in the first wiring network and the second wiring network exists and the metal pattern in the upper and lower adjacent metal layers, and for each first overlap The through hole defect check is performed on the area and each second overlapping area, and the first overlapping area and the second overlapping area where there are through hole defects are output; where, when there is no through hole in the overlapping area and the overlap When there is space within the area that allows placement of through holes, it is determined that there is a through hole defect in the overlapping area.

In one embodiment, the graphics acquisition module is used to acquire all metal graphics contained in the first wiring network and the second wiring network in the target layout, specifically including: obtaining the structure file of the target layout and inputting the structure file into the layout. A verification tool; based on the layout verification tool, obtain all metal patterns contained in the wiring network in the target layout; wherein the first wiring network is a power line network, and the second wiring network is a ground line network.

In one embodiment, performing spatial verification on each overlapping area and generating an intermediate layer metal pattern in each overlapping area that passes the spatial verification specifically includes: performing a first step on each overlapping area. Spatial verification, one by one determines whether there is an intermediate metal pattern in each overlapping area and eliminates the overlapping areas where there is an intermediate metal pattern. When there is no intermediate metal pattern in each overlapping area, the first spatial verification is output. Result; wherein, the first space verification result contains all overlapping areas without intermediate layer metal graphics; perform a second space verification on each overlapping area within the first space verification result, one by one Determine whether there is space in each overlapping area that allows the placement of the intermediate metal graphics. When there is space in the overlapping area that allows the placement of the intermediate metal graphics, it is determined that the overlapping area passes the space check.

In one embodiment, each first overlapping area where the middle layer metal pattern generated by the extraction overlaps with the metal pattern in the upper and lower adjacent metal layers specifically includes: obtaining the intersection where each middle layer metal pattern is located one by one. The metal graphics in the upper and lower non-adjacent metal layers corresponding to the overlapping area are matched; the metal graphics in the middle layer are position-matched with the metal graphics in the upper and lower non-adjacent metal layers corresponding to the overlapping area to generate the middle layer metal graphics and the upper and lower adjacent metal graphics. The metal patterns in the metal layer have an overlapping first overlapping area.

In one embodiment, the layout through hole defect detection method further includes automatically reinforcing the target layout based on the through hole defect verification results, which specifically includes: collecting the first overlapping area and the third overlapping area where each through hole defect exists. generate through-hole defect verification results in two overlapping areas; generate corresponding reinforced through-hole graphics in each overlapping area of the through-hole defect verification results according to the design rules of the target layout; summarize each generated A reinforcement via pattern and each intermediate layer metal pattern are generated and a reinforcement information file is generated, and the reinforcement information file is merged with the structure file of the target layout to generate a reinforcement layout file.

In one embodiment, before aggregating the generated through hole pattern information and the interlayer metal pattern information and generating the reinforcement information file, the method further includes: performing through hole verification on the first overlapping area where each interlayer metal pattern is located, When it is detected that the reinforcing via hole pattern does not exist in the first overlapping area, the intermediate layer metal pattern corresponding to the first overlapping area is eliminated. Those skilled in the art can clearly understand that for the convenience and simplicity of description, the specific working process of the device described above can be referred to the corresponding process in the foregoing method embodiment, and will not be described again here.

Embodiments of the present invention provide a layout through-hole defect detection device. After acquiring all metal graphics in the target layout, further based on the positional relationship of the metal graphics, the existence of the metal graphics and the metal graphics in the upper and lower non-adjacent metal layers in the wiring network is obtained. For overlapping areas, perform spatial verification on each overlapping area and generate the middle layer metal pattern in the overlapping area that passes the spatial verification. Extract the existence of the middle layer metal pattern and the metal patterns in the upper and lower adjacent metal layers. Each first overlapping area of overlap. Using the middle layer metal graphics as a medium, the area where the metal graphics in the upper and lower non-adjacent metal layers overlap is converted into the first overlapping area where the metal graphics in the upper and lower adjacent metal layers overlap, reducing through-hole defect detection. difficulty. Further, a second overlapping area is obtained in which each metal pattern overlaps with the metal patterns in the upper and lower adjacent metal layers in the wiring network, and overlaps with the metal pattern in the middle layer and the metal patterns in the upper and lower adjacent metal layers. Through-hole defects are checked one by one in the first intersection area of the overlap. When there are no through-holes in the overlap area and there is space that allows placement of through-holes, it is determined that there are through-hole defects in the overlap area at this time, so as to achieve the target layout. Through-hole defect detection. A through-hole defect detection device provided by an embodiment of the present invention is based on the idea of constructing an intermediate layer metal pattern as a medium to convert the overlapping area of metal patterns in upper and lower non-adjacent metal layers into metal patterns in upper and lower adjacent metal layers. The overlapping area reduces the difficulty of through-hole defect detection. Furthermore, through-hole defects are directly determined in the overlapping area without manual inspection, and there is no need to perform performance testing on the target layout to determine whether there are through-hole defects. Operation Simple and easy to implement. And the through hole defect detection results are not affected by the through hole density, which improves the accuracy of through hole defect detection.

The above are only preferred embodiments of the present invention. It should be noted that those of ordinary skill in the art can also make several improvements and substitutions without departing from the technical principles of the present invention. These improvements and substitutions It should also be regarded as the protection scope of the present invention.

Claims (10)

1. A layout through hole defect detection method is characterized by comprising the following steps:

acquiring all metal patterns contained in a first wiring network and a second wiring network in a target layout;

respectively acquiring overlapping areas of each metal pattern in the first wiring network and the second wiring network, which are in existence with metal patterns in upper and lower non-adjacent metal layers, performing space verification on each overlapping area, generating an intermediate layer metal pattern in each overlapping area passing the space verification, and extracting each first overlapping area of the generated intermediate layer metal pattern and the metal patterns in the upper and lower adjacent metal layers;

extracting second overlapping areas of each metal pattern in the first wiring network and the second wiring network and the metal patterns in the upper and lower adjacent metal layers respectively, performing through hole defect verification on each first overlapping area and each second overlapping area, and outputting the first overlapping area and the second overlapping area with the through hole defects; and when the through holes are not present in the overlapped area and the space allowing the through holes to be placed is present in the overlapped area, judging that the through holes are defective in the overlapped area.

2. The method for detecting a defect of a through hole in a layout according to claim 1, wherein the step of obtaining all metal patterns contained in the first wiring network and the second wiring network in the target layout specifically comprises the steps of:

obtaining a structure file of a target layout and inputting the structure file into a layout verification tool;

acquiring all metal patterns contained in a wiring network in the target layout based on the layout verification tool; the first wiring network is a power line network, and the second wiring network is a ground line network.

3. The method for detecting defects of a layout through hole according to claim 1, wherein the performing a spatial verification on each overlapping region, and generating an interlayer metal pattern in each overlapping region passing the spatial verification, specifically comprises:

carrying out first space verification on each overlapping area, judging whether an interlayer metal pattern exists in each overlapping area one by one, eliminating the overlapping area where the interlayer metal pattern exists, and outputting a first space verification result when the interlayer metal pattern does not exist in each overlapping area; wherein, the first space verification result comprises all overlapped areas without intermediate layer metal patterns;

And carrying out second space verification on each overlapping area in the first space verification result, judging whether a space allowing the middle layer metal pattern to be placed exists in each overlapping area one by one, and judging that the overlapping area passes through the space verification when the space allowing the middle layer metal pattern to be placed exists in the overlapping area.

4. The method for detecting a defect of a layout through hole according to claim 1, wherein each first overlapping region where the metal pattern of the intermediate layer generated by extraction overlaps with the metal pattern in the upper and lower adjacent metal layers specifically comprises:

acquiring metal patterns in upper and lower non-adjacent metal layers corresponding to overlapping areas where each middle layer metal pattern is located one by one;

and matching the positions of the metal patterns of the middle layer and the metal patterns in the upper and lower non-adjacent metal layers corresponding to the overlapping region to generate a first overlapping region where the metal patterns of the middle layer and the metal patterns in the upper and lower adjacent metal layers overlap.

5. An automatic reinforcement method, comprising:

performing through hole defect detection on the target layout by adopting the layout through hole defect detection method according to any one of claims 1-4;

Collecting a first overlapping area and a second overlapping area with through hole defects, and generating a through hole defect verification result;

generating corresponding reinforced through hole patterns in each overlapping area of the through hole defect verification result according to the design rule of the target layout;

summarizing each generated reinforcement through hole pattern and each middle layer metal pattern, generating a reinforcement information file, and merging the reinforcement information file with the structure file of the target layout to generate a reinforcement layout file.

6. The automatic reinforcement method according to claim 5, further comprising, before summarizing the generated via pattern information and the intermediate layer metal pattern information and generating the reinforcement information file:

and carrying out through hole verification on a first overlapping area where each middle layer metal pattern is located, and eliminating the middle layer metal pattern corresponding to the first overlapping area when the fact that the reinforcing through hole pattern does not exist in the first overlapping area is detected.

7. The layout through hole defect detection device is characterized by comprising a graph acquisition module, a first verification module and a second verification module;

the pattern acquisition module is used for acquiring all metal patterns contained in the first wiring network and the second wiring network in the target layout;

The first verification module is used for respectively obtaining overlapping areas of each metal pattern in the first wiring network and the second wiring network, which are in overlap with the metal patterns in the upper and lower non-adjacent metal layers, performing space verification on each overlapping area, generating an intermediate layer metal pattern in each overlapping area passing the space verification, and extracting each first overlapping area of the generated metal patterns in the intermediate layer metal layer;

the second checking module is used for respectively extracting second overlapping areas of each metal pattern in the first wiring network and the second wiring network and the metal patterns in the upper and lower adjacent metal layers, checking through hole defects of each first overlapping area and each second overlapping area, and outputting the first overlapping area and the second overlapping area with the through hole defects; and when the through holes are not present in the overlapped area and the space allowing the through holes to be placed is present in the overlapped area, judging that the through holes are defective in the overlapped area.

8. The layout through hole defect detection device according to claim 7, wherein the pattern acquisition module is configured to acquire all metal patterns included in the first wiring network and the second wiring network in the target layout, and specifically includes:

Obtaining a structure file of a target layout and inputting the structure file into a layout verification tool;

acquiring all metal patterns contained in a wiring network in the target layout based on the layout verification tool; the first wiring network is a power line network, and the second wiring network is a ground line network.

9. The layout through hole defect detection device according to claim 7, wherein the performing spatial verification on each overlapping area, and generating an interlayer metal pattern in each overlapping area passing the spatial verification, specifically comprises:

carrying out first space verification on each overlapping area, judging whether an interlayer metal pattern exists in each overlapping area one by one, eliminating the overlapping area where the interlayer metal pattern exists, and outputting a first space verification result when the interlayer metal pattern does not exist in each overlapping area; wherein, the first space verification result comprises all overlapped areas without intermediate layer metal patterns;

and carrying out second space verification on each overlapping area in the first space verification result, judging whether a space allowing the middle layer metal pattern to be placed exists in each overlapping area one by one, and judging that the overlapping area passes through the space verification when the space allowing the middle layer metal pattern to be placed exists in the overlapping area.

10. The layout through hole defect detection device according to claim 7, wherein each first overlapping region where the intermediate layer metal pattern generated by extraction overlaps with the metal pattern in the upper and lower adjacent metal layers specifically comprises:

acquiring metal patterns in upper and lower non-adjacent metal layers corresponding to overlapping areas where each middle layer metal pattern is located one by one;

and matching the positions of the metal patterns of the middle layer and the metal patterns in the upper and lower non-adjacent metal layers corresponding to the overlapping region to generate a first overlapping region where the metal patterns of the middle layer and the metal patterns in the upper and lower adjacent metal layers overlap.