CN117350936A - Layout through hole defect detection method, device and automatic reinforcement method - Google Patents
Layout through hole defect detection method, device and automatic reinforcement method Download PDFInfo
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Abstract
The invention discloses a method and a device for detecting defects of a layout through hole and an automatic reinforcement method, wherein the method for detecting the defects of the layout through hole comprises the following steps: acquiring metal patterns contained in a first wiring network and a second wiring network in a target layout; respectively acquiring overlapping areas of each metal pattern in the first wiring network and the second wiring network, which are overlapped with the metal patterns in the upper and lower non-adjacent metal layers, and performing space verification, generating an intermediate layer metal pattern in the area passing the space verification, and extracting each first overlapping area of the generated intermediate layer metal pattern and the metal patterns in the upper and lower adjacent metal layers; and extracting second overlapping areas of each metal pattern in the wiring network and the metal patterns in the upper and lower adjacent metal layers, performing through hole defect verification on each first and each second overlapping area, and outputting the first overlapping area and the second overlapping area with the through hole defects. The invention can be used for accurately and rapidly detecting and reinforcing the defects of the through holes in the layout.
Description
Technical Field
The invention relates to the technical field of integrated circuit layout design defect inspection, in particular to a layout through hole defect detection method, a layout through hole defect detection device and an automatic reinforcement method.
Background
With the progress of the semiconductor integrated circuit manufacturing process, the feature size of the transistor is smaller, the integrated level of the circuit per unit area is higher, the metal wiring level is more and more, and the interconnection line density is more and more. It is counted that more than 70% of the causes of product failure originate from interconnect defects. When the layout design of the chip is carried out, the metals of different layers in the chip are utilized to carry out alternate vertical and horizontal arrangement between the upper layer and the lower layer, and the upper layer and the lower layer are connected through different through holes to form a grid-shaped power line network and a grid-shaped ground line network for ensuring the power supply in the chip.
It is difficult to inspect defects of the through holes in the layout as the layout design becomes more and more complex. The existing through hole defect detection method mainly comprises the following three steps: the first is manual inspection, the method has large workload, and the inspection result has the risk of missing the detection; the second method is through automatic tool detection, but this method can't locate the area with insufficient density of the through hole accurately, and the software cost is higher; the third method is performance test, which is to connect metal wires with different layers with test pads to perform performance test, and the method can ensure the accuracy of detection, but needs to test the metal wires and the test pads, has complex operation and is not suitable for high-integration layout design. How to accurately and rapidly verify whether the metal layers are fully connected in the layout design of the connection of a plurality of metal layers is a technical problem to be solved urgently.
Disclosure of Invention
The application provides a method and a device for detecting defects of through holes in a layout and an automatic reinforcement method, which are used for accurately and rapidly detecting the defects of the through holes in the layout.
In a first aspect, the present application provides a method for detecting a defect of a layout through hole, including:
acquiring all metal patterns contained in a first wiring network and a second wiring network in a target layout;
respectively acquiring overlapping areas of each metal pattern in the first wiring network and the second wiring network, which are in existence with metal patterns in upper and lower non-adjacent metal layers, performing space verification on each overlapping area, generating an intermediate layer metal pattern in each overlapping area passing the space verification, and extracting each first overlapping area of the generated intermediate layer metal pattern and the metal patterns in the upper and lower adjacent metal layers;
extracting second overlapping areas of each metal pattern in the first wiring network and the second wiring network and the metal patterns in the upper and lower adjacent metal layers respectively, performing through hole defect verification on each first overlapping area and each second overlapping area, and outputting the first overlapping area and the second overlapping area with the through hole defects; and when the through holes are not present in the overlapped area and the space allowing the through holes to be placed is present in the overlapped area, judging that the through holes are defective in the overlapped area.
In this way, after all the metal patterns in the target layout are acquired, according to the position relation of the metal patterns, the overlapping areas of the metal patterns and the metal patterns in the upper and lower non-adjacent metal layers exist in the wiring network, the space verification is carried out on each overlapping area, the middle layer metal patterns are generated in the overlapping areas passing the space verification, and each first overlapping area of the middle layer metal patterns and the upper and lower adjacent metal patterns is extracted. And the intermediate layer metal patterns are used as media, and the area where the metal patterns in the upper and lower non-adjacent metal layers overlap is converted into the first overlapping area where the metal patterns in the upper and lower adjacent metal layers overlap, so that the difficulty of through hole defect detection is reduced. Further, a second overlapping area of each metal pattern in the wiring network, which overlaps with the metal patterns in the upper and lower adjacent metal layers, is obtained, through hole defect verification is carried out on first intersection areas of the metal patterns in the middle layer and the metal patterns in the upper and lower non-adjacent metal layers one by one, and when no through hole exists in the overlapping area and a space allowing the through hole to be placed exists, through hole defects exist in the overlapping area at the moment, so that through hole defect detection of the target layout is realized. According to the through hole defect detection method, based on the thought that the middle layer metal patterns are constructed as media, the overlapping area of the metal patterns in the upper and lower non-adjacent metal layers is converted into the overlapping area of the metal patterns in the upper and lower adjacent metal layers, so that the through hole defect detection difficulty is reduced, further, through hole defect judgment is directly carried out on the overlapping area, manual inspection is not needed, performance test is not needed to be carried out on a target layout to judge whether through hole defects exist, and the operation is simple and easy to realize. And the defect detection result of the through holes is not influenced by the density of the through holes, so that the accuracy of the defect detection of the through holes is improved.
In one implementation manner, the obtaining all the metal patterns contained in the first wiring network and the second wiring network in the target layout specifically includes:
obtaining a structure file of a target layout and inputting the structure file into a layout verification tool;
acquiring all metal patterns contained in a wiring network in the target layout based on the layout verification tool; the first wiring network is a power line network, and the second wiring network is a ground line network.
Therefore, all metal patterns in the layout are extracted through a layout verification tool commonly used in the field, detection is not needed manually, the manual operation cost is reduced, and false leakage detection is avoided.
In one implementation manner, the performing a spatial verification on each overlapping area, and generating an intermediate layer metal pattern in each overlapping area passing the spatial verification specifically includes:
carrying out first space verification on each overlapping area, judging whether an interlayer metal pattern exists in each overlapping area one by one, eliminating the overlapping area where the interlayer metal pattern exists, and outputting a first space verification result when the interlayer metal pattern does not exist in each overlapping area; wherein, the first space verification result comprises all overlapped areas without intermediate layer metal patterns;
And carrying out second space verification on each overlapping area in the first space verification result, judging whether a space allowing the middle layer metal pattern to be placed exists in each overlapping area one by one, and judging that the overlapping area passes through the space verification when the space allowing the middle layer metal pattern to be placed exists in the overlapping area.
And judging whether the interlayer metal patterns can be generated or not in each overlapping space by judging whether the interlayer metal patterns exist in the overlapping area and whether the space for allowing the interlayer metal patterns to be placed exists or not.
In one implementation manner, each first overlapping area where the intermediate layer metal pattern generated by extraction overlaps with the metal pattern in the upper and lower adjacent metal layers specifically includes:
acquiring metal patterns in upper and lower non-adjacent metal layers corresponding to overlapping areas where each middle layer metal pattern is located one by one;
and matching the positions of the metal patterns of the middle layer and the metal patterns in the upper and lower non-adjacent metal layers corresponding to the overlapping region to generate a first overlapping region where the metal patterns of the middle layer and the upper and lower adjacent metal patterns overlap.
In this way, the overlapping area of the upper and lower non-adjacent metal patterns in the wiring network is converted into the first overlapping area where the upper and lower adjacent metal patterns overlap by taking the middle layer metal patterns as the medium, so that whether the positions of the through holes and the number of the through holes between the upper and lower adjacent metal patterns have defects or not can be detected.
In a second aspect, the present application further provides an automatic reinforcement method, including:
performing defect detection on the target layout by adopting the layout through hole defect detection method;
collecting a first overlapping area and a second overlapping area with through hole defects, and generating a through hole defect verification result;
generating corresponding reinforced through hole patterns in each overlapping area of the through hole defect verification result according to the design rule of the target layout;
summarizing each generated reinforced through hole pattern and each middle layer metal pattern, generating a reinforced information file, merging the reinforced information file with the structure file of the target layout, and generating a reinforced layout file
Thus, the information of each generated reinforcement through hole pattern and the information of the middle layer metal pattern are summarized and output as a reinforcement information file, and the generated reinforcement information file and the structure file of the target layout are combined to form a complete reinforcement layout file. The reinforcement layout file contains through hole information to be reinforced, thereby realizing automatic reinforcement of a power line network and a ground line network in a target power supply network.
In one implementation, before summarizing the generated through hole pattern information and the intermediate layer metal pattern information and generating the reinforcement information file, the method further includes:
and carrying out through hole verification on a first overlapping area where each middle layer metal pattern is located, and eliminating the middle layer metal pattern corresponding to the first overlapping area when the fact that the reinforcing through hole pattern does not exist in the first overlapping area is detected.
Therefore, before the information of the middle layer metal patterns is collected, through hole verification is further carried out on the first overlapping area where the middle layer metal patterns are located, if the reinforcing through hole patterns do not exist in the first overlapping area, the middle layer metal patterns corresponding to the first overlapping area are removed, so that the fact that a space allowing the reinforcing through hole patterns to be generated does exist in the first overlapping area where the middle layer metal patterns are located is ensured, and accuracy of through hole defect detection is improved.
In a third aspect, the present application further provides a layout through hole defect detection device, including a graph acquisition module, a first verification module and a second verification module;
the pattern acquisition module is used for acquiring all metal patterns contained in the first wiring network and the second wiring network in the target layout;
the first verification module is used for respectively obtaining overlapping areas of each metal pattern in the first wiring network and the second wiring network, which are in overlap with the metal patterns in the upper and lower non-adjacent metal layers, performing space verification on each overlapping area, generating an intermediate layer metal pattern in each overlapping area passing the space verification, and extracting each first overlapping area of the generated metal patterns in the intermediate layer metal layer;
The second checking module is used for respectively extracting second overlapping areas of each metal pattern in the first wiring network and the second wiring network and the metal patterns in the upper and lower adjacent metal layers, checking through hole defects of each first overlapping area and each second overlapping area, and outputting the first overlapping area and the second overlapping area with the through hole defects; and when the through holes are not present in the overlapped area and the space allowing the through holes to be placed is present in the overlapped area, judging that the through holes are defective in the overlapped area.
In this way, after all the metal patterns in the target layout are acquired, according to the position relation of the metal patterns, the overlapping areas of the metal patterns and the metal patterns in the upper and lower non-adjacent metal layers exist in the wiring network, space verification is carried out on each overlapping area, an intermediate layer metal pattern is generated in the overlapping area passing the space verification, and each first overlapping area of the intermediate layer metal pattern and the metal patterns in the upper and lower adjacent metal layers is extracted. And the intermediate layer metal patterns are used as media, and the area where the metal patterns in the upper and lower non-adjacent metal layers overlap is converted into the first overlapping area where the metal patterns in the upper and lower adjacent metal layers overlap, so that the difficulty of through hole defect detection is reduced. Further, a second overlapping area of each metal pattern in the wiring network, which overlaps with the metal patterns in the upper and lower adjacent metal layers, is obtained, through hole defect verification is carried out one by one on a first intersection area of the metal patterns in the middle layer and the metal patterns in the upper and lower adjacent metal layers, and when no through hole exists in the overlapping area and a space allowing the through hole to be placed exists, the through hole defect exists in the overlapping area at the moment is judged, so that through hole defect detection of the target layout is realized. According to the through hole defect detection device, based on the thought that the middle layer metal patterns are constructed as media, the overlapping area of the metal patterns in the upper and lower non-adjacent metal layers is converted into the overlapping area of the metal patterns in the upper and lower adjacent metal layers, so that the through hole defect detection difficulty is reduced, further, through hole defect judgment is directly carried out on the overlapping area, manual inspection is not needed, performance test is not needed to be carried out on a target layout to judge whether through hole defects exist, and the operation is simple and easy to realize. And the defect detection result of the through holes is not influenced by the density of the through holes, so that the accuracy of the defect detection of the through holes is improved.
In one implementation manner, the pattern obtaining module is configured to obtain all metal patterns contained in the first wiring network and the second wiring network in the target layout, and specifically includes:
obtaining a structure file of a target layout and inputting the structure file into a layout verification tool;
acquiring all metal patterns contained in a wiring network in the target layout based on the layout verification tool; the first wiring network is a power line network, and the second wiring network is a ground line network.
In one implementation manner, the performing a spatial verification on each overlapping area, and generating an intermediate layer metal pattern in each overlapping area passing the spatial verification specifically includes:
carrying out first space verification on each overlapping area, judging whether an interlayer metal pattern exists in each overlapping area one by one, eliminating the overlapping area where the interlayer metal pattern exists, and outputting a first space verification result when the interlayer metal pattern does not exist in each overlapping area; wherein, the first space verification result comprises all overlapped areas without intermediate layer metal patterns;
and carrying out second space verification on each overlapping area in the first space verification result, judging whether a space allowing the middle layer metal pattern to be placed exists in each overlapping area one by one, and judging that the overlapping area passes through the space verification when the space allowing the middle layer metal pattern to be placed exists in the overlapping area.
In one implementation manner, each first overlapping area where the intermediate layer metal pattern generated by extraction overlaps with the metal pattern in the upper and lower adjacent metal layers specifically includes:
acquiring metal patterns in upper and lower non-adjacent metal layers corresponding to overlapping areas where each middle layer metal pattern is located one by one;
and matching the positions of the metal patterns of the middle layer and the metal patterns in the upper and lower non-adjacent metal layers corresponding to the overlapping region to generate a first overlapping region where the metal patterns of the middle layer and the metal patterns in the upper and lower adjacent metal layers overlap.
In one implementation manner, the layout through hole defect detection method further includes automatically reinforcing the target layout based on a through hole defect verification result, and specifically includes:
collecting a first overlapping area and a second overlapping area with through hole defects, and generating a through hole defect verification result;
generating corresponding reinforced through hole patterns in each overlapping area of the through hole defect verification result according to the design rule of the target layout;
summarizing each generated reinforcement through hole pattern and each middle layer metal pattern, generating a reinforcement information file, and merging the reinforcement information file with the structure file of the target layout to generate a reinforcement layout file.
In one implementation, before summarizing the generated through hole pattern information and the intermediate layer metal pattern information and generating the reinforcement information file, the method further includes:
and carrying out through hole verification on a first overlapping area where each middle layer metal pattern is located, and eliminating the middle layer metal pattern corresponding to the first overlapping area when the fact that the reinforcing through hole pattern does not exist in the first overlapping area is detected.
Drawings
FIG. 1 is a schematic flow chart of a layout through hole defect detection method provided by an embodiment of the invention;
FIG. 2 is a plan view of a layout routing network provided by an embodiment of the present invention;
FIG. 3 is a schematic flow chart of an automatic reinforcement method according to an embodiment of the present invention;
fig. 4 is an exemplary application flow chart of an automatic reinforcement method according to an embodiment of the present invention.
Detailed Description
The following describes in further detail the embodiments of the present invention with reference to the drawings and examples. The following examples are illustrative of the invention and are not intended to limit the scope of the invention.
The terms first and second and the like in the description and in the claims of the present application and in the drawings are used for distinguishing between different objects and not for describing a particular sequential order. Furthermore, the terms "comprise" and "have," as well as any variations thereof, are intended to cover a non-exclusive inclusion. For example, a process, method, system, article, or apparatus that comprises a list of steps or elements is not limited to only those listed steps or elements but may include other steps or elements not listed or inherent to such process, method, article, or apparatus.
Reference herein to "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment may be included in at least one embodiment of the present application. The appearances of such phrases in various places in the specification are not necessarily all referring to the same embodiment, nor are separate or alternative embodiments mutually exclusive of other embodiments. Those of skill in the art will explicitly and implicitly appreciate that the embodiments described herein may be combined with other embodiments.
Example 1
Referring to fig. 1, fig. 1 is a schematic flow chart of a layout through hole defect detection method according to an embodiment of the present invention. The embodiment of the invention provides a layout through hole defect detection method, which comprises steps 101 to 103, wherein the steps are as follows:
step 101: and acquiring all metal patterns contained in the first wiring network and the second wiring network in the target layout.
In an embodiment, the obtaining all the metal patterns included in the first wiring network and the second wiring network in the target layout specifically includes: obtaining a structure file of a target layout and inputting the structure file into a layout verification tool; acquiring all metal patterns contained in a wiring network in the target layout based on the layout verification tool; the first wiring network is a power line network, and the second wiring network is a ground line network. In the embodiment of the invention, the structure file of the target layout is converted into the GDS-format file and is input into the layout verification tool. GDSII is a binary file containing the geometry, text, or labels of planes in an integrated circuit layout for data conversion of the integrated circuit layout. Preferably, in the embodiment of the present invention, the converted GDS file is input to a Mentor Calibre layout verification tool, and all metal graph graphs included in the power line network and the ground line network in the target layout are obtained through the verification tool.
Referring to fig. 2, fig. 2 is a plan view of a layout wiring network according to an embodiment of the present invention. The embodiment of the invention provides a top view of a wiring network in a layout for auxiliary explanation, wherein a metal 1 shows a metal pattern positioned on a first layer of the layout, and a metal 2, a metal 3 and a metal 4 are sequentially recursively shown to show metal patterns positioned on different layers. The metal patterns among different layers are connected by adopting different through hole patterns. The through hole 1 is used for connecting the metal 1 and the metal 2, the through hole 2 is used for connecting the metal 2 and the metal 3, and the through hole 3 is used for connecting the metal 3 and the metal 4. It should be noted that, in the layout, a plurality of layers of metals, shapes of connecting through holes among the metals and the like are specifically used and adjusted according to different specific application products, and the top view of the wiring network in the layout provided by the embodiment of the invention is only used for auxiliary description.
Step 102: and respectively acquiring overlapping areas of each metal pattern in the first wiring network and the second wiring network, which are in overlap with the patterns in the upper and lower non-adjacent metal layers, performing space verification on each overlapping area, generating an intermediate layer metal pattern in each overlapping area passing the space verification, and extracting each first overlapping area of the generated intermediate layer metal pattern and the patterns in the upper and lower adjacent metal layers.
And respectively acquiring the overlapping area of each metal pattern in the power line network and the metal patterns in the upper and lower non-adjacent metal layers, and the overlapping area of each metal pattern in the ground line network and the metal patterns in the upper and lower non-adjacent metal layers. In an embodiment, the performing a spatial verification on each overlapping area, and generating an intermediate layer metal pattern in each overlapping area passing the spatial verification specifically includes: carrying out first space verification on each overlapping area, judging whether an interlayer metal pattern exists in each overlapping area one by one, eliminating the overlapping area where the interlayer metal pattern exists, and outputting a first space verification result when the interlayer metal pattern does not exist in each overlapping area; wherein, the first space verification result comprises all overlapped areas without intermediate layer metal patterns; and carrying out second space verification on each overlapping area in the first space verification result, judging whether a space allowing the middle layer metal pattern to be placed exists in each overlapping area one by one, and judging that the overlapping area passes through the space verification when the space allowing the middle layer metal pattern to be placed exists in the overlapping area. And respectively acquiring overlapping areas of the metal patterns in the power line network and the ground line network and the upper and lower non-adjacent metal patterns, and performing space verification on each overlapping area. And when detecting that the middle layer metal pattern exists in the overlapped area during the first space check, rejecting the overlapped area. Judging whether the middle layer metal patterns exist in each overlapping area one by one until all the middle layer metal patterns are detected to be absent in all the overlapping areas, and outputting a first space verification result. And the first space verification result comprises all overlapped areas without the interlayer metal patterns. And carrying out second space verification on each overlapping area in the first space verification result, and judging whether a space allowing the middle layer metal pattern to be placed exists in each overlapping area one by one. The space size of each interlayer metal pattern is determined according to the metal pattern design of a specific layout on different metal layers, and the space for placing the interlayer metal patterns in the overlapping area is not limited. When the overlap region satisfies both "no interlayer metal pattern exists" and "space allowing the interlayer metal pattern to be placed" at the same time, it is determined that the overlap region passes the space verification. As an alternative to the embodiment of the present invention, in performing the space verification, the order of the first space verification and the second space verification may be replaced, where the second space verification is performed first, and then the first space verification is performed after the overlapping area where the middle layer metal pattern is allowed to be placed is present.
In an embodiment, each first overlapping area where the metal pattern of the intermediate layer and the metal pattern in the upper and lower adjacent metal layers generated by extraction overlap specifically includes: acquiring metal patterns in upper and lower non-adjacent metal layers corresponding to overlapping areas where each middle layer metal pattern is located one by one; and matching the positions of the metal patterns of the middle layer and the metal patterns in the upper and lower non-adjacent metal layers corresponding to the overlapping area, selecting the metal patterns which are in the upper and lower adjacent metal layers relation with the metal patterns of the middle layer from the metal patterns in the upper and lower non-adjacent metal layers corresponding to the overlapping area, and acquiring a first overlapping area where the metal patterns of the middle layer and the metal patterns in the upper and lower adjacent metal layers overlap. When the intermediate layer metal patterns are generated in each overlapping area passing through the space verification, the shapes of the intermediate layer metal patterns depend on the design requirements of the target layout. And acquiring upper and lower non-adjacent metal patterns corresponding to the overlapping region where each middle layer metal pattern is positioned one by one, and performing position matching to generate a first overlapping region of the middle layer metal pattern and the upper and lower adjacent metal patterns. In the embodiment of the invention, the metal patterns in the upper and lower non-adjacent metal layers are used as media, and the overlapping area of the metal patterns in the wiring network is converted into the first overlapping area where the metal patterns in the upper and lower adjacent metal layers overlap, so that whether defects exist in the positions of the through holes and the number of the through holes between the upper and lower adjacent metal patterns or not can be detected conveniently.
Step 103: extracting second overlapping areas of each metal pattern in the first wiring network and the second wiring network and the metal patterns in the upper and lower adjacent metal layers respectively, performing through hole defect verification on each first overlapping area and each second overlapping area, and outputting the first overlapping area and the second overlapping area with the through hole defects; and when the through holes are not present in the overlapped area and the space allowing the through holes to be placed is present in the overlapped area, judging that the through holes are defective in the overlapped area.
In the embodiment of the invention, a first overlapping area in which metal patterns exist in upper and lower adjacent metal layers in a power supply network and a ground network is obtained, a second overlapping area in which metal patterns in an intermediate layer and the upper and lower adjacent metal layers exist is obtained, through hole defect verification is carried out on each first overlapping area and each second overlapping area, and when no through hole exists in the overlapping area and a space allowing the through hole to be placed exists in the overlapping area, the through hole defect is judged to exist in the overlapping area.
The embodiment of the invention also provides layout through hole defect detection equipment, which comprises a processor, a memory and a computer program stored in the memory and configured to be executed by the processor, wherein the layout through hole defect detection method is realized when the processor executes the computer program.
In an embodiment of the present invention, a computer readable storage medium is further provided, where the computer readable storage medium includes a stored computer program, and when the computer program runs, a device where the computer readable storage medium is located is controlled to execute the above method for detecting a defect of a layout through hole.
The computer program may be divided into one or more modules, which are stored in the memory and executed by the processor to accomplish the present invention, for example. The one or more modules may be a series of computer program instruction segments capable of performing a specific function for describing the execution of the computer program in a layout through hole defect detection device.
The layout through hole defect detection equipment can be computing equipment such as a desktop computer, a notebook computer, a palm computer and a cloud server. The layout through hole defect detection device may include, but is not limited to, a processor, a memory, and a display. It will be appreciated by those skilled in the art that the above components are merely examples of a layout via defect detection device and do not constitute a limitation of the layout via defect detection device, and may include more or fewer components than those described, or may be combined with certain components, or different components, e.g., the layout via defect detection device may further include an input/output device, a network access device, a bus, etc.
The processor may be a central processing unit (Central Processing Unit, CPU), other general purpose processors, digital signal processors (Digital Signal Processor, DSP), application specific integrated circuits (Application Specific Integrated Circuit, ASIC), off-the-shelf programmable gate arrays (Field-Programmable Gate Array, FPGA) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, or the like. The general purpose processor may be a microprocessor or the processor may be any conventional processor or the like, which is a control center of the layout through hole defect detection apparatus, and which connects various parts of the entire layout through hole defect detection apparatus using various interfaces and lines.
The memory may be used to store the computer program and/or module, and the processor may implement various functions of the layout through hole defect detection device by running or executing the computer program and/or module stored in the memory and invoking data stored in the memory. The memory may mainly include a storage program area and a storage data area, wherein the storage program area may store an operating system, an application program (such as a sound playing function, a text conversion function, etc.) required for at least one function, and the like; the storage data area may store data (such as audio data, text message data, etc.) created according to the use of the cellular phone, etc. In addition, the memory may include high-speed random access memory, and may also include non-volatile memory, such as a hard disk, memory, plug-in hard disk, smart Media Card (SMC), secure Digital (SD) Card, flash Card (Flash Card), at least one disk storage device, flash memory device, or other volatile solid-state storage device.
Wherein the module integrated by the layout through hole defect detection device can be stored in a computer readable storage medium if the module is realized in the form of a software functional unit and sold or used as a separate product. Based on this understanding, the present invention may implement all or part of the flow of the method of the above embodiment, or may be implemented by a computer program to instruct related hardware, where the computer program may be stored in a computer readable storage medium, and the computer program may implement the steps of each method embodiment described above when executed by a processor. Wherein the computer program comprises computer program code which may be in source code form, object code form, executable file or some intermediate form etc. The computer readable medium may include: any entity or device capable of carrying the computer program code, a recording medium, a U disk, a removable hard disk, a magnetic disk, an optical disk, a computer Memory, a Read-Only Memory (ROM), a random access Memory (RAM, random Access Memory), an electrical carrier signal, a telecommunications signal, a software distribution medium, and so forth. It should be noted that the computer readable medium contains content that can be appropriately scaled according to the requirements of jurisdictions in which such content is subject to legislation and patent practice, such as in certain jurisdictions in which such content is subject to legislation and patent practice, the computer readable medium does not include electrical carrier signals and telecommunication signals. Those of ordinary skill in the art will understand and implement the present invention without undue burden.
The embodiment of the invention provides a layout through hole defect detection method, which is characterized in that after all metal patterns in a target layout are acquired, the overlapping areas of the metal patterns and the metal patterns in the upper and lower non-adjacent metal layers are acquired according to the position relation of the metal patterns, the space verification is carried out on each overlapping area, an intermediate layer metal pattern is generated in the overlapping area passing the space verification, and each first overlapping area of the intermediate layer metal pattern and the metal patterns in the upper and lower adjacent metal layers is extracted. And the intermediate layer metal patterns are used as media, and the area where the metal patterns in the upper and lower non-adjacent metal layers overlap is converted into the first overlapping area where the metal patterns in the upper and lower adjacent metal layers overlap, so that the difficulty of through hole defect detection is reduced. Further, a second overlapping area of each metal pattern in the wiring network, which overlaps with the metal patterns in the upper and lower adjacent metal layers, is obtained, through hole defect verification is carried out one by one on a first intersection area of the metal patterns in the middle layer and the metal patterns in the upper and lower adjacent metal layers, and when no through hole exists in the overlapping area and a space allowing the through hole to be placed exists, the through hole defect exists in the overlapping area at the moment is judged, so that through hole defect detection of the target layout is realized. According to the through hole defect detection method provided by the embodiment of the invention, based on the thought of constructing the middle layer metal patterns as the medium, the overlapping area of the metal patterns in the upper and lower non-adjacent metal layers is converted into the overlapping area of the metal patterns in the upper and lower adjacent metal layers, so that the through hole defect detection difficulty is reduced, further, the through hole defect judgment is directly carried out on the overlapping area, the manual inspection is not needed, the performance test is not needed to be carried out on the target layout to judge whether the through hole defect exists, and the operation is simple and easy to realize. And the defect detection result of the through holes is not influenced by the density of the through holes, so that the accuracy of the defect detection of the through holes is improved.
Example 2
Referring to fig. 3, fig. 3 is a schematic flow chart of an automatic reinforcement method according to an embodiment of the invention. The embodiment of the invention provides an automatic reinforcement method, which comprises the following steps 201 to 204:
step 201: performing through hole defect detection on the target layout by adopting the layout through hole defect detection method described in the embodiment 1;
step 202: collecting a first overlapping area and a second overlapping area with through hole defects, and generating a through hole defect verification result;
step 203: generating corresponding reinforced through hole patterns in each overlapping area of the through hole defect verification result according to the design rule of the target layout;
step 204: summarizing each generated reinforcement through hole pattern and each middle layer metal pattern, generating a reinforcement information file, and merging the reinforcement information file with the structure file of the target layout to generate a reinforcement layout file.
In the embodiment of the invention, the structure file of the target layout is input into the layout verification tool, and the through hole defect detection is performed on the target layout based on the layout through hole defect detection method described in the embodiment 1. Referring to fig. 4, fig. 4 is an exemplary application flow chart of an automatic reinforcement method according to an embodiment of the present invention. After the through hole defect detection is completed, summarizing each generated reinforced through hole graph and each middle layer metal graph, generating a reinforced information file, and merging the reinforced information file with the structure file of the target layout to generate a reinforced layout file. And automatically adding reinforcing through hole patterns corresponding to the through hole layers in each overlapping area with the through hole defects according to the design rule of the target layout by a layout verification tool, wherein the generated reinforcing through hole patterns are required to meet drc verification requirements. Summarizing the information of each generated reinforcement through hole pattern and the information of the middle layer metal pattern, outputting the information as a GDS format reinforcement information file, merging the generated reinforcement information file with the GDS file of the target layout, and merging the generated reinforcement information file with the GDS file of the target layout into a complete GDS file, namely, a reinforcement layout file. The reinforced layout file contains through hole information to be reinforced, so that the automatic reinforcement of the power line network and the ground line network is realized.
As an optimization scheme of the embodiment of the invention, before summarizing the generated through hole pattern information and the middle layer metal pattern information and generating the reinforcement information file, the method further comprises the following steps: and carrying out through hole verification on a first overlapping area where each middle layer metal pattern is located, and eliminating the middle layer metal pattern corresponding to the first overlapping area when the fact that the reinforcing through hole pattern does not exist in the first overlapping area is detected. Before the information of the middle layer metal patterns is collected, through hole verification is carried out on a first overlapping area where the middle layer metal patterns are located, if the first overlapping area does not contain the reinforcing through hole patterns, the middle layer metal patterns corresponding to the first overlapping area are removed, and therefore the fact that a space allowing the reinforcing through hole patterns to be generated does exist in the first overlapping area where the middle layer metal patterns are located is ensured.
Example 3
The embodiment of the invention provides a layout through hole defect detection device, which comprises a graph acquisition module, a first verification module and a second verification module;
the pattern acquisition module is used for acquiring all metal patterns contained in the first wiring network and the second wiring network in the target layout;
the first verification module is used for respectively obtaining overlapping areas of each metal pattern in the first wiring network and the second wiring network, which are in overlap with the metal patterns in the upper and lower non-adjacent metal layers, performing space verification on each overlapping area, generating an intermediate layer metal pattern in each overlapping area passing the space verification, and extracting each first overlapping area of the generated metal patterns in the intermediate layer metal layer;
The second checking module is used for respectively extracting second overlapping areas of each metal pattern in the first wiring network and the second wiring network and the metal patterns in the upper and lower adjacent metal layers, checking through hole defects of each first overlapping area and each second overlapping area, and outputting the first overlapping area and the second overlapping area with the through hole defects; and when the through holes are not present in the overlapped area and the space allowing the through holes to be placed is present in the overlapped area, judging that the through holes are defective in the overlapped area.
In an embodiment, the pattern obtaining module is configured to obtain all metal patterns included in the first wiring network and the second wiring network in the target layout, and specifically includes: obtaining a structure file of a target layout and inputting the structure file into a layout verification tool; acquiring all metal patterns contained in a wiring network in the target layout based on the layout verification tool; the first wiring network is a power line network, and the second wiring network is a ground line network.
In an embodiment, the performing a spatial verification on each overlapping area, and generating an intermediate layer metal pattern in each overlapping area passing the spatial verification specifically includes: carrying out first space verification on each overlapping area, judging whether an interlayer metal pattern exists in each overlapping area one by one, eliminating the overlapping area where the interlayer metal pattern exists, and outputting a first space verification result when the interlayer metal pattern does not exist in each overlapping area; wherein, the first space verification result comprises all overlapped areas without intermediate layer metal patterns; and carrying out second space verification on each overlapping area in the first space verification result, judging whether a space allowing the middle layer metal pattern to be placed exists in each overlapping area one by one, and judging that the overlapping area passes through the space verification when the space allowing the middle layer metal pattern to be placed exists in the overlapping area.
In an embodiment, each first overlapping area where the metal pattern of the intermediate layer and the metal pattern in the upper and lower adjacent metal layers generated by extraction overlap specifically includes: acquiring metal patterns in upper and lower non-adjacent metal layers corresponding to overlapping areas where each middle layer metal pattern is located one by one; and matching the positions of the metal patterns of the middle layer and the metal patterns in the upper and lower non-adjacent metal layers corresponding to the overlapping region to generate a first overlapping region where the metal patterns of the middle layer and the metal patterns in the upper and lower adjacent metal layers overlap.
In one embodiment, the layout through hole defect detection method further includes automatically reinforcing the target layout based on a through hole defect verification result, and specifically includes: collecting a first overlapping area and a second overlapping area with through hole defects, and generating a through hole defect verification result; generating corresponding reinforced through hole patterns in each overlapping area of the through hole defect verification result according to the design rule of the target layout; summarizing each generated reinforcement through hole pattern and each middle layer metal pattern, generating a reinforcement information file, and merging the reinforcement information file with the structure file of the target layout to generate a reinforcement layout file.
In one embodiment, before the generated through hole pattern information and the intermediate layer metal pattern information are summarized and the reinforcing information file is generated, the method further comprises: and carrying out through hole verification on a first overlapping area where each middle layer metal pattern is located, and eliminating the middle layer metal pattern corresponding to the first overlapping area when the fact that the reinforcing through hole pattern does not exist in the first overlapping area is detected. It will be clear to those skilled in the art that, for convenience and brevity of description, reference may be made to the corresponding process in the foregoing method embodiment for the specific working process of the above-described apparatus, which is not described herein again.
The embodiment of the invention provides a layout through hole defect detection device, which is used for further acquiring overlapping areas of metal patterns in upper and lower non-adjacent metal layers in a wiring network according to the position relation of the metal patterns after acquiring all the metal patterns in a target layout, performing space verification on each overlapping area, generating an intermediate layer metal pattern in the overlapping area passing the space verification, and extracting each first overlapping area of the intermediate layer metal pattern and the metal patterns in the upper and lower adjacent metal layers. And the intermediate layer metal patterns are used as media, and the area where the metal patterns in the upper and lower non-adjacent metal layers overlap is converted into the first overlapping area where the metal patterns in the upper and lower adjacent metal layers overlap, so that the difficulty of through hole defect detection is reduced. Further, a second overlapping area of each metal pattern in the wiring network, which overlaps with the metal patterns in the upper and lower adjacent metal layers, is obtained, through hole defect verification is carried out one by one on a first intersection area of the metal patterns in the middle layer and the metal patterns in the upper and lower adjacent metal layers, and when no through hole exists in the overlapping area and a space allowing the through hole to be placed exists, the through hole defect exists in the overlapping area at the moment is judged, so that through hole defect detection of the target layout is realized. According to the through hole defect detection device provided by the embodiment of the invention, the overlapping area of the metal patterns in the upper and lower non-adjacent metal layers is converted into the overlapping area of the metal patterns in the upper and lower adjacent metal layers based on the thought of constructing the middle layer metal patterns as the medium, so that the through hole defect detection difficulty is reduced, further, the through hole defect judgment is directly carried out on the overlapping area, the manual inspection is not needed, the performance test is not needed to be carried out on the target layout to judge whether the through hole defect exists, and the operation is simple and easy to realize. And the defect detection result of the through holes is not influenced by the density of the through holes, so that the accuracy of the defect detection of the through holes is improved.
The foregoing is merely a preferred embodiment of the present invention, and it should be noted that modifications and substitutions can be made by those skilled in the art without departing from the technical principles of the present invention, and these modifications and substitutions should also be considered as being within the scope of the present invention.
Claims (10)
1. A layout through hole defect detection method is characterized by comprising the following steps:
acquiring all metal patterns contained in a first wiring network and a second wiring network in a target layout;
respectively acquiring overlapping areas of each metal pattern in the first wiring network and the second wiring network, which are in existence with metal patterns in upper and lower non-adjacent metal layers, performing space verification on each overlapping area, generating an intermediate layer metal pattern in each overlapping area passing the space verification, and extracting each first overlapping area of the generated intermediate layer metal pattern and the metal patterns in the upper and lower adjacent metal layers;
extracting second overlapping areas of each metal pattern in the first wiring network and the second wiring network and the metal patterns in the upper and lower adjacent metal layers respectively, performing through hole defect verification on each first overlapping area and each second overlapping area, and outputting the first overlapping area and the second overlapping area with the through hole defects; and when the through holes are not present in the overlapped area and the space allowing the through holes to be placed is present in the overlapped area, judging that the through holes are defective in the overlapped area.
2. The method for detecting a defect of a through hole in a layout according to claim 1, wherein the step of obtaining all metal patterns contained in the first wiring network and the second wiring network in the target layout specifically comprises the steps of:
obtaining a structure file of a target layout and inputting the structure file into a layout verification tool;
acquiring all metal patterns contained in a wiring network in the target layout based on the layout verification tool; the first wiring network is a power line network, and the second wiring network is a ground line network.
3. The method for detecting defects of a layout through hole according to claim 1, wherein the performing a spatial verification on each overlapping region, and generating an interlayer metal pattern in each overlapping region passing the spatial verification, specifically comprises:
carrying out first space verification on each overlapping area, judging whether an interlayer metal pattern exists in each overlapping area one by one, eliminating the overlapping area where the interlayer metal pattern exists, and outputting a first space verification result when the interlayer metal pattern does not exist in each overlapping area; wherein, the first space verification result comprises all overlapped areas without intermediate layer metal patterns;
And carrying out second space verification on each overlapping area in the first space verification result, judging whether a space allowing the middle layer metal pattern to be placed exists in each overlapping area one by one, and judging that the overlapping area passes through the space verification when the space allowing the middle layer metal pattern to be placed exists in the overlapping area.
4. The method for detecting a defect of a layout through hole according to claim 1, wherein each first overlapping region where the metal pattern of the intermediate layer generated by extraction overlaps with the metal pattern in the upper and lower adjacent metal layers specifically comprises:
acquiring metal patterns in upper and lower non-adjacent metal layers corresponding to overlapping areas where each middle layer metal pattern is located one by one;
and matching the positions of the metal patterns of the middle layer and the metal patterns in the upper and lower non-adjacent metal layers corresponding to the overlapping region to generate a first overlapping region where the metal patterns of the middle layer and the metal patterns in the upper and lower adjacent metal layers overlap.
5. An automatic reinforcement method, comprising:
performing through hole defect detection on the target layout by adopting the layout through hole defect detection method according to any one of claims 1-4;
Collecting a first overlapping area and a second overlapping area with through hole defects, and generating a through hole defect verification result;
generating corresponding reinforced through hole patterns in each overlapping area of the through hole defect verification result according to the design rule of the target layout;
summarizing each generated reinforcement through hole pattern and each middle layer metal pattern, generating a reinforcement information file, and merging the reinforcement information file with the structure file of the target layout to generate a reinforcement layout file.
6. The automatic reinforcement method according to claim 5, further comprising, before summarizing the generated via pattern information and the intermediate layer metal pattern information and generating the reinforcement information file:
and carrying out through hole verification on a first overlapping area where each middle layer metal pattern is located, and eliminating the middle layer metal pattern corresponding to the first overlapping area when the fact that the reinforcing through hole pattern does not exist in the first overlapping area is detected.
7. The layout through hole defect detection device is characterized by comprising a graph acquisition module, a first verification module and a second verification module;
the pattern acquisition module is used for acquiring all metal patterns contained in the first wiring network and the second wiring network in the target layout;
The first verification module is used for respectively obtaining overlapping areas of each metal pattern in the first wiring network and the second wiring network, which are in overlap with the metal patterns in the upper and lower non-adjacent metal layers, performing space verification on each overlapping area, generating an intermediate layer metal pattern in each overlapping area passing the space verification, and extracting each first overlapping area of the generated metal patterns in the intermediate layer metal layer;
the second checking module is used for respectively extracting second overlapping areas of each metal pattern in the first wiring network and the second wiring network and the metal patterns in the upper and lower adjacent metal layers, checking through hole defects of each first overlapping area and each second overlapping area, and outputting the first overlapping area and the second overlapping area with the through hole defects; and when the through holes are not present in the overlapped area and the space allowing the through holes to be placed is present in the overlapped area, judging that the through holes are defective in the overlapped area.
8. The layout through hole defect detection device according to claim 7, wherein the pattern acquisition module is configured to acquire all metal patterns included in the first wiring network and the second wiring network in the target layout, and specifically includes:
Obtaining a structure file of a target layout and inputting the structure file into a layout verification tool;
acquiring all metal patterns contained in a wiring network in the target layout based on the layout verification tool; the first wiring network is a power line network, and the second wiring network is a ground line network.
9. The layout through hole defect detection device according to claim 7, wherein the performing spatial verification on each overlapping area, and generating an interlayer metal pattern in each overlapping area passing the spatial verification, specifically comprises:
carrying out first space verification on each overlapping area, judging whether an interlayer metal pattern exists in each overlapping area one by one, eliminating the overlapping area where the interlayer metal pattern exists, and outputting a first space verification result when the interlayer metal pattern does not exist in each overlapping area; wherein, the first space verification result comprises all overlapped areas without intermediate layer metal patterns;
and carrying out second space verification on each overlapping area in the first space verification result, judging whether a space allowing the middle layer metal pattern to be placed exists in each overlapping area one by one, and judging that the overlapping area passes through the space verification when the space allowing the middle layer metal pattern to be placed exists in the overlapping area.
10. The layout through hole defect detection device according to claim 7, wherein each first overlapping region where the intermediate layer metal pattern generated by extraction overlaps with the metal pattern in the upper and lower adjacent metal layers specifically comprises:
acquiring metal patterns in upper and lower non-adjacent metal layers corresponding to overlapping areas where each middle layer metal pattern is located one by one;
and matching the positions of the metal patterns of the middle layer and the metal patterns in the upper and lower non-adjacent metal layers corresponding to the overlapping region to generate a first overlapping region where the metal patterns of the middle layer and the metal patterns in the upper and lower adjacent metal layers overlap.
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