JP3979835B2 - Logic circuit verification method and through current improvement method - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention is used in a CAD device or the like for supporting design of an electronic circuit, and a logic circuit verification method for verifying whether or not a logic circuit in a created electronic circuit is correctly connected according to a protocol, and Through current improvement method It is about.
[0002]
[Prior art]
In recent years, the scale of semiconductor chips has increased dramatically, and development of semiconductor integrated circuits has become the mainstream using CAD devices. Furthermore, it is very difficult to manually check the connection rules, and a method using a CAD device that automatically performs verification has been proposed (see Japanese Patent Laid-Open No. 10-334124).
[0003]
In this conventional logic circuit verification device, a net list indicating the connection state of the logic circuit is extracted from the circuit diagram created by the logic circuit diagram creation device, input to the net list input unit, and the logic list is input to the verification unit. It conveys circuit connection information.
[0004]
In addition, a library with high impedance control information is input to the library input section, and it is determined whether the tristate pin is directly connected to power supply or ground according to the flowchart and whether the next stage connection is independent or not. In addition, the floating state is determined, and information for each logic circuit is transmitted to the verification unit. Based on these, the verification unit determines whether the connection state of the logic circuit in the circuit diagram conforms to the rules based on the verification rule stored in the verification rule storage area, and the result is an error / warning. Output from the output section.
[0005]
[Problems to be solved by the invention]
However, in such a conventional logic circuit verification method and through current verification method, when performing floating and short check, the control terminal of the cell having the output terminal of the previous tri-state cell is directly connected to the power supply or ground. Need to be. Therefore, even if the potential is fixed upstream of the upstream circuit connected to this control terminal, etc., since the potential of the control terminal is not directly fixed, it is treated as a floating error. Since there is a possibility, when a designer avoids a problem in terms of a circuit, it is necessary to visually determine whether or not it is a pseudo error.
[0006]
Even if there is a terminal that outputs a high-impedance state, depending on the structure receiving the signal, a through current does not flow, and although there is a possibility that it will not cause a problem in the circuit, it is all handled as a floating error. Therefore, since this may also be a pseudo error, it is necessary for the designer to visually determine whether it is a pseudo error as described above.
[0007]
As described above, if the potential of the control terminal of the circuit having the output terminal of the tri-state cell is not directly fixed, it is recognized as a floating error regardless of the cell configuration of the next stage. It was necessary to visually check whether or not the design period was prolonged and the work efficiency was lowered.
[0008]
The present invention can automatically perform error determination even when the potential of a control terminal of a cell having an output terminal of a tristate cell, which has conventionally been visually checked, is not fixed, and is high. Logic that can automatically improve the work efficiency by shortening the design period and increasing efficiency by automatically recognizing the configuration on the receiving side of the impedance state and automatically detecting the problematic configuration in the high impedance state An object is to provide a circuit verification method and a through current verification method. In addition, a method for improving through current is proposed.
[0009]
[Means for Solving the Problems]
The logic circuit verification method of the present invention solves the above-mentioned problem by taking the following measures. That is, A design apparatus having a netlist input unit, a library in which circuit information is stored, a verification rule storage unit in which verification rules are stored, and a verification unit that makes a determination based on the verification rules Semiconductor integrated circuit design Design method to do In Based on the net list input from the net list input unit, the verification unit, Extracting a portion where a plurality of output terminals of the tri-state cell are commonly connected; The verification unit Determining whether the input to the control terminal from the circuit connected to the control terminal of the extracted tri-state cell is exclusive; The verification unit A step of detecting that a high impedance state is generated at the common connection portion when the output terminals of all the tristate cells output a high impedance state among the cases where they are not exclusive.
[0010]
In this case, if the circuits connected to the control terminals of the plurality of tristate cells are extracted and the outputs from all the tristate cells are in a high impedance state by a combination of signals input to the control terminals, this is common. Assuming that the connected location is in the high impedance state, the location where the high impedance state is generated is detected.
[0011]
Thereby, in the situation where a plurality of output terminals of the tri-state cell are connected in common, the location where the high impedance state is generated can be correctly verified. As a result, it is possible to smoothly shift to a process for avoiding a high impedance state after the fact and a process for checking whether or not a through current actually occurs.
[0042]
In addition, the present invention about the through current improvement method, The verification unit In the logic circuit verification method described above, the high impedance state is avoided by inserting a high impedance state avoidance circuit for the location detected as the high impedance state, and more preferably, The verification unit In the above circuit change, the circuit change is performed by inserting a bus hold circuit at a location detected as a high impedance state.
[0043]
By inserting the bus hold circuit, the signal state before entering the high impedance state can be held. Thereby, generation | occurrence | production of a through current can be suppressed.
[0044]
DETAILED DESCRIPTION OF THE INVENTION
Embodiments of a logic circuit verification method and a through current verification method according to the present invention will be described below in detail with reference to the drawings.
[0045]
(First embodiment)
The first embodiment of the present invention will be described based on the flow shown in FIG.
[0046]
In step S101, a portion where the output terminals of the tristate cells are commonly connected is extracted. The extracted result is shown in FIG.
[0047]
G101 and G102 surrounded by dotted lines in FIG. 2 are tristate inverters, and C101 and C102 are control terminals. The tri-state inverter functions as an ordinary inverter when a “High” input is input to the control terminal, and the output is in a high impedance state (Hiz) when a “Low” input is input.
[0048]
In the extracted circuit shown in FIG. 2, two output terminals of the tri-state inverters G101 and G102 are commonly connected.
[0049]
Next, in step S102, a circuit connected to the control terminals C101 and C102 of the tristate cell extracted in step S101 is extracted.
[0050]
FIG. 3 shows the result of extracting the circuits connected to the control terminals C101 and C102 of the tristate inverters G101 and G102 in the circuit extracted in step S101. IN101 and IN102 represent input terminals to the circuits G103 and G104 connected to the control terminals C101 and C102 of the tri-state inverters G101 and G102. G103 represents an inverter, and G104 represents a NOR gate.
[0051]
Next, in step S103, a signal input to the control terminal of the tristate cell is checked. In FIG. 3, it can be seen that when the inputs to the input terminals IN101 and IN102 are both “High”, the inputs to the control terminals C101 and C102 of the tristate inverters G101 and G102 are both “Low”.
[0052]
Next, in step S104, it is determined whether or not the input to the control terminal in the plurality of tri-state cells whose output terminals are commonly connected is not exclusive.
[0053]
In the example of the circuit of FIG. 3, it can be seen that the inputs to the control terminals C101 and C102 of the tristate inverters G101 and G102 are both “Low” and are not exclusive.
[0054]
Next, in step S105, it is checked whether the outputs of all the tristate cells extracted in step S101 are in a high impedance state with respect to the inputs to the control terminals that are not exclusive.
[0055]
In the circuit shown in FIG. 3, the outputs of the two tri-state inverters G101 and G102 in the extracted circuit are both in a high impedance state, and a location where the two outputs are connected in common is detected as a location where a high impedance state is generated. The
[0056]
The control terminals C101 and C102 of the two tristate inverters G101 and G102 are not directly fixed in potential. In such a case, in the prior art, all are unconditionally determined to be floating errors, which is a factor including pseudo errors.
[0057]
On the other hand, according to the present embodiment, only the actual high-impedance state occurrence location is correctly determined as a high-impedance state occurrence location. , It is determined that the high impedance state is not generated. That is, occurrence of a pseudo error can be avoided.
[0058]
Since it is possible to avoid a pseudo error in the verification of the high impedance state occurrence location, it is reasonable and efficient to check the processing to avoid the subsequent high impedance state and whether or not a through current actually occurs. Can be performed in an efficient manner. That is, the design period can be shortened and the efficiency can be improved, and the working efficiency can be improved.
[0059]
(Second Embodiment)
Next, a logic circuit verification method according to the second embodiment of the present invention will be described with reference to the drawings.
[0060]
FIG. 4 is a block diagram showing a schematic configuration of a logic circuit verification apparatus according to the second embodiment of the present invention. In FIG. 4, reference numeral 41 is a logic circuit diagram creation device comprising a CAD device body, 42 is a net list input unit for inputting a net list indicating connection information between logic circuits, and 43 is a library indicating circuit information of the logic circuit. A library input unit 44, a verification unit 44, an error / warning output unit 45 for outputting a verification result of the verification unit 44, and a verification rule storage region 46 for storing a logic circuit verification rule.
[0061]
The feature of this embodiment is that transistor level connection information is input to the library input to the library input unit 43, and the verification unit 44 determines the tristate cell based on the verification rules stored in the verification rule storage area 46. A transistor connection verification process is performed on the input pin at the next stage of a cell where a high impedance state may be output from the output terminal, and a through current flows when a high impedance state is input. This is because the floating determination is performed for the cell in which the current cell is located.
[0062]
Hereinafter, a method for verifying a cell receiving a high impedance state will be described in detail with reference to FIG.
[0063]
FIG. 5 is a flowchart showing processing in the verification unit 44. This shows a verification method of a cell that receives a signal when there is a possibility that a high impedance state is output from a cell having an output terminal of a tristate cell.
[0064]
The verification unit 44 first detects a cell having a tristate cell output terminal (step S51).
[0065]
Next, a cell whose potential is not directly fixed to the control terminal and which may output a high impedance state is detected (step S52).
[0066]
Here, if there is no possibility that the cells having the output terminals of all the tristate cells output the high impedance state, the normal output terminal connection check is performed (step S53).
[0067]
Attention is paid to the cell connected to the next stage with respect to the cell determined to have the possibility of outputting the high impedance state in step S52. The target cell is extracted from the transistor level cell library, and the transistor set 1 connected to the input terminal of the target cell is detected (step S54).
[0068]
Next, a list of transistor pairs of a p-type transistor and an n-type transistor and one pair of terminals, that is, a drain terminal and a source terminal connected to each other, is created from the transistor set 1 detected in step S54 ( Step S55).
[0069]
Next, the connection destination of the other terminal of the transistor pair to which one terminal (drain and source) detected in step S55 is connected is checked to determine whether or not it is directly connected to the power supply and ground. (Step S56).
[0070]
In step S56, if there is no transistor pair having a terminal directly connected to the power source and the ground, no through current flows even when a high impedance state is input. Step S53) is performed.
[0071]
If there is a pair of transistors that are directly connected to the power supply and the ground, a through error flows when this terminal is in a high impedance state, and a floating error is output (step S57).
[0072]
As described above, according to the second embodiment, in the logic circuit verification process, when the potential of the control terminal of the circuit having the output terminal of the tristate cell is not directly fixed, there is an input in the high impedance state. However, since the floating error is determined according to the configuration of the cell in the next stage, it is possible to clearly recognize what was conventionally a pseudo error as not an error, and eliminate the need for subsequent visual confirmation. . Therefore, the design period can be shortened and the work efficiency can be improved.
[0073]
Also, since only existing libraries such as transistor level cell information such as SPICE netlist are used, it can be easily incorporated into the design flow.
[0074]
(Third embodiment)
Next, a logic circuit verification method according to the third embodiment of the present invention will be described with reference to the drawings.
[0075]
FIG. 6 is a flowchart for adding information to the library input to the library input unit 43 of FIG. FIG. 7 shows an example of connection of transistors in the cell, and FIG. 8 is a flowchart showing a method of verifying the cell on the signal receiving side when the high impedance state is output in the verification unit 44 of FIG. is there.
[0076]
First, in order to add information on cells and input terminals in which a problem occurs in a high impedance state to the library input to the library input unit 43, for all cells in the cell library, the transistors connected to each input terminal Detection is performed to create information on transistor set 1 (step S61).
[0077]
Next, a list of transistor pairs in which one terminal of each transistor, that is, a drain terminal and a source terminal is connected, is created from the transistor set 1 as a transistor pair of a p-type transistor and an n-type transistor (step S62).
[0078]
In the list of transistor pairs created here, it is determined whether or not the terminal connected to each other and the other terminal are directly connected to the power supply and the ground (step S63).
[0079]
In step S63, if there is no transistor pair having a terminal directly connected to the power supply and the ground, no through current flows even when a high impedance state is input. A pin having no problem even in the state is added to the cell library information (step S64).
[0080]
In addition, if there is a transistor pair that is directly connected to the power supply and the ground in the transistor pair list connected to each input terminal, a through current flows when this terminal enters a high impedance state. Is added to the cell library as a floating error in response to the input (step S65).
[0081]
Next, the connection determination in step S63 in FIG. 6 will be described using an example with reference to FIG.
[0082]
For example, a case will be described where cells having transistor connection information as shown in FIGS. 7A and 7B exist in the library.
[0083]
In the case of FIG. 7A, the input terminal A is connected to one p-type transistor and one n-type transistor, and the terminals are connected to each other through the OUT terminal. The other terminal connected to each other is directly connected to the power supply and the ground. Therefore, a through current flows when the input terminal A is in a high impedance state. Therefore, information that causes a floating error when a high impedance state is input is added to the library.
[0084]
Further, in the case of FIG. 7B, there are two input terminals A and B, and the transistor connected to the input terminal A has a structure in which a through current flows as in FIG. Add the information.
[0085]
As for the transistor connected to the input terminal B, there is one transistor pair having terminals connected to each other by a p-type transistor and an n-type transistor (Q _P1 And Q _N1 ), One transistor Q _P1 Is connected to the power supply, while the other transistor Q is connected to the power supply. _N1 Since the other terminal is not directly connected to the ground, it is not determined that a through current flows.
[0086]
Next, a method for verifying a cell that receives a signal when a high impedance state is output will be described with reference to the flowchart of FIG.
[0087]
First, a net list having circuit connection information is read, and a cell having a tristate cell output terminal is detected (step S81).
[0088]
Next, it is determined whether there is a possibility that the detected cell outputs an output in a high impedance state (step S82).
[0089]
If there is no possibility of outputting a high impedance state, the through current detection process is terminated.
[0090]
If there is a possibility of outputting a high impedance state, check the cell and input terminal connected to the next stage, perform verification processing with a library that has information on whether or not a through current flows when inputting in the high impedance state, If the cell and pin match, a floating error is output (step S83).
[0091]
When the process of step S83 is compared with the case of the second embodiment, it corresponds to a case in which steps S54, S55, and S56 of FIG. 5 are omitted, and a great simplification is performed.
[0092]
As described above, according to the third embodiment, in the logic circuit verification processing, the terminal through which the through current flows through the input in the high impedance state is determined from the cell information at the transistor level in advance, and the through circuit is created. The verification processing time for whether or not current flows can be shortened compared to the second embodiment, and the design period can be further shortened.
[0093]
(Fourth embodiment)
9 to 13 show a fourth embodiment of the present invention.
[0094]
FIG. 9 is a flowchart illustrating a through current verification method according to the fourth embodiment. In FIG. 9, reference numeral 301 denotes a net list in which connection relationships of cells constituting the semiconductor integrated circuit are entered. Reference numeral 302 denotes a transistor switching table that describes whether or not the p-type transistor and the n-type transistor are driven when the input of the inverter cell is changed to 1, 0 or a high impedance state. . Reference numeral 303 denotes a cell internal netlist describing the connection relationship of the transistors in the cell. A through current input pattern 304 indicates an input pattern through which a through current flows when two input pins are provided.
[0095]
FIG. 10 is a diagram showing the contents of the transistor switching table 302.
[0096]
FIG. 11A is a diagram showing a transistor configuration of a 2-input NAND cell. FIG. 11B is a diagram showing a transistor configuration of a 2-input NOR cell.
[0097]
FIG. 12 is a diagram showing a result of analyzing a transistor structure in the case of a two-input NAND.
[0098]
A vertically stacked structure is defined as a structure in which p-type transistors or n-type transistors are connected in series. A laterally stacked structure is defined as a structure in which p-type transistors or n-type transistors are connected in parallel.
[0099]
An example of a vertically stacked structure of n-type transistors is a NAND cell. An example of a vertically stacked structure of p-type transistors is a NOR cell.
[0100]
FIG. 13 is a diagram showing the contents of the through current input pattern 304. FIG. 13A shows a through current input pattern when n-type transistors in a two-input cell have a vertically stacked structure. FIG. 13B shows a through current input pattern when the p-type transistors in the 2-input cell have a vertically stacked structure.
[0101]
Next, a through current verification method will be described with reference to FIGS. 9 to 13 by taking a 2-input NAND cell as an example.
[0102]
In the cell extraction process of step S301 in FIG. 9, a tristate cell is searched from the netlist 301, and a cell connected to the output terminal of the tristate cell (hereinafter referred to as a verification target cell) is extracted.
[0103]
In the transistor switching table creation step in step S302, the transistor switching table 302 is created.
[0104]
As illustrated in FIG. 10, when the input value of the inverter cell is 1, the n-type transistor is driven and the p-type transistor is not driven. When the input value of the inverter cell is 0, the n-type transistor is not driven and the p-type transistor is driven. When the input value of the inverter cell is in a high impedance state, both the n-type transistor and the p-type transistor are driven.
[0105]
Based on this concept, in step S302 of FIG. 9, a transistor switching table 302 is generated that indicates whether or not the transistor is driven according to the input value.
[0106]
In the cell structure analysis step of step S303, the extracted cell internal netlist 303 of the verification target cell is input, and whether the transistor having a vertically stacked transistor for each input pin is an n-type transistor or a p-type transistor. Judging.
[0107]
The reason for judging the vertically stacked transistors is that a through current does not flow unless the transistors connected in series are in a driving state.
[0108]
If the extracted verification target cell is a two-input NAND having an a pin and a b pin as input pins, as shown in FIG. 11 (a), n-type transistors are vertically stacked on both the a pin and the b pin. . Therefore, it is remembered that n-type transistors have a vertically stacked structure.
[0109]
In the through current input pattern extraction step of step S304, the input value driven by the vertically stacked transistor is referred to from the transistor switching table 302, and the through current input when the input pin owned by the extraction cell enters the high impedance state Create a pattern.
[0110]
When the extraction cell is a two-input NAND, the n-type transistors have a vertically stacked structure. Therefore, when a high impedance state is input to the a pin, the b pin is a condition for driving the n-type transistor of the transistor switching table 302. An input value of 1 is a through current input pattern for passing through current.
[0111]
Specifically, it is as follows.
[0112]
The two-input NAND shown in FIG. 11A causes a through current to flow through the p-type transistor Q. _P3 N-type transistor Q _N3 , Q _N4 And p-type transistor Q _P4 N-type transistor Q _N3 , Q _N4 Are turned on at the same time.
[0113]
In the former case, if the a pin is an input in a high impedance state, the p-type transistor Q _P3 N-type transistor Q _N3 Will be turned on at the same time. _N4 This is the case when the two are simultaneously turned on, which is when the input value of the b pin is 1.
[0114]
In the latter case, if the b pin is an input in a high impedance state, the p-type transistor Q _P4 N-type transistor Q _N4 Are turned on at the same time. _P3 This is the case when the two are simultaneously turned on, when the input value of the a pin is 1.
[0115]
Therefore, FIG. 13A is a through-current input pattern of 2-input NAND.
[0116]
Returning to FIG. 9, in the through current verification process in step S <b> 305, it is confirmed whether the extracted input pin of the verification target cell may correspond to the through current input pattern 304. If the verification target cell is a two-input NAND, it may be confirmed whether the input pin may have two types of input patterns shown in FIG. That is, the input pattern to be confirmed is when the a pin is in a high impedance state and the b pin has an input value of 1, and when the b pin is in a high impedance state and at the same time the a pin has an input value of 1. Yes, in these cases a through current flows, otherwise no through current flows.
[0117]
As described above, according to the present embodiment, by creating a through current input pattern from the transistor switching table, whether the input pin of the extracted verification target cell may become a through current input pattern (the through current is It can be confirmed at high speed without performing circuit simulation.
[0118]
(Fifth embodiment)
FIG. 17 is a flowchart showing a through current verification method according to the fifth embodiment of the present invention. In the figure, reference numeral 311 denotes a through current input pattern of all cells storing through current input patterns of all cells expected to be used in the semiconductor integrated circuit. S301 to S305 indicate the same steps as those in the fourth embodiment.
[0119]
Next, a through current verification method according to a fifth embodiment will be described below with reference to FIG.
[0120]
Unlike the fourth embodiment, the through current input pattern 304 is not created after the extracted verification target cell is determined, but the through current input patterns 311 of all the cells included in the semiconductor integrated circuit are created in advance. I am doing it.
[0121]
In the through current input pattern creation cell selection step in step S311, a cell in which a through current input pattern is to be created is selected as a verification candidate cell from a group of cells expected to be used in the semiconductor integrated circuit.
[0122]
In step S312 for determining whether or not a through current input pattern has been created in all cells, the through current input pattern creation cell selection step in step S311 until step S311 creates a through current input pattern in all cells in the cell group, step S303 The cell structure analysis step and the through current input pattern extraction step in step S304 are repeated.
[0123]
In the through current input pattern selection step in step S313, the through current input pattern of the verification target cell extracted in step S301 is selected from the through current input pattern 311 of all cells.
[0124]
As described above, according to the present embodiment, the input pin of the verification target cell becomes the through current input pattern by creating the through current input pattern of all the cells of the cell group in advance from the transistor switching table. It is possible to check at high speed without performing circuit simulation.
[0125]
FIG. 15 shows a portion where the high impedance state occurs. G401 and G402 are tri-state inverters, and their outputs are connected in common. A net N401 indicates a net in a high impedance state.
[0126]
FIG. 16 shows the result of inserting the high impedance state avoidance circuit K401 at the location where the high impedance state occurs. If the output of the high impedance state avoidance circuit K401 is not in the high impedance state, the high impedance state can be avoided.
[0127]
FIG. 17 shows the result of inserting the bus hold circuit K402 at the location where the high impedance state occurs. Thereby, since the information before the high impedance state is held in the bus hold circuit K402, even if the signal output to the net N401 is in the high impedance state, in the portion after the bus hold circuit K402, High impedance state does not occur.
[0128]
【The invention's effect】
As explained above, Logic circuit verification method According to the present invention, a high impedance state occurrence location can be correctly verified in a situation where a plurality of output terminals of the tristate cell are commonly connected. As a result, it is possible to smoothly shift to a process for avoiding a high impedance state after the fact and a process for checking whether or not a through current actually occurs.
[0134]
Further, according to the present invention for the through current improvement method, a signal state before entering the high impedance state by inserting a circuit that avoids the high impedance state, for example, a bus hold circuit, at a location where the high impedance state occurs. Can be held, and a high impedance state can be avoided. Thereby, generation | occurrence | production of a through current can be suppressed.
[Brief description of the drawings]
FIG. 1 is a flowchart showing a high impedance state occurrence location verification process of a logic circuit verification method according to a first embodiment of the present invention.
FIG. 2 is a diagram showing a result of extracting a portion where a plurality of output terminals of a tristate cell are commonly connected in the logic circuit verification method according to the first embodiment of the present invention;
FIG. 3 is a diagram showing a result of extracting a circuit connected to a control signal of a tristate cell in the logic circuit verification method according to the first embodiment of the present invention;
FIG. 4 is a block diagram showing a through current verification method according to a second embodiment of the present invention.
FIG. 5 is a flowchart showing a through current verification method according to the second embodiment of the present invention;
FIG. 6 is a flowchart related to a process of adding a library including possibility information of a through current in the through current verification method according to the third embodiment of the present invention.
FIG. 7 is a circuit diagram showing a transistor configuration example inside a cell in a step of detecting the possibility of a through current by the through current verification method according to the third embodiment of the present invention;
FIG. 8 is a flowchart showing a through current verification method according to the third embodiment of the present invention;
FIG. 9 is a flowchart of a through current verification method according to a fourth embodiment of the present invention.
FIG. 10 is a diagram showing a transistor switching table of the through current verification method according to the fourth embodiment of the present invention.
FIG. 11 is a circuit diagram (a) of a two-input NAND and a circuit diagram (b) of a two-input NOR in the through current verification method according to the fourth embodiment of the present invention.
FIG. 12 is a diagram showing a result of determining a transistor structure by a through current verification method according to the fourth embodiment of the present invention;
FIG. 13A is a diagram showing a through current input pattern when n-type transistors have a vertically stacked structure in the through current verification method according to the fourth embodiment of the present invention, and FIG. (B) which shows a penetration current input pattern in the case of
FIG. 14 is a flowchart of a through current verification method according to a fifth embodiment of the present invention.
FIG. 15 is a diagram showing a portion in a high impedance state in the embodiment of the present invention.
FIG. 16 is a diagram in which a high-impedance state avoidance circuit is inserted at a high-impedance state occurrence location in the embodiment of the present invention.
FIG. 17 is a diagram in which a bus hold circuit is inserted at a high impedance state occurrence location in the embodiment of the present invention.
[Explanation of symbols]
41 Logic circuit diagram creation device
42 Netlist input section
43 Library input section
44 Verification Department
45 Error / warning output section
46 Verification rule storage area
301 Netlist
302 Cell internal netlist
303 Transistor switching table
304 Through-current input pattern
A Input terminal
B Input terminal
OUT output terminal
C101, C102 Control terminal
G101, G102 Tri-state inverter
G103 inverter
G104 NOR gate
G401, G402 Tri-state cell
N401 High impedance state net
K401 High impedance state avoidance circuit
K402 Bus hold circuit
S51 Tristate cell output terminal detection processing
S52 High impedance state output discrimination processing
S53 Connection check process
S54 Input terminal detection process
S55 Transistor pair list creation process
S56 Through current configuration detection processing
S57 Error output processing
S61 Transistor detection processing
S62 Transistor pair list creation processing
S63 Through current configuration detection processing
S64 Through current non-occurrence information addition processing
S65 Through current generation information addition processing
S81 Tristate cell output terminal detection processing
S82 High impedance state output discrimination processing
S83 Error output processing
S101 Tristate cell extraction process
S102 Circuit extraction process connected to control signal of tri-state cell
S103 Control signal investigation process
S104 Exclusive check process
S105 High impedance state check process
S301 Cell extraction process
S302 Transistor switching table creation step
S303 Cell structure analysis process
S304 Through-current input pattern extraction process
S305 Through current verification process
S311 Through current input pattern creation cell selection step
S312 judgment process
S313 Through current input pattern selection process

Claims (3)

Design for designing a semiconductor integrated circuit by a design apparatus having a net list input unit, a library in which circuit information is stored, a verification rule storage unit in which verification rules are stored, and a verification unit that makes a determination based on the verification rules In the method
Based on the net list input from the net list input unit, the verification unit, the step of extracting a location where a plurality of tristate cell output terminals are commonly connected;
The step of determining whether or not the input to the control terminal from the circuit connected to the control terminal of the extracted tristate cell is exclusive, the verification unit ;
A step of detecting when a high impedance state occurs in the common connection portion when the output unit of all the tri-state cells outputs a high impedance state among cases where the verification unit is not exclusive. A characteristic logic circuit verification method. The logic circuit verification method according to claim 1 , wherein the verification unit avoids a high impedance state by inserting a high impedance state avoidance circuit at a location detected as the high impedance state. Current improvement method. 3. The through current improvement method according to claim 2 , wherein the verification unit changes the circuit by inserting a bus hold circuit at a location detected as the high impedance state in the circuit change.

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