CN117829080A - Method, device, equipment and storage medium for processing interval error result - Google Patents

Abstract

The disclosure discloses a method, a device, equipment and a storage medium for processing a distance error result, wherein the method comprises the following steps: obtaining a plurality of interval error results, wherein each interval error result is obtained by checking a design rule of a layout, the layout comprises a plurality of layout layers, and each interval error result at least comprises a unit name corresponding to the layout layer where the interval error result is located; performing de-duplication treatment on the multiple interval error results according to the unit name to obtain multiple interval error results after de-duplication; and aiming at each space error result after the duplication removal, filtering the space error result after the duplication removal according to the correlation between two layout elements related to the space error result after the duplication removal to obtain a space error result after the filtration so as to present the space error result after the filtration. The method greatly saves the diagram checking time of the special-shaped display layout and improves the diagram checking efficiency of the special-shaped display layout.

Description

Method, device, equipment and storage medium for processing interval error result

Technical Field

The present disclosure relates generally to the field of electronic design automation technology. More particularly, the present disclosure relates to a pitch error result processing method, apparatus, device, and storage medium.

Background

Electronic design automation (Electronic Design Automation, EDA), which is industrial software used to assist in the design and production of very large scale integrated circuits, covers the entire process of circuit chip design, fabrication, packaging, and testing. It can be classified into integrated circuits (Integrated Circuit, IC), printed circuit boards (Printed Circuit Board, PCB), flat panel displays (Flat Panel Display, FPD) by product classification.

Along with the development of the design of the display panel of the mobile phone, the full-screen design of the display panel of the special-shaped mobile phone gradually becomes a design hot spot. For example, four corners of the display panel of the mobile phone are designed to be arc-shaped, and the placement area of the camera is curved by arc-shaped or oval hole digging. For another example, the watch display may be in a variety of forms, such as transitioning from a straight edge to a circular arc, etc. In the layout design process of the special-shaped display screen, as the number of line pitch error reporting results generated by design rule checking (Design Rule Check, DRC) is increased sharply, the number of line pitch error reporting results of DRC at present can reach millions, and the error reporting results are all presented to a layout engineer and manually confirmed and modified one by one, so that the traditional diagram checking mode needs to consume a great amount of time and has extremely low efficiency.

In view of this, it is desirable to provide a pitch error result processing scheme so as to improve the inspection efficiency of the special-shaped display layout.

Disclosure of Invention

To address at least one or more of the technical problems mentioned above, the present disclosure proposes, in various aspects, pitch error result processing methods, apparatuses, devices, and storage medium.

In a first aspect, the present disclosure provides a pitch error result processing method, the method comprising: obtaining a plurality of interval error results, wherein each interval error result is obtained by checking a design rule of a layout, the layout comprises a plurality of layout layers, and each interval error result at least comprises a unit name corresponding to the layout layer where the interval error result is located; performing de-duplication treatment on the multiple interval error results according to the unit name to obtain multiple interval error results after de-duplication; and aiming at each space error result after the duplication removal, filtering the space error result after the duplication removal according to the correlation between two layout elements related to the space error result after the duplication removal to obtain a space error result after the filtration so as to present the space error result after the filtration.

In a second aspect, the present disclosure provides a pitch error result processing apparatus comprising: the error result acquisition module is used for acquiring a plurality of interval error results, each interval error result is obtained by checking a design rule of a layout, the layout comprises a plurality of layout layers, and each interval error result at least comprises a unit name corresponding to the layout layer where the interval error result is located; the error result deduplication module is used for performing deduplication processing on the multiple interval error results according to the unit name to obtain multiple interval error results after deduplication; the error result filtering module is used for filtering each repeated interval error result according to the correlation between the two layout elements related to the repeated interval error result, so as to obtain a filtered interval error result, and the filtered interval error result is displayed.

In a third aspect, the present disclosure provides an electronic device comprising a memory, a processor and a computer program stored on the memory and executable on the processor, the processor implementing the method as described in the first aspect when executing the computer program.

In a fourth aspect, the present disclosure provides a computer readable storage medium having stored thereon a computer program which, when executed by a processor, implements a method as described in the first aspect.

Through the method, the device, the equipment and the storage medium for processing the interval error result, provided by the above, the embodiment of the disclosure obtains a plurality of interval error results; performing de-duplication treatment on the multiple interval error results according to the unit name to obtain multiple interval error results after de-duplication; and then, aiming at each space error result after the duplication removal, filtering the space error result after the duplication removal according to the correlation between two layout elements related to the space error result after the duplication removal to obtain a filtered space error result so as to present the filtered space error result, effectively presenting the space error result to a layout engineer, greatly saving the diagram checking time of the special-shaped display layout and effectively improving the diagram checking efficiency of the special-shaped display layout. Further, in some embodiments, according to the network attribute identifier, the distance error result is filtered, so that false errors in the special-shaped display layout can be effectively filtered, and the accuracy of graph detection is improved. Furthermore, in some embodiments, according to the network attribute identifier and the pitch value, the pitch error result is filtered, and the remaining pitch error result with the false errors removed can be further screened to determine the true pitch error result which is only required to be modified by the layout engineer, so that the efficiency of checking the graph is greatly improved.

Drawings

The above, as well as additional purposes, features, and advantages of exemplary embodiments of the present disclosure will become readily apparent from the following detailed description when read in conjunction with the accompanying drawings. Several embodiments of the present disclosure are illustrated by way of example, and not by way of limitation, in the figures of the accompanying drawings and in which like reference numerals refer to similar or corresponding parts and in which:

FIG. 1 illustrates one exemplary application scenario of an embodiment of the present disclosure;

FIG. 2 shows a layout schematic of a pixel circuit cell with pitch error results;

FIG. 3 illustrates an exemplary flow chart of a pitch error result processing method of some embodiments of the present disclosure;

FIG. 4 illustrates an exemplary flowchart of a pitch error result processing method of other embodiments of the present disclosure;

FIG. 5 illustrates an exemplary block diagram of a pitch error result processing apparatus according to an embodiment of the present disclosure;

FIG. 6 illustrates an exemplary block diagram of a pitch error result processing apparatus according to further embodiments of the present disclosure;

fig. 7 illustrates a schematic diagram of a user terminal or server of some embodiments of the present disclosure.

Detailed Description

The following description of the embodiments of the present disclosure will be made clearly and fully with reference to the accompanying drawings, in which it is evident that the embodiments described are some, but not all embodiments of the disclosure. Based on the embodiments in this disclosure, all other embodiments that may be made by those skilled in the art without the inventive effort are within the scope of the present disclosure.

It should be understood that the terms "comprises" and "comprising," when used in this specification and the claims, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.

It is also to be understood that the terminology used in the description of the present disclosure is for the purpose of describing particular embodiments only, and is not intended to be limiting of the disclosure. As used in the specification and claims of this disclosure, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It should be further understood that the term "and/or" as used in the present disclosure and claims refers to any and all possible combinations of one or more of the associated listed items, and includes such combinations.

As used in this specification and the claims, the term "if" may be interpreted as "when..once" or "in response to a determination" or "in response to detection" depending on the context. Similarly, the phrase "if a determination" or "if a [ described condition or event ] is detected" may be interpreted in the context of meaning "upon determination" or "in response to determination" or "upon detection of a [ described condition or event ]" or "in response to detection of a [ described condition or event ]".

Specific embodiments of the present disclosure are described in detail below with reference to the accompanying drawings.

Exemplary application scenarios

FIG. 1 illustrates one exemplary scenario in which embodiments of the present disclosure may be applied.

The method for processing the distance error result provided by the embodiment of the disclosure can be applied to an application environment as shown in fig. 1. Wherein the user terminal 102 communicates with the server 104 via a network. The data storage system may store data that the server 104 needs to process. The data storage system may be integrated on the server 104 or may be located on a cloud server or other server.

A software product for implementing a flat panel display design is installed on the user terminal 102. The software product used to implement the flat panel display design may be an EDA product. In an operation interface of the software product, an externally entered inspection request may be received. The inspection request is for requesting a design rule inspection of the physical layout of the completed layout wiring. The check request may be externally entered click operation information received in an operation interface presented by the software product, selection operation information, or voice control operation information indicating an operation on an associated icon within the operation interface presented by the software product. The physical layout at least comprises a multi-level layout design unit (such as a cell). A plurality of layout elements (such as polygon, line, examples) are arranged in the layout design unit of the physical layout, and each layout element is used for realizing a physical function, for example, a signal line for transmitting signals. After the user terminal 102 receives the inspection request, the processor in the terminal 102 may process the inspection request to obtain an error reporting result corresponding to the inspection request, or transmit the inspection request to the server 104 for processing, to obtain an error reporting result corresponding to the inspection request.

The user terminal 102 may be, but is not limited to, various desktop computers, notebook computers, intelligent terminals, etc.

The server 104 may be implemented as a stand-alone server or as a server cluster of multiple servers. The server may be an independent physical server, a server cluster or a distributed system formed by a plurality of physical servers, or a cloud server for providing cloud computing service, where the cloud server may be a public cloud server, a hybrid cloud server or a private cloud server. The terminal and the server may be directly or indirectly connected through wired or wireless communication, and the disclosure is not limited herein.

Fig. 2 shows a layout diagram of a pixel circuit unit in which a pitch error result exists.

At present, the special-shaped design area of the display panel is more. The special-shaped area can be at least an area with the periphery of the mobile phone display screen presenting an arc shape, the placement area of the camera presents an arc-shaped area, or an area formed by the periphery of the oval hole, and the watch display screen is more various in form, such as transition from an arc to a straight edge. In the layout design process of the special-shaped display screens, the design of the pixel circuit units can adaptively change the positions of layout elements along with the bending radian of the special-shaped areas so as to better match the outlines of the special-shaped areas. The special-shaped display area of the special-shaped display panel is slightly different from the pixel circuit arrangement of the conventional display area, even the same, and millions of error results can be generated by adopting conventional DRC inspection according to the design result of conventional layout and wiring due to the limited position space of the special-shaped display area. The false results with huge numbers are manually filtered and modified one by one, so that the graph checking efficiency in the prior art is extremely low. The research and development workers of the present disclosure analyze the above-mentioned numerous inspection results, and find that in the layout design of the special-shaped display panel, since layout elements and wiring of the special-shaped display area need to be adaptively matched with radians of the special-shaped display area, the layout and wiring positions of part of wiring or layout elements are adjusted, so that DRC error results generated in the special-shaped display area are abnormally large, and account for more than 90% of all DRC error results.

It is assumed that the layout of the pixel circuit units is laid out in accordance with the hierarchy illustrated in fig. 2. The pixel circuit unit comprises a Top layer unit (Top), a Middle layer unit (Middle), a bottom layer unit (group), and the Top layer unit is named as Top under the assumption that the unit name of the bottom layer unit is group, the unit name of the Middle layer unit is Middle, and the unit name of the Top layer unit is group. The top level cell may invoke one or more middle level cells, each of which may in turn invoke one or more bottom level cells. As shown in FIG. 2, the layout element E and the layout element F, which were originally in the bottom level cells, are checked from the top level cells according to DRC, and are recognized as error results by the background program because of the violation of the design rules. The erroneous result is still present in other layer units calling the underlying unit, again due to the calling relationship that exists between the units. In addition, two layout elements are possibly overlapped in the same layer of unit, and the non-overlapped area of the two layout elements forms a space smaller than 90 degrees, so that in DRC inspection, the included angle of the two adjacent layout elements is smaller than 90 degrees, errors are directly reported, and the number of the errors in the layout design process of the special-shaped display panel is extremely large.

In view of this, the embodiment of the disclosure provides a processing scheme of a pitch error result, which filters the pitch error result after de-duplication according to the correlation between two layout elements related to the pitch error result after de-duplication, so as to obtain a filtered pitch error result, which can effectively reduce the data size of the error result, present the true error expected to be acquired by a layout engineer, and effectively improve the efficiency of checking the complex layout.

FIG. 3 illustrates an exemplary flow chart of a pitch error result processing method of some embodiments of the present disclosure.

In step 310, a plurality of pitch error results are obtained.

Each pitch error result is obtained by checking a design rule of a layout, the layout comprises a plurality of layout layers, and each pitch error result at least comprises a unit name corresponding to the layout layer where the pitch error result is located.

And 320, performing de-duplication processing on the multiple pitch error results according to the unit names to obtain multiple de-duplicated pitch error results.

Step 330, for each de-duplicated pitch error result, filtering the de-duplicated pitch error result according to the correlation between two layout elements related to the de-duplicated pitch error result to obtain a filtered pitch error result, so as to present the filtered pitch error result.

As shown, in step 310, a plurality of pitch error results are obtained. After the layout is completed, the layout engineer triggers DRC inspection of the layout by operating areas or sub-interfaces displayed in the operating interface for performing design rule detection. After the processor performs DRC checking according to a preset checking rule, a plurality of pitch error results are obtained.

For example, as shown in FIG. 2, the layout includes a plurality of layout levels, top level, middle level, and group level in this order. The Top layer may invoke one or more Middle layers, each of which may invoke one or more group layers. Each layout level represents a layout design cell (cell) in the layout. A plurality of layout elements may be included in each cell, including but not limited to a variety of graphics, such as polygons, line segments, circles, and the like. The cell names corresponding to the layout levels can be set according to requirements, and the group shown in fig. 2 is the cell name of the bottommost cell where the error reporting graph is located.

DRC is performed starting from the Top layer, resulting in a pitch error result {1,2,3,4,5,6}. The pitch error result 1 indicates that the layout elements E and F in the group layer are considered to have pitch errors. The pitch error result 2 indicates that the pitch error exists in the Middle layer layout element C and the Middle layer layout element D, and the pitch error result 3 is a reference example for calling the layout element E and the layout element F, and is also determined to be a pitch error result because of the calling relation between the layout layers. Similarly, there is a pitch error result 4 on the Top layer, which indicates that there is a pitch error between the layout elements a and B, and a pitch error result 5 and a pitch error result 6 respectively indicate pitch errors identified due to the calling relationship between the layout layers. For example, the Top layer calls the reference examples of the layout element C and the layout element D, and the reference examples of the layout element E and the layout element F respectively, and then the Top layer checks the interval error result 5 existing in the reference examples of the layout element C and the layout element D, and the interval error result 6 existing in the reference examples of the layout element E and the layout element F. The layout elements A, B, C, D, E, F all belong to the same process layer structure, for example, a first metal layer (M1 layer) or a second metal layer (M2 layer).

In one implementation, the spacing error result 1 data structure may be represented as { (E, F) }, group }, or may be represented using other forms of data structures. Those skilled in the art will appreciate that the disclosed embodiments are not limited in this respect.

Next, in step 320, the multiple pitch error results are deduplicated according to the unit name.

In one implementation, step 320 may be performed after obtaining a plurality of pitch error results, and may include at least: acquiring a unit name contained in each of a plurality of interval error results; classifying the plurality of interval error results according to the unit names to obtain a plurality of classification results, wherein each classification result comprises a plurality of interval error results with the same unit name; and according to the calling relation among the layout layers, carrying out duplication elimination on each classification result to obtain a duplication-eliminated interval error result corresponding to each classification result.

The spacing error result is displayed in a graphic form on the layout level corresponding to the layout, and the spacing error result can be highlighted by highlighting. The relevant data of the pitch error result may be stored in a corresponding storage system or storage device. After the DRC is executed, the processor calls related data of the interval error result, extracts the data and acquires a unit name corresponding to each interval error result. And then the unit names classify the distance processing results. The calling relation between the layout layers is a hierarchical relation corresponding to the technological principle of the circuit. For example, the pixel circuit unit is realized through a multi-layer process, and hierarchical connection relation exists among different process layers, which is related to a specific circuit realization process. As shown in FIG. 2, after DRC is performed, a space error result {1,2,3,4,5,6} is obtained, wherein the unit name of space error result 1 is group, the unit name of space error result 3 is group, the unit name of space error result 6 is group, and the space error result corresponding to group has {1,3,6}. Because the Top layer calls the reference instance on the Middle layer, the interval error results 5 and 6 are also reported in the error statistics result of the Top layer. The multiple classification results may be group class {1,3,6}, middle class {2,5}, top class {4}.

In one implementation, deduplicating each classification result according to a calling relationship between layout layers, including: determining a current classification result among the plurality of classification results; in the current classification result, determining the layout level of each interval error result; and determining a spacing error result at the bottommost layer of the layout hierarchy in the current classification result according to the calling relation between the layout hierarchy and other layout hierarchies, and taking the spacing error result as a duplication-removed spacing error result corresponding to the current classification result.

Assuming that the current classification result is group {1,3,6}, the layout layers are in Top-to-bottom order, the Top layer, the Middle layer, the group layer and the spacing error result 6 are in turn according to the calling relationship between the layout layers, and the relationship between the spacing error result 6 and the spacing error result 1 can be traced back through a correlation algorithm. The spacing error result 1 is taken as the deduplication result of the group class {1,3,6 }. Namely, the pitch error result of the bottommost layer of the layout hierarchy is used as a duplication removal result. Similarly, the pitch error result 2 is a deduplication result of the Middle class.

According to the method and the device, the repeated processing is carried out on a large number of interval error results, so that the data volume of filtering processing is effectively reduced, and the processing efficiency of the interval error results is improved.

In one implementation, step 320 may be performed after the filtering process is performed for each pitch error result, and the method may be performed in the following order to obtain a plurality of pitch error results; aiming at each spacing error result, filtering the spacing error result according to the correlation between two layout elements related to the spacing error result to obtain a filtered spacing error result; and performing de-duplication processing on the pitch error result after the filtering processing according to the unit name to obtain a plurality of pitch error results after de-duplication so as to present the pitch error result after de-duplication. The unit name obtaining method, the filtering processing method and the deduplication processing method are all as described above, and are not described here again.

In step 330, for each de-duplicated pitch error result, filtering the de-duplicated pitch error result according to the correlation between the two layout elements related to the de-duplicated pitch error result to obtain a filtered pitch error result, so as to present the filtered pitch error result.

In one implementation, the filtering process is performed on each given de-duplicated pitch error result, i.e., whether the de-duplicated pitch error result is a true pitch error or a false pitch error due to a constraint that the adjacent line angle is less than 90 °, i.e., a false error. The embodiment of the disclosure greatly saves the diagram checking time of the layout by distinguishing the authenticity of the pitch error results and converging the number of the pitch error results from millions to hundreds or even tens of levels.

In one implementation, the authentication of the authenticity of the pitch error result may include at least the steps of: determining a current pitch error result from the multiple de-duplicated pitch error results; acquiring network attribute identifiers corresponding to two layout elements one by one, which are related to the current interval error result; filtering the current interval error result according to the network attribute identifier; and returning to the step of determining the current pitch error result from the multiple de-duplicated pitch error results, and continuing the subsequent steps until the current pitch error result is the last of the multiple de-duplicated pitch error results.

In one implementation, the network attribute identifiers corresponding to two layout elements one by one to the current pitch error result refer to identifiers for electrical characteristics of the layout elements. For example, in a layout, signal lines with the same network identification are connected together by default. Network attribute identification, which may also be referred to as a network tag, is used to identify the connection relationship between two wires. The network attribute identifiers of the layout element A and the layout element B can be sign1 through searching the data results corresponding to the layout elements, for example, the layout element A and the layout element B are connected together. But according to the rule that the adjacent line is smaller than 90 deg., the pitch error result 4 is also counted as an error result. In an actual layout, this is not a true pitch error. Thus, pitch error result 4 is identified as a false error that does not require modification at the time of presentation to the layout engineer.

According to the embodiment of the disclosure, the false errors in the re-processed pitch error results are identified and filtered, so that only the residual real pitch error results are presented, the number of the pitch error results subjected to filtering processing is reduced from millions to hundreds, the graph checking time is greatly saved, and the graph checking efficiency of the layout is effectively improved.

FIG. 4 illustrates an exemplary flow chart of a pitch error result processing method of other embodiments of the present disclosure.

In step 410, a plurality of pitch error results are obtained. Each pitch error result is obtained by checking a design rule of a layout, the layout comprises a plurality of layout layers, and each pitch error result at least comprises a unit name corresponding to the layout layer where the pitch error result is located.

And step 420, performing de-duplication processing on the multiple pitch error results according to the unit names to obtain multiple de-duplicated pitch error results.

Step 430, for each de-duplicated pitch error result, filtering the de-duplicated pitch error result according to the correlation between the two layout elements related to the de-duplicated pitch error result to obtain a filtered pitch error result, so as to present the filtered pitch error result.

The step 410 and the step 420 are the same as the step 310 and the step 320, and are not repeated here.

In step 430, for each de-duplicated pitch error result, filtering the de-duplicated pitch error result according to the correlation between the two layout elements related to the de-duplicated pitch error result to obtain a filtered pitch error result, so as to present the filtered pitch error result.

In an implementation, according to the correlation between two layouts related to the pitch error result, the pitch error result is filtered, and after the filtering adjacent lines are less than 90 degrees and have false errors, the pitch error result can be further filtered through line pitch rules. It may include at least:

step 4301, determining a current pitch error result from a plurality of de-duplicated pitch error results;

step 4302, obtaining network attribute identifiers corresponding to two layout elements one by one and related to the current pitch error result and a pitch value between the two layout elements related to the current pitch error result;

step 4303, filtering the current gap error result according to the network attribute identifier and the gap value; and returning to the step of determining the current pitch error result from the multiple de-duplicated pitch error results, and continuing the subsequent steps until the current pitch error result is the last of the multiple de-duplicated pitch error results.

In one implementation, step 4303 may reclassify the range error result based on the network attribute identification to obtain a same class of network attribute identification and a different class of network attribute identification. And then adopting different processing strategies for the network attribute identification same class and the network attribute identification different class. Step 4303 may include: and filtering the current interval error result when the network attribute identifiers are identical.

And when the network attribute identifiers are determined to be different, further identifying a distance error result according to the distance value. Step 4303 may further include:

and when the network attribute identifiers are different and the distance value is larger than or equal to the threshold value, filtering the current distance error result. And when the network attribute identifiers are different and the distance value is smaller than a preset threshold value, providing a current distance error result to the storage unit so as to present the current distance error result.

For example, the gap layer reports the gap error results {1,2,3,4,5,6}, and network attribute identifiers of each gap error result are respectively obtained. Assuming that network attribute identifiers of the layout element A and the layout element B are sign1, the layout element A and the layout element B are signal lines connected together, and because the two layout elements are adopted, the two layout elements are recognized as a distance error result and are presented in a DRC because the included angle between the two layout elements is smaller than 90 degrees, and the error is gathered in a large quantity in a special-shaped display area in the special-shaped display layout, but the error is a false error which does not need to be processed. The number of gap error results is converged from millions to hundreds by identification of network attribute identities. For example, the deduplicated range error result {1,2,4} is filtered by the network attribute identification, and the remaining range error result {1,2}.

And then, screening the rest space error results according to a preset space threshold, as shown in fig. 2, assuming that the space value between the layout element E and the layout element F related to the space error result 1 is d1, and further judging that the space value between the layout element E and the layout element F is less than 3 μm if the space threshold is 3 μm, considering that the space error result 1 needs to be presented to a layout engineer, and modifying errors of corresponding positions in the layout. ,

and if the distance value between the layout element C and the layout element D related to the distance error result 2 is D2 and the distance value between the layout element C and the layout element D is judged to be more than 3 mu m, the distance error result 2 is considered not to be presented to a layout engineer.

According to the processing scheme of the pitch error result provided by the embodiment of the disclosure, the false errors belonging to the same network are eliminated according to whether two layout elements related to the pitch error result after the duplication removal belong to the same network. And then further screening the distance value between the two layout elements to determine a real distance error result which does not meet the distance threshold value of the adjacent lines in the special area, and accurately identifying the real distance error result, thereby improving the accuracy of the graph checking result. The technical scheme only presents the true errors expected to be acquired by the layout engineer, effectively reduces the data volume of the error result, simultaneously effectively improves the accuracy of the error result, and improves the graph checking efficiency of the complex layout.

In summary, according to the processing scheme of the pitch error result provided by the embodiment of the disclosure, according to the correlation between two layout elements related to the pitch error result after duplication removal, the pitch error result after duplication removal is filtered to obtain a pitch error result after filtration, so that the data volume of the error result can be effectively reduced, the true error expected to be acquired by a layout engineer is presented, and the efficiency of checking the complex layout is effectively improved.

As shown in fig. 5, fig. 5 illustrates an exemplary block diagram of a pitch error result processing apparatus according to an embodiment of the present disclosure. The device comprises:

the error result obtaining module 510 is configured to obtain a plurality of pitch error results, where each pitch error result is obtained by performing a design rule check on a layout, the layout includes a plurality of layout levels, and each pitch error result includes at least a unit name corresponding to the layout level where the pitch error result is located;

the error result deduplication module 520 is configured to deduplicate the multiple pitch error results according to the unit name, so as to obtain multiple deduplicated pitch error results;

the error result filtering module 530 is configured to filter, for each de-duplicated pitch error result, the de-duplicated pitch error result according to a correlation between two layout elements related to the de-duplicated pitch error result, so as to obtain a filtered pitch error result, so as to present the filtered pitch error result.

In one implementation, the error result filtering module 530 further includes:

the determining submodule is used for determining a current pitch error result from a plurality of pitch error results after de-duplication;

the acquisition sub-module is used for acquiring network attribute identifiers corresponding to two layout elements one by one, which are related to the current interval error result;

the filtering sub-module is used for filtering the current interval error result according to the network attribute identification; and returning to the determination sub-block, and continuing the follow-up steps until the current spacing error result is the last of the plurality of spacing error results after the duplication removal.

According to the embodiment of the disclosure, the false errors in the re-processed pitch error results are identified and filtered, so that only the residual real pitch error results are presented, the number of the pitch error results subjected to filtering processing is reduced from millions to hundreds, the graph checking time is greatly saved, and the graph checking efficiency of the layout is effectively improved.

As shown in fig. 6, fig. 6 illustrates an exemplary block diagram of a pitch error result processing apparatus of other embodiments of the present disclosure. The device comprises:

the error result obtaining module 610 is configured to obtain a plurality of pitch error results, where each pitch error result is obtained by performing a design rule check on a layout, and the layout includes a plurality of layout levels, and each pitch error result includes at least a unit name corresponding to the layout level where the pitch error result is located;

The error result deduplication module 620 is configured to deduplicate the multiple pitch error results according to the unit name, so as to obtain multiple deduplicated pitch error results;

the error result filtering module 630 is configured to filter, for each de-duplicated pitch error result, the de-duplicated pitch error result according to a correlation between two layout elements related to the de-duplicated pitch error result, so as to obtain a filtered pitch error result, so as to present the filtered pitch error result.

In one implementation, the error result filtering module 630 further includes:

a determining submodule 6301, configured to determine a current pitch error result from a plurality of pitch error results after de-duplication;

an obtaining submodule 6302, which is used for obtaining network attribute identifiers corresponding to two layout elements related to the current spacing error result one by one and a spacing value between the two layout elements related to the current spacing error result;

a filtering sub-module 6303, configured to filter the current spacing error result according to the network attribute identifier and the spacing value; and returning to the determining sub-module, and continuing the follow-up steps until the current spacing error result is the last of the plurality of spacing error results after the duplication removal.

In an implementation, the filtering sub-module is further configured to filter the current distance error result when the network attribute identifiers are determined to be the same.

In an implementation, the filtering sub-module is further configured to filter a current distance error result when it is determined that the network attribute identifiers are different and the distance value is greater than or equal to a threshold value.

In an implementation, the filtering sub-module is further configured to provide a current pitch error result to the storage unit when it is determined that the network attribute identifiers are different and the pitch value is less than the preset threshold, so as to present the current pitch error result.

In one implementation, the error result deduplication module 620 is configured to obtain a unit name included in each of the plurality of pitch error results; classifying the plurality of interval error results according to the unit names to obtain a plurality of classification results, wherein each classification result comprises a plurality of interval error results with the same unit name; and according to the calling relation among the layout layers, carrying out duplication elimination on each classification result to obtain a duplication-eliminated interval error result corresponding to each classification result.

In one implementation, the error result deduplication module 620 is further configured to: determining a current classification result among the plurality of classification results; in the current classification result, determining the layout level of each interval error result; according to the calling relation between the layout level and other layout levels, determining a spacing error result at the bottommost layer of the layout level in the current classification result, and taking the spacing error result as a duplication-removed spacing error result corresponding to the current classification result.

According to the processing scheme of the pitch error result provided by the embodiment of the disclosure, the false errors belonging to the same network are eliminated according to whether two layout elements related to the pitch error result after the duplication removal belong to the same network. And then further screening the distance value between the two layout elements to determine a real distance error result which does not meet the distance threshold value of the adjacent lines in the special area, and accurately identifying the real distance error result, thereby improving the accuracy of the graph checking result. The technical scheme only presents the true errors expected to be acquired by the layout engineer, effectively reduces the data volume of the error result, simultaneously effectively improves the accuracy of the error result, and improves the graph checking efficiency of the complex layout.

It should be understood that the units or modules described in the apparatus correspond to the individual steps in the method described above. Thus, the operational instructions and features described above for the method are equally applicable to the apparatus and the units contained therein, and are not described in detail herein. The device can be pre-implemented in a browser of the electronic equipment or other security applications, or can be loaded into the browser of the electronic equipment or the security applications thereof by means of downloading and the like. Corresponding units in the apparatus may cooperate with units in the electronic device to implement aspects of embodiments of the present disclosure.

The division of the modules or units mentioned in the above detailed description is not mandatory. Indeed, the features and functions of two or more modules or units described above may be embodied in one module or unit in accordance with embodiments of the present disclosure. Conversely, the features and functions of one module or unit described above may be further divided into a plurality of modules or units to be embodied.

Referring now to fig. 7, fig. 7 illustrates a schematic diagram of a user terminal or server of some embodiments of the present disclosure.

As shown in fig. 7, the computer system includes a Central Processing Unit (CPU) 701, which can perform various appropriate actions and processes according to a program stored in a Read Only Memory (ROM) 702 or a program loaded from a storage section 708 into a Random Access Memory (RAM) 703. In the RAM703, various programs and data required for the operation instructions of the system 700 are also stored. The CPU 701, ROM 702, and RAM703 are connected to each other through a bus 704. An input/output (I/O) interface 705 is also connected to bus 704.

The following components are connected to the I/O interface 705: an input section 706 including a keyboard, a mouse, and the like; an output portion 707 including a Cathode Ray Tube (CRT), a Liquid Crystal Display (LCD), and the like, a speaker, and the like; a storage section 708 including a hard disk or the like; and a communication section 709 including a network interface card such as a LAN card, a modem, or the like. The communication section 709 performs communication processing via a network such as the internet. The drive 710 is also connected to the I/O interface 705 as needed. A removable medium 711 such as a magnetic disk, an optical disk, a magneto-optical disk, a semiconductor memory, or the like is mounted on the drive 710 as necessary, so that a computer program read therefrom is mounted into the storage section 708 as necessary.

In particular, according to embodiments of the present disclosure, the process described above with reference to flowchart fig. 3 or fig. 4 may be implemented as a computer software program. For example, embodiments of the present disclosure include a computer program product comprising a computer program embodied on a machine-readable medium, the computer program comprising program code for performing the method shown in the flow diagrams. In such an embodiment, the computer program may be downloaded and installed from a network via the communication portion 709, and/or installed from the removable medium 711. The above-described functions defined in the system of the present disclosure are performed when the computer program is executed by a Central Processing Unit (CPU) 701.

It should be noted that the computer readable medium shown in the present disclosure may be a computer readable signal medium or a computer readable storage medium or any combination of the two. The computer readable storage medium can be, for example, but not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or a combination of any of the foregoing. More specific examples of the computer-readable storage medium may include, but are not limited to: an electrical connection having one or more wires, a portable computer diskette, a hard disk, a Random Access Memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing. In the context of this disclosure, a computer-readable storage medium may be any tangible medium that can contain, or store a program for use by or in connection with an instruction execution system, apparatus, or device. In the present disclosure, however, the computer-readable signal medium may include a data signal propagated in baseband or as part of a carrier wave, with the computer-readable program code embodied therein. Such a propagated data signal may take any of a variety of forms, including, but not limited to, electro-magnetic, optical, or any suitable combination of the foregoing. A computer readable signal medium may also be any computer readable medium that is not a computer readable storage medium and that can communicate, propagate, or transport a program for use by or in connection with an instruction execution system, apparatus, or device. Program code embodied on a computer readable medium may be transmitted using any appropriate medium, including but not limited to: wireless, wire, fiber optic cable, RF, etc., or any suitable combination of the foregoing.

The flowcharts and block diagrams in the figures illustrate the architecture, functionality, and operation instructions of possible implementations of systems, methods and computer program products according to various embodiments provided by the present disclosure. In this regard, each block in the flowchart or block diagrams may represent a module, segment, or portion of code, which comprises one or more executable instructions for implementing the specified logical function(s). It should also be noted that, in some alternative implementations, the functions noted in the block may occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved. It will also be noted that each block of the block diagrams and/or flowchart illustration, and combinations of blocks in the block diagrams and/or flowchart illustration, can be implemented by special purpose hardware-based systems which perform the specified functions or acts, or combinations of special purpose hardware and computer instructions.

The units or modules referred to in the embodiments of the disclosure may be implemented in software or in hardware. The described units or modules may also be provided in a processor, for example, as: a processor includes an error result acquisition module, an error result deduplication module, and an error result filtering module. The names of these units or modules do not in some cases limit the units or modules themselves, and may be described as "a module for acquiring a plurality of pitch error results", for example, an error result acquisition module ".

As another aspect, the present disclosure also provides a computer-readable storage medium that may be included in the electronic device described in the above embodiments; or may be present alone without being incorporated into the electronic device. The computer-readable storage medium stores one or more programs that when executed by one or more processors perform the methods of processing pitch error results described in the present disclosure.

While various embodiments of the present disclosure have been shown and described herein, it will be obvious to those skilled in the art that such embodiments are provided by way of example only. Numerous modifications, changes, and substitutions will occur to those skilled in the art without departing from the spirit and scope of the present disclosure. It should be understood that various alternatives to the embodiments of the disclosure described herein may be employed in practicing the disclosure. The appended claims are intended to define the scope of the disclosure and are therefore to cover all equivalents or alternatives falling within the scope of these claims.

Claims (11)

1. A method for processing pitch error results, the method comprising:

Obtaining a plurality of interval error results, wherein each interval error result is obtained by checking a design rule of a layout, the layout comprises a plurality of layout layers, and each interval error result at least comprises a unit name corresponding to the layout layer where the interval error result is located;

performing de-duplication processing on the multiple interval error results according to the unit names to obtain multiple interval error results after de-duplication;

and aiming at each space error result after the duplication removal, filtering the space error result after the duplication removal according to the correlation between two layout elements related to the space error result after the duplication removal to obtain a space error result after the filtration so as to present the space error result after the filtration.

2. The method according to claim 1, wherein for each of the de-duplicated pitch error results, the filtering the de-duplicated pitch error result according to a correlation between two layout elements related to the de-duplicated pitch error result includes:

determining a current pitch error result from the multiple de-duplicated pitch error results;

Acquiring network attribute identifiers corresponding to two layout elements one by one, which are related to the current interval error result;

filtering the current interval error result according to the network attribute identifier;

and returning the step of determining the current pitch error result from the multiple de-duplicated pitch error results, and continuing the subsequent step until the current pitch error result is the last one of the multiple de-duplicated pitch error results.

3. The method according to claim 1, wherein for each of the de-duplicated pitch error results, the filtering the de-duplicated pitch error result according to a correlation between two layout elements related to the de-duplicated pitch error result includes:

determining a current pitch error result from the multiple de-duplicated pitch error results;

acquiring network attribute identifiers corresponding to two layout elements one by one and related to the current spacing error result and a spacing value between the two layout elements related to the current spacing error result;

filtering the current interval error result according to the network attribute identifier and the interval value;

And returning the step of determining the current pitch error result from the multiple de-duplicated pitch error results, and continuing the subsequent step until the current pitch error result is the last one of the multiple de-duplicated pitch error results.

4. A method according to claim 3, wherein said filtering the current pitch error result according to the network attribute identification and the pitch value comprises:

and filtering the current interval error result when the network attribute identifiers are determined to be the same.

5. A method according to claim 3, wherein said filtering the current pitch error result according to the network attribute identification and the pitch value comprises:

and filtering the current interval error result when the network attribute identifiers are different and the interval value is larger than or equal to the threshold value.

6. A method according to claim 3, wherein said filtering the current pitch error result according to the network attribute identification and the pitch value comprises:

and when the network attribute identifiers are different and the distance value is smaller than a preset threshold value, providing the current distance error result to a storage unit so as to present the current distance error result.

7. The method of claim 1, wherein performing the deduplication on the plurality of pitch error results according to the unit name to obtain a plurality of deduplicated pitch error results comprises:

obtaining a unit name contained in each of the plurality of pitch error results;

classifying a plurality of interval error results according to the unit names to obtain a plurality of classification results, wherein each classification result comprises a plurality of interval error results with the same unit name;

and according to the calling relation among the layout layers, performing deduplication on each classification result to obtain a deduplicated interval error result corresponding to each classification result.

8. The method according to claim 7, wherein said deduplicating each of the classification results according to the calling relationship between the layout levels, comprises:

determining a current classification result among the plurality of classification results;

determining the layout level of each interval error result in the current classification result;

and determining a spacing error result at the bottommost layer of the layout layers in the current classification result according to the calling relation between the layout layers and other layout layers, and taking the spacing error result as a duplication-removed spacing error result corresponding to the current classification result.

9. A pitch error result processing apparatus, the apparatus comprising:

the error result acquisition module is used for acquiring a plurality of interval error results, each interval error result is obtained by checking a design rule of a layout, the layout comprises a plurality of layout layers, and each interval error result at least comprises a unit name corresponding to the layout layer in which the interval error result is positioned;

the error result de-duplication module is used for performing de-duplication processing on the multiple interval error results according to the unit names to obtain multiple interval error results after de-duplication;

and the error result filtering module is used for filtering the repeated interval error result according to the correlation between the two layout elements related to the repeated interval error result aiming at each repeated interval error result to obtain a filtered interval error result so as to present the filtered interval error result.

10. An electronic device comprising a memory, a processor and a computer program stored on the memory and executable on the processor, wherein the processor implements the method of any of claims 1-8 when the program is executed by the processor.

11. A computer readable storage medium having stored thereon a computer program which, when executed by a processor, implements the method of any of claims 1-8.