CN117829087A - Layout wiring method, device, equipment and storage medium - Google Patents

Abstract

The disclosure discloses a layout wiring method, a layout wiring device, layout wiring equipment and a storage medium, wherein the layout wiring method comprises the following steps: the method comprises the steps of obtaining a first auxiliary layer and a second auxiliary layer from an initial physical layout of a laid-out target circuit, wherein the target circuit comprises at least one subunit, each subunit comprises at least one device, and the device at least comprises a first hierarchical structure and a second hierarchical structure which are stacked in a direction perpendicular to a substrate of the target circuit. And generating a target auxiliary layer according to the first auxiliary layer and the second auxiliary layer. In the target auxiliary layer, generating a wiring result according to the wiring parameters acquired in advance, wherein the wiring result at least comprises the following steps: a connection line for electrically connecting devices included in the current sub-unit within the current sub-unit, and a connection line for electrically connecting the current sub-unit with a target position outside the current sub-unit. The layout wiring efficiency is effectively improved through the wiring area determined by the auxiliary layers.

Description

Layout wiring method, device, equipment and storage medium

Technical Field

The present disclosure relates generally to the field of electronic design automation technology. More particularly, the present disclosure relates to a layout wiring method, apparatus, device, and storage medium.

Background

Electronic design automation (Electronic Design Automation, EDA), which is industrial software used to assist in the design and production of very large scale integrated circuits, covers the entire process of circuit chip design, fabrication, packaging, and testing. It can be classified into integrated circuits (Integrated Circuit, IC), printed circuit boards (Printed Circuit Board, PCB), flat panel displays (Flat Panel Display, FPD) by product classification.

The flat panel display class EDA mainly comprises a flat panel display design EDA, which faces panel manufacturers. The flat panel display design flow comprises circuit schematic diagram design, layout design, circuit simulation, circuit layout parasitic parameter extraction, circuit design verification and the like.

When drawing a layout of a display panel by using a flat panel display design EDA, firstly, a layout engineer is required to manually place each device, and the layout of the layout is completed. Then, they need to manually draw wiring between each device in consideration of the problems of wiring layers, wiring directions, wiring pitches, and the like, and finally complete wiring. For example, in drawing an array substrate gate drive (Gate Driver on Array, GOA) circuit layout of a display panel, a layout engineer needs to consider wiring between individual devices inside GOA cells, wiring between GOA cells, and complex situations of various wiring, and then manually draw these wiring step by the layout engineer. Therefore, the manual connection process is complicated, and the time consumption for drawing the whole layout is long. If the drawing process has a place to be changed or RC load of the connection line does not meet the design condition, the layout engineer also needs to redraw the connection line, so that the efficiency of the whole drawing process is extremely low.

In view of this, it is desirable to provide a layout wiring scheme so as to save the layout drawing time of the driving circuit and improve the layout drawing efficiency of the driving circuit.

Disclosure of Invention

To address at least one or more of the technical problems mentioned above, the present disclosure proposes, among other aspects, a layout wiring scheme based on a driving circuit.

In a first aspect, the present disclosure provides a layout routing method, the method comprising: the method comprises the steps of obtaining a first auxiliary layer and a second auxiliary layer from an initial physical layout of a laid-out target circuit, wherein the target circuit comprises at least one subunit, each subunit comprises at least one device, and the device at least comprises a first hierarchical structure and a second hierarchical structure which are stacked in a direction perpendicular to a substrate of the target circuit. And generating a target auxiliary layer according to the first auxiliary layer and the second auxiliary layer. In the target auxiliary layer, generating a wiring result according to the wiring parameters acquired in advance, wherein the wiring result at least comprises the following steps: a connection line for electrically connecting devices included in the current sub-unit within the current sub-unit, and a connection line for electrically connecting the current sub-unit with a target position outside the current sub-unit.

In a second aspect, the present disclosure provides a layout wiring device comprising: an auxiliary layer obtaining module, configured to obtain a first auxiliary layer and a second auxiliary layer from an initial physical layout of a laid-out target circuit, where the target circuit includes at least one subunit, each subunit includes at least one device, and the device includes at least a first hierarchical structure and a second hierarchical structure stacked in a direction perpendicular to a substrate of the target circuit; the auxiliary layer generation module is used for generating a target auxiliary layer according to the first auxiliary layer and the second auxiliary layer; the wiring result generation module is used for generating a wiring result according to the wiring parameters acquired in advance in the target auxiliary layer, wherein the wiring result at least comprises the following steps: a connection line for electrically connecting devices included in the current sub-unit within the current sub-unit, and a connection line for electrically connecting the current sub-unit with a target position outside the current sub-unit.

In a third aspect, the present disclosure provides an electronic device comprising a memory, a processor and a computer program stored on the memory and executable on the processor, the processor implementing the method as described in the first aspect when executing the computer program.

In a fourth aspect, the present disclosure provides a computer readable storage medium having stored thereon a computer program which, when executed by a processor, implements a method as described in the first aspect.

Through the layout wiring method, the layout wiring device, the electronic equipment and the storage medium provided by the above, the embodiment of the disclosure aims at a target circuit comprising at least one subunit, a first auxiliary layer and a second auxiliary layer are obtained from an initial physical layout of the laid target circuit, and a target auxiliary layer is generated according to the first auxiliary layer and the second auxiliary layer; then, in the target auxiliary layer, a wiring result is generated according to the wiring parameters acquired in advance, and the wiring result at least comprises: the connecting wire used for electrically connecting the devices contained in the current subunit within the range of the current subunit and the connecting wire used for electrically connecting the current subunit with the target position outside the range of the current subunit can be rapidly wired in the target auxiliary layer, so that the time for carrying out layout wiring on the target circuit is effectively saved, and the efficiency of drawing the target circuit layout is improved. Further, in some embodiments, by determining the first auxiliary layer and the second auxiliary layer in response to the operation information received in the initial physical layout, the auxiliary layers may be quickly extracted, saving time in drawing the layout. Still further, in some embodiments, the starting position information and the ending position information of the connection line to be generated are determined according to the wiring parameters by responding to the operation information received in the target auxiliary layer; according to the initial position information and the end position information, a connecting wire for electrically connecting devices contained in the current subunit within the range of the current subunit or a connecting wire for electrically connecting the current subunit with a target position outside the range of the current subunit is generated, one-key wiring can be realized on the target auxiliary layer, wiring of a complex circuit can be efficiently and rapidly completed, and the efficiency of layout drawing is effectively improved.

Drawings

The above, as well as additional purposes, features, and advantages of exemplary embodiments of the present disclosure will become readily apparent from the following detailed description when read in conjunction with the accompanying drawings. Several embodiments of the present disclosure are illustrated by way of example, and not by way of limitation, in the figures of the accompanying drawings and in which like reference numerals refer to similar or corresponding parts and in which:

FIG. 1 illustrates an exemplary application scenario in which embodiments of the present disclosure may be applied;

FIG. 2 is a schematic diagram of a display panel with a GOA circuit arranged on two sides;

FIG. 3 illustrates an exemplary flow chart of a layout routing method of some embodiments of the present disclosure;

FIG. 4 illustrates an initial physical layout schematic of some embodiments of the present disclosure;

FIG. 5 illustrates an unwired layout and a layout diagram containing the result of wiring of some embodiments of the present disclosure;

FIG. 6 illustrates a schematic device layout of some embodiments of the present disclosure;

FIG. 7 illustrates an exemplary flow chart of a layout routing method of other embodiments of the present disclosure;

FIG. 8 illustrates an exemplary block diagram of a layout routing device of some embodiments of the present disclosure;

FIG. 9 illustrates an exemplary block diagram of a layout routing device of other embodiments of the present disclosure;

Fig. 10 illustrates a user terminal or server architecture diagram of some embodiments of the present disclosure.

Detailed Description

The following description of the embodiments of the present disclosure will be made clearly and fully with reference to the accompanying drawings, in which it is evident that the embodiments described are some, but not all embodiments of the disclosure. Based on the embodiments in this disclosure, all other embodiments that may be made by those skilled in the art without the inventive effort are within the scope of the present disclosure.

It should be understood that the terms "comprises" and "comprising," when used in this specification and the claims, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.

It is also to be understood that the terminology used in the description of the present disclosure is for the purpose of describing particular embodiments only, and is not intended to be limiting of the disclosure. As used in the specification and claims of this disclosure, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It should be further understood that the term "and/or" as used in the present disclosure and claims refers to any and all possible combinations of one or more of the associated listed items, and includes such combinations.

As used in this specification and the claims, the term "if" may be interpreted as "when..once" or "in response to a determination" or "in response to detection" depending on the context. Similarly, the phrase "if a determination" or "if a [ described condition or event ] is detected" may be interpreted in the context of meaning "upon determination" or "in response to determination" or "upon detection of a [ described condition or event ]" or "in response to detection of a [ described condition or event ]".

Specific embodiments of the present disclosure are described in detail below with reference to the accompanying drawings.

Exemplary application scenarios

FIG. 1 illustrates one exemplary scenario in which embodiments of the present disclosure may be applied.

The layout wiring method provided by the embodiment of the disclosure can be applied to an application environment shown in fig. 1. Wherein the user terminal 102 communicates with the server 104 via a network. The data storage system may store data that the server 104 needs to process. The data storage system may be integrated on the server 104 or may be located on a cloud server or other server.

A software product for implementing a flat panel display design is installed on the user terminal 102. The software product used to implement the flat panel display design may be an EDA product. In an operating interface of the software product, an externally entered design request may be received. The design request is for requesting generation of layout elements in the physical layout. The design request may include at least one or two, or a plurality of design parameters. The design request may be externally entered click operation information, selection operation information, or voice control operation information received in an operation interface presented by the software product, the operation information indicating an operation on an associated icon within the operation interface presented by the software product. The layout elements at least may include: and the graphic elements are in one-to-one correspondence with devices, connecting wires, through holes and the like in the physical layout. The design parameters may include at least: the parameter values required for generating various devices, connection lines, vias, and the like may be referred to as device parameters, wiring parameters, and the like, for example. After the user terminal 102 receives the design request, the design request may be processed by a processor in the terminal 102 to obtain a design result corresponding to the design request, or the design request may be transmitted to the server 104 for processing to obtain a design result corresponding to the design request.

The user terminal 102 may be, but is not limited to, various desktop computers, notebook computers, intelligent terminals, etc.

The server 104 may be implemented as a stand-alone server or as a server cluster of multiple servers. The server may be an independent physical server, a server cluster or a distributed system formed by a plurality of physical servers, or a cloud server for providing cloud computing service, where the cloud server may be a public cloud server, a hybrid cloud server or a private cloud server. The terminal and the server may be directly or indirectly connected through wired or wireless communication, and the disclosure is not limited herein.

Fig. 2 is a schematic diagram of a display panel with a GOA circuit arranged on two sides.

Due to the requirements of thin and narrow frames of the display panel, the GOA technology integrates the gate drive IC on the array substrate, removes the original gate drive IC, and uses TFT wiring to form a gate circuit to form a GOA unit instead of an external drive chip. The GOA implementation process is the same as the liquid crystal display TFT manufacturing process, a new process flow is not needed to be added, and the gate drive IC is removed, so that the product cost can be reduced. As shown in fig. 2, GOA circuits are provided on both sides of the display panel. The display panel may include a display area AA and peripheral areas B disposed at both sides of the display area, the peripheral areas B being provided as GOA circuits. The GOA circuit is assumed to include 1080 cascaded GOA cells, each of which employs an 8T1C architecture, and is shown here by way of illustration and not limitation of a particular type. In general, the M1 metal can be adopted for all the clock signal wires, the clock signal wires and the GOA unit can be connected by using a jumper wire, and the M2 metal can be adopted for the jumper wire; and wiring in the GOA unit, wherein M1 metal is used as a grid electrode (G) of the thin film transistor, and M2 metal is used as a source/drain electrode (S/D) of the thin film transistor. The TFTs in the GOA units are provided with M1 metal wires and M2 metal wires, and the crossing wires between the clock signal wires and the GOA units need to avoid the TFTs in the GOA units while crossing the inorganic layer to overlap with the driving TFTs, so that short circuits between the metal wires are prevented.

According to the principle of the GOA circuit, a physical layout corresponding to the GOA circuit is drawn, and a layout engineer firstly manually places all devices of the GOA circuit, such as a TFT device and a capacitor device, and then manually connects all devices. In the case of the GOA units of the LCD vehicle-mounted display screen, more than 20 TFT devices are arranged in each GOA unit, wiring is complex, manual wiring is only adopted at present, the whole wiring time needs to take 1-2 weeks, and if RC load is unsuitable or other places connected with the GOA units are changed, the connection needs to be re-wired, so that the use time is prolonged. This time consuming manual drawing of the join line takes up 90% of the total time consumed in drawing the GOA unit. Obviously, the GOA circuit is subjected to layout drawing, and because the manual connection process is tedious, errors are easy to occur, so that the drawing time of the GOA circuit is overlong, and the efficiency is lower.

In view of this, the disclosed embodiments provide a layout wiring scheme, for a GOA circuit including at least one subunit, by acquiring a first auxiliary layer and a second auxiliary layer from an initial physical layout of a laid-out target circuit, generating a target auxiliary layer according to the first auxiliary layer and the second auxiliary layer, and then generating a wiring result in the target auxiliary layer according to a wiring parameter acquired in advance, it is possible to quickly complete the wiring of the GOA circuit, greatly save wiring time, and improve efficiency of physical layout drawing of the GOA circuit.

As shown in connection with fig. 1, the layout wiring method provided by the present disclosure may be implemented on the user terminal 102 or the server 104 as follows.

FIG. 3 illustrates an exemplary flow chart of a layout routing method of some embodiments of the present disclosure.

Step 310, obtaining a first auxiliary layer and a second auxiliary layer from the initial physical layout of the laid-out target circuit.

Wherein the target circuit comprises at least one subunit, each subunit comprising at least one device. The device includes at least a first hierarchical structure and a second hierarchical structure stacked in a direction perpendicular to a substrate of a target circuit.

And 330, generating a target auxiliary layer according to the first auxiliary layer and the second auxiliary layer.

The first auxiliary layer is determined according to the area which corresponds to each subunit contained in the laid-out target circuit in the initial physical layout. The second auxiliary layer is defined by the area corresponding to each device contained in the subunit alone.

In step 350, in the target auxiliary layer, a wiring result is generated according to the wiring parameter acquired in advance. The wiring result includes at least: a connection line for electrically connecting devices included in the current sub-unit within the current sub-unit, and a connection line for electrically connecting the current sub-unit with a target position outside the current sub-unit.

As further understood in connection with FIG. 4, at step 310, a first auxiliary layer and a second auxiliary layer are obtained from the initial physical layout of the laid out target circuit. The laid out target circuit includes one, two, or more sub-cells. As shown in fig. 4, in the initial physical layout a shown in the operation interface, the GOA circuit layout has a plurality of GOA cells. For example, the values of GOA1, GOA2, … … GOAn can be adjusted according to the specific design requirements, for example, n is 1080. At least the GOA units comprise: one or more TFT devices, and one or more capacitive devices. According to the externally input operation information, a first auxiliary layer A1 and a second auxiliary layer A2 are determined in response to the operation information received in the initial physical layout. Wherein the first auxiliary layer A1 is determined by the area individually corresponding to each subunit (i.e. GOA unit) comprised by the target circuit. The second auxiliary layer A2 is defined by an area individually corresponding to each device (i.e., TFT device or capacitor device) included in the sub-unit.

In an implementation, the acquiring the first auxiliary layer may be acquiring a coordinate parameter of a frame corresponding to the first auxiliary layer. The acquiring the second auxiliary layer may be acquiring a coordinate parameter of a frame corresponding to the second auxiliary layer. The frames of the auxiliary layer take into account the spacing of adjacent sub-units.

In one implementation, the externally entered operational information may take a variety of forms. Those skilled in the art will appreciate that the disclosed embodiments are not limited in this respect. For example, the first auxiliary layer A1 and the second auxiliary layer A2 may be extracted by one-touch, or operation information performed for an area individually corresponding to each sub-unit included in the target circuit and operation information performed for an area individually corresponding to each device included in the sub-unit may be received, respectively.

In one implementation, the external input operation information adopts a frame selection mode, the user controls external input equipment such as a mouse, and in an operation interface for displaying the initial physical layout, the target area is operated by the external input equipment to perform frame selection so as to determine the first auxiliary layer and the second auxiliary layer.

In another implementation, the externally entered operational information may also be extracted using one-touch. The keys for extracting the auxiliary layers can be triggered by external input operations, such as clicking keys, voice control, or remote input operations, aiming at the function keys in an operation interface for displaying the initial physical layout. And determining a first auxiliary layer and a second auxiliary layer in response to operation information received in the initial physical layout, wherein the operation information is respectively executed for an area which is respectively corresponding to each subunit contained in the target circuit and an area which is respectively corresponding to each device contained in the subunit. By adopting the mode, the auxiliary layer can be extracted rapidly and conveniently, the time for generating the target auxiliary layer is further saved, and the efficiency of layout drawing is improved.

In step 330, a target auxiliary layer is generated from the first auxiliary layer and the second auxiliary layer.

Optionally, a logic operation may be performed according to the coordinate parameter corresponding to the first auxiliary layer and the coordinate parameter corresponding to the second auxiliary layer, so as to obtain the target auxiliary layer. Logical operations may include and operations, non-operations, and the like in sequence. According to the method and the device, the target auxiliary layer is obtained through simple logic operation, so that the layout processing time can be saved, and the layout drawing efficiency is further improved.

Next, in step 350, in the target auxiliary layer, a wiring result is generated from the wiring parameters acquired in advance.

Step 350 is further understood in conjunction with fig. 5, as shown in fig. 5, (a) is a schematic diagram of a target auxiliary layer A3 to be wired, where the auxiliary layer A3 refers to an area other than the area occupied by the device layout position. (b) The figure is a schematic diagram of the target auxiliary layer A3 of the completed wiring. Displaying a plurality of different patterns of connection lines in (b), the connection lines including connection lines for electrically connecting devices included in the current sub-unit within the range of the current sub-unit, and connection lines for electrically connecting the current sub-unit with a target location outside the range of the current sub-unit. The same pattern of the connection lines as the hierarchical structure of the device means that the connection lines are made of the same material as the hierarchical structure.

In one implementation, step 350 may at least include: determining initial position information and termination position information of a connecting line to be generated according to wiring parameters in response to operation information received in a target auxiliary layer; and generating a connecting wire for electrically connecting devices contained in the current subunit within the range of the current subunit or a connecting wire for electrically connecting the current subunit with a target position outside the range of the current subunit according to the starting position information and the ending position information.

In one implementation, the operation information may be at least one-key triggering implemented by operating a function key through an external input device in an operation interface for displaying the initial physical layout. For example, clicking a key, voice control, or remote input operation triggers a key for acquiring a wiring parameter. The method can also be a mode of operating on the area corresponding to the target auxiliary layer, for example, clicking a right button or a shortcut key is adopted in the area corresponding to the target auxiliary layer to trigger generation of the wiring result. In response to the operation information received in the target auxiliary layer, a wiring result can be generated in the target auxiliary layer according to the wiring parameters, and one-key generation wiring of the complex circuit is realized. The target circuit may be a GOA circuit or a circuit similar in structure to the GOA circuit.

According to the layout wiring scheme provided by the embodiment of the disclosure, the wiring result is generated in the target auxiliary layer through one-key triggering, so that the physical layout wiring time of the GOA circuit is effectively saved, and the layout wiring efficiency of the complex circuit is improved.

In an implementation, the wiring parameters at least include an input port, an output port, a label of the input port, a label of the output port, a category of a metal layer to which the label belongs, a position of a via, via information of a crossover, a via size, a resistance value of a connecting line, and the like. The connection lines used to electrically connect the input ports or output ports of the device may be associated by pairing the label of the input port with the label of the output port. For example, the routing parameters may include at least predefined Gate line and SD line widths (widths), line distances (spaces), SD line/Gate line spaces, and other rule; the routing parameters may include at least defining a film connection relationship setting: gate and SD connected by Via; ITO and SD connected by Via; and defines a rule of the line extension Via;

in an implementation, the initial position information at least includes a port identifier, and a metal class corresponding to the port (i.e. a hierarchy attribute corresponding to the port). As shown in fig. 5, it is assumed that an output port label 1 of TFT2 included in the GOA unit 1 needs to be associated with an input port label 1 of TFT 3. Taking the output port of the TFT2 as an example, the output port label 1 of the TFT2 is predefined to be connected by adopting a second metal wire (namely an S/D wire), the line width of the second metal wire needs to be smaller than a preset threshold value, and the line distance between two adjacent second metal wires needs to be larger than or equal to a certain threshold value and other limiting conditions. Alternatively, other input ports, other output ports may be similarly defined. Those skilled in the art will appreciate that the disclosed embodiments are not limited in this respect.

In an implementation, generating, according to the start position information and the end position information, a connection line for electrically connecting devices included in the current subunit within the range of the current subunit may at least include:

determining a hierarchy attribute contained in the initial position information and a hierarchy attribute contained in the final position information; and determining to generate a first connecting line, a second connecting line or a third connecting line according to the hierarchy attribute contained in the initial position information and the hierarchy attribute contained in the end position information. The first connecting wire and the first hierarchical structure are made of the same material, the second connecting wire and the second hierarchical structure are made of the same material, and the third connecting wire is a through hole communicated with different hierarchical structures. The first hierarchical structure and the second hierarchical structure are stacked in a direction perpendicular to the substrate of the target circuit. The first hierarchical structure may be a first metal layer, i.e., an M1 metal layer. The second hierarchical structure may be a second metal layer, i.e., an M2 metal layer. The first connection lines, the second connection lines may be designed according to a wiring hierarchy, and the layer-to-layer connection may be connected through vias (i.e., third connection lines).

The first connection line and the second connection line are also stacked in a direction perpendicular to the substrate of the target circuit, which coincides with the stacking direction of the first hierarchical structure and the second hierarchical structure on the substrate. It is contemplated that the TFT device may be a top gate structure or a bottom gate structure. Taking a top Gate structure as an example, a first level structure (Gate layer) is disposed above a second level structure (S/D layer) with the array substrate as a starting position, and a Gate insulating layer is disposed between the first level structure and the second level structure. Taking a bottom Gate structure as an example, a second level structure (S/D layer) is disposed above the first level structure (Gate layer) with the array substrate as a starting position, and a Gate insulating layer is disposed between the first level structure and the second level structure. The first connecting line and the second connecting line respectively correspond to the stacking positions of the Gate layer and the S/D layer.

Optionally, determining to generate the first connection line, the second connection line, or the third connection line according to the hierarchy attribute contained in the start position information and the hierarchy attribute contained in the end position information, at least includes:

if the hierarchy attribute contained in the initial position information and the hierarchy attribute contained in the end position information are the same as the first hierarchy (or called a first metal layer), obtaining a wiring parameter associated with the first hierarchy; a first connection line for electrically connecting devices included in the current sub-unit within the current sub-unit is generated according to wiring parameters associated with the first hierarchical structure. The first connecting wire is made of the same material as the first hierarchical structure.

If the hierarchy attribute contained in the initial position information and the hierarchy attribute of the end position information are the second hierarchy (or called a second metal layer), obtaining a wiring parameter associated with the second hierarchy; and generating a second connecting line for electrically connecting devices contained in the current subunit within the range of the current subunit according to the wiring parameters associated with the second hierarchical structure. The second connecting wire is made of the same material as the second hierarchical structure.

If the hierarchy attribute contained in the initial position information is different from the hierarchy attribute contained in the termination position information, acquiring wiring parameters related to the set via holes; and generating a third connecting wire for electrically connecting devices contained in the current subunit within the range of the current subunit according to the wiring parameters related to the set via holes. The third connecting line is a via hole for connecting different hierarchical structures.

Optionally, the connection relationship between the current subunit and the target position outside the current subunit can be determined according to the starting position information and the ending position information; and determining and generating a fourth connecting line according to the connection relation, wherein the fourth connecting line is a cross line for connecting the current subunit and the target position outside the current subunit.

The layout wiring scheme provided by the embodiment of the disclosure obtains a first auxiliary layer and a second auxiliary layer from an initial physical layout of a laid-out target circuit; generating a target auxiliary layer according to the first auxiliary layer and the second auxiliary layer; in the target auxiliary layer, a wiring result is generated according to the wiring parameters acquired in advance, and the wiring result is used for electrically connecting devices contained in the current subunit within the range of the current subunit and connecting wires used for electrically connecting the current subunit with target positions outside the range of the current subunit. According to the method, the wiring area is determined, the wiring result is generated in the wiring area according to the wiring parameters, so that the drawing time of the physical layout of the GOA circuit is effectively saved, and the drawing efficiency of the physical layout is improved.

Still further embodiments of the present disclosure provide a layout routing method, prior to step 330, which may further include: and acquiring a pre-stored wiring parameter file in response to the operation information received in the target auxiliary layer. The routing parameter file includes routing parameters.

In one implementation, in response to operation information received in a target auxiliary layer, a call request is sent to a storage device or a data storage system, the call request being for requesting to call one or more routing parameter files corresponding to devices included in a second auxiliary layer, and then routing parameters are obtained from the routing parameter files.

In another implementation, the acquisition of the routing parameters may be prior to generating the target auxiliary layer, or after generating the target auxiliary layer, prior to generating the routing result. The routing parameters may be entered via an external input device, and then one or more routing parameter files may be generated based on the entered routing parameters and stored to a data storage system or a storage device of the user terminal 102. According to the layout wiring scheme provided by the embodiment of the disclosure, the wiring parameter file is preset, so that the drawing efficiency of the physical layout of the GOA circuit is further improved.

In still other embodiments of the present disclosure, the layout routing method may further include, before acquiring the first auxiliary layer and the second auxiliary layer from the initial physical layout of the laid-out target circuit:

generating a device according to the device generation parameters acquired in advance;

and determining the position of the device in the initial physical layout according to the layout information of the target circuit.

The device generation parameter may be the W size of the device, which is from 28um to 350um, and according to the W size, the S-shaped lines may be arranged to save space, as shown in fig. 6, the left side view is the device layout with w=28 um, which requires only 3S bends. The right plot is a device layout with w=350 um, which requires 9S-bends. The width of the S-bend is the L value of the channel. The line width of the channel may be defined according to the minimum value that the exposure machine can expose. The area of the device can be reduced by adopting the W-shaped design, so that the wiring space is increased, the line width of the corresponding connecting line can be properly widened, and the corresponding resistance value can be reduced.

According to the layout wiring method of other embodiments of the present disclosure, by automatically generating devices and automatically arranging the positions of the devices in the physical layout, the time for drawing the layout is saved to a certain extent, and the drawing efficiency of the physical layout of the complex circuit is improved.

FIG. 7 illustrates an exemplary flow chart of a layout routing method of other embodiments of the present disclosure.

Step 710, obtaining a first auxiliary layer and a second auxiliary layer from the initial physical layout of the laid-out target circuit. Wherein the target circuit comprises at least one subunit, each subunit comprising at least one device comprising at least a first hierarchical structure and a second hierarchical structure arranged in a stack in a direction perpendicular to the substrate of the target circuit.

In step 720, a target auxiliary layer is generated according to the first auxiliary layer and the second auxiliary layer. The first auxiliary layer is determined according to the area which corresponds to each subunit contained in the target circuit in the initial physical layout. The second auxiliary layer is defined by the area individually corresponding to each device comprised by the subunit.

Step 730, generating a wiring result according to the wiring parameter acquired in advance in the target auxiliary layer, where the wiring result at least includes: a connection line for electrically connecting devices included in the current sub-unit within the current sub-unit, and a connection line for electrically connecting the current sub-unit with a target position outside the current sub-unit.

Step 740, extracting RC load value corresponding to the wiring result;

and 750, when the RC load value is determined not to meet the RC load threshold, adjusting the wiring result until the RC load threshold is met, and outputting a final wiring result and a final RC load value.

Step 760, when it is determined that the RC load value satisfies the RC load threshold, outputting the wiring result and the RC load value.

The RC load threshold can be adjusted and set according to actual requirements. After the layout wiring scheme provided by the embodiment of the disclosure is used for generating the wiring result, by setting the RC automatic extraction function, whether the wiring result meets RC load requirements can be rapidly judged, the accuracy of the wiring result is improved, the wiring time of the physical layout of the whole GOA circuit is effectively saved, and the layout wiring efficiency of the complex circuit is improved.

The embodiment of the disclosure also provides a layout wiring device. Fig. 8 shows an exemplary block diagram of a layout wiring device provided in accordance with an embodiment of the present disclosure. As shown in fig. 8, the apparatus includes:

the auxiliary layer obtaining module 810 is configured to obtain a first auxiliary layer and a second auxiliary layer from the initial physical layout of the laid-out target circuit. Wherein the target circuit comprises at least one subunit, each of said subunits comprising at least one device. The device includes at least a first hierarchical structure and a second hierarchical structure stacked in a direction perpendicular to a substrate of a target circuit;

The target layer generating module 820 is configured to generate a target auxiliary layer according to the first auxiliary layer and the second auxiliary layer.

The wiring result generating module 830 is configured to generate, in the target auxiliary layer, a wiring result according to a wiring parameter acquired in advance. The wiring result includes at least: a connection line for electrically connecting devices included in the current sub-unit within the current sub-unit, and a connection line for electrically connecting the current sub-unit with a target position outside the current sub-unit.

Optionally, the auxiliary layer acquisition module 810 is further configured to: and determining the first auxiliary layer and the second auxiliary layer in response to operation information received in the initial physical layout, wherein the operation information is executed for each sub-unit individually corresponding area contained in the target circuit and each device individually corresponding area contained in the sub-unit.

The target layer generating module 820 is further configured to perform a logic operation according to the first auxiliary layer and the second auxiliary layer to obtain a target auxiliary layer.

The routing result generation module 830 further includes:

the position information determining sub-module is used for responding to the operation information received in the target auxiliary layer and determining the initial position information and the end position information of the connecting line to be generated according to the wiring parameters;

And the wiring result generation sub-module is used for generating a connecting wire for electrically connecting devices contained in the current sub-unit within the range of the current sub-unit or a connecting wire for electrically connecting the current sub-unit with a target position outside the range of the current sub-unit according to the starting position information and the ending position information.

The wiring result generation sub-module is further configured to: determining a hierarchy attribute contained in the initial position information and a hierarchy attribute contained in the final position information; and determining and generating a first connecting wire, a second connecting wire or a third connecting wire according to the hierarchy structure attribute contained in the initial position information and the hierarchy structure attribute contained in the termination position information, wherein the first connecting wire and the first hierarchy structure are made of the same material, the second connecting wire and the second hierarchy structure are made of the same material, and the third connecting wire is a through hole communicated with different hierarchy structures.

The wiring result generation sub-module is also used for determining the connection relation between the current sub-unit and the target position outside the current sub-unit according to the starting position information and the ending position information; and determining and generating a fourth connecting line according to the connection relation, wherein the fourth connecting line is a cross line for connecting the current subunit and the target position outside the current subunit.

The device may further include: the device generation module is used for generating a device according to the device generation parameters acquired in advance; and determining the position of the device in the initial physical layout according to the layout information of the target circuit.

The device may further include:

and the wiring parameter acquisition module is used for responding to the operation information received in the target auxiliary layer and acquiring a pre-stored wiring parameter file, wherein the wiring parameter file at least comprises wiring parameters. According to the device provided by the embodiment of the disclosure, a first auxiliary layer and a second auxiliary layer are obtained from an initial physical layout of a laid target circuit; generating a target auxiliary layer according to the first auxiliary layer and the second auxiliary layer; in the target auxiliary layer, a wiring result is generated according to a wiring parameter acquired in advance. According to the method, the wiring area is determined, the wiring result is generated in the wiring area according to the wiring parameters, so that the drawing time of the physical layout of the GOA circuit is effectively saved, and the drawing efficiency of the physical layout is improved.

The embodiment of the disclosure also provides a layout wiring device. Fig. 9 shows an exemplary block diagram of a layout wiring device provided in accordance with an embodiment of the present disclosure. As shown in fig. 9, the apparatus includes:

The auxiliary layer obtaining module 910 is configured to obtain a first auxiliary layer and a second auxiliary layer from an initial physical layout of the laid-out target circuit. Wherein the target circuit comprises at least one subunit, each of said subunits comprising at least one device. The device includes at least a first hierarchical structure and a second hierarchical structure stacked in a direction perpendicular to a substrate of a target circuit;

the target layer generating module 920 is configured to generate a target auxiliary layer according to the first auxiliary layer and the second auxiliary layer.

A wiring result generating module 930, configured to generate a wiring result according to a wiring parameter acquired in advance in the target auxiliary layer. The wiring result includes at least: a connection line for electrically connecting devices included in the current sub-unit within the current sub-unit, and a connection line for electrically connecting the current sub-unit with a target position outside the current sub-unit.

The wiring result generation module 930 includes at least:

a wiring result generation sub-module 9301 for generating a wiring result according to the wiring parameter;

a load extraction submodule 9302 for extracting an RC load value corresponding to the wiring result;

And a wiring result adjustment submodule 9303, configured to, when it is determined that the RC load value does not meet the RC load threshold, adjust the wiring result until the RC load threshold is met, and output a final wiring result and a final RC load value.

The wiring result output submodule 9304 is configured to output a wiring result and an RC load value when the RC load value satisfies the RC load threshold.

After the wiring result is generated, the layout wiring device provided by the embodiment of the disclosure can quickly judge whether the wiring result meets RC load requirements or not by setting the RC automatic extraction function, so that the accuracy of the wiring result is improved, the wiring time of the physical layout of the whole GOA circuit is effectively saved, and the layout wiring efficiency of the complex circuit is improved.

It should be understood that the units or modules described in the apparatus correspond to the individual steps in the method described above. Thus, the operational instructions and features described above for the method are equally applicable to the apparatus and the units contained therein, and are not described in detail herein. The device can be pre-implemented in a browser of the electronic equipment or other security applications, or can be loaded into the browser of the electronic equipment or the security applications thereof by means of downloading and the like. Corresponding units in the apparatus may cooperate with units in the electronic device to implement aspects of embodiments of the present disclosure.

The division of the modules or units mentioned in the above detailed description is not mandatory. Indeed, the features and functions of two or more modules or units described above may be embodied in one module or unit in accordance with embodiments of the present disclosure. Conversely, the features and functions of one module or unit described above may be further divided into a plurality of modules or units to be embodied.

Referring now to fig. 10, fig. 10 illustrates a schematic diagram of a user terminal or server of some embodiments of the present disclosure.

As shown in fig. 10, the computer system includes a Central Processing Unit (CPU) 1001 that can execute various appropriate actions and processes according to a program stored in a Read Only Memory (ROM) 1002 or a program loaded from a storage section 1008 into a Random Access Memory (RAM) 1003. In the RAM 1003, various programs and data required for the operation instructions of the system 1000 are also stored. The CPU 1001, ROM 1002, and RAM 1003 are connected to each other by a bus 1004. An input/output (I/O) interface 1005 is also connected to bus 1004.

The following components are connected to the I/O interface 1005: an input section 1006 including a keyboard, a mouse, and the like; an output portion 1007 including a Cathode Ray Tube (CRT), a Liquid Crystal Display (LCD), etc., and a speaker, etc.; a storage portion 1008 including a hard disk or the like; and a communication section 1009 including a network interface card such as a LAN card, a modem, or the like. The communication section 1009 performs communication processing via a network such as the internet. The drive 1010 is also connected to the I/O interface 1005 as needed. A removable medium 1011, such as a magnetic disk, an optical disk, a magneto-optical disk, a semiconductor memory, or the like, is installed as needed in the drive 1010, so that a computer program read out therefrom is installed as needed in the storage section 1008.

In particular, the process described above with reference to flowchart fig. 3 may be implemented as a computer software program according to embodiments of the present disclosure. For example, embodiments of the present disclosure include a computer program product comprising a computer program embodied on a machine-readable medium, the computer program comprising program code for performing the method shown in the flow diagrams. In such an embodiment, the computer program may be downloaded and installed from a network via the communication portion 1009, and/or installed from the removable medium 1011. The above-described functions defined in the system of the present disclosure are performed when the computer program is executed by a Central Processing Unit (CPU) 1001.

It should be noted that the computer readable medium shown in the present disclosure may be a computer readable signal medium or a computer readable storage medium or any combination of the two. The computer readable storage medium can be, for example, but not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or a combination of any of the foregoing. More specific examples of the computer-readable storage medium may include, but are not limited to: an electrical connection having one or more wires, a portable computer diskette, a hard disk, a Random Access Memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing. In the context of this disclosure, a computer-readable storage medium may be any tangible medium that can contain, or store a program for use by or in connection with an instruction execution system, apparatus, or device. In the present disclosure, however, the computer-readable signal medium may include a data signal propagated in baseband or as part of a carrier wave, with the computer-readable program code embodied therein. Such a propagated data signal may take any of a variety of forms, including, but not limited to, electro-magnetic, optical, or any suitable combination of the foregoing. A computer readable signal medium may also be any computer readable medium that is not a computer readable storage medium and that can communicate, propagate, or transport a program for use by or in connection with an instruction execution system, apparatus, or device. Program code embodied on a computer readable medium may be transmitted using any appropriate medium, including but not limited to: wireless, wire, fiber optic cable, RF, etc., or any suitable combination of the foregoing.

The flowcharts and block diagrams in the figures illustrate the architecture, functionality, and operation instructions of possible implementations of systems, methods and computer program products according to various embodiments provided by the present disclosure. In this regard, each block in the flowchart or block diagrams may represent a module, segment, or portion of code, which comprises one or more executable instructions for implementing the specified logical function(s). It should also be noted that, in some alternative implementations, the functions noted in the block may occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved. It will also be noted that each block of the block diagrams and/or flowchart illustration, and combinations of blocks in the block diagrams and/or flowchart illustration, can be implemented by special purpose hardware-based systems which perform the specified functions or acts, or combinations of special purpose hardware and computer instructions.

The units or modules referred to in the embodiments of the disclosure may be implemented in software or in hardware. The described units or modules may also be provided in a processor, for example, as: a processor includes an auxiliary layer acquisition module, an auxiliary layer generation module, and a wiring result generation module. The names of these units or modules do not in some cases limit the unit or module itself, for example, the auxiliary layer acquisition module may also be described as "a module for acquiring the first auxiliary layer and the second auxiliary layer from the initial physical layout of the laid out target circuit".

As another aspect, the present disclosure also provides a computer-readable storage medium that may be included in the electronic device described in the above embodiments; or may be present alone without being incorporated into the electronic device. The computer-readable storage medium stores one or more programs that when used by one or more processors perform the layout routing methods described in the present disclosure.

While various embodiments of the present disclosure have been shown and described herein, it will be obvious to those skilled in the art that such embodiments are provided by way of example only. Numerous modifications, changes, and substitutions will occur to those skilled in the art without departing from the spirit and scope of the present disclosure. It should be understood that various alternatives to the embodiments of the disclosure described herein may be employed in practicing the disclosure. The appended claims are intended to define the scope of the disclosure and are therefore to cover all equivalents or alternatives falling within the scope of these claims.

Claims (13)

1. A layout wiring method, the method comprising:

Obtaining a first auxiliary layer and a second auxiliary layer from an initial physical layout of a laid-out target circuit, wherein the target circuit comprises at least one subunit, each subunit comprises at least one device, and the device at least comprises a first hierarchical structure and a second hierarchical structure which are stacked in a direction perpendicular to a substrate of the target circuit;

generating a target auxiliary layer according to the first auxiliary layer and the second auxiliary layer;

in the target auxiliary layer, generating a wiring result according to a wiring parameter acquired in advance, wherein the wiring result at least comprises: a connection line for electrically connecting devices included in the current sub-unit within the current sub-unit, and a connection line for electrically connecting the current sub-unit with a target position outside the current sub-unit.

2. The method of claim 1, wherein the obtaining the first auxiliary layer and the second auxiliary layer from the initial physical layout of the laid out target circuit comprises:

and determining the first auxiliary layer and the second auxiliary layer in response to operation information received in the initial physical layout, wherein the operation information is executed for each sub-unit individually corresponding area contained in the target circuit and each device individually corresponding area contained in the sub-unit.

3. The method of claim 1, wherein generating a target auxiliary layer from the first auxiliary layer and the second auxiliary layer comprises:

and carrying out logic operation according to the first auxiliary layer and the second auxiliary layer to obtain the target auxiliary layer.

4. The method of claim 1, wherein generating a routing result in the target auxiliary layer from pre-acquired routing parameters comprises:

determining initial position information and termination position information of a connecting line to be generated according to the wiring parameters in response to operation information received in the target auxiliary layer;

and generating a connecting wire for electrically connecting devices contained in the current subunit within the range of the current subunit or a connecting wire for electrically connecting the current subunit with a target position outside the range of the current subunit according to the starting position information and the ending position information.

5. The method of claim 4, wherein generating connection lines for electrically connecting devices included in a current subunit within a range of the current subunit based on the start position information and the end position information, at least comprises:

Determining a hierarchical structure attribute contained in the initial position information and a hierarchical structure attribute contained in the end position information;

and determining and generating a first connecting wire, a second connecting wire or a third connecting wire according to the hierarchy attribute contained in the initial position information and the hierarchy attribute contained in the end position information, wherein the first connecting wire and the first hierarchy are made of the same material, the second connecting wire and the second hierarchy are made of the same material, and the third connecting wire is a through hole communicated with different hierarchies.

6. The method of claim 4, wherein generating a connection line for electrically connecting a current subunit with a target location outside a range of the current subunit based on the start location information and the end location information, comprises at least:

determining the connection relation between the current subunit and the target position outside the current subunit according to the initial position information and the termination position information;

and determining and generating a fourth connecting line according to the connection relation, wherein the fourth connecting line is an overline for connecting the current subunit and the target position outside the current subunit.

7. The method according to claim 1, wherein generating a routing result in the target auxiliary layer from a pre-acquired routing parameter comprises at least:

generating the wiring result according to the wiring parameters;

extracting an RC load value corresponding to the wiring result;

and when the RC load value is determined not to meet the RC load threshold, adjusting the wiring result until the RC load threshold is met, and outputting a final wiring result and a final RC load value.

8. The method of claim 7, wherein generating a routing result in the target auxiliary layer from pre-acquired routing parameters, further comprises:

and outputting the wiring result and the RC load value when the RC load value meets the RC load threshold.

9. The method of claim 1, wherein prior to said obtaining the first auxiliary layer and the second auxiliary layer from the initial physical layout of the laid out target circuit, the method further comprises:

generating the device according to the device generation parameters acquired in advance;

and determining the position of the device in the initial physical layout according to the layout information of the target circuit.

10. The method of claim 1, wherein prior to generating a routing result in the target auxiliary layer from pre-acquired routing parameters, the method further comprises:

and responding to the operation information received in the target auxiliary layer, acquiring a pre-stored wiring parameter file, wherein the wiring parameter file at least comprises the wiring parameters.

11. A layout wiring device, the device comprising:

an auxiliary layer obtaining module, configured to obtain a first auxiliary layer and a second auxiliary layer from an initial physical layout of a laid-out target circuit, where the target circuit includes at least one subunit, each subunit includes at least one device, and the device includes at least a first hierarchical structure and a second hierarchical structure that are stacked in a direction perpendicular to a substrate of the target circuit;

the auxiliary layer generation module is used for generating a target auxiliary layer according to the first auxiliary layer and the second auxiliary layer;

the wiring result generation module is used for generating a wiring result according to the wiring parameters acquired in advance in the target auxiliary layer, and the wiring result at least comprises: a connection line for electrically connecting devices included in the current sub-unit within the current sub-unit, and a connection line for electrically connecting the current sub-unit with a target position outside the current sub-unit.

12. An electronic device comprising a memory, a processor and a computer program stored on the memory and executable on the processor, wherein the processor implements the method of any one of claims 1-10 when the program is executed by the processor.

13. A computer readable storage medium having stored thereon a computer program which, when executed by a processor, implements the method of any of claims 1-10.