CN1173406C - Semiconductor memory device with capacitor protective layer and preparing method thereof - Google Patents

Semiconductor memory device with capacitor protective layer and preparing method thereof Download PDF

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Publication number
CN1173406C
CN1173406C CNB001318926A CN00131892A CN1173406C CN 1173406 C CN1173406 C CN 1173406C CN B001318926 A CNB001318926 A CN B001318926A CN 00131892 A CN00131892 A CN 00131892A CN 1173406 C CN1173406 C CN 1173406C
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layer
capacitor
storage unit
semiconductor storage
barrier
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CN1292571A (en
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李容卓
赵学柱
金荣宽
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Samsung Electronics Co Ltd
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Samsung Electronics Co Ltd
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Priority claimed from KR10-1999-0065074A external-priority patent/KR100370235B1/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H01L28/55—Capacitors with a dielectric comprising a perovskite structure material
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B53/00—Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B53/00—Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors
    • H10B53/30—Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors characterised by the memory core region

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  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Semiconductor Memories (AREA)
  • Formation Of Insulating Films (AREA)
  • Non-Volatile Memory (AREA)

Abstract

The present invention relates to a semiconductor memory device having a capacitor protection layer and a method for manufacturing the same. A capacitor of the semiconductor memory device is entirely covered with an encapsulating layer having a multi-layered structure. The encapsulating layer comprises at least a blocking layer and a capacitor protection layer, each of which is formed of different materials. The blocking is formed of a material capable of preventing a capacitor dielectric layer from volatilizing and/or capable of preventing a reaction between a material layer under the blocking layer and the capacitor protection layer. The capacitor protection layer is formed of a material layer capable of preventing diffusion of hydrogen into the capacitor dielectric layer. In addition, the semiconductor memory device may has a hydrogen barrier layer as another capacitor protection layer, between the capacitor and a passivity layer.

Description

Has semiconductor storage unit of capacitor protective layer and preparation method thereof
Technical field
The present invention relates to semiconductor storage unit and preparation method thereof, especially relate to semiconductor storage unit that has capacitor protective layer and preparation method thereof.
Background technology
In recent years, in preparation semiconductor storage unit field, the method for utilizing ferroelectric material to form capacitor dielectric layer causes great concern.This is because in non-volatile semiconductor devices, the remanent polarization (P of ferroelectric material r) being adapted to the notion of binary storage device, binary storage device forms the basis of the digital memory device of extensive use.At present, obtain two kinds of main ferroelectric material: PZT (Pb (Zr, Ti) O of using 3And SBT (SrBi 2Ta 2O 9).
Yet, utilizing ferroelectric material to form in the capacitor dielectric layer of semiconductor storage unit, serious problems are during the integrated step of the semiconductor storage unit finished form capacitor after, the ferroelectric properties degeneration of ferroelectric material.Particularly, form after the capacitor, connect with inter-level dielectric (ILD) step, inter-metal medium (IMD) step, passivation step etc.During these steps, derive especially hydrogen ion of impurity.During forming step, the hydrogen ion of deriving is mingled with and enters after ILD layer, IMD layer or the passivation layer, can directly be diffused into capacitor, or can be diffused into capacitor gradually.As a result, remanent polarization (P r) (as the ferroelectric properties of the ferroelectric material of capacitor dielectric layer a kind of) drops to critical level, thereby capacitor is undesired.
For example, be formed on the ferroelectric condenser on the semiconductor so that when forming the ild film of the silicon oxide layer on it when exposing during the ILD step, capacitor dielectric layer worsens.Promptly using plasma enhanced chemical vapor deposition (PECVD) formation to have in the ILD step of silicon oxide layer silane (SiH 4) and oxygen (O 2) as reacting gas, derive hydrogen ion as accessory substance.The hydrogen ion of deriving directly is diffused into the dielectric layer of ferroelectric condenser or is mingled with the ild film that the ILD step forms, thereby has worsened capacitor dielectric layer.As a result, the P of capacitor dielectric layer rValue drops to critical level, causes the degeneration of the ferroelectric properties of capacitor dielectric layer.The deterioration of the capacitor dielectric layer in the integrated step of semiconductor storage unit has more than and is defined in the ILD step, also takes place in the passivation step of IMD step that forms the IMD film and formation passivation layer thereof.
For addressing this problem, the technology of preparing of conventional semiconductors memory device adopts the method for single insulating barrier sealed capacitor.For example, U.S. patent No.5822175 discloses the method with silicon oxide layer, doped silicon oxide layer or silicon nitride layer sealed capacitor, so that prevent the deterioration of capacitor dielectric layer by the hydrogen diffusion.
Simultaneously, in forming capacitor, form after the capacitor dielectric layer at semiconductor-based the end, heat with crystallization under 600-800 ℃ the temperature under the oxygen atmosphere, thereby can improve its insulation property.In addition, form after the capacitor, heat-treat under 450-600 ℃ the temperature under the oxygen atmosphere, the damage that the dry etching steps that reparation is carried out during the formation capacitor causes, and the capacitor of stable gained.
Yet during heating treatment, oxygen is diffused into the contact embolism, and the contact embolism is electrically connected doped region for example source region and capacitor, thereby improves contact resistance.For example, under the situation that the contact embolism is formed by doped polycrystalline silicon, be diffused into the oxygen and the polysilicon reaction of contact embolism, thereby on the interface between contact embolism and the capacitor, form silicon oxide layer.As a result, contact resistance is elevated to the degree of the speed of service that reduces semiconductor storage unit.
Summary of the invention
For addressing the above problem, the purpose of this invention is to provide the semiconductor storage unit that has capacitor protective layer and be used to form the material layer of low resistance contact, capacitor protective layer can prevent the deterioration of capacitor dielectric layer by the diffusion of impurity.
Another object of the present invention provides the method for preparing semiconductor storage unit, and it guarantees the integrated capacitor protection of semiconductor device that carries out after forming capacitor.
For realizing first purpose of the present invention, comprise according to an embodiment of semiconductor storage unit of the present invention have bottom electrode, the capacitor of top electrode and the capacitor dielectric layer between lower and upper electrode.Sealant with sandwich construction also is provided.But the whole surface except that the part top electrode of sealant covering capacitor, and comprise barrier layer and the capacitor protective layer that forms by the different insulative material at least, wherein barrier layer is formed under the capacitor protective layer.Optionally, bottom electrode can be made up of silicon cobalt substrate.
Preferably, interlayer dielectric layer also is formed on the sealant, and Metal Contact forms with interlayer dielectric layer so that contact the part that the not sealed layer of top electrode covers through sealant.
Preferred sealant has double-decker, and except that the top electrode part that forms Metal Contact thereon, barrier layer can be the dielectric layer on the whole surface of covering capacitor, and capacitor protective layer can be the dielectric layer that covers the whole surface of barrier layer.Preferred barrier layer forms by preventing to be formed on the material layer under the barrier layer and the material layer of the reaction between the capacitor protective layer, and especially preferably barrier layer is by TiO 2Layer, Ta 2O 5Layer, BaTiO 3Layer, SrTiO 3Layer, Bi 4Ti 3O 12Layer or PbTiO 3Layer forms.
The preferred capacitor protective layer is made up of the material that the hydrogen that can prevent to be absorbed in interlayer dielectric layer is diffused into capacitor dielectric layer, and this interlayer dielectric layer is formed on the capacitor protective layer, and special preferred capacitor protective layer is by Al 2O 3Layer, TiO 2Layer, Ta 2O 5Layer, BaTiO 3Layer, SrTiO 3Layer, Bi 4Ti 3O 12Layer or PbTiO 3Layer forms.The material layer of preferred capacitor protective layer is different from the material layer of barrier layer.
Preferably, capacitor protective layer is the material layer that forms by atom layer deposition process.Barrier layer and capacitor protective layer all have the thickness of 50-1500 .
Semiconductor storage unit also comprises passivation layer and the interlayer dielectric layer on the Metal Contact.In addition, the hydrogen barrier layer alternative hinders hydrogen (being mixed in the passivation layer) and is diffused into capacitor dielectric layer between Metal Contact and passivation layer.Preferred hydrogen barrier layer is by Al 2O 3Layer, TiO 2Layer, Ta 2O 5Layer, BaTiO 3Layer, SrTiO 3Layer, Bi 4Ti 3O 12Layer or PbTiO 3Layer forms.
Preferably also comprise resilient coating between Metal Contact and hydrogen barrier layer according to semiconductor storage unit of the present invention.
According to semiconductor storage unit of the present invention also comprise under the capacitor the inter-level dielectric film and through the film formed conductive plug of inter-level dielectric.Conductive plug is electrically connected with the interlayer that capacitor lower electrode and silicon cobalt substrate are formed, and silicon cobalt substrate extends between capacitor lower electrode and conductive plug.
According to semiconductor storage unit of the present invention also comprise under the capacitor the inter-level dielectric film and through the film formed conductive plug of inter-level dielectric.Conductive plug can be electrically connected with capacitor lower electrode.Conductive plug can only be formed by silicon cobalt substrate or as the bilayer of conductive layer and silicon cobalt substrate.
Comprise according to another embodiment of semiconductor storage unit of the present invention have bottom electrode, the capacitor of top electrode and the capacitor dielectric layer between bottom electrode and top electrode.The whole surface of sealant with covering capacitor also is provided.Sealant can have and comprises the barrier layer be made up of the different insulative material and the sandwich construction of capacitor protective layer at least, and wherein barrier layer is formed under the capacitor protective layer.
Comprise according to the embodiment again of semiconductor storage unit of the present invention have bottom electrode, the capacitor of top electrode and the capacitor dielectric layer between bottom electrode and top electrode.Dielectric layer is formed on the capacitor.Metal Contact forms so that contact with top electrode through dielectric layer, and passivation layer forms on the Metal Contact.In this embodiment, hydrogen barrier layer is between Metal Contact and passivation layer.
For realizing second purpose of the present invention, an embodiment who prepares the method for semiconductor storage unit comprises the step that forms the capacitor with bottom electrode, top electrode and the capacitor dielectric layer between bottom electrode and top electrode.Also form sealant with sandwich construction, thus the whole surface except that the part top electrode of covering capacitor, sealant comprises barrier layer and the capacitor protective layer of being made up of the different insulative material at least, wherein barrier layer is formed under the capacitor protective layer.
Sealant with sandwich construction can comprise barrier layer and the capacitor protective layer of being made up of different materials.Barrier layer can be formed under the capacitor protective layer.For the double-layer seal layer, the whole surface of barrier layer covering capacitor, and capacitor covers barrier layer.
In according to semiconductor storage unit preparation method of the present invention, form after the barrier layer, can under 400-600 ℃ temperature, heat-treat process in the oxygen atmosphere.Barrier layer can be by preventing the reaction between lower floor and the capacitor protective layer and/or can preventing that the material of capacitor dielectric material volatilization from forming.Preferred barrier layer can be by TiO 2Layer, Ta 2O 5Layer, BaTiO 3Layer, SrTiO 3Layer, Bi 4Ti 3O 12Layer or PbTiO 3Layer forms.
Capacitor protective layer can be by stopping that the material layer that hydrogen is diffused into capacitor dielectric layer forms.The preferred capacitor protective layer can be by TiO 2Layer, Ta 2O 5Layer, Al 2O 3Layer, BaTiO 3Layer, SrTiO 3Layer, Bi 4Ti 3O 12Layer or PbTiO 3Layer forms.At this, capacitor protective layer is by forming with the different materials of the material that is used to form barrier layer.
In according to semiconductor storage unit preparation method of the present invention, form after the sealant, can carry out on the semiconductor-based end that forms interlayer dielectric layer on the sealant, contacts and have Metal Contact, forming the step of passivation layer through interlayer dielectric layer formation Metal Contact so that with top electrode.
Before forming passivation layer, hydrogen barrier layer can be formed on the whole surface at the semiconductor-based end.Preferred hydrogen barrier layer can be formed by metal oxide, more preferably by Al 2O 3Layer, TiO 2Layer, Ta 2O 5Layer, BaTiO 3Layer, SrTiO 3Layer, Bi 4Ti 3O 12Layer or PbTiO 3Layer forms.Preferably form hydrogen barrier layer by ald (ALD) technology.Preferred hydrogen barrier layer is stable material layer by the Technology for Heating Processing under 400-600 ℃ of temperature in oxygen atmosphere.
In another embodiment, be included in to form at semiconductor-based the end and be scheduled to semiconductor device and have the step that forms passivation layer at the semiconductor-based end of semiconductor device according to semiconductor storage unit preparation method of the present invention.Hydrogen barrier layer also can be formed on the whole surface at the semiconductor-based end before forming passivation layer.
A kind of integrated circuit (IC)-components also is provided in one embodiment of the invention, comprises: integrated-circuit capacitor structure, the capacitor dielectric layer that has bottom electrode, top electrode and between lower and upper electrode, extend; Sealant seals described integrated-circuit capacitor structure, and described sealant comprises at least the combination at barrier layer that extends on the capacitor dielectric layer and the capacitor protective layer on barrier layer, and wherein barrier layer is by from TiO 2, Ta 2O 5, BaTiO 3, SrTiO 3, Bi 4Ti 3O 12And PbTiO 3The material of selecting in the group that constitutes is formed, and capacitor protective layer is by Al 2O 3Form; And dielectric layer, be positioned on the described sealant.Preferably, the composition that described barrier layer stops capacitor dielectric layer is to outdiffusion and pass through, and described capacitor protective layer stops that hydrogen ion diffuses through.
Description of drawings
With reference to the accompanying drawings, by describing preferred embodiment in detail, can clearer above-mentioned purpose of the present invention and advantage.
Figure 1A is the profile of explanation according to first embodiment of semiconductor storage unit of the present invention;
Figure 1B is the profile of explanation according to second embodiment of semiconductor storage unit of the present invention;
Fig. 2 A-2E is the plane graph of 5 schematic construction of part explanation, and each has conductive plug, interlevel layer and capacitor, and can be used as parts and be included in according in the semiconductor storage unit of the present invention;
Fig. 3 A-3J is the plane graph of explanation according to first embodiment of preparation semiconductor storage unit method of the present invention;
Fig. 4 A and 4B are the plane graph of explanation according to second embodiment of preparation semiconductor storage unit method of the present invention;
Fig. 5 is the plane graph of explanation according to the 6th embodiment of preparation semiconductor storage unit method of the present invention;
Fig. 6 and 7 is relative to the sample C1 according to method of the present invention preparation, represents the figure of the leakage current performance of the hysteresis loop of capacitor dielectric layer of capacitor and capacitor respectively;
Fig. 8 and 9 is for preparing sample C2 and C3, the curve chart of expression hysteresis loop and barrier layer contact resistance according to the sample C1 of method preparation of the present invention and by distinct methods.
Embodiment
Be described in detail with reference to the attached drawings the present invention, wherein represent the preferred embodiments of the present invention to relate to semiconductor storage unit that has with multi-layer sealed capacitor and preparation method thereof.Yet the present invention can and not limit with multi-form embodiment and lists embodiment herein and constitute; And, provide these embodiment to make the disclosure thoroughly also fully, theory of the present invention is expressed to those skilled in the art.Among the figure, for the purpose of illustrating, exaggerated the thickness in layer and zone.Should be understood that also this shows when mentioning " one deck is in another layer or substrate ", this one deck can be directly in another layer or substrate, or also has the intermediate layer.In an embodiment of the present invention, described with reference to figure 1-Fig. 5, the capacitor of semiconductor storage unit forms with the capacitor on the bit line structure (COB).Yet the present invention also can be applicable to the situation that capacitor forms with the capacitor under the bit line structure (CUB).
Figure 1A is the profile of explanation according to the semiconductor memory device junction structure of the first embodiment of the present invention.With reference to Figure 1A, by silicon selective oxidation (LOCOS) technology, separator 101 is formed at semiconductor-based the end, defines the source region, and field-effect transistor (FET) T is formed on the active area.The separator 101 that defines the source region can form by trench isolation techniques.Field-effect transistor T comprises grid 102, source region 104 and drain region 106.The gate oxide layers of being made up of oxide 108 at grid 102 and at the semiconductor-based end 100.Simultaneously, sidewall spacers 110 is formed by the nitride layer on the sidewall of grid 102.
Whole surface with semiconductor-based end 100 of separator 101 and field-effect transistor T is covered by first inter-level dielectric (ILD) film 112, and second ild film 114 deposits on first ild film 112 once more.First and second ild films 112 and 114 can be borosilicate glass (BSG) layer, phosphosilicate glass (PSG) layer, boron phosphorus silicate glass (BPSG) layer, the former silane glass of tetraethoxy (TEOS), undoped silicate glass (USG) layer, ozone (O 3)-TEOS layer, plasma strengthen the composite bed of (PE)-TEOS layer or these layers.In addition, in first ild film 112, form landing embolism 116, and in second ild film 114, form bit line contact mat 118.And conductive plug 120 forms through first and second ild films 112 and 114.Although not shown, bit line contact mat 118 is electrically connected with the bit line (not shown), and the doped region that landing embolism 116 is electrically connected the semiconductor-based end 100 for example drain region 106 and bit line contact mat 118.Conductive plug 120 for example is connected in source region 104 with the capacitor C and the doped region at the semiconductor-based end 100 on being formed on second ild film 114.The capacitor C of semiconductor storage unit comprises bottom electrode 122, capacitor dielectric layer 124 and top electrode 126, and middle interlayer 128 is between the capacitor C and second ild film 114.
The ad hoc structure of conductive plug 120, middle interlayer 128 and capacitor C among Figure 1A, schematically illustrates conductive plug 120, boundary layer 128 and capacitor C, because can change respectively in according to semiconductor storage unit of the present invention.Below with reference to Fig. 2 A and 2E, the various structures of boundary layer 128 and capacitor C are described.
The sealant EL with sandwich construction that is used for capacitor for voltage protection C is formed on the whole surface (except that the part surface of top electrode 126) of capacitor C and the surface of second ild film 114.Simultaneously, the 3rd ild film 134 is formed on the sealant EL, and top electrode Metal Contact 136 is formed on the part surface of the top electrode 126 that not sealed layer EL cover.The 3rd ild film 134 can be bsg layer, PSG layer, bpsg layer, TEOS layer, USG layer, O 3The composite bed of-TEOS layer, PE-TEOS layer or these layers.
Expect that multi-layer sealed layer EL in capacitor for voltage protection, finishes following function.At first, sealant EL must be able to prevent the volatilization of capacitor dielectric layer 124.For example, when capacitor dielectric layer 124 when for example PZT, BST or PLZT layer are formed by ferroelectric layer, prevent that importantly oxygen atom from removing from capacitor dielectric layer 124.This is because the volatilization of capacitor dielectric layer 124 can make the mis-behave of capacitor C, thereby can degenerate the built-in function of store information by building up electric charge.Secondly, sealant EL should be able to stop that hydrogen is diffused into capacitor dielectric layer 124, and hydrogen is mixed near the material layer that forms the capacitor C for example the 3rd ild film 134.
Preferred sealant EL comprises the barrier layer and the capacitor protective layer of different insulative material composition at least.Capacitor protective layer works to prevent that hydrogen is diffused in the capacitor dielectric layer 124.Be formed on the volatilization that barrier layer under the capacitor protective layer prevents the reaction between capacitor protective layer and the material beneath layer and/or prevents capacitor dielectric layer.Barrier layer is different with the main effect of capacitor protective layer, but barrier layer and capacitor protective layer can be finished these protective effects jointly.
As for the sandwich construction of sealant EL, sealant EL can have following structure.For example, for three-layer sealed layer EL, can have the structure of barrier layer, resilient coating and capacitor protective layer order lamination.On the other hand, for double-layer seal layer EL, can have the structure of barrier layer and capacitor protective layer order lamination.The structure that should understand sealant EL does not limit material layer quantity double-deck and three-decker and formation sealant EL, and its structure can change.
In expression Figure 1A according to the structure of the semiconductor storage unit of first embodiment of the invention, sealant has double-decker.The surface (except that the part surface of top electrode 126) of barrier layer 130 direct covering capacitor C and the surface of the 2nd ILD layer 114.Simultaneously, capacitor protective layer 132 is formed directly on the barrier layer 130.
Consider the function of barrier layer 130, select to be used for the material layer of barrier layer 130.Preferred barrier layer 130 can be TiO 2Layer, Ta 2O 5Layer, BaTiO 3Layer, SrTiO 3Layer, Bi 4Ti 3O 12Layer or PbTiO 3Layer.At the material layer of selecting to be used for barrier layer 130, preferred not with the material layer of capacitor dielectric layer 124 reactions.Therefore, according to selected material layer type, be identified for the material layer type of barrier layer 130 so that form capacitor dielectric layer 124.For example, for example PZT, BST or PLZT layer are formed the TiO that barrier layer 130 can be formed by so-called sputtering technology if capacitor dielectric layer 124 is by ferroelectric layer 2The sputtered with Ti O of layer 2Layer is formed.Yet, selecting TiO 2Under the situation as the material of barrier layer 130, utilization comprises the kinds of processes of chemical vapor deposition (PECVD), ald (ALD) and laser ablation (LA) that chemical vapor deposition (CVD), low-pressure chemical vapor deposition (LPCVD), subatmospheric chemical vapor deposition (SACVD), plasma strengthen, can form barrier layer 130.Utilizing non-TiO 2The situation of other material as barrier layer 130 under, can adopt above-mentioned technology.In view of the physics and the chemical property of needed function and selected material as barrier layer 130, determine the thickness of barrier layer 130.The thickness of preferred barrier layer 130 is about 50-150 .Simultaneously, barrier layer 130 can be heat treatment and stablize the material layer of the required function of barrier layer 130 in the oxygen atmosphere under 400-600 ℃ of temperature.
In view of the function of capacitor protective layer 132, be identified for the material of capacitor protective layer 132.Preferred capacitor protective layer 132 can be TiO 2Layer, Ta 2O 5Layer, Al 2O 3Layer, BaTiO 3Layer, SrTiO 3Layer, Bi 4Ti 3O 12Layer or PbTiO 3Layer.At this,, can change the material layer type that is used for capacitor protective layer 132 according to selected material layer type as capacitor dielectric layer 124 and barrier layer 130.For example, be easy to be not suitable for capacitor protective layer 132 with the material layer of barrier layer 130 reactions.In addition, preferred capacitor protective layer 132 is made up of the material layer that is different from barrier layer 130.For example, when capacitor dielectric layer 124 by ferroelectric layer for example PZT, BST or PLZT layer form, and barrier layer 130 is by sputtered with Ti O 2When layer forms, the Al that preferred capacitor protective layer 132 is formed by so-called ALD technology 2O 3The ALD-Al of layer 2O 3Layer is formed, yet, selecting Al 2O 3Under the situation as the material of capacitor protective layer 132; utilization comprises the kinds of processes of chemical vapor deposition (PECVD), ald (ALD) and laser ablation (LA) that chemical vapor deposition (CVD), low-pressure chemical vapor deposition (LPCVD), subatmospheric chemical vapor deposition (SACVD), plasma strengthen, can form capacitor protective layer 132.Utilizing non-Al 2O 3The situation of other material under, above-mentioned technology can be applicable to capacitor protective layer 132.Capacitor protective layer 132 can be the material layer of the required function of heat treatment and stabilising condenser protective layer 132 in the oxygen atmosphere under the 400-600 ℃ of temperature.In view of needed function and the physics and the chemical property that form the selected material of capacitor protective layer, determine the thickness of capacitor protective layer 132.The thickness of preferred capacitor protective layer 132 is about 50-5000 , and more preferably thickness is about 50-1500 .
On top electrode Metal Contact 136 and the 3rd ild film 134, form passivation layer 138.Passivation layer 138 can be silicon oxide layer, silicon nitride layer or silicon oxynitride layer.The thickness of passivation layer 138 is about 2000-20000 .
For preventing that hydrogen is diffused among the capacitor C of semiconductor storage unit, hydrogen barrier layer 140 can alternately be formed between the 3rd ild film 134 and the passivation layer 138.It is identical with capacitor protective layer 132 that hydrogen barrier layer 140 plays a part basically.In other words, hydrogen barrier layer 140 stops that the hydrogen that is mixed in the passivation layer 138 is diffused in the capacitor through top electrode Metal Contact 136, thereby capacitor for voltage protection dielectric layer 124 is avoided the hydrogen impact.Preferred hydrogen barrier layer 140 can be Al 2O 3Layer, TiO 2Layer, Ta 2O 5Layer, BaTiO 3Layer, SrTiO 3Layer, Bi 4Ti 3O 12The composite bed of layer or these layers.More preferably ALD-Al 2O 3Layer is as hydrogen barrier layer 140, because its crystal structure is stable than other layer densification and have 100% step covering.Selecting Al 2O 3Under the situation as the material that forms hydrogen barrier layer 140, hydrogen barrier layer 140 can be CVD-Al 2O 3Layer, LPCVD-Al 2O 3Layer, SACVD-Al 2O 3Layer, PECVD-Al 2O 3Layer, sputter-Al 2O 3Layer or LA-Al 2O 3Layer.The thickness of preferred hydrogen barrier layer 140 is about 50-2000 , and more preferably thickness is about 200-300 .
Under a stable condition, hydrogen barrier layer 140 can be heat treatment and a stable material layer in the oxygen atmosphere under the 400-600 ℃ of temperature.Utilize stable material layer can improve the effect of hydrogen diffusion barrier as hydrogen barrier layer 140.
Although not shown, resilient coating can be between hydrogen barrier layer 140 and the 3rd ILD layer 134.For example, resilient coating can be the oxide skin(coating) of APCVD technology (atmospheric pressure cvd) formation or the oxide skin(coating) that pecvd process forms.At resilient coating is under the situation of the oxide skin(coating) that forms of APCVD technology, can be O 3-TEOS layer, PSG layer or bpsg layer.Simultaneously, be under the situation of the oxide skin(coating) that forms of pecvd process at resilient coating, can be PE-TEOS layer or PE-SiH 4Layer.Preferred buffer layer thickness is about 50-1000 .
Figure 1B has illustrated the structure according to the semiconductor storage unit of second embodiment of the invention.Be formed on landing embolism 116 on separator 101 at the semiconductor-based end 100, field-effect transistor T, first ild film 112, second ild film 114, first ild film 112, the bit line contact mat 118 on second ild film 114, the structure with Figure 1A is identical basically through first and second ild film 112 and 114 conductive plugs 120 that form.
With reference to Figure 1B, the conductive plug 120 of semiconductor storage unit and capacitor C are electrically connected, and middle interlayer 128 is therebetween.Capacitor C comprises bottom electrode 122, capacitor dielectric layer 124 and top electrode 126.On the bottom electrode 122 of capacitor C and capacitor dielectric layer 124 and the 3rd ild film 134, diffusion barrier spacer 142 is between the sidewall and the 3rd ild film 134 of capacitor dielectric layer 124.
Conductive plug 120, boundary layer 128 and capacitor C according to the semiconductor storage unit of second embodiment of the invention can realize with various structures, as the semiconductor storage unit of first embodiment of Figure 1A.Below with reference to Fig. 2 A-2E these structures will be described.
Preferred diffusion stops that at interval 142 material layers that are diffused in the capacitor dielectric layer 124 by the hydrogen that can prevent to be mixed in the 3rd ild film form.Preferred diffusion stops that interval 142 can be Al 2O 3Layer, TiO 2Layer, Ta 2O 5Layer, BaTiO 3Layer, SrTiO 3Layer, Bi 4Ti 3O 12Layer, PbTiO 3The composite bed of layer or these layers, more preferably diffusion barrier spacer 142 is ALD-Al 2O 3Layer.When forming non-Al 2O 3The material layer of layer preferably adopts the ALD technology during as diffusion barrier spacer 142.
Sealant EL with sandwich construction covers the part surface and the sidewall of the top electrode 126 of the part surface of the surface of the 3rd ild film 134, capacitor dielectric layer 124 and capacitor C.
For the first embodiment of the present invention, the sealant EL of the semiconductor storage unit of second embodiment also has the double-decker that comprises barrier layer 130 and capacitor protective layer 132.The 4th ild film 144 is formed on the sealant EL, and top electrode Metal Contact 136 forms through the 4th ild film 144 and sealant EL.In addition, passivation layer 138 is formed on the 4th ild film 144 and the top electrode Metal Contact 136.The 3rd ild film 134 and the 4th ild film 144 are basically by forming with first ild film, 112 identical materials layers.The material layer type that is used for passivation layer 138 was described at the semiconductor storage unit according to first embodiment of the invention, did not therefore repeat this description.
As for first embodiment according to semiconductor storage unit of the present invention, hydrogen barrier layer 140 can be used for more effective capacitor for voltage protection C and suffer the diffusion of hydrogen alternately between the 4th ild film 144 and passivation layer 138.The material layer type and the thickness thereof that are used for hydrogen barrier layer 140 were described at the semiconductor storage unit according to first embodiment of the invention, did not therefore repeat this description.
For first embodiment of semiconductor storage unit, the resilient coating (not shown) can alternately be formed between diffusion barrier 140 and the 4th ild film 144.The material layer type and the thickness thereof that are used for resilient coating were described at the semiconductor storage unit according to first embodiment of the invention, did not therefore repeat this description.
As mentioned above, in Figure 1A and 1B, schematically illustrate conductive plug 120, boundary layer 128 and capacitor C.Therefore, the preferred embodiment of conductive plug 120 structures hereinafter will be described boundary layer 128 and capacitor C in detail with reference to figure 2A-2E relatively.The described conductive plug 120 of Fig. 2 A, boundary layer 128 and capacitor C are defined in the zone shown in the R of Figure 1A and 1B, thereby the side profile of capacitor C is not considered.The following various structures of conductive plug 120, boundary layer 128 and capacitor can be adopted by the semiconductor storage unit shown in Figure 1A and the 1B respectively.
Fig. 2 A explanation is included in conductive plug 120, boundary layer 128 and the capacitor C according to first embodiment in the semiconductor storage unit of the present invention.With reference to figure 2A, second and first ild film 114 and 112 and form of the conductive plug 120a that contacts with the source region 104 at for example semiconductor-based end 100 of doped region on the semiconductor-based end 100.Conductive plug 120a comprises embolism 200 and last embolism 202 down.Preferred embolism 200 is down formed by low-resistance electric conducting material, is made up of electric conducting material anti-oxidant and that have a thermally-stabilised film resistor and preferably go up embolism 202.Preferred embolism 200 down can be a doped polysilicon layer, is silicon cobalt substrates and go up embolism 202.Last embolism 200 can be by the composite bed of doped polysilicon layer, tungsten (W) layer, tantalum (Ta) layer, ruthenium (Ru) layer, iridium (Ir) layer, platinum (Pt) layer, osmium (Os) layer, tungsten silicide layer, tungsten nitride layer or these layers.Last embolism 202 can be formed by nickel silicide layer, titanium silicide, silication tantalum layer, chromium silicide layer or hafnium suicide (Hf) layer.The thickness of last embolism 202 is about 50-1000 , and more preferably thickness is about 300-500 .
Wherein the boundary layer 128a of adhesive layer 204 and diffusion barrier 206 order laminations is formed on second ild film 114.In addition, wherein the capacitor lower electrode 122a of metal oxide layer 208 and heat resistant metal layer 210 order laminations is formed on the boundary layer 128a.Simultaneously, capacitor dielectric layer 124a and capacitor top electrode 126a are formed on the capacitor lower electrode 122a in proper order.Preferred adhesive layer 204 can by can improve diffusion barrier 206 with its down surface layer be that bonding material layer between second ild film 114 is formed.Therefore, preferred adhesive layer 204 is made up of transition metal layer.Diffusion barrier 206 can be formed by the material layer and the conductive plug 120a that can make metal oxide layer 208 and be formed on the reaction minimum between the material layer on the metal oxide layer 208.Therefore, preferred diffusion barrier layer 206 is formed by transition metal nitride layer or layer of precious metal.For example, preferred Ti layer is as adhesive layer, and the thickness range of adhesive layer 204 is 20-150 , more preferably 50 .In addition, the transition metal nitride layer that is used for diffusion barrier 206 can be formed by the TiN layer, and the layer of precious metal that is used for diffusion barrier 206 can be Ir layer and Ru layer.The thickness of preferred diffusion barrier layer 206 is about 500-1500 , and more preferably thickness is about 1000 .Although introduce Ti layer and TiN layer, Ir layer and Ru layer in the present embodiment respectively as being used for the material layer of adhesive layer 204 with diffusion barrier 206, one skilled in the art should appreciate that the material layer that is used for adhesive layer 204 and diffusion barrier 206 is not limited to the above-mentioned material layer, any suitable material goes for adhesive layer 204 and diffusion barrier 206.
When the oxygen among the capacitor dielectric layer 124a was removed, preferable alloy oxide skin(coating) 208 be by providing oxygen to form to the material layer of the capacitor dielectric layer 124a on the bottom electrode 122a, thereby prevented the deterioration of the dielectric behavior of capacitor dielectric layer.More preferably metal oxide layer 208 is by IrO 2Layer is formed.Metal oxide layer 208 can be by IrO 2Layer, RuO 2Layer, LaSrCoO 3Layer, (Ca, Sr) RuO 3The composite bed of layer or these layers is formed.According to the material layer that forms metal oxide layer, change the thickness of metal oxide layer 208.Yet the thickness of preferable alloy oxide skin(coating) is about 200-800 .For example, if select IrO 2Layer can form the metal oxide layer 208 of about 500 of thickness as the material layer of metal oxide layer 208.
Preferred heat resistant metal layer 210 is made up of the material layer that relative capacitor dielectric layer 124a has the good interface performance.Heat resistant metal layer 210 can be made up of the Pt layer.Preferred heat resistant metal layer 210 can be made up of the composite bed of Pt layer, Ir layer, Ru layer, Rh layer, Os layer, protactinium (Pa) layer or these layers.Material layer according to forming heat resistant metal layer changes heat-resisting 210 thickness.Yet the thickness of preferred heat resistant metal layer 210 is about 1000-2000 .For example, if select the material layer of Pt layer, can form the heat resistant metal layer 210 of about 1500 of thickness as heat resistant metal layer 210.
For the capacitor C1 of high power capacity, capacitor dielectric layer 124a can be by TiO 2Layer, SiO 2Layer, Ta 2O 5Layer, Al 2O 3Layer, SiO 2/ SiN layer, BaTiO 3Layer, SrTiO 3Layer, (Ba, Sr) TiO 3Layer, Bi 4Ti 3O 12Layer, PbTiO 3Layer, PZT (Pb, La) (Zr, TiO 3) layer, (SrBi 2Ta 2O 3) (SBT) layer or the composite bed of these layers constitute.
Capacitor top electrode 126a can be the composite bed of heat resistant metal layer, metal oxide layer or these layers.Be preferably formed and have double-deck capacitor top electrode 126a, wherein order lamination metal oxide layer 212 and heat resistant metal layer 214.Preferable alloy oxide skin(coating) 212 is IrO 2Layer, and heat resistant metal layer 214 is Ir layers.Metal oxide layer 212 can be IrO 2Layer, RuO 2Layer, IrO 2Layer, (Ca, Sr) RuO 2Layer, LaSrCoO 3The composite bed of layer or these layers.Heat resistant metal layer 214 can be the composite bed of Pt layer, Ir layer, Ru layer, Rh layer, Os layer, Pd layer or these layers.126a has the IrO of comprising in capacitor top electrode 2Under the double-deck situation of layer and Ir layer, form the IrO of the about 100-1000 of thickness 2The Ir layer of layer and the about 400-2000 of thickness.
As mentioned above, embolism 202 on the conductive plug 120a by the situation that for example silicon cobalt substrate is formed of the material layer with thermally-stabilised film resistor under, contact resistance between capacitor C1 and the conductive plug 120 reduces, thereby improves the speed of service of semiconductor storage unit.
Fig. 2 B has illustrated conductive plug 120, boundary layer 128 and the capacitor C that can be included in according to second embodiment in the semiconductor storage unit of the present invention.With reference to figure 2B, with doped region for example second and first ild film 114 and 112 of the conductive plug 120b that contacts of source region 104 on the semiconductor-based end 100 form.Opposite with the contact embolism 120a shown in Fig. 2 A, the conductive plug 120b of Fig. 2 B is formed by single material layer.Preferred conductive plug 120b is formed by electric conducting material anti-oxidant and that have a thermally-stabilised film resistor.For example, conductive plug 120b can be formed by silicon cobalt substrate.Various material layers can be used as conductive plug 120b, comprise for example nickel silicide layer, titanium silicide layer, silication tantalum layer, silication hafnium layer and chromium silicide layer.
The boundary layer 128b of order lamination adhesive layer 216 and diffusion barrier 218 is formed on the conductive plug 120b.In addition, the capacitor lower electrode 122b of order lamination metal oxide layer 220 and heat resistant metal layer 222 is formed on the boundary layer 128b.And capacitor dielectric layer 124b and capacitor top electrode 126b are formed on the capacitor lower electrode 126b in proper order.The structure that is used for the material layer type of adhesive layer 216, diffusion barrier 218, metal oxide layer 220, heat resistant metal layer 222, capacitor dielectric layer 124b and capacitor top electrode 126b and these layers is identical with the structure shown in Fig. 2 A basically with thickness.
As conductive plug 120b when for example silicon cobalt substrate forms by the material layer with thermally-stabilised film resistor, the contact resistance between capacitor C2 and the conductive plug 120b can reduce, thereby improves the speed of service of semiconductor storage unit.
Fig. 2 C has illustrated conductive plug 120, boundary layer 128 and the capacitor C that can be included in according to the 3rd embodiment in the semiconductor storage unit of the present invention.With reference to figure 2C, second and first ild film 114 and 112 of conductive plug 120c on the semiconductor-based end 100 with single layer structure forms.Conductive plug 120a for example contacts in the source region 104 at the semiconductor-based end with doped region.Conductive plug 120c can be formed by following embolism 200 same materials of Fig. 2 A basically.For example, conductive plug 120c can be made up of doped polycrystalline silicon.The boundary layer of order lamination conductive layer 224, silicide layer 226 and diffusion barrier 228 is formed on the conductive plug 120c and second ild film 114.Conductive layer 224 material layer with the following embolism 200 of Fig. 2 A basically is identical.For example, conductive layer 224 can be formed by doped polycrystalline silicon.The thickness of preferred conductive layer 224 is about 3000-10000 .In addition, preferred silicide layer 226 is silicon cobalt substrates, and thickness is about 300-500 .Diffusion barrier 228 is basically by forming with the same material of the diffusion barrier 206 of Fig. 2 A.For example, diffusion barrier 228 can be the Ir layer, and thickness is about 300-1500 .
In addition, the capacitor lower electrode 122c of order lamination metal oxide layer 230 and heat resistant metal layer 232 is formed on the boundary layer 128c.Capacitor dielectric layer 124c and capacitor top electrode 126c are formed on the capacitor lower electrode 122c in proper order.The structure that is used for the material layer type of metal oxide layer 230, heat resistant metal layer 232, capacitor dielectric layer 124c and capacitor top electrode 126c and these layers is identical with the structure shown in Fig. 2 A basically with thickness.
As mentioned above, heat-resisting and silicide layer 226 with thermally-stabilised film resistor for example silicon cobalt substrate be included under the situation among the boundary layer 128c, contact resistance between capacitor C3 and the conductive plug 210c can reduce, thereby improves the speed of service of semiconductor storage unit.
Fig. 2 D has illustrated conductive plug 120, boundary layer 128 and the capacitor C that can be included in according to the 4th embodiment in the semiconductor storage unit of the present invention.With reference to figure 2D, second and first ild film 114 and 112 of conductive plug 120d on the semiconductor-based end 100 with single layer structure forms.Conductive plug 120d contacts with the source region 104 at for example semiconductor-based end 100 of doped region.In addition, the boundary layer 128d as conductive layer is formed on the conductive plug 120d and second ild film 114.Conductive plug 120d and boundary layer 128d can be formed by following embolism 200 same materials with Fig. 2 A basically.For example, conductive plug 120d and boundary layer 128d can be made up of doped polycrystalline silicon.Interfacial layer 128d can be formed by conductive layer, has the thickness of about 3000-10000 .Capacitor lower electrode 122d is formed on the boundary layer 128d with conductive material layer, and conductive material layer is heat-resisting and have a thermally-stabilised film resistor.Capacitor dielectric layer 124d and capacitor top electrode 126d are stacked on the capacitor lower electrode 122d in proper order.Capacitor lower electrode 122d can be basically by forming with the same material of the last embolism 202 of Fig. 2 A, for example, capacitor lower electrode 122d can be a silicon cobalt substrate and thickness is about 500-3000 .The capacitor dielectric layer 124a with Fig. 2 A is identical with capacitor top electrode 126a basically with thickness to be used for the material type of capacitor dielectric layer 124d and capacitor top electrode 126d and structure thereof.
As mentioned above, at capacitor lower electrode 122d by heat-resisting and have under the conductive material layer situation that for example silicon cobalt substrate is formed of thermally-stabilised film resistor, contact resistance between capacitor C4 and the conductive plug 120d can reduce, thereby improves the speed of service of semiconductor storage unit.
Fig. 2 E has illustrated conductive plug 120, boundary layer 128 and the capacitor C that can be included in according to the 5th embodiment in the semiconductor storage unit of the present invention.With reference to figure 2E, second and first ild film 114 and 112 of conductive plug 120e on the semiconductor-based end 100 with single layer structure forms.Conductive plug 120e contacts with the source region 104 at for example semiconductor-based end 100 of doped region.Conductive plug 120e can be formed by following embolism 200 same materials of Fig. 2 A basically.For example, conductive plug 120e can be made up of doped polycrystalline silicon.In addition, the boundary layer 128e of order lamination silicide layer 232 and diffusion barrier 234 is formed on the conductive plug 120e and second ild film 114.Silicide layer 232 can be basically by forming with last embolism 202 same materials of Fig. 2 A.For example, silicide layer 232 can be a silicon cobalt substrate, and thickness is about 50-1000 .Diffusion barrier 234 is basically by forming with the same material of the diffusion barrier 206 of Fig. 2 A.For example, diffusion barrier 234 can be made up of the Ir layer.
In addition, the capacitor lower electrode 122e of order lamination metal oxide layer 236 and heat resistant metal layer 238 is formed on the boundary layer 128e.Capacitor dielectric layer 124e and capacitor top electrode 126e are formed on the capacitor lower electrode 122e in proper order.The structure that is used for the material layer type of metal oxide layer 236, heat resistant metal layer 238, capacitor dielectric layer 124e and capacitor top electrode 126e and these layers is identical with the structure shown in Fig. 2 A basically with thickness.
As mentioned above, heat-resisting and silicide layer 232 with thermally-stabilised film resistor for example silicon cobalt substrate be included under the situation among the boundary layer 128e, contact resistance between capacitor C5 and the conductive plug 210e can reduce, thereby improves the speed of service of semiconductor storage unit.
With reference to the accompanying drawings, hereinafter will describe preferred embodiment in detail according to semiconductor storage unit preparation method of the present invention.
Fig. 3 A-3J is the profile of explanation according to the semiconductor storage unit preparation technology of first embodiment of the invention.With reference to figure 3A, separator 302 is formed on so that define the source region at semiconductor-based the end 300, and transistor T is formed on the active area.By general technology for example LOCOS technology form separator 302.Trench isolation techniques can be used for the formation of separator 302, so that define the source region.Transistor T can be the field-effect transistor (FET) with grid 308 and drain region 310 and source region 312, and grid 308 has spaced walls 304 and is formed on the gate insulation layer 306 at the semiconductor-based end 300 at its sidewall.
Then, landing embolism 314 and bit line contact mat 316 form by common process.Especially first ild film 318 is formed on the structure with transistor T, and the embolism 314 that lands then forms through first ild film 318, thereby contacts with the drain region 310 of transistor T.In other words, opening 315 forms exposing for example drain region 310 of doped region by photoetching process, and opening 315 by conductive layer for example doped polysilicon layer fill.Form bit line contact mat 316 then on landing embolism 314, for the formation of bit line contact mat 316, conductive layer for example doped polysilicon layer deposits on first ild film 318, and is patterned into bit line contact mat 316 by photoetching process.Afterwards, second ild film 320 is formed on the bit line contact mat 316.
Various material layers can be used as first ild film 318 and second ild film 320, comprise for example silicon oxide layer, silicon oxynitride layer, bsg layer, PSG layer, bpsg layer, TEOS layer, O 3The composite bed of-TEOS layer, PE-TEOS layer, USG layer and these layers.For example CVD, LPCVD or pecvd process can form first and second ild films 318 and 320 by general technology.
Then, the contact hole 322 in the source region 312 of exposed transistor T forms through first and second ild films 318 and 320 by photoetching process.
With reference to figure 3B, utilize general technology can use conductive layer filling contact hole 322, form conductive plug 324.For example, utilize the sputtering technology conductive layer deposition on the whole surface at the semiconductor-based end 300 and utilize chemico-mechanical polishing (CMP) or dark etching technique to make it into plane 54, until the surface that exposes second ild film 320.Conductive plug 324 can be made up of doped polysilicon layer.More preferably conductive plug 324 is made up of the composite bed of doped polysilicon layer, W layer, Ta layer, Ru layer, Ir layer, Os layer, Pt layer, tungsten silicide layer, silicon cobalt substrate, tungsten nitride layer or these layers.
After contact hole 322 forms conductive plug 324, pre-clean process is carried out on the whole surface of semiconductor substrate 300, remove the natural oxide layer on the conductive plug 324 afterwards.For example, when conductive plug 324 is made up of doped polycrystalline silicon, transport the semiconductor-based end 300 during the operation subsequently or during the precleaning conductive plug 324 polluted by the natural oxide layer.Therefore, because the contact resistance of the semiconductor storage unit that natural oxide causes improves, must remove the natural oxide layer before the operation subsequently for preventing.
Especially after precleaning, by under the dried state with characteristic frequency for example the radio frequency of 13.56MHz (RF) impose on the whole surface at the semiconductor-based end 300, but clean semiconductor substrate 300, thereby the natural oxide layer is got rid of from conductive plug 324.Can finish the RF cleaning procedure by the whole bag of tricks.Yet, preferably utilize the argon ion (Ar+) that quicken in the forceful electric power place in the sputtering equipment, finish cleaning procedure.
Utilizing after above-mentioned clean method removes the natural oxide layer that is formed on the conductive plug 324, for example sputter or CVD method order on the whole surface at the semiconductor-based end 300 form dystectic high melting metal layer 326 and complanation layer 328 by ordinary skill.When conductive plug 324 is made up of doped polysilicon layer, be preferably formed the material layer of high melting metal layer 326, this material layer is showing the good diffusion towards conductive plug 324 during the silicidation subsequently, and has the stable for example low film resistor of high temperature resistance performance after silicidation changes silicide layer into subsequently.Therefore, be preferably formed the high melting metal layer 326 of cobalt layer.High melting metal layer 326 can be made up of Ni layer, Ti layer, Ta layer, Hf layer or Cr layer.When conductive plug 324 was formed by doped polycrystalline silicon, high melting metal layer 326 served as the source material of silicidation subsequently.Therefore, in view of the formed silicide layer thickness of silicidation subsequently, be preferably formed the high melting metal layer 326 of adequate thickness.The thickness of high melting metal layer 326 is about 50-200 , and more preferably thickness is about 130 .
The effect of complanation layer 328 is to prevent that high melting metal layer 326 from becoming coarse during the silicidation subsequently, avoided subsequently silicidation during oxygen be diffused in the conductive plug 324 through high melting metal layer 326.For this reason, complanation layer 328 can be made up of the TiN layer.Be preferably formed the complanation layer 328 of the about 50-150 of thickness, more preferably about 100 of thickness.
Prepare required step number for reducing semiconductor storage unit, preferably the original position in same equipment is finished the step of RF cleaning, formation high melting metal layer 326 and formation complanation layer 328.
With reference to figure 3C, form after high melting metal layer 326 shown in Fig. 3 B and the complanation layer 328, heat-treat technology, between high melting metal layer 326 and conductive plug 324, cause silication.Preferably heat-treat technology by rapid thermal treatment (RTP) pattern.For example,, under 400-1000 ℃ of temperature, carry out rapid thermal treatment in the nitrogen atmosphere, more preferably descended about 90 seconds at about 480 ℃ for the silication of conductive plug 324.Can change the quick heat treatment duration according to the desirable thickness of silicide layer.During Technology for Heating Processing, the atom that constitutes high melting metal layer 326 for example the Co atom with estimated rate continuously with the atom that constitutes conductive plug 324 Si atomic reaction for example.After Technology for Heating Processing, oxidation resistant refractory metal silicide layer is formed on the top of conductive plug 324.
After silicidation, remove complanation layer 328 (referring to Fig. 3 B) and be not transformed into the part of the high melting metal layer 326 (referring to Fig. 3 B) of silicide layer by wet etch techniques.For example, utilize the solution that contains phosphoric acid and nitric acid can remove the non-silicification part of complanation layer 328 and high melting metal layer 326.Afterwards, resulting structure can make stable reaction greater than 650 ℃ of following rapid thermal treatment once.About 30 seconds of the rapid thermal treatment that for example, can under nitrogen atmosphere, be used for stable reaction.
As for the result of silicidation, the following embolism of forming by conductive layer 330 and be formed in the contact hole 322 by the last embolism 332 that refractory metal silicide layer is formed, conductive layer keeps the material that constitutes conductive plug 324.For example, be made up of doped polysilicon layer when conductive plug 324, the following embolism 330 of doped polysilicon layer and the last embolism 332 of silicon cobalt substrate are formed in the contact hole 330.
The silicide layer for example last embolism 332 of silicon cobalt substrate can be used as ohmic contact layer, forms silicide layer through above-mentioned series of steps on the top of conductive plug 324.The preferred about 30-1000 of thickness that goes up embolism 332.
With reference to figure 3D, boundary layer 334 is formed on the embolism 332 and second ild film 320.Although do not describe in detail, by sequential aggradation adhesive layer and diffusion barrier on the last embolism 332 and second ild film 320, can form boundary layer 334.
Adhesive layer is made up of material layer and diffusion barrier, and material layer can improve bonding between the last embolism 332 and second ild film 320.For this reason, adhesive layer can by transition metal layer for example the Ti layer form.According to forming the selected material layer of adhesive layer, can change the thickness of adhesive layer, be preferably formed the adhesive layer of the about 10-200 of thickness.If select the Ti layer as adhesive layer, can form the adhesive layer of about 50 of thickness.
The effect of diffusion barrier is to prevent to be formed on during operation subsequently material layer on the boundary layer 334 and the reaction between the conductive plug 324 under the boundary layer 334, and the deterioration of the conductive plug 324 that causes owing to the oxygen diffusion during the technology subsequently under oxygen atmosphere.The preferred diffusion barrier layer is made up of suitable these materials with function layers.For example, diffusion barrier can be made up of the Ir layer.The preferred diffusion barrier layer is made up of Ti layer, Ta layer, W layer, Ni layer, Cr layer, Ir layer, Ru layer, nitride, boride, carbide or silicide layer or these composite bed.In addition, diffusion barrier can be made up of Ti-Si-N series layer, Ti-B-N series layer, Ta-Si-N series layer, Ta-B-N series layer, Ta-Al-N series layer, W-B-N series layer, W-Si-N series layer, Ti-Al series layer or Ta-Al series layer.According to forming the selected material layer of diffusion barrier, can change the thickness of diffusion barrier, be preferably formed the diffusion barrier of the about 40-1800 of thickness.If select the Ir layer as diffusion barrier, can form the diffusion barrier of about 1100 of thickness.
After forming boundary layer 334, lower conductiving layer 336 is formed on the boundary layer 334.Preferably sequential aggradation metal oxide layer and heat resistant metal layer on boundary layer 334 form lower conductiving layer 336.
When removing the dielectric layer 338 of oxygen atom from lower conductiving layer 336, the preferable alloy oxide skin(coating) is by having conductance and the material layer of oxygen supply dielectric layer 338 can being formed.For this effect, metal oxide layer can be by IrO 2Layer is formed.Various material layers can be used as metal oxide layer, comprises for example IrO 2Layer, RuO 2Layer, (Ca, Sr) RuO 3The composite bed of layer and these layers.Utilization comprises the kinds of processes of CVD technology, ALD technology, PVD technology and LA technology, can form metal oxide layer.Yet,, can change the method that is suitable for forming metal oxide layer according to forming the selected material layer of metal oxide layer.If select IrO 2Layer can use sputtering technology so that form metal oxide layer as the material layer of metal oxide layer.In addition, the about 100-1000 of the thickness of metal oxide layer.If select IrO 2Layer can form the metal oxide layer of about 500 of thickness as the material layer of metal oxide layer.
Heat-treat technology after being preferably formed metal oxide layer, so that the crystallization metal oxide layer.According to forming the selected material layer of metal oxide layer, change heat treatment temperature.If select IrO 2Layer is as metal oxide layer, and metal oxide layer can be 600 ℃ of heating down.
Preferred heat resistant metal layer can be by having the crystal growth of inducing dielectric layer 338 and the material layer of the uniform ability of crystal growth being formed, and dielectric layer 338 is formed on the lower conductiving layer 336 later.For this reason, preferred heat resistant metal layer is made up of the Pt layer.Yet heat resistant metal layer can be made up of the composite bed of Pt layer, Ir layer, Ru layer, Rh layer, Os layer, Pd layer or these layers.For the formation of heat resistant metal layer, can adopt CVD, PVD, AD, sputter or LA.If select the material layer of Pt layer, preferably use sputtering method to form heat resistant metal layer as heat resistant metal layer.According to forming the selected material layer of heat resistant metal layer, change the thickness of heat resistant metal layer, the about 400-2500 of thickness of preferred heat resistant metal layer.For example, selecting to form the heat resistant metal layer of about 1500 of thickness under the situation of Pt layer as heat resistant metal layer.
After forming lower conductiving layer 336, dielectric layer 338 is formed on the lower conductiving layer 336.Dielectric layer 338 can be by TiO 2Layer, Ta 2O 5Layer, Al 2O 3Layer, BaTiO 3Layer, SrTiO 3Layer, Bi 4Ti 3O 12Layer, PbTiO 3Layer, SiO 2Layer, SiN layer, (Ba, Si) TiO 3Layer, (Pb, La) (Zr, Ti) O 3Layer, Pb (Zr, Ti) O 3Layer, (SrBi 2Ta 2O 3) layer or the composite bed of these layers form.For the electric capacity of the capacitor that forms in the further raising later step, dielectric layer 338 can be formed by ferroelectric material layer.For example, dielectric layer 338 can be the composite bed of PZT layer, BST layer, PLZT layer or these layers.According to forming dielectric layer 338 selected material layers, change the method that formation dielectric layer 338 is adopted.Preferable medium layer 338 can utilize sol-gel process to be made up of the PZT layer.In addition, according to forming the selected material layer of dielectric layer, change the thickness of dielectric layer 338, the about 500-2000 of the thickness of preferable medium layer 338.Selecting to form the dielectric layer 338 of about 2000 of thickness under the situation of PZT layer as dielectric layer 338.
Formed dielectric layer 338 is heat-treated in 600-900 ℃ of following oxygen atmosphere.Under the situation of selection PZT layer, can under about 750 ℃, heat-treat dielectric layer 338 as dielectric layer 338.Technology for Heating Processing makes the quality densification of dielectric layer 338, thereby improves the electric capacity of capacitor and improve the leakage current performance.Simultaneously, because heat-treat technology at oxygen atmosphere, oxygen can be diffused in the conductive plug 324.Yet, since have diffusion barrier boundary layer 324 and by refractory metal silicide layer for example the last embolism 332 formed of silicon cobalt substrate on conductive plug 324, prevented that oxygen is diffused into down in the embolism 330.
After forming dielectric layer 338, last conductive layer 340 is formed on the dielectric layer 338.Various material layers can be used as conductive layer 340, comprises for example composite bed of heat resistant metal layer, metal oxide layer and these layers.At this, metal level can comprise Pt layer, Ir layer, Rh layer, Os layer or Pd layer, and metal oxide layer can be RuO 2Layer, IrO 2Layer, (Ca, Sr) RuO 3Layer and LaSrCoO 3Layer.The preferred conductive layer 340 of going up has and comprises order lamination IrO 2The double-decker of layer and Ir layer.At oxygen atom when dielectric layer 338 is deviate from, IrO 2Layer also provides oxygen to dielectric layer 338.Certainly, go up the selected material layer of conductive layer, can change the thickness of going up conductive layer 340, preferably go up the about 500-3000 of thickness of conductive layer 340 according to forming.The double-decker of selecting metal oxide layer and heat resistant metal layer order lamination wherein as under the situation of structure of conductive layer 340, the thickness of metal oxide layer is about 100-1000 , and forms the heat resistant metal layer of the about 400-2000 of thickness.Selecting to comprise IrO 2Under the situation of double-decker as the structure of last conductive layer 340 of layer and Ir layer, can form the IrO of about 300 of thickness 2Layer, and the Ir layer of about 1200 of formation thickness.
With reference to figure 3E,, form boundary layer composition 334 ＇, capacitor lower electrode 336 ＇, capacitor dielectric layer 338 ＇ and capacitor top electrode 340 ＇ respectively by boundary layer 334, lower conductiving layer 336, dielectric layer 338 and the upper electrode layer 340 of composition Fig. 3 D.Can carry out the composition of capacitor C with one or two or more lithography steps.The composition that relates to two lithography steps forms capacitor C, at first last conductive layer 340 is carried out composition, forms top electrode 340 ＇.Then, dielectric layer 338, lower conductiving layer 336 and boundary layer 334 are carried out composition, form capacitor dielectric layer 338 ＇, capacitor lower electrode 336 ＇ and boundary layer composition 334 ＇.The composition that relates to three lithography steps forms capacitor C, can pass through independent lithography step, and last conductive layer 340, dielectric layer 338 and lower conductiving layer 336 and boundary layer 334 are carried out composition.On the other hand, can carry out composition to last conductive layer 340 and dielectric layer 338 by independent lithography step, and can carry out composition simultaneously to lower conductiving layer 336 and boundary layer by another lithography step.
With reference to figure 3F and 3G, compare with the capacitor C shown in Fig. 3 E, if carry out two or three lithography steps to form capacitor C, capacitor C can have the sidewall profile that rank are advanced.Two resulting capacitor C of lithography step are carried out in Fig. 3 F explanation, and three resulting capacitor C of lithography step of Fig. 3 G explanation carrying out.
After the formation of finishing capacitor C, preferably structure is carried out the Technology for Heating Processing in the oxygen atmosphere under about 450-600 ℃ temperature.Technology for Heating Processing stabilising condenser C and repair carries out forming during the etch process damage of the capacitor C that capacitor C causes.Especially select in addition 900 ℃ of temperature under have a stable film resistor silicon cobalt substrate as conductive plug 324 under the situation of embolism 332, contact resistance during can effectively avoiding carrying out high-temperature heat treatment process under 600 ℃ or higher temperature between capacitor C and the following embolism 330 worsens, after metal oxide layer that forms lower conductiving layer 336 and dielectric layer 338 or after the formation capacitor C, carry out high-temperature heat treatment process.
As above, in case form capacitor C, capacitor C is carried out ILD processing, IMD processing and Passivation Treatment.Yet these technologies can make the dielectric behavior of capacitor dielectric layer 338 ＇ worsen.For example, the hydrogen that for example produces during ILD, IMD and the Passivation Treatment of hydrogen based gas can cause the deterioration of capacitor dielectric layer 338 ＇.Therefore, for example form the hydrogen that carries out technology generation subsequently after the capacitor C, form the functional layer of salable capacitor C for capacitor for voltage protection C avoids polluting.Provide this functional layer according to semiconductor storage unit preparation method of the present invention for sealant EL with sandwich construction.
Wish that sealant EL has following function.At first, must prevent the volatilization of capacitor dielectric layer 338 ＇ by sealant EL.Especially as capacitor dielectric layer 338 ＇ when for example PZT layer, BST layer or PLZT layer are formed by ferroelectric layer, in integrated technique subsequently, must prevent the volatilization of capacitor dielectric layer 338 ＇ by sealant EL.This is because the volatilization of ferroelectric layer worsens capacitor C, thereby the built-in function of store information disappears by building up electric charge.The second, sealant EL must not react with capacitor dielectric layer 338 ＇.The 3rd, during integrated technique subsequently sealant EL must prevent hydrogen based gas be diffused into capacitor dielectric layer 338 ' in.The 4th, sealant EL must effectively stop hydrogen based gas be diffused into capacitor dielectric layer 338 ' in, during integrated technique subsequently hydrogen based gas be mixed in the ild film, in IMD layer or the passivation layer.
For satisfying above-mentioned requirements, the invention provides the sealant EL that comprises barrier layer and capacitor protective layer.The major function of capacitor protective layer is to prevent that hydrogen based gas is diffused among capacitor dielectric layer 338 ＇ during the integrated technique subsequently.Be formed on barrier layer under the capacitor protective layer and prevent to be formed on material layer under the barrier layer and the reaction between the capacitor protective layer, and/or prevent the volatilization of capacitor dielectric layer 338 ＇.The major function that should understand barrier layer and capacitor protective layer is different, yet the combination of these two layers by sealant EL can be satisfied needed all above-mentioned functions.The function of barrier layer and capacitor protective layer is mainly embodied in the formation of sealant EL or in the integrated technique after forming capacitor.The functional effect of two layers will describe in detail below.
Under the situation of the sealant EL that forms multilayer, make up sealant EL and have the following structure of covering capacitor C.For example, under the situation that forms three-layer sealed layer EL, form sealant EL by order lamination barrier layer, resilient coating and capacitor protective layer, covering capacitor C.Forming under the situation of two layers of sealant EL, by order lamination barrier layer and capacitor protective layer but form sealant EL, covering capacitor C.Can change the quantity and the structure thereof of the laminated material layer that forms sealant EL.Form restriction of technology or the like in view of sealant EL, determine the quantity of the laminated material layer of formation sealant EL.
With reference to figure 3H, provide double-layer seal layer EL according to semiconductor storage unit preparation method's of the present invention first embodiment.Barrier layer 342 at first is formed at semiconductor-based the end 300, directly covering capacitor C.Then, capacitor protective layer 344 is formed directly on the barrier layer 342.Need to consider the function of barrier layer 342 generations, select to be used for the material layer of barrier layer.Preferred barrier layer 342 can be by TiO 2Layer, Ta 2O 5Layer, BaTiO 3Layer, SrTiO 3Layer, Bi 4Ti 3O 12Layer or PbTiO 3Layer is formed.The preferred material layer of selecting not with capacitor protective layer 344 reactions forms barrier layer 342.Therefore, according to the material layer that is used to form capacitor dielectric layer 338 ＇, the preferred material layer of selecting as barrier layer.For example, for example PZT layer, BST layer or PLZT layer are as capacitor dielectric layer 338 ＇ if select ferroelectric layer, and barrier layer 342 can be by TiO 2Layer is formed.In addition, according to the required function of barrier layer 342, the physics that forms barrier layer 342 selected material layers and chemical property etc., determine the thickness of barrier layer 342.Be preferably formed the barrier layer 342 of thickness 50-1500 .
On the other hand, according to forming the selected material layer type of barrier layer, change the ad hoc approach that is used to form barrier layer 342.This be because according to the material layer of selecting from the above-mentioned material layer as barrier layer 342, can change form barrier layer 342 technology so that more convenient application.Kinds of processes be can use to form barrier layer 342, for example CVD, PVD, sputter, ALD and LA technology comprised.Yet, if TiO 2Layer is used as barrier layer, preferred sputtering technology.Certainly, in forming barrier layer 342, can use technology except that sputtering technology.
For example, utilizing sputtering method to form TiO 2Under the situation of the barrier layer 342 of layer, titanium can be used as target material, and Ar can be used as sputter gas and O 2Can be used as reacting gas.Utilizing the DC sputtering equipment to form under the situation of barrier layer 342, it is as follows to set process conditions.The power that puts on the DC sputtering equipment can be 1-6kW, and cavity temperature can be set at 25-700 ℃, and cavity pressure is adjustable as 1-5mTorr.In addition, Ar and O 2Flow velocity can remain on 8-14sccm.More preferably at about 10sccm of flow velocity and the O of about 630 ℃ of power, the cavity temperature of about 6kW, the about 1mtorr of cavity pressure, Ar 2The condition of the about 10sccm of flow velocity under, form the sputter of barrier layer 342.
Need to consider the function of capacitor protective layer 344 generations, select to form material layer as capacitor protective layer 344.Preferred capacitor protective layer 344 can be TiO 2Layer, Ta 2O 5Layer, Al 2O 3Layer, BaTiO 3Layer, SrTiO 3Layer, Bi 4Ti 3O 12Layer or PbTiO 3Layer.Material layer type as capacitor protective layer 344 depends on formation capacitor dielectric layer 338 ＇ and barrier layer 342 selected material layers.For example, do not wish to select material layer with barrier layer 342 reactions as capacitor protective layer 344.Preferred capacitor protective layer 344 is made up of the material that is different from barrier layer 342, more preferably by Al 2O 3Layer is formed.
Consider the function of capacitor protective layer 344 and physics and the chemical property that forms the selected material layer of capacitor protective layer, determine the thickness of capacitor protective layer 344.Be preferably formed the capacitor protective layer 344 of the about 50-5000 of thickness, more preferably the about 50-1500 of thickness.If the thickness of capacitor protective layer 344 surpasses 1500 , capacitor protective layer 344 can be used as ild film, thereby need not to carry out the ILD technology of back.
Owing to,, can change the technology that is used to form capacitor protective layer 344 according to from the above-mentioned material layer, selecting material layer as capacitor protective layer 344 with the same cause that forms barrier layer 342.Can adopt kinds of processes to form capacitor protective layer 344, comprise for example CVD, PVD, sputter, ALD and LA technology.
Yet, because following advantage, more preferably ALD technology in forming capacitor protective layer 344.Be that ALD technology can be carried out at low temperatures.In addition, ALD technology causes physics and chemically stable capacitor protective layer, thereby can strengthen the above-mentioned functions of capacitor protective layer 344.Simultaneously, utilizing ALD technology to form in the capacitor protective layer 344, monoatomic layer repeats lamination, makes the thickness of capacitor protective layer 344 accurately control.In addition, no matter how complicated form the layout on surface thereon for capacitor protective layer, and the capacitor protective layer 344 that provides 100% step to cover can be provided.
When capacitor protective layer utilizes ALD technology by Al 2O 3When layer formed, aluminum source gas pulse at first in addition added on the upper surface of substrate of semiconductor in the chamber that is contained in ALD equipment.The composite gas of trimethyl aluminium (TMA), dimethyl hydrogenation aluminium (DAMH), dimethyl amine aluminium alkane (DMEAA), triisobutyl aluminium (TIBA) or these gases can be used as aluminum source gas.The pulse aluminum source gas is chemistry or Physical Absorption on the whole surface at the semiconductor-based end.Afterwards, behind the aluminum source gas that in removing the chamber, keeps,, remove the aluminum source gas of physical absorption on semiconductor-based basal surface with the upper surface of inert gas clean semiconductor substrate.Inert gas can be Ar, N 2, N 2The composite gas of O or these gases.Then, oxygen source gas in addition pulse add on the upper surface of substrate of semiconductor.Oxygen source gas can be H 2O, N 2O, O 3Or the composite gas of these gases.Reaction between aluminum source gas and the oxygen source gas only takes place on upper surface of substrate of semiconductor, aluminum source gas chemisorbed on upper surface of substrate of semiconductor, thereby form the film of thickness level with list or polyatom layer.After this, from the chamber, remove the oxygen source gas that keeps,, remove the oxygen source gas of physical absorption on semiconductor-based basal surface with the upper surface of the inert gas clean semiconductor substrate of selecting in the above-mentioned inert gas.The film that formation has a thickness level of list or polyatom layer is called 1 circulation of ALD technology.Repeat the ALD process cycles of predetermined quantity, reach for example 100 of desirable thickness until capacitor protective layer 344.
Utilizing ALD technology to form Al 2O 3In the capacitor protective layer of layer, the temperature range of substrate can be 150-500 ℃, more preferably from about 300 ℃.In addition, the burst length of aluminum source gas can be 0.1-2 second, more preferably from about 1 second.In addition, the cleaning time that is used to remove the inert gas of physical absorption aluminum source gas can be 0.1-10 second, more preferably from about 5 seconds.The burst length of oxygen source gas can be 0.1-20 second, more preferably from about 0.2 second.The cleaning time that is used to remove the inert gas of physical absorption oxygen source gas can be 0.1-20 second, more preferably from about 6 seconds.
In addition, for further improving the function of sealant EL, can after forming barrier layer 342 and/or forming capacitor protective layer 344, alternative heat-treat technology.Specifically, after forming barrier layer 342, for improving the dielectric behavior of barrier layer 342, can be at O 2Heat-treat technology under the atmosphere.Preferably under 600 ℃ or lower temperature, heat-treat technology.This is because when for example under 600 ℃ or the higher high temperature barrier layer 342 being heat-treated, oxygen can be diffused in the conductive plug 324.More preferably under about 400-600 ℃ temperature, heat-treat technology.
After forming capacitor protective layer 344, for improving the dielectric behavior of capacitor protective layer 344, can be at O 2Selectivity is heat-treated technology under the atmosphere, preferably 600 ℃ or lower temperature.Preferably under about 400-600 ℃ temperature, can heat-treat technology.
Under a stable condition, can after forming capacitor protective layer 344, carry out the Technology for Heating Processing under 600 ℃ or the higher temperature.This is because the sealant EL that finishes is insensitive to the diffusion of oxygen because of conductive plug 324.Adopting the technology except that ALD technology, preferably after forming capacitor protective layer 344, can heat-treat technology so that form capacitor protective layer 344.According to forming capacitor protective layer 344 selected technologies, this chemistry and physics with capacitor protective layer 344 can be relevant.In other words, the capacitor protective layer that other technology forms because the capacitor protective layer 344 that ALD technology forms compares is more stable, and ALD technology makes capacitor protective layer 128 effectively and not heat-treat technology.Yet, forming with other technology except that ALD technology under the situation of capacitor protective layer 344, need be through the dielectric behavior of the Technology for Heating Processing raising capacitor protective layer 344 under 600 ℃ or the higher temperature.Especially after forming barrier layer 342, do not heat-treat technology and utilize under the situation of the technology formation capacitor protective layer 344 except that LAD technology, preferably under 600 ℃ or higher temperature, carry out annealing in process.
Simultaneously because the capacitor protective layer 344 that utilizes ALD technology to form is stable, can prevent Technology for Heating Processing reliably during oxygen be diffused in the conductive plug 324, thereby improve processing limit to the Technology for Heating Processing of capacitor protective layer 344.
Utilize sealant EL covering capacitor C as mentioned above, can prevent the deterioration of the capacitor C in the technology subsequently, now give to describe.
With reference to figure 3I, after forming sealant EL, carry out ILD and handle.Promptly on the whole surface at the semiconductor-based end 300, form the 3rd ild film 346.The 3rd ild film 346 can be by silicon oxide layer, silicon oxynitride layer, bsg layer, PSG layer, bpsg layer, TEOS layer, O 3The composite bed of-TEOS layer, PE-TEOS layer, USG layer or these layers is formed.
For example, under the situation of the 3rd ild film 346 that utilizes CVD technology formation silicon oxide layer, silane (SiH 4) and oxygen (O 2) as reacting gas.The resulting hydrogen of reaction can make capacitor dielectric layer 338 ＇ degenerate between silane and the oxygen.Yet, because be coated with double-deck sealant EL according to capacitor C of the present invention, stopped ILD basically during hydrogen be diffused among the capacitor C.The capacitor protective layer 344 of sealant EL helps to stop the diffusion of hydrogen especially.Barrier layer 342 also helps to prevent the diffusion of hydrogen, although its effect is unlike the height of wanting of capacitor protective layer 344.
After this, carry out metallization process.Especially utilize common process at first capacitor protective layer 344 and barrier layer 342 to be carried out composition, form the contact hole 348 of expose portion capacitor top electrode 340 ＇.Utilize fluorine-based wet or dry ecthing that the 3rd ild film 46 is carried out composition.In addition, can be at Ar and CF 4Utilize reactive ion etching that capacitor protective layer 344 is carried out composition under the atmosphere.After forming contact hole 348, form top electrode Metal Contact 350.After forming contact 348, can repair Technology for Heating Processing.Can be at O 2For example repair Technology for Heating Processing under 450-500 ℃ the temperature under the atmosphere.Although not shown among Fig. 3 I, form the bottom electrode Metal Contact with top electrode Metal Contact 350.
With reference to figure 3J, after forming top electrode Metal Contact 350, structure is carried out Passivation Treatment can form by the composite bed of silicon oxide layer, silicon nitride layer, silicon oxynitride layer or these layers, more preferably form by silicon nitride layer or silicon oxynitride layer with formation passivation layer 352, passivation layer 352.Form the passivation layer 352 of the about 2000-20000 of thickness.Can use kinds of processes and form passivation layer 352, comprise for example CVD technology, PVD technology, ALD technology, sputtering technology or LA technology, but more preferably pecvd process forms passivation layer 352.
Utilizing after pecvd process forms the passivation layer 352 of silicon nitride layer, the RF power that preferably applies about 400W gives formation passivation layer 352 used equipment.In addition, the pressure limit 1-15torr of reative cell, preferably about 5torr.The temperature range 150-500 of reative cell ℃, preferred about 300 ℃.Silane (SiH as the reacting gas supply 4) flow rates 50-500sccm, preferably about 150sccm.In addition, the ammonia (NH that uses as reacting gas 4) flow rates 20-200sccm, preferably about 40sccm.
In addition, utilizing pecvd process to form under the situation of the passivation layer of being made up of silicon oxynitride layer 352, the pressure and temperature of reative cell is identical with the situation that passivation layer 352 is made up of silicon nitride layer basically.Preferred silane (the SiH that uses as reacting gas 4) flow rates 10-200sccm, more preferably from about 50sccm.Ammonia (NH as the reacting gas use 4) flow rates 20-500sccm, preferably about 150sccm.In addition, the N that uses as reacting gas 2The flow rates 20-500sccm of O, preferably about 150sccm.
During forming passivation layer 352, hydrogen based gas is diffused among the capacitor C, as in ILD technology.Yet capacitor protective layer 344 capacitor for voltage protection C avoid the diffusion of hydrogen based gas, thereby have also prevented the degeneration of capacitor C during Passivation Treatment.Certainly, barrier layer 342 also helps to prevent the diffusion of hydrogen, although its effect is unlike the height of wanting of capacitor protective layer 344.
The part sealant EL that is formed on capacitor top electrode 340 ＇ is removed during being described in the formation contact hole 348 that is used for top electrode Metal Contact 350 in the front.For this reason, hydrogen based gas can partly enter capacitor top electrode 340 ＇ through the removal of sealant EL during Passivation Treatment.In addition, because passivation layer 352 self comprises the hydrogen based gas of capturing, even the hydrogen based gas that is mingled with after Passivation Treatment wherein can be diffused among the capacitor C, and capacitor dielectric layer 338 ＇ are worsened.For avoiding causing the deterioration problem of capacitor dielectric layer 338, the alternative hydrogen barrier layer 354 that forms before carrying out Passivation Treatment by the diffusion of hydrogen.Hydrogen barrier layer 354 stops the diffusion of hydrogen based gas, for taking place during forming passivation layer 352 or afterwards, thereby prevents the deterioration of capacitor dielectric layer 338 ＇.
Hydrogen barrier layer 354 provides and capacitor protective layer 344 identical functions that constitute sealant EL basically.Therefore, hydrogen barrier layer 354 needed physics, chemistry and crystal property are identical with capacitor protective layer 344 basically.Hydrogen barrier layer 354 can be by Al 2O 3Layer, TiO 2Layer, Ta 2O 5Layer, BaTiO 3Layer, SrTiO 3Layer, Bi 4Ti 3O 12Layer, PbTiO 3The composite bed of layer or these layers forms.Preferred hydrogen barrier layer 354 is by Al 2O 3Layer is formed.Can use kinds of processes and form barrier layer 354, comprise for example CVD technology, PVD technology, sputtering technology, ALD technology and LA technology.Advantageous applications ALD technology forms hydrogen barrier layer 354.The advantage of using ALD technology in forming hydrogen barrier layer 354 is basically also with to use ALD technology resulting identical in forming capacitor protective layer 344.In addition, the desirable treatment conditions that form ALD technology in the hydrogen barrier layer 354 are basically with to utilize ALD technology to form passivation protection layer 344 applied identical.
The thickness 50-20000 of preferred hydrogen barrier layer 354, more preferably thickness 200-300 .
Although not shown, before forming hydrogen barrier layer 354, the resilient coating alternative is formed by oxide skin(coating).In forming resilient coating, can use APCVD technology or PEVCD technology.For example, forming under the situation of resilient coating by APCVD technology, resilient coating can be by O 2-TEOS layer, PSG layer or bpsg layer are formed.Under the situation of using PEVCD technology formation resilient coating, resilient coating can be by PE-TEOS layer or PE-SiH 4Layer is formed.
Utilizing pecvd process to form under the situation of resilient coating, preferred silane or TEOS gas are as reacting gas.When utilizing pecvd process to form the resilient coating of PE-TEOS layer, preferred RF power bracket 100-500W, best 200W.Chamber pressure scope 1-15torr, preferred 5torr.15-450 ℃ of preferred reaction room temperature scope, more preferably 300 ℃.
With reference to figure 3A and 3I as mentioned above, be coated with sealant (EL) at capacitor C and carry out ILD afterwards and handle and Passivation Treatment, thereby can prevent the deterioration of capacitor dielectric layer 338 ＇.In addition, before carrying out Passivation Treatment, can further form hydrogen barrier layer 354, thus the deterioration of capacitor dielectric layer 338 ＇ that take place during more effective integrated operation of semiconductor subsequently that prevents to carry out after forming capacitor C.
Except that conductive plug 324 (referring to Fig. 3 B) form by doped polycrystalline silicon and whole conductive plug 324 (referring to Fig. 3 B) being transformed into the silicide layer during the silicidation subsequently, copy the step of first embodiment according to semiconductor storage unit preparation method's of the present invention second embodiment.
In a second embodiment, owing to use silication, be preferably formed high melting metal layer 326 (referring to Fig. 3 B), as the source material layer during the silicidation, than thicker among first embodiment so that whole conductive plug 324 (referring to Fig. 3 B) is transformed into silicide layer.Be preferably formed thickness 130 or thicker high melting metal layer 326 (referring to Fig. 3 B), thereby after silicidation, still keep high melting metal layer.Under the treatment conditions substantially the same, be used for the heat treatment of the silication of whole conductive plug 324 (referring to Fig. 3 B) with first embodiment.
The 3rd embodiment according to semiconductor storage unit preparation method of the present invention is different with first embodiment, and refractory metal silicide layer for example silicon cobalt substrate is formed in the boundary layer 334 (referring to Fig. 3 D), rather than formation is gone up in the embolism (referring to Fig. 3 C).
With reference to figure 4A, utilize and the essentially identical step of first embodiment, form conductive plug 324 through first and second ild films 318 and 320.Conductive plug 324 can be made up of the material layer identical materials layer of basic up and down embolism 330 (referring to Fig. 3 C).For example, conductive plug 324 can be made up of doped polysilicon layer.Then, conductive layer 356, high melting metal layer 358 and complanation layer 360 orders are stacked on the conductive plug 324 and second ild film 320.Conductive layer 356 can be by forming with the following embolism 330 identical materials layers shown in Fig. 3 C basically.For example, conductive layer 356 can be formed by the doped polysilicon layer of the about 3000-10000 of thickness.High melting metal layer 358 can be by forming with the material layer identical materials layer of the metal level 326 shown in Fig. 3 B basically.For example, high melting metal layer 358 can be formed by the cobalt layer of the about 50-200 of thickness.Complanation layer 360 can be by forming with the material layer identical materials layer of the complanation layer 328 shown in Fig. 3 B basically.For example, complanation layer 360 can be made up of the titanium nitride layer of thickness 50-150 .
As under the situation of conductive layer 356, the natural oxide layer can be formed on the surface of conductive layer 356 at doped polysilicon layer.Therefore, preferably before forming high melting metal layer 358, remove the natural oxide layer from conductive layer 356.The technology that is used for removing this natural oxide layer was described at first embodiment, therefore no longer was repeated in this description.
With reference to figure 4B, after depositing conducting layer 356, high melting point metal layer 358 and complanation layer 360, structure is heat-treated technology, the top of conductive layer 356 is transformed into silicide layer 362.For example, when high melting point metal layer 356 was made up of the cobalt layer, the top of conductive layer 356 was transformed into silicon cobalt substrate during the heat treatment that is used for silication.Utilize basically and the identical step of silication that forms the last embolism 332 shown in Fig. 3 C, can finish the Technology for Heating Processing that is used for silication.
After the Technology for Heating Processing of the silication that is used for conductive plug 356, remove the complanation layer 360 and a part of high melting metal layer 358 that are not transformed into silicide layer.The technology of removing the non-reacted parts of high melting metal layer 358 and complanation layer 360 is identical with semiconductor storage unit preparation method's the used technology of first embodiment basically.
After the non-reacted parts of removing complanation layer 360 and high melting metal layer 358, the diffusion barrier (not shown) is formed on the silicide layer 362.Identical with first embodiment basically from forming diffusion barrier to the step of finishing semiconductor storage unit, therefore no longer be repeated in this description.
In above-mentioned second embodiment, utilize independent step to obtain conductive plug 324 and conductive layer 356 according to semiconductor storage unit preparation method of the present invention.Yet, utilize single step can form conductive plug 324 and conductive layer 356, thereby reduce the quantity of treatment step.For example, doped polycrystalline silicon can be deposited on second ild film 320, thereby filling contact hole 322 makes the polysilicon layer complanation on second ild film 320 then, until the polysilicon layer that keeps predetermined thickness on second ild film 320.Thus, by available conductive plug 324 of single step and conductive layer 356.
Except that the formation of ignoring diffusion barrier and lower conductiving layer, copy the step of the 3rd embodiment basically according to semiconductor storage unit preparation method's of the present invention the 4th embodiment.In other words, the silicide layer that forms among semiconductor storage unit preparation method's the 4th embodiment for example silicon cobalt substrate serves as diffusion barrier and capacitor lower electrode, therefore need not to form separately diffusion barrier and lower conductiving layer.
In addition, because utilize silicide layer that silicidation forms for example silicon cobalt substrate be preferably formed the conductive layer 356 (referring to Fig. 4 A) that is used as the silicon source during the enough thick silication as the capacitor lower electrode among the 4th embodiment.The about 3000-10000 of thickness of preferred conductive layer 356 (referring to Fig. 4 A).In addition, preferred control is used for the treatment conditions of silicidation so that form the silicide layer 362 (referring to Fig. 4 B) of the about 3000-10000 of thickness.
Basically copy the same steps as of the third embodiment of the present invention according to semiconductor storage unit preparation method's of the present invention the 5th embodiment.Yet semiconductor storage unit preparation method's the 5th embodiment is different from the 3rd embodiment, and silicide layer and barrier diffusion are formed on the conductive plug and second ild film in proper order before forming lower conductiving layer, forms silicide layer by CVD or sputtering technology.Preferred silicide layer is by forming the about 50-1000 of thickness with the last conductive plug 332 identical materials layers shown in Fig. 3 C basically.Diffusion barrier is by forming with the diffusion barrier identical materials layer that is included in the boundary layer 334 shown in Fig. 3 D basically.
With reference to figure 5, utilize the step identical with first embodiment, finish the 6th embodiment, the conductive plug 324 of embolism 330 and last embolism 332 under formation comprises according to semiconductor storage unit preparation method of the present invention.
Then, on embolism 332 on the conductive plug 324, form boundary layer composition 364 and capacitor lower electrode 366.Especially boundary layer and lower conductiving layer are stacked on the embolism 332 and second ild film 320 in proper order, and last embolism 332 is identical with lower conductiving layer 336 with the boundary layer 334 shown in Fig. 3 D respectively basically with second ild film 320.And then, utilize photoetching process that boundary layer and lower conductiving layer are carried out composition, form boundary layer composition 364 and capacitor lower electrode 366.
After forming boundary layer composition 364 and capacitor lower electrode 366, utilize for example pecvd process of common process, the 3rd ild film 368 is formed at semiconductor-based the end 300.The material layer with first ild film 318 is identical basically to be used for the material layer type of the 3rd ild film 368.Then, the 3rd ild film 368 is carried out composition, form the opening 370 that electricity under the exposed capacitor has 366 top surface by photoetching process.Then, diffusion barrier spacer 372 is formed on the sidewall of opening 370.Diffusion barrier spacer 372 can be by forming with the capacitor protective layer 342 identical materials layers shown in Fig. 3 H basically.For example, diffusion barrier spacer 372 can be by ALD-Al 2O 3Layer is formed.Selectivity is heat-treated technology to formed diffusion barrier spacer 372 in the oxygen atmosphere under about 400-600 ℃ temperature, is used for enhancement function thereby stablize diffusion barrier spacer 372.Utilize for example so-gel technology of common process, opening 370 is filled by capacitor dielectric layer 374.Capacitor dielectric layer 374 can be by forming with the same material layer of Fig. 3 E capacitor dielectric layer 338 ＇ basically.Afterwards, for improving the dielectric behavior of capacitor dielectric layer 374, capacitor dielectric layer 374 is heat-treated technology.Can under about 600-800 ℃ temperature, heat-treat technology to capacitor dielectric layer 374 in the oxygen atmosphere.After this, form capacitor top electrode 376 at capacitor dielectric layer 374.For forming capacitor top electrode 376, utilize for example sputtering technology of common process, on the whole surface at the semiconductor-based end, form conductive layer, carry out composition by photoetching process, form capacitor top electrode 376.Be used for type, thickness and the structure of the material layer of conductive layer and form go up the used technology of conductive layer identical with the last conductive layer 340 that forms Fig. 3 D basically.After this, form sealant EL ＇, cover resulting structure, contact with the partition capacitance device dielectric layer 374 that does not form capacitor top electrode layer 376 thereon and the surface of capacitor top electrode 376 like this.Be preferably formed the sealant EL ＇ of sandwich construction, as the sealant EL of Fig. 3 H.In addition, be preferably formed sealant EL ＇, comprise barrier layer 378 and capacitor protective layer 380 at least.The material layer type that is used for barrier layer 378 and capacitor protective layer 380 and thickness and form the used technology of these layers identical with barrier layer 342 that forms Fig. 3 H and capacitor protective layer 344 basically.In addition, after forming barrier layer 342 and/or capacitor protective layer 380, can heat-treat technology.With first embodiment the same terms according to semiconductor storage unit preparation method of the present invention under, can heat-treat technology.
After forming sealant EL ＇, utilize ILD to handle, on the whole surface at the semiconductor-based end 300, form the 4th ild film 382.The material layer type that is used for the 4th ild film 382 basically be used for the identical of first ild film 318.Then, the 4th ild film 382 is carried out metalized, form top electrode Metal Contact 384 through the 4th ild film 382, top electrode Metal Contact 384 contacts with capacitor top electrode 376.Although not shown, during this metalized, can form the bottom electrode Metal Contact.Then, on the semiconductor-based end 300, form passivation layer 386.Be used for type, thickness and the structure of the material layer of passivation layer 386 and form the used technology of passivation layer 386 identical with the passivation layer 352 that forms Fig. 3 J basically.
In the 6th embodiment according to semiconductor storage unit preparation method of the present invention; capacitor dielectric layer 374 direct sealed layer EL ＇ and diffusion barrier spacer 372 cover; as the foregoing description according to semiconductor storage unit preparation method of the present invention, thereby but capacitor for voltage protection dielectric layer 374 is avoided the diffusion of the hydrogen based gas that produces during the ILD and Passivation Treatment subsequently.
On the other hand, before carrying out as the Passivation Treatment among first embodiment, hydrogen barrier layer 388 can be formed on the whole surface at the semiconductor-based end 300.In addition, although not shown, before forming hydrogen barrier layer 388, can selectivity forms resilient coating on the whole surface at the semiconductor-based end 300.Be used for material layer type, thickness and the structure of hydrogen barrier layer 388 and resilient coating and form the used technology of these layers identical with according to semiconductor storage unit preparation method's of the present invention first embodiment basically.Before carrying out Passivation Treatment, form resilient coating and/or hydrogen barrier layer 388, guarantee that more effective capacitor for voltage protection dielectric layer 374 avoids hydrogen based gas and enter wherein through top electrode Metal Contact 384.
Except that the conductive plug 342 of wadding warp first and second ild films 318 and 320 contact holes 322 that form is made up of refractory metal silicide layer fully, the step of copying semiconductor storage unit preparation method's the 6th embodiment according to semiconductor storage unit preparation method's of the present invention the 7th embodiment.In semiconductor storage unit preparation method's second embodiment, described forming, therefore no longer be repeated in this description by the refractory metal silicide layer in the contact hole 322 of first and second ild films 318 and 320.
The 8th embodiment according to semiconductor storage unit preparation method of the present invention is different from the 6th embodiment, have 324 fillings of conductive plug that single layer structure for example only is made up of doped polycrystalline silicon and pass through the contact hole 322 of first and second ild films 318 and 320, and boundary layer composition 364 has three-decker, wherein conductive layer composition and diffusion barrier composition order lamination.
For the boundary layer composition 364 with three-decker, conductive layer, silicide layer and diffusion barrier are deposited in order on the conductive plug 324 and second ild film 320.At this, it is identical with the 3rd embodiment according to semiconductor storage unit preparation method of the present invention basically to deposit three layers of used technology.Certainly, the 3rd embodiment with above-mentioned semiconductor storage unit preparation method is identical basically with thickness as the material type of conductive layer and silicide layer and diffusion barrier.
The step of copying the 7th embodiment according to semiconductor storage unit preparation method's of the present invention the 9th embodiment is until have for example conductive plug 324 of doped polycrystalline silicon of single layer structure forming in first and second ild films 318 and 320 contact holes 322 that form.After this, by the used step of semiconductor storage unit preparation method's the 4th embodiment, on the conductive plug 324 and second ild film 320, form doped polysilicon layer and silicide layer.Utilize photoetching process that silicide layer and doped polysilicon layer are carried out composition, obtain capacitor lower electrode 366 and boundary layer composition 364.After forming capacitor lower electrode 366, structure carried out basically the same steps as that is adopted with the 6th embodiment.
The step of copying the 7th embodiment according to semiconductor storage unit preparation method's of the present invention the tenth embodiment is until have for example conductive plug 324 of doped polycrystalline silicon of single layer structure forming in first and second ild films 318 and 320 contact holes 322 that form.After this, silicide layer and diffusion barrier are deposited in order on the conductive plug 324 and second ild film 320, and utilize photoetching process to be patterned into boundary layer composition 364.Structurally finish the 6th embodiment same steps as with the semiconductor storage unit preparation method, form semiconductor storage unit.
Hereinafter by following experimental example, the hydrogen based gas that produces during preventing that ILD from handling, IMD handles etc. the effect to double-deck EL on this aspect of the deterioration of capacitor C will be described in.For this reason, form sample 1 under the following conditions.Afterwards ,-5～5V voltage is put on the capacitor of sample 1, the degree of polarization of Measurement of capacitor and leakage current.The result is shown in Fig. 6 and 7.
Prepare sample 1 as follows.At first, on the semiconductor-based end, form ferroelectric condenser.The area 1.44 * 10 of capacitor -6Cm 2, and capacitor dielectric layer is made up of the PZT of about 2000 of thickness.The top electrode of capacitor is Ir layer and IrO 2The bilayer of layer, and the thickness of these layers is respectively 1200 and 300 .The bottom electrode of capacitor also is Pt and IrO 2The bilayer of layer, and the thickness of these layers is respectively 1500 and 500 .
Then, form double-layer seal layer EL.Promptly by sputtering technology with at O 2450 ℃ of following heat treatment is 30 minutes in the atmosphere, forms the TiO of about 1000 of thickness 2The barrier layer of layer.After this, utilize ALD technology to form the Al of about 120 of thickness 2O 3The capacitor protective layer of layer.
After this, carry out ILD and handle, ILD produces hydrogen source gas during handling, and forms interlayer dielectric layer on the whole surface at the semiconductor-based end, forms part then and exposes the contact hole that upper and lower electricity has.Form the damage that causes during the contact hole for repairing, in oxygen atmosphere, under 450 ℃, sample 1 was heat-treated 30 minutes.Then, form top electrode Metal Contact and bottom electrode Metal Contact.
With reference to figure 6, can be from about 25 μ C/cm 2The reasoning of residual polarization value, approximate identical with initial level, at formation TiO 2And Al 2O 3After the double-layer seal layer EL of layer, adopt ILD to handle capacitor dielectric layer is worsened.This result confirms that double-layer seal layer EL prevents the deterioration of capacitor dielectric layer.
With reference to figure 7, can see the leakage current about 10 of capacitor under the voltage of 1-4V -10Ampere.The leakage current of promptly determining capacitor has stable the distribution in the working voltage scope of semiconductor storage unit.From this result, also can infer the deterioration that double-layer seal layer EL prevented capacitor dielectric layer.
The perparation of specimen 2 and 3 is to compare with sample 1.Relatively utilize the same procedure that forms sample 1 for convenient, the TiO that in sample 1, forms as barrier layer and capacitor protective layer respectively 2And Al 2O 3Layer, the single sealant EL as sample 2 and 3 forms separately respectively.Promptly form and remove TiO by sputtering technology 2Outside the sealant EL of sample 2, remove Al and form by ALD technology 2O 3Outside the sealant EL of sample 3.
Specifically, preparation sample 2 and 3 adopts capacitor to form technology, with the same terms of sample 1 under form the suprabasil capacitor of semiconductor.Afterwards, form the sealant EL of individual layer.Form the individual layer sealant EL of sample 2 and 3 under the following conditions.
Under the situation of sample 2, form the TiO of about 1000 of thickness by sputtering technology 2The sealant EL of layer.Then, at O 2Under 650 ℃ sealant EL was heat-treated 30 minutes in the atmosphere.At this, to compare with the barrier layer that forms sample 1, the temperature of Technology for Heating Processing raises.
Under the situation of sample 3, form the Al of about 120 of thickness by ALD technology 2O 3The sealant EL of layer.At this, Al (CH 4) 3And H 2O gas is used separately as aluminum source gas and oxygen source gas.Yet the sealant EL to sample 3 does not heat-treat technology.
Afterwards, sample 2 and 3 is carried out ILD and metalized, form bottom electrode Metal Contact and top electrode Metal Contact with the same procedure of sample 1.After this, under the situation as sample 1, change voltage, measuring samples 2 and 3 degree of polarization, thus obtain hysteresis loop (respectively by the S of Fig. 8 2And S 3Shown in).The hysteresis loop of sample 1 is (by S 1Shown in) also shown in Fig. 8.
In addition, from sample 1,2 and 3, select 12 chip small pieces, measure the barrier layer contact resistance.Result shown in Fig. 9. Sample 1,2 and 3 barrier layer contact resistance are respectively by S in Figure 11 1, S 2And S 3Expression.
As shown in Figure 8, by S 2The hysteresis loop area of shown sample 2 compares S 1Shown sample 1 little.This shows with sample 1 compares, and the ferroelectric properties of the capacitor dielectric layer of sample 2 worsened during ILD handled.In addition, from almost nil by S 3The residual polarization value of shown sample 3, but the ferroelectric properties of the capacitor dielectric layer of reasoning sample 3 almost completely worsens.From these results, can obtain as drawing a conclusion.
At first, the sealant EL (TiO of sample 2 during ILD handles 2Layer) can stop the diffusion of hydrogen.Yet, and comprise TiO 2And Al 2O 3The sample 1 of the double-layer seal layer EL of layer is compared, a little less than this blocking effect.
The second, to the barrier layer (TiO of sample 1 2Layer) heat-treats the sealant EL (TiO of the temperature of technology than sample 2 2) low.Therefore, compare, a little less than the insulation property of the barrier layer of sample 1 are wanted with the sealant EL of sample 2.But sample 1 stop the effective of hydrogen.This function that shows the diffusion that stops hydrogen mainly realizes by the capacitor protective layer of sample 1.
The 3rd, in addition the insulation property that form sealant EL (sample 2) after the individual layer sealant EL by the situation of under 600 ℃ or higher temperature, heat-treating technology and improving under, can not prevent the capacitor deterioration problem that causes by the hydrogen diffusion fully.
The 4th, the deterioration of the capacitor dielectric layer of sample 3 and formation sealant EL (Al 2O 3Layer) used technology is relevant.Be that deterioration reason has been to use the H that serves as oxygen source gas 2O.Simultaneously, under the situation of sample 1, after forming barrier layer, form capacitor protective layer.Promptly because capacitor is coated with barrier layer, H 2O can be used as by ALD method formation capacitor protective layer (Al 2O 3Layer) oxygen source gas, and do not cause the deterioration of capacitor dielectric layer.
As shown in Figure 9, the barrier layer contact resistance of sample 1 is lower than sample 3.In addition, improve the barrier layer contact resistance of sample 2 to about 1M Ω or bigger degree.Can propose as drawing a conclusion from Figure 12.
At first, the Technology for Heating Processing temperature (450 ℃) of the barrier layer of formation sample 1 is lower than the Technology for Heating Processing temperature (600 ℃) of the sealant EL that forms sample 2.The rising that is the barrier layer contact resistance of sample 2 is that the high-temperature heat treatment process owing to sealant EL makes oxygen be diffused into the contact embolism.
The second, aspect anti-block diffusion, the sealant EL (Al of sample 3 2O 3Layer) than the sealant EL (TiO of sample 2 2Layer) more effective.Although with the capacitor protective layer the same terms that forms sample 1 under form the sealant EL of sample 3, the ability that stops the oxygen diffusion of the sealant EL of sample 1 is good.Therefore, by forming double-deck sealant EL, can improve the effect that stops the oxygen diffusion.
Aspect semiconductor storage unit of the present invention, can prevent during the integrated technique that because hydrogen is attacked the deterioration of the capacitor dielectric layer that causes, integrated technique carries out after capacitor forms.On the other hand,, can improve the speed of service owing to have the barrier layer of low contact resistance according to semiconductor storage unit of the present invention according to semiconductor storage unit of the present invention.
Preparing aspect semiconductor storage unit of the present invention, but by avoiding hydrogen based gas with the sealant covering capacitor capacitor for voltage protection with sandwich construction.In other words, can prevent that because the deterioration of the capacitor dielectric layer that causes of hydrogen based gas, hydrogen based gas results from the integrated technique that carries out subsequently after forming capacitor.In preparation on the other hand, avoided the raising of the contact resistance of semiconductor storage unit during the high-temperature heat treatment process in the oxygen atmosphere according to semiconductor storage unit of the present invention.And, if before passivation layer forms, form resilient coating and/or hydrogen barrier layer, can prevent because the deterioration of the capacitor dielectric layer that the hydrogen that produces during the Passivation Treatment causes.
With reference to preferred embodiment, part illustrates and has described the present invention, should understand those skilled in the art and can make multiple change to form and details, and not break away from the determined the spirit and scope of the present invention of appended claims.

Claims (25)

1. semiconductor storage unit comprises:
Capacitor has bottom electrode, top electrode and the capacitor dielectric layer between lower and upper electrode;
Sealant, the whole surface except that the part top electrode of covering capacitor, sealant has and comprises the barrier layer be made up of the different insulative material and the sandwich construction of capacitor protective layer at least,
Wherein barrier layer is formed under the capacitor protective layer.
2. according to the semiconductor storage unit of claim 1, also comprise:
Interlayer dielectric layer is formed on the sealant; With
Metal Contact forms through sealant and interlayer dielectric layer, and the part that covers with the not sealed layer of top electrode contacts.
3. according to the semiconductor storage unit of claim 2; wherein sealant has double-decker; except that the part top electrode that forms Metal Contact, barrier layer is the dielectric layer on the whole surface of covering capacitor, and capacitor protective layer is the dielectric layer that covers the whole surface of barrier layer.
4. according to the semiconductor storage unit of claim 2; wherein barrier layer is formed by preventing to be formed on the material layer that reacts between material layer under the barrier layer and the capacitor protective layer; and capacitor protective layer is made up of the material layer that the hydrogen that can prevent to be trapped in the interlayer dielectric layer is diffused in the capacitor dielectric layer, and this interlayer dielectric layer is formed on the capacitor protective layer.
5. according to the semiconductor storage unit of claim 2; wherein barrier layer is made up of the material layer that can prevent the capacitor dielectric layer volatilization; and capacitor protective layer is made up of the material layer that the hydrogen that can prevent to be trapped in the interlayer dielectric layer is diffused in the capacitor dielectric layer, and this interlayer dielectric layer is formed on the capacitor protective layer.
6. according to the semiconductor storage unit of claim 2; wherein barrier layer by can prevent capacitor dielectric layer volatilization and can prevent to be formed on material layer under the barrier layer and capacitor protective layer between the material layer that reacts form; and capacitor protective layer is made up of the material layer that the hydrogen that can prevent to be trapped in the interlayer dielectric layer is diffused in the capacitor dielectric layer, and this interlayer dielectric layer is formed on the capacitor protective layer.
7. according to the semiconductor storage unit of claim 1, wherein barrier layer is stable material layer by the Technology for Heating Processing under 400-600 ℃ of temperature in oxygen atmosphere.
8. according to the semiconductor storage unit of claim 1, wherein capacitor protective layer is the material layer that forms by atom layer deposition process.
9. according to the semiconductor storage unit of claim 1, wherein barrier layer and capacitor protective layer all have the thickness of 50-1500 .
10. according to the semiconductor storage unit of claim 1, wherein barrier layer is by TiO 2Layer, Ta 2O 5Layer, BaTiO 3Layer, SrTiO 3Layer, Bi 4Ti 3O 12Layer or PbTiO 3Layer forms.
11. according to the semiconductor storage unit of claim 1, wherein capacitor protective layer is by Al 2O 3Layer, TiO 2Layer, Ta 2O 5Layer, BaTiO 3Layer, SrTiO 3Layer, Bi 4Ti 3O 12Layer or PbTiO 3Layer forms, and the material layer that is used for capacitor protective layer is different from the material layer that is used for barrier layer.
12., also be included in the passivation layer on Metal Contact and the interlayer dielectric layer according to the semiconductor storage unit of claim 2.
13., also comprise the hydrogen barrier layer between Metal Contact and passivation layer according to the semiconductor storage unit of claim 12.
14. according to the semiconductor storage unit of claim 13, wherein hydrogen barrier layer is a metal oxide layer.
15. according to the semiconductor storage unit of claim 13, wherein hydrogen barrier layer is the material layer that forms by atom layer deposition process.
16. according to the semiconductor storage unit of claim 13, wherein hydrogen barrier layer is by Al 2O 3Layer, TiO 2Layer, Ta 2O 5Layer, BaTiO 3Layer, SrTiO 3Layer, Bi 4Ti 3O 12Layer or PbTiO 3Layer forms.
17. according to the semiconductor storage unit of claim 13, wherein hydrogen barrier layer is stable material layer by the Technology for Heating Processing under 400-600 ℃ of temperature in oxygen atmosphere.
18., also comprise the resilient coating between Metal Contact and hydrogen barrier layer according to the semiconductor storage unit of claim 13.
19. according to the semiconductor storage unit of claim 1, wherein capacitor lower electrode is made up of silicon cobalt substrate.
20. the semiconductor storage unit according to claim 1 also comprises:
The inter-level dielectric film is positioned under the capacitor;
Conductive plug forms through the inter-level dielectric film, and conductive plug is electrically connected capacitor lower electrode; With
Boundary layer is made up of the silicon cobalt substrate between capacitor lower electrode and the conductive plug.
21. the semiconductor storage unit according to claim 1 also comprises:
The inter-level dielectric film is positioned under the capacitor; With
Conductive plug forms through the inter-level dielectric film, and conductive plug is electrically connected capacitor lower electrode;
Wherein conductive plug only is made up of the bilayer of silicon cobalt substrate or conductive layer and silicon cobalt substrate.
22. a method for preparing semiconductor storage unit comprises:
Formation has the capacitor of bottom electrode, top electrode and the capacitor dielectric layer between lower and upper electrode;
Formation has the sealant of sandwich construction, thus the whole surface except that the part top electrode of covering capacitor, sealant comprises barrier layer and the capacitor protective layer of being made up of the different insulative material at least, wherein barrier layer is formed under the capacitor protective layer.
23. an integrated circuit (IC)-components comprises:
The integrated-circuit capacitor structure, the capacitor dielectric layer that has bottom electrode, top electrode and between lower and upper electrode, extend;
Sealant seals described integrated-circuit capacitor structure, and described sealant comprises at least the combination at barrier layer that extends on the capacitor dielectric layer and the capacitor protective layer on barrier layer, and wherein barrier layer is by from TiO 2, Ta 2O 5, BaTiO 3, SrTiO 3, Bi 4Ti 3O 12And PbTiO 3The material of selecting in the group that constitutes is formed, and capacitor protective layer is by Al 2O 3Form; With
Dielectric layer is positioned on the described sealant.
24. according to the device of claim 23, the composition that wherein said barrier layer stops capacitor dielectric layer is to outdiffusion and pass through.
25. according to the device of claim 23, wherein said capacitor protective layer stops that hydrogen ion diffuses through.
CNB001318926A 1999-09-10 2000-09-10 Semiconductor memory device with capacitor protective layer and preparing method thereof Expired - Fee Related CN1173406C (en)

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