CN117334658A - 半导体封装 - Google Patents
半导体封装 Download PDFInfo
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- CN117334658A CN117334658A CN202310791186.6A CN202310791186A CN117334658A CN 117334658 A CN117334658 A CN 117334658A CN 202310791186 A CN202310791186 A CN 202310791186A CN 117334658 A CN117334658 A CN 117334658A
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Classifications
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Abstract
本发明提供一种半导体封装。所述半导体封装包含集成电路IC块及第一衬底。所述IC块具有第一互连层。所述第一衬底承载所述IC块。所述第一衬底包含面向所述第一互连层的第二互连层及与所述第二互连层相对的第三互连层。此外,所述第二互连层或所述第三互连层中的至少一者由与所述第一互连层的对应介电材料及对应导电材料基本上相同的介电材料及导电材料组成。
Description
优先权主张及交叉参考
本申请案主张2022年6月30日申请的先前申请的第63/357,059号美国临时申请案的权益且其全部内容以引用方式并入本文中。
技术领域
本公开大体上涉及半导体封装,且更特定来说,涉及经配置以加速3D IC及先进系统级封装(SiP)的互连缩放的半导体封装。
背景技术
传统晶体管的2D几何微缩正快速接近难度最高、在突破上可能有许多待克服瓶颈的部分的“红砖墙”,尽管最近归因于工程及材料科学的伟大成就而有很大发展,涉及极其复杂的多步光刻图案化、新型应变增强材料及金属氧化物栅极。3D IC(3D集成电路)集成表示与传统2D IC及2D封装集成的根本不同在于:在IC、中介层或衬底上垂直堆叠IC及/或晶体管层以提供极其密集IC。3D IC已被公认为下一代半导体技术,其具有高性能、低功耗、小物理大小及高集成密度的优点。3D IC提供一种途径来不断满足下一代装置的性能/成本要求,同时保持更宽松栅极长度及更低工艺复杂性。3D IC的商业应用主要包含高带宽存储器(HBM)及混合存储立方体,其是基底裸片上的3D存储器堆叠,如由图1中的906所说明。
最近,还展示了逻辑/处理器IC上的高速缓存。展望未来,3D IC应用的数目将稳定增加。预期3D IC将在例如高性能计算(HPC)、数据中心、AI(人工智能)/ML(机器学习)、5G/6G网络、图形、智能手机/可穿戴设备、汽车及需要“极致”、超高性能、高能效装置的其它应用的应用中找到广阔应用。这些装置包含CPU(中央处理单元)、GPU(图形处理单元)、FPGA(现场可编程门阵列)、ASIC(专用集成电路)、TPU(张量处理单元)、集成光子学、AP(手机应用处理器)及数据包缓冲/路由器装置。
商用3D IC(例如逻辑上的3D HBM DRAM存储器裸片堆叠)越来越多由含有硅穿孔(TSV)的商用2.5D IC结构用于有源存储器及逻辑裸片及硅中介层中。3D IC可使用互连技术(例如TSV、含有互连布线及微通孔的重布层(RDL)、铜柱微凸块/焊料凸块及由索尼(Sony)最先证明用于裸片间通信的互补金属氧化物半导体(CMOS)图像传感器的倒装芯片接合或新兴铜混合接合)实现存储器上存储器、逻辑上存储器、逻辑上逻辑。3D IC允许来自不同制造工艺及节点的异质裸片垂直堆叠、芯片重复使用及高性能应用的SiP(系统级封装)小芯片,其已推到最先进节点处单个裸片的极限。单片3D IC构建于多个有源硅层及层之间的垂直互连件上。其仍处于早期发展阶段且尚未广泛部署。
为了加速采用,必须经由IC封装系统协同设计以更全面方式架构3D IC系统,其涉及硅IP、IC/小芯片及IC封装且解决伴随功率及热挑战。与2D封装的每“平方厘米”PPAC(性能、功率、面积及成本)优化相比,3D IC的IC封装系统协同设计旨在实现每“立方毫米”PPAC优化,其中在所有权衡决策中现在必须考虑涵盖IC、中介层、IC封装衬底、IC封装及系统印刷电路板(PCB)的垂直尺寸。3D IC通常含有行业必须提供的最先进IC。先进IC现今可含有数千亿个晶体管,其通过前段工艺(FEOL)工艺制造且有时通过后段工艺(BEOL)SiO2/Cu(二氧化硅/铜)及低κ介电质(κ=相对介电常数)/Cu RDL工艺构建的多层级(10个或更多个层)垂直互连件内的超过30英里互连件来互连。连接微小且紧密堆积晶体管的低层级互连件或线称为局部互连件(LC),其通常又细又短。在IC BEOL结构中较高的全局互连件(GC)在不同电路块之间行进且通常又粗又长且相距甚远。互连布线层之间的通孔或连接允许信号及功率从一个层传输到下一层。在IC层级之外(且如图1中可见),先进存储器及逻辑IC通常通过中介层上的RDL中的PI/Cu(聚酰亚胺/Cu)互连布线/微通孔层、中介层及有源裸片中的铜TSV及基于有源裸片上的铜柱微凸块的倒装芯片接合来互连。中介层继而使用焊料凸块来安装于IC封装衬底上,例如含有多个ABF(日本Ajinomoto Fine-Techno公司的Ajinomoto堆积膜)/Cu互连层及铜填充电镀通孔(PTH)的层压衬底,其中层压衬底组装于PCB上。3D IC的性能取决于通过IC、中介层、IC衬底及PCB中的这些细线移动信号及功率的能力。此陈述不仅应用于2.5D IC(见图1),而且应用于其它先进SiP(系统级封装),尤其是扇出结构(见图2)、嵌入式SiP(见图3)及硅光子学(图23A及23B)以及其组合。
随着晶体管变得越来越小(随着IC或硅技术缩放不断发展),IC上的互连件的大小及R与C的乘积(即,RC)也必须缩放,其中R为电阻且C为电容。快速芯片需要低RC值,因为装置速度与RC成反比。涵盖IC、中介层、IC衬底及3D IC封装的互连件尺寸(主要是线宽(L)/线间距(S))、通孔的直径及间距及接合垫间距的压缩或减小电子必须行进的距离、线电阻R及功率损耗,有助于晶体管速度不断提高,同时使其它条件保持相同。20世纪90年代从铝互连件到低电阻铜互连件的迁移也有助于减小先进IC的R值(且提高可靠性)。与纯二氧化硅的κ=4.2相比,现今用于先进IC的BEOL结构中的低κ介电质(κ=2.5)也减小C值,因为电容是介电质κ值的函数。相比之下,用于中介层的RDL、IC层压衬底中的ABF及PCB中的FR4/5中的聚酰亚胺的κ值分别为2.78到3.48、3.2到3.4及3.3到4.8,取决于玻璃纤维编织方式。
对于含有位置近距离紧密的最先进不同IC的3D IC,互连缩放不仅需要涵盖IC而且需要涵盖中介层、IC封装衬底、IC封装及PCB以获得3D IC的全部益处。尽管3D IC比2D集成实现显著益处,但在有源裸片中晶体管的尺寸与TSV的尺寸之间存在明显差异或不对称。现今,现代晶体管的沟道长度已达到10nm或更小,其远小于有源IC中几微米的典型TSV的直径。另外,以下的L/S、通孔间距及互连接合垫间距存在明显差异:(1)晶片BEOL与中介层工艺之间;(2)中介层与IC衬底工艺之间;及(3)IC衬底与系统级PCB工艺之间。如图4中可见,L/S及层厚度从PCB到IC衬底到先进SIP(例如晶片级扇出封装)到晶片BEOL减小以涵盖L/S从100μm/100μm到0.2μm/0.2μm及层厚度从100μm到0.1μm的宽范围。关于图5中所展示的TSV尺寸及互连接合垫间距,有源裸片及中介层中的TSV的间距可为1μm到40μm,而较薄有源裸片通常趋向于比较厚中介层实施更小间距。在HBM裸片堆叠上,SK Hynix最近发布由12个DRAM裸片(各自约30μm厚)组成的其HBM3 DRAM,其中μm级TSV安装于控制IC上。相比之下,堆积层压衬底中的电镀通孔可具有小到30μm直径及约50μm间距。PCB的对应通孔尺寸通常远大于IC衬底的通孔尺寸且趋向于随应用大幅变化。
仍参考图5,倒装芯片组合件及新兴铜混合接合是现今使用的两种主要芯片/互连接合技术。3D IC的接合垫间距或I/O缩放(及其它所需SiP)是为高性能计算及在存储器中(in-memory)计算应用提供更高带宽及更低功率的关键。基于超精细间距微凸块焊料的主流倒装芯片可实现40μm的芯片到芯片接合的接合间距,而用于芯片到芯片接合或硅层接合的无焊料铜混合接合技术现今实现1μm的接合间距且将来会更小。
上述芯片/封装/系统互连明显差异或不对称对可通过3D IC集成实现的密度及粒度以及3D IC的“每立方毫米”PPAC优化提出很大限制。
发明内容
本公开的一个方面是提供一种半导体封装,其包含具有第一互连层的集成电路(IC)块及承载所述IC块的第一衬底。所述第一衬底包含面向所述第一互连层的第二互连层及与所述第二互连层相对的第三互连层。所述第二互连层或所述第三互连层中的至少一者由与所述第一互连层的对应介电材料及对应导电材料基本上相同的介电材料及导电材料组成。
本公开的另一方面是提供一种半导体封装,其包含具有第一互连层及与所述第一互连层相对的第二互连层的第一衬底。所述第一互连层经配置用于混合接合到集成电路(IC)块或第二衬底,其中所述第一互连层具有第一介电质及第一线宽。所述第二互连层具有第二介电质及第二线宽。所述第一介电质与所述第二介电质相同或不同,且所述第一线宽与所述第二线宽相同或不同。
本公开的又一方面是提供一种半导体封装,其包含第一衬底,所述第一衬底具有预浸布线层、所述预浸布线层的顶面上方的第一堆积布线层及所述第一堆积布线层的顶面上方的第一再钝化布线层。所述第一堆积布线层具有6μm/6μm到10μm/10μm之间的最小L/S。所述第一再钝化布线层具有等于或小于2μm/2μm的最小L/S。所述第一再钝化布线层由聚酰亚胺或氧化物组成以形成经配置以接合到集成电路(IC)块或另一衬底的第一互连层。
附图说明
从结合附图阅读的以下详细描述最佳理解本公开的方面。应注意,根据行业标准做法,各种结构未按比例绘制。事实上,为使讨论清楚,可任意增大或减小各种结构的尺寸。
图1说明根据本公开的一些比较实施例的2.5D/3D IC封装结构的横截面图。
图2说明根据本公开的一些比较实施例的扇出结构的横截面图。
图3说明根据本公开的一些比较实施例的嵌入式SiP结构的横截面图。
图4说明先进半导体封装技术的概况的示意图。
图5说明半导体封装技术的I/O缩放的示意图。
图6说明衬底技术响应于最先进IC进步的发展的示意图。
图7说明根据本公开的一些实施例的有源IC的横截面图。
图8说明根据本公开的一些实施例的IC封装衬底的横截面图。
图9说明根据本公开的一些实施例的半导体封装中的无源组件的横截面图。
图10A说明根据本公开的一些实施例的TSV的横截面图。
图10B说明根据本公开的一些实施例的混合接合工艺的横截面图。
图10C提供根据本公开的一些实施例的各种3D IC封装选项。
图10D提供根据本公开的一些实施例的2.5D硅中介层的制造工艺。
图11说明根据本公开的一些实施例的3D IC堆叠工艺的横截面图。
图12说明根据本公开的一些实施例的3D IC堆叠工艺的横截面图。
图13说明根据本公开的一些实施例的3D IC堆叠工艺的横截面图。
图14说明根据本公开的一些实施例的3D IC堆叠的横截面图。
图15说明根据本公开的一些实施例的3D IC堆叠的横截面图。
图16A到16F说明根据本公开的一些实施例的经由扇出处理的3D IC堆叠工艺的横截面图。
图16G说明根据本公开的一些实施例的使用扇出衬底的3D IC堆叠的横截面图。
图17A说明根据本公开的一些实施例的半导体封装的横截面图。
图17B说明根据本公开的一些实施例的半导体封装的横截面图。
图18说明根据本公开的一些实施例的半导体封装的横截面图。
图19说明根据本公开的一些实施例的半导体封装的横截面图。
图20说明根据本公开的一些实施例的半导体封装的横截面图。
图21说明根据本公开的一些实施例的半导体封装的横截面图。
图22说明根据本公开的一些实施例的半导体封装的横截面图。
图23A说明根据本公开的一些实施例的SiP共封装的横截面图。
图23B说明根据本公开的一些实施例的处理器-光子SiP共封装的横截面图。
图24说明根据本公开的一些实施例的具有单面RDL的层压衬底的横截面图。
图25说明根据本公开的一些实施例的具有双面RDL的层压衬底的横截面图。
在以下详细描述中,出于解释目的,阐述许多具体细节来提供所公开实施例的全面理解。然而,应明白,可在没有这些具体细节的情况下实施一或多个实施例。在其它例子中,示意性展示熟知结构及装置以简化图式。
具体实施方式
以下公开内容提供用于实施所提供标的物的不同特征的许多不同实施例或实例。下文描述元件及布置的具体实例以简化本公开。当然,这些仅为实例且不意在限制。例如,在以下描述中,在第二特征上方或上形成第一特征可包含其中第一及第二特征直接接触形成的实施例,且还可包含其中额外特征可形成于第一与第二特征之间使得第一及第二特征可不直接接触的实施例。另外,本公开可在各种实例中重复参考数字及/或字母。此重复是为了简单及清楚且本身不指示所讨论的各种实施例及/或配置之间的关系。
此外,为便于描述,本文中可使用例如“下面”、“下方”、“下”、“上方”、“上”、“在…上”及其类似者的空间相对术语来描述一个元件或特征与另一(些)元件或特征的关系,如图中所说明。除图中所描绘的定位之外,空间相对术语希望涵盖装置在使用或操作中的不同定位。设备可以其它方式定向(旋转90度或依其它方向)且也可相应地解译本文中所使用的空间相对描述词。
如本文中所使用,例如“第一”、“第二”及“第三”的术语描述各种元件、组件、区域、层及/或区段,这些元件、组件、区域、层及/或区段不应受这些术语限制。这些术语可仅用于使元件、组件、区域、层或区段彼此区分。除非上下文明确指示,否则本文中所使用的例如“第一”、“第二”及“第三”的术语不隐含序列或顺序。
本公开公开用于加速3D IC(及其它所需先进系统级封装(SiP))互连缩放的方法、工艺及结构,其遥遥领先于相关IC、中介层、IC衬底、IC封装及测试及印刷电路板(PCB)行业的传统互连缩放曲线,同时在工艺中弥合上述关键互连尺寸的上述芯片/封装/系统差异。本公开的另一目的是公开用于允许“连续地”弥合这些差异及随着其发展“连续”缩放互连尺寸以导致“连续地”产生新颖、最密集3D IC及3D IC封装的方法。尽管本文中基于3D IC及3D IC封装提供实例,但本公开也可应用于主要包括2.5D/3D IC(见图1中的实例)、扇出(见图2中的实例)、嵌入式SiP(见图3中的实例)、硅光子学(见图23A及23B中的实例)及其组合的其它类型的先进IC及先进SiP。
如同图1中所描绘的2.5D IC结构,在一些比较实施例中,PCB 901用作载体,而层压衬底902通过多个球栅阵列(BGA)球921接合于PCB 901上方。层压衬底902可具有安装于层压衬底902的一或两侧上及/或嵌入层压衬底902中的一或多个无源组件904。硅中介层903通过多个焊料凸块922接合于层压衬底902上方。具有硅穿孔(TSV)905的硅中介层903可用作弥合层压衬底902与IC 906、907及908之间的细微L/S/间距能力缺口的平台。在硅中介层903上方,不同电子组件(例如动态随机存取存储器(DRAM)结构906、逻辑结构907或中央计算单元908等)可安装于硅中介层903的上侧上,其中电子组件中的IC可3D堆叠,如图1中由906及907所展示。例如,图1中的DRAM结构906可为HBM DRAM堆叠,其包含多个垂直(在厚度方向上)安装的DRAM裸片906a(使用基于微凸块的倒装芯片接合或混合接合),DRAM裸片906a垂直堆叠于基底裸片(即,控制IC 906b)上(再次使用微凸块),同时这些微凸块与DRAM裸片906a中的TSV耦合。在另一实例中,逻辑结构907可包含垂直堆叠于逻辑裸片907b上的存储器裸片907a,同时存储器裸片907a通过混合接合层(或倒装芯片接合)接合到逻辑裸片907b,且一些混合接合的接合垫可与逻辑裸片907b中的TSV耦合。
参考图2,在一些比较实施例中,可采用扇出封装结构,其中连接从芯片表面扇出以实现更多外部I/O。如图2中所展示,半导体芯片910可包含连接到扇出结构911(例如RDL)的一或多个半导体裸片(例如裸片910a及裸片910b),扇出结构911可由用于后续混合接合的层组成或与焊料凸块922(或微凸块)耦合。使用倒装芯片接合或铜混合接合,扇出结构911接合到层压衬底902。
参考图3,在一些比较实施例中,嵌入式SiP可包含嵌入层压衬底902中的无源装置912及硅互连件913。硅互连件913在DRAM结构906的物理层(PHY)906c与装置结构914的PHY914c之间建立电性连接。装置结构914可包含处理器裸片、存储器裸片、射频(RF)裸片、现场可编程化逻辑闸阵列(FPGA)裸片等914a,其接合于含有TSV的基底逻辑裸片914b上。DRAM结构906及装置结构914通过焊料凸块922接合到层压衬底902。
不管先进SiP方式如何,对于具有1μm、5μm及20μm的对应互连层厚度的基于晶片BEOL、2.5D/3D/扇出及ABF的层压衬底,现今部署于先进SiP中的主流最佳线宽(L)/线间距(S)通常分别约为0.2μm/0.2μm、2μm/2μm及6μm/6μm。如图4中可见,PCB的对应尺寸通常远大于IC衬底的尺寸且即使对于相同最终应用,其也通常变化很大。有源裸片中的TSV(如图5中所展示)可具有2μm到6μm直径、4μm到15μm间距及25μm到30μm深度(或有时称为长度),而2.5D硅中介层中的TSV尺寸通常为5μm到20μm直径、10μm到40μm间距及25μm到100μm深度(即,硅中介层厚度)。有源裸片的TSV尺寸通常远小于较大中介层的尺寸,但两种应用的基本技术相同。相比之下,堆积层压衬底中的电镀通孔可具有小到30μm直径及60μm间距且可具有400μm深度(假设为双层核心)或更大。倒装芯片接合与铜混合接合之间也存在接合间距(及接合垫直径)差距(如图5中所展示)。现今基于焊料的微凸块的主流最精细间距约为40μm(有时约36μm),而无焊料铜混合接合的主流为6μm,与用于将中介层焊料接合到层压衬底约400μm和远大于400μm间距将层压基板焊料接合到PCB形成对比。
随着先进硅技术从5nm缩小到2nm以支持高性能计算(HPC)、数据中心及其它高性能应用(例如人工智能(AI)),先进处理器IC(例如CPU、GPU及FPGA)需要更大及更高层计数的有机层压衬底,即使并入2.5D硅中介层,其从层压衬底减去一些互连任务(如图6中所展示)。在接下来几年中,随着行业缩放到2nm,将需要含有惊人的10+6+10个层(6层核心及堆积于核心两侧上的10个层,总共26个层)的巨大130mm x 130mm层压衬底来支持超过3nm的硅技术。此下一代衬底含有比5nm硅技术所需的更多30%的层且具有5nm技术所需的1.4倍的面积,如图6中所展示。鉴于上述最佳主流L/S堆积衬底能力,在依赖基于ABF树脂及BT树脂(双马来酰亚胺三嗪树脂,其由日本Mitsubishi Gas公司开发)的大面板(例如20"x 24")的层压衬底处理中,比以往更大的层压衬底大小及比以往更高的层计数将不可避免地导致更低衬底良率及更高衬底成本。
即使衬底行业及相关设备行业已努力缩放到面板级衬底处理中的超精细线及间距以减小衬底大小及层计数,但仍需数年才能将主流、高容量、高良率面板级堆积衬底工艺高良率缩放到2μm/2μm L/S及更小(即,现今中介层能力),尤其对于需要前述前所未有的大衬底大小及高层计数的应用。随着先进IC缩放,不仅层压衬底变大,而且中介层也需要变大,如图6中所展示。在中介层及PCB互连缩放上可做出类似陈述:层压板上的集成度越高,中介层及PCB上需要的集成度越高。
当尤其涉及具有3D IC封装的先进SIP时,关键尺寸存在以下三个主要差异:IC/晶片BEOL与中介层之间、中介层与层压板之间及层压板与PCB之间。需要弥合所有差异以最大化3D IC的益处。加快互连缩放具有很多益处。通过更快互连缩放实现的更高集成度可导致更小中介层及衬底大小且更少互连层以及更低成本。此不仅将解决先进IC对先进中介层及IC层压衬底提出的挑战,而且将使3D IC及3D IC封装能够以更高功能密度堆积以实现更高性能及更低功耗,同时使其它条件保持相同。
对于IC、IC封装、层压衬底及PCB行业且如本文中所公开,通过使用或借用其它或相邻行业的主流更精细L/S/间距技术来加快互连尺寸缩放准备比遵守相应行业内的正常技术进步曲线更快地弥合上述芯片/封装/系统互连差异。更重要地,其允许人们在正常行业技术进步曲线之前大量生产更密集堆积3D IC及先进SIP(例如图1、2、3、23A及23B及其组合中所展示)。随着IC、IC封装、层压衬底及PCB行业的L/S/间距技术不断缩放及改进,本文中所公开的方法、结构及工艺可继续实施(例如,通过持续利用来自相邻行业的最佳主流更精细L/S/间距技术)以允许人们在任何给定时间产生具有尽可能最高功能集成密度的SIP。
在本公开中,涵盖3D IC堆叠的互连缩放能力的主要差异及涉及3D IC到中介层、中介层到层压板及层压板到PCB的互连通过应用以下来以全面及普遍方式弥合:
(1)对于更密集3D IC堆叠:更精细间距晶片BEOL氧化物对氧化物(或其它合适材料组合)铜混合接合及后通孔集成取代基于微凸块的传统倒装芯片接合;
(2)对于更密集3D IC到中介层互连:更精细间距晶片BEOL SiO2/Cu RDL取代中介层的IC侧上的传统PI/Cu RDL,IC的更精细尺度TSV取代中介层的更粗糙尺寸TSV,及3D IC到中介层的更精细间距晶片BEOL氧化物对氧化物混合接合取代倒装芯片接合;
(3)对于更密集中介层到层压板互连:更精细间距PI/Cu RDL(或更精细间距低沉积温度(LDT)氧化物/Cu RDL)取代中介层侧上的层压衬底中的传统ABF/Cu RDL,及更精细间距PI对PI(或氧化物对氧化物)混合接合取代中介层到层压衬底的使用焊料的倒装芯片接合,及/或
(4)对于更密集层压板到PCB互连:类似于上述中介层到层压板。
根据需要,人们还可:
(1)应用更精细间距晶片BEOL SiO2/Cu RDL来取代中介层的顶侧及底侧上的传统PI/Cu RDL以通过倒装芯片及/或混合接合进行接合。
(2)应用更精细间距PI/Cu RDL(或更精细间距LDT氧化物/Cu RDL)来取代层压衬底的顶侧及底侧上的RDL的传统ABF/Cu RDL以通过倒装芯片及/或混合接合进行接合。
通过最少工艺调谐,本文中所公开的方法、工艺及结构允许在关于IC、中介层、层压板及PCB的行业中利用相邻行业中已存在的能力来实现遥遥领先于传统缩放的互连缩放。
与本文中所公开的图1、2、3、23A及23B以及其它SiP相关图相关的先前所展示的比较实施例说明先进SiP的具体应用。此外,图7到10描绘实现这些先进SiP的最先进构建块技术的实例。这些技术包含图7中实现的有源IC、图8中实现的IC封装衬底(包含中介层)、图9中实现的无源实例及图10A中的TSV选项。
参考图7,展示与HBM DRAM堆叠中出现的IC类似的最先进IC,其中TSV、RDL在裸片的一侧或顶侧及底侧两者上,接合垫在两侧上,其中至少一者含有焊料/微焊料凸块。图7中的半导体结构930包含具有多个TSV 935的硅衬底931。前段工艺(FEOL)结构932位于硅衬底931的正面上方,后段工艺(BEOL)结构933位于FEOL结构932上方,且RDL 934可安置于硅衬底931的背面及BEOL结构933上。在一些实施例中,BEOL结构包含低κ材料及铜的组合、SiO2及铜的组合或其类似者。在一些实施例中,芯片上无源组件可形成于BEOL结构933中。在一些实施例中,RDL 934含有用于外部连接的多个接合垫。替代地,在其它实施例中,RDL 934的表面可配备有或没有接合垫936、微凸块或焊料凸块。
在顶侧上,RDL 934实际上可与其下的BEOL结构933为一体。在一些实施例中,RDL934包含介电材料及铜的组合或聚酰亚胺及铜的组合。在一些实施例中,RDL 934可根据需要形成有表面处理及钝化层。在一些实施例中,RDL 934及/或半导体结构930可具有形成于内部或安装于其上的无源组件(及/或光学组件)。此外,在一些实施例中,RDL 934可含有混合接合所需的介电质/Cu结构。
图8展示三种类型的可能IC封装衬底:(a)具有PI/Cu RDL 934a及TSV 935的硅衬底931(例如中介层);(b)由晶片级(或在本公开中类似面板级)PI/Cu RDL 934a及模塑料937组成的扇出结构;及(c)具有通常由基于ABF/Cu或BT/Cu的堆积层组成的RDL 934b及通常由BT/玻璃或FR4/FR5/玻璃组成的核心938的IC层压衬底。多个电镀通孔(PTH)939形成于核心938中以在两个RDL 934b之间建立电性连接。在一些实施例中,图8中所展示的三个衬底结构可具有形成于内部或安装于其上的无源组件(及/或光学组件)。
在一些实施例中,通过IC工艺原位产生的芯片上无源装置以及离散无源装置可与BEOL/RDL结构集成。如图9中所展示,在高性能计算(HPC)应用中,包含嵌入层压衬底902内以使不同裸片915互连的例如硅互连件913(其可为无源或有源)的无源组件通常是可取的。在其它实施例中,例如IC电容器(例如深沟槽电容器及低电感芯片阵列电容器)的无源组件可使用类似于IC生产中采用的工艺来制造。
图10A说明通用TSV结构。如图10A中所描绘,TSV可使用粘附屏障/种子层及导体的不同组合来产生。在一些实施例中,TDV中的导体917的候选材料包含铜、钨、钴及钌,而粘附屏障层916的候选者包含Ti、TiN/Ti、Ta、TaN/Ta、TaN/Co或其类似者。当铜用作镀铜的种子层时,导体材料应为铜。
本公开提出混合接合,如图10B中所说明,其在更精细间距、RC延迟、IC压降、热特性、带宽、I/O能量及占用面积方面提供优于倒装芯片技术的若干优点。然而,应注意,在成熟度、宽松平坦化要求及测试及良率管理方面,倒装芯片技术比混合接合具有优势。
图10B说明铜混合接合工艺流程。能够实现超高功能集成密度的混合接合依赖沉积于两个相对晶片表面上的接合层(通常为SiO2)的利用。也可考虑替代介电材料,如Si3N4。
铜混合接合方法允许在相对较低温度下(通常低于400℃)进行对准晶片到晶片接合。通过将热暴露温度限制于低于400℃(尽可能低于250℃),可利用常规金属化及低κ介电质,例如含铜及碳的低κBEOL。通常,低温接合的优点包含避免由热膨胀匹配效应引起的过度晶片变形及最小化对下层晶体管高κ金属栅极堆叠及功能的热效应。
可在典型晶片BEOL互连层的顶部上产生用于混合接合的介电层。此后,进行晶片表面的化学机械研磨(CMP)以基本上平坦化晶片表面且暴露金属垫,以及进行介电表面的表面清洁、等离子体表面活化及水预润湿以使介电表面准备用于晶片到晶片接合。参考图10B中的操作(a)到(c),将晶片94A接合到晶片94B,其中晶片94A(例如)包含与BEOL结构942a接触的硅衬底943a。在BEOL结构942a的表面上,RDL/接合层940a的厚度略大于导电金属垫941a的厚度。在一些实施例中,晶片94A的结构基本上为晶片94B的结构的镜像(如包含与BEOL结构942b接触的硅衬底s943b),且关于RDL/接合层940b及导电金属垫941b的特征基本上与晶片94A中的特征相同。
再次参考图10B中的操作(a)到(c),三步骤晶片到晶片工艺可包含:(a)低温/室温下的氧化物对氧化物接合(即,二氧化硅对二氧化硅接合);(b)加热封闭导电金属垫之间的间隙(利用金属的热膨胀系数(CTE)相对高于氧化物的CTE);及(c)在借助或无需外部压力的情况下,进一步加热压缩及接合导电金属垫。总体来说,操作(a)到(c)在晶片介电界面处形成化学键且在存在金属垫时实现金属接合。直接氧化物对氧化物接合通常依以下工艺序列进行:(1)通过使用例如O2(氧气)/N2(氮气)/Ar(氩气)的气体进行等离子体活化来形成悬挂键及氢氧基与水分子之间的接合;(2)通过去离子水清洁及擦洗来移除缺陷;(3)在室温及大气压下经由水分子及极性氢氧基(OH)基(其终止于天然及热SiO2)的两到三个单层之间的范德华氢键来接合晶片(或晶片及晶片级中介层)与类似氧化物接合层;(4)在晶片表面上形成H2O分子与硅烷醇基(Si-OH-(H2O)x-HO-Si;硅烷醇基=Si-OH)之间的范德华键;及(5)退火移除界面处的水分子且在通常低于400℃(优选地低于250℃)的温度下形成共价键以防止金属间层熔化及植入掺杂剂扩散。必须通过控制例如等离子体条件、表面粗糙度、清洁度、晶片翘曲/平坦度及接合条件的关键参数来避免在直接接合期间由晶片边缘处的水滴形成(焦耳-汤姆孙膨胀效应)引起的空隙形成。在氧化物对氧化物接合的情况中,人们还可改变氧化物类型及沉积技术、工艺条件(例如等离子体气体、等离子体功率、关于化学机械研磨(CMP)的表面粗糙度、表面清洁度、来自去离子清洁的单层到多层水分子、接合条件(例如温度及速度)及退火条件(例如退火温度、退火时间及退火步骤数))以最大化两个晶片之间的接合良率及剪切强度。
图10C例示基于本文中所公开的方法、工艺及结构的PCB上3D IC封装的各种材料/工艺选项。除图10C指出的之外,还存在其它选项。本文中所描述的实施例包含一或多个IC块、一或多个中介层、一或多个层压衬底或封装衬底及一或多个PCB的配置。IC块、中介层、层压衬底或封装衬底或PCB中的每一者拥有经配置以彼此形成电性连接的相应互连层。本文中所描述的组件及互连层的材料及结构选项至少可从与图10C相关联的描述选择。
图10D提供2.5D硅中介层的制造过程。用于在两侧上具有RDL的硅中介层中产生TSV的主流工艺可用于制造在一侧或两侧上具有氧化物/Cu RDL的中介层以支持图17A到图22中所展示的3D IC封装工艺。TSV开口可通过使用氟化气体(例如CF4、SF6或二氟化氙(即,博世(Bosch)蚀刻工艺)作为蚀刻气体对硅进行深度反应离子蚀刻(DRIE)来产生。为了制造高深宽比TSV,选择的掩模可包含铝/二氧化硅、铝/硅/铝、不锈钢、铝、钛、金、铬、二氧化硅、氧化铝、光阻剂及/或旋涂玻璃。在DRIE中,蚀刻掩模材料需要比硅更慢蚀刻,具高选择性。取决于用于提高蚀刻性能的掩模及DRIE条件,也可使用超短脉冲(例如飞秒脉冲)激光微加工。DRIE及外延沉积的组合可在硅中产生超高深宽比(高达500)沟槽。在TSV孔打开之后,人们可继续遵循图10D中所展示的2.5D硅中介层工艺流程(在操作(B)TSV形成下),从氧化物的等离子体增强化学气相沉积(PECVD)及屏障/种子层钛/铜(Ti/Cu)或氮化钽/Cu(TaN/Cu)衬层的物理气相沉积(PVD)开始,通过溅镀到镀铜以填充TSV,到CMP以移除过量Cu且接着到正面(芯片侧)μm级细线RDL及凸块下金属(UBM)处理。此后,进行操作(C)TSV后工艺,从载体接合到晶片减薄到背面RDL及UBM到焊料球沉积到裸片带附接到载体脱离到分割单粒化中介层。关于芯片上的微凸块的操作(A)指代在IC或3D IC上产生微凸块,其将在中介层组装于层压衬底上之后接合到中介层(在操作(D)倒装芯片组装下)。因为中介层非常薄,所以载体(通常为玻璃衬底;见操作(C))通过粘合/释放层接合到中介层衬底,粘合/释放层可承受在基于聚酰亚胺的重布层(RDL)的形成期间引起的高温且随后可通过用激光照射其来移除。尽管存在变型,但图10D中的操作(C)及(D)下的流程展示构建TSV后的中介层、将其组装于层压衬底上及随后将芯片倒装芯片组装于中介层上以形成先前图1中描述的2.5DIC的流程。
图11到13展示使用混合接合及后通孔集成的3D IC堆叠工艺的实例。堆叠所涉及的裸片可为存储器裸片、逻辑裸片或存储器及逻辑裸片且可基于各种IC技术,例如Si(硅)、GaN(氮化镓)、SOI(绝缘体上硅)、SiC(碳化硅)等。
如图11的操作(a)到(d)中所展示,描绘面对面(F2F)双裸片接合工艺,其利用两个相对氧化物/Cu层与第一晶片95A的Cu金属垫及第二晶片95B的Cu金属垫之间的混合接合。
在一些实施例中,第一晶片95A及第二晶片95B包括两个硅衬底950a及950b及两个BEOL结构953a及953b。正面951a及951b位于相应晶片95A及95B的BEOL结构953a及953b的顶部上,且背面952a及952b位于951a及951b的相对侧上。在一些实施例中,在第一晶片95A通过混合接合层955a及955b来面对面(F2F)接合到第二晶片95B(见操作(b))之后,两个硅衬底中的一者(例如硅衬底950b)可如操作(c)中所展示般减薄。在硅衬底950b中形成至少一或多个TSV 954,其将BEOL结构953b连接到硅衬底950a的另一侧上的RDL。混合接合层955a及955b的结构可参考与图10B相关联的先前描述且为简洁起见,此处不再重复。混合接合层955a及955b可为PI/Cu或氧化物/Cu RDL。当使用PI/Cu时,在混合接合期间施加外部压力是有利的。如图11的操作(d)中所展示,接着在硅衬底950b上方形成RDL 957,接着形成表面处理/凸块下金属(未展示)及焊料/微焊料凸块。在图11中所描述的实施例中,在晶片到晶片接合之后使用后通孔工艺在硅衬底950b中产生TSV 954。
图12说明以两个裸片为例的背对面(B2F)接合工艺。如图12中的操作(a)中所展示,将基底衬底958附接到第一晶片95A的BEOL结构953a。硅衬底950a中的TSV 954'通过先通孔或中通孔工艺形成,即,在晶片对晶片接合操作之前。混合接合层955a安置于硅衬底950a上方,且混合接合层955a的表面与第一晶片95A的正面952a重合。图12中的第二晶片95B的详细描述可参考图11中的对应物(952a),其中相同元件符号标示相同或等效组件。在操作(b)中,第一晶片95A的背面952a以背对面(B2F)方式混合接合到第二晶片95B的正面951b。混合接合层955a及955b的结构可参考与图10B相关联的先前描述且为简洁起见,此处不再重复。混合接合层955a及955b两者可基于PI/Cu或氧化物/Cu RDL。当使用PI/Cu时,可在混合接合期间施加外部压力。在操作(d)及(e)中,硅衬底中的一者(例如硅衬底950b)可被减薄且至少一或多个TSV 954'形成于硅衬底950b中以连接BEOL结构953b及硅衬底的相对侧上的RDL。接着在硅衬底950b上方形成RDL 957,接着在RDL 957上形成表面处理/凸块下金属层(未展示)及焊料/微焊料凸块。在图12中所描述的实施例中,在晶片对晶片接合之前使用后通孔方法在硅衬底950b中产生TSV 954'。
图13说明以两个裸片为例的背对背(B2B)接合工艺。图13中第一晶片95A的详细描述可参考图12中其对应物的描述,其中相同元件符号标示相同或等效组件。关于图13中的第二晶片95B,在晶片到晶片接合之前使用先通孔或中通孔工艺形成硅衬底950b中的TSV954',與第一晶片95A之情况相同。混合接合层955b安置于硅衬底950b上方,且第二晶片95B的背面上的混合接合层955b的表面952b与第二晶片95A的背面952a重合。在操作(b)中,第一晶片95A的背面952a以背对背方式混合接合到第二晶片95B的背面952b。在晶片与晶片接合后,透过研磨/减薄/蚀刻的方式去除第二晶片95B的基底衬底958。混合接合层955a及955b的结构可参考与图10B相关联的先前描述且为简洁起见,此处不再重复。混合接合层955a及955b两者可基于PI/Cu或氧化物/Cu RDL。当使用PI/Cu时,可在混合接合期间施加外部压力。在操作(c)中,在硅衬底950b上形成RDL 957,接着产生表面处理/凸块下金属(未展示)及焊料/微焊料凸块,且依需求而减薄基底衬底958。
图11到13中所展示的实施例说明涉及两个裸片的F2F、B2F及B2B接合工艺。上述工艺可以各种组合重复以产生两个以上裸片的3D堆叠。
本公开的图14及15呈现可从图11到13中所描绘的步骤及方法得到的5裸片堆叠的实例。如图14中所说明,晶片95A、95B、95C、95D及95E通过使用F2F及B2B工艺的组合进行混合接合来接合。在图15中,这些晶片通过使用F2B工艺进行混合接合来接合。重要的是应注意,本文中所描述的方法可扩展到堆叠超过五个裸片。
当执行本文中所描述的晶片接合工艺时,市售晶片到晶片接合机可用于低温(例如室温)介电质到介电质接合。通常,此涉及在真空中使用离子或中性原子来物理移除待接合的晶片或衬底的介电表面上的氧化膜且在表面上形成悬挂键,其随后实现直接接合。
为了在执行本文中所描述的晶片接合工艺时实现高晶片接合良率,可使用快速原子束(FAB)枪(例如,通过使用氩(Ar)中性原子束)或离子枪(例如,通过使用Ar离子)清洁接合表面以在真空中移除(例如)晶片表面上的氧化膜且在表面处产生悬空键。FAB适用于Si/Si、Si/SiO2、金属、化合物半导体及单晶氧化物,而离子枪已知适用于SiO2/SiO2、玻璃、SiN/SiN、Si/Si、Si/SiO2、金属、化合物半导体及单晶氧化物。在一些实施例中,在接合期间需要10-6Pa(帕斯卡)真空来防止再吸附到上述活化接合表面。另外,在待接合的两个晶片的表面处优选约1nm Ra(算术平均表面粗糙度)的表面粗糙度。此Ra水平可通过硅的化学机械抛光(CMP)来实现。
对于空间受限应用(例如智能手持装置),可使用扇出工艺产生超薄多裸片3D IC封装。图16A到16F说明经由扇出处理进行3D IC堆叠的实施例。如同图16A到16F中所展示的实施例,聚酰亚胺(PI)对PI混合接合可藉由介电质实现,例如衍生自PMDA及ODA的完全固化PI,其中PMDA代表苯均四酸二酐且ODA代表4,4'-二氨基二苯醚,并且在混合接合期间在施加外部压力下PI/Cu RDL层位于配对表面上。先前图11到15中描述的工艺也可用于制造图16A到16F中的3D IC。关于以基于PMDA及ODA的完全固化聚酰亚胺到完全固化聚酰亚胺接合为例的PI对PI接合,人们可通过改变例如引入水量、接合时间及氧气(O2)等离子体活化时间的条件来最大化剪切强度。为了实现无空隙PI对PI接合,重要的是通过氧气等离子体活化来活化PI表面以在PI表面上产生低密度亲水基,其有效增强由去离子水润湿工艺引入的水分子的吸附。所吸附的水分子继而带来相当高密度OH基(氢氧基),其促进预接合。在PI表面活化及润湿之后,可在250℃或以下的相对低温下进行几分钟,达到PI对PI混合接合可在250℃或以下的相对低温下进行几分钟。仅单独靠等离子体工艺或润湿或水合工艺无法实现良好接合。为了实现良好接合良率而操纵的关键参数包含等离子体活化时间、引入水量、接合温度及接合时间。氧化物对氧化物混合接合需要高组件平坦度及表面清洁度以避免由二氧化硅的高硬度及不良变形特性导致的电互连故障。与常规氧化物对氧化物混合接合相比,PI对PI接合允许更高表面粗糙度且由于PI的低模量及更柔顺特性而更能容忍组件平坦度。
参考图16A到16F中的操作,可通过(例如)激光照射来释放的释放层961形成于载体960上,如图16A中所展示,其中载体960可为玻璃晶片。接下来,如图16B中所展示,在释放层961上形成第一RDL 962。第一RDL 962可包含PI/Cu混合接合表面用于随后混合接合到含有匹配PI/Cu混合接合表面的IC封装。除使用PI/Cu用于混合接合之外,还可考虑LDT氧化物/Cu。
参考图16C及图16D,接着通过微凸块或焊料凸块956将裸片963接合到具有表面处理的第一RDL 962上的接合垫,且通过混合接合将横向于裸片963安置的第一3D IC964接合到第一RDL 962。随后,裸片963及第一3D IC 964可由模塑料(或合适嚢封材料,例如可层压在其上的厚膜光阻剂)965通过模制嚢封。在一些实施例中,模塑料965在研磨及抛光操作中研磨及抛光(例如,通过化学机械抛光)以暴露3D IC 964的顶侧以暴露3D IC 964的电性连接(例如铜柱微凸块)或具有较厚厚度的电子组件的电性连接。应注意,位于扇出衬底的相同层中的裸片963及3D IC 964可拥有不同厚度。在一些实施例中,多个穿塑孔(TMV)966可在裸片接合之前或在模制操作之后形成。TMV 966电性连接第一RDL 962及第二RDL 967。类似于第一RDL 962,第二RDL 967可包含PI/Cu(或氧化物/Cu)混合接合表面。
在一些实施例中,图16D中的单层扇出衬底971可在相同层中含有两个以上IC结构,例如963及964。
参考图16E,在一些实施例中,第二3D IC 968及第三3D IC 969可安装于第二RDL967上方。第二3D IC 968及第三3D IC 969可在另一模制操作中由模塑料965嚢封。模塑料965可经研磨及抛光到期望厚度且根据需要暴露3D IC 968及/或969以通过使用热界面材料附接散热片及散热器来促进裸片冷却。接着,如图16F中所展示,在堆叠裸片及/或3DIC之后,载体960及释放层961通过分离操作(例如,通过激光照射及湿法清洁的组合)移除以暴露第一RDL 962的底侧。在一些实施例中,多个接合垫及导电凸块(例如焊料凸块)970可形成于第一RDL 962上用于外部连接。
在一些实施例中,图16F中所说明的3D结构是双层扇出衬底(971及972),其可含有比所展示的更多的裸片及3D IC。在一些实施例中,可根据需要通过重复图16A到16F中所说明的工艺来形成具有2个以上扇出层的扇出衬底。
另外,在其它实施例中,参考图16G,单层扇出衬底971或双层扇出衬底971及972的至少一侧包含混合接合层。混合接合层的介电材料包含PI、沉积温度优选低于250℃的后段工艺(BEOL)氧化物或固化温度低于250℃且L/S能力小于5μm/5μm的聚合物
最终扇出多裸片封装可通过微凸块、焊料凸块或混合接合来安装到下一级衬底(例如层压衬底)。
一旦组装裸片/3D IC,则如先前图11到16G中所展示,裸片/3D IC可安装于层压衬底或组装于层压衬底上的中介层上,且层压衬底随后接合到PCB用于功率、信号及接地。换句话说,多层级封装充当空间转换器以允许功率从PCB的电源线传输到IC上的超微型晶体管。
本公开旨在提供各种3D IC封装结构,其异质集成涵盖IC、IC封装及/或衬底行业的相邻行业的最佳L/S/间距及接合技术以实现最高功能集成密度。图10C提供涵盖IC、中介层、封装衬底及PCB的可用结构及工艺选项的实例。
以2裸片堆叠及5裸片3D IC的组合件为例,参考图17A到22中所说明的实施例,可使用前述工艺来组装至少4个新颖3D IC封装结构用于演示:
结构1:参考图17A,(a)分别用于3D IC 100与中介层200之间及中介层200与层压衬底300之间互连的微凸块103及焊料凸块203,及(b)中介层的一侧或两侧上的PI/CuRDL或LDT氧化物/Cu RDL(例如互连层201及/或202);
结构2:参考图17B,(a)分别用于3D IC与中介层之间及中介层与层压衬底之间的互连的氧化物对氧化物混合接合(例如互连层101及互连层201的接合)及微凸块/焊料凸块203,及(b)用于3D IC安装的中介层的顶侧上的晶片BEOL氧化物/Cu RDL(例如互连层201)及中介层的底侧上的PI/Cu RDL或LDT氧化物/Cu RDL(例如互连层202);
结构3:参考图18,(a)分别用于3D IC与中介层之间及中介层与层压衬底之间的互连的氧化物对氧化物混合接合(例如互连层101及互连层201的接合)及PI对PI混合接合(例如互连层202及互连层301的接合;或LDT氧化物对LDT氧化物),及(b)用于氧化物对氧化物混合接合的中介层的顶侧上的晶片BEOL氧化物/Cu RDL(例如互连层201)及用于PI对PI混合接合的中介层的底侧及层压衬底的顶侧两者上的PI/Cu RDL(例如互连层202;或LDT氧化物/Cu RDL);及
结构4:参考图19,将基于PI/Cu(或LDT氧化物/Cu)的中介层到层压衬底接合工艺应用于也基于PI/Cu的层压衬底到PCB接合。
本文中所描述的实施例包含一或多个IC块、一或多个中介层、一或多个层压衬底或封装衬底、一或多个PCB的配置。IC块、中介层、层压衬底、封装衬底或PCB中的每一者拥有相应互连层,其经配置以形成到彼此、到嵌入式装置、到无源装置、到光学装置及/或到其它邻接电子组件的电(及光学)连接。本文中所描述的组件及互连层的材料及结构选项可至少从与本文中所公开的图相关联的选项选择。
参考图17A,半导体封装10包含集成电路(IC)块100及支撑或承载IC块100的第一衬底200。IC块100具有面向第一衬底200的第二互连层201的第一互连层101。IC块100至少包含半导体裸片、裸片堆叠或芯片结构,例如本文中所描述的3D IC,例如图11到图16G中的3D IC堆叠。在一些实施例中,IC块100包含多个IC或IC结构。在一些实施例中,IC或IC结构中的至少两者与相应无机到导电混合或有机到导电混合接合层混合接合。在一些实施例中,至少一个IC或IC结构包含多个第一通孔107。在图17A中所展示的实施例中,IC块100包含2裸片堆叠104及相邻5裸片3D IC 105。2裸片堆叠104及/或3D IC 105可使用热界面材料与散热片/散热器106附接,热界面材料经设计以高效传递由其下方的堆叠裸片产生的热。用于制造2裸片堆叠104及5裸片3D IC 105的工艺的实例可见于与图11到15相关联的实施例中。
在一些实施例中,第一互连层101位于IC块100的一侧上用于外部连接。第一互连层101由介电材料及导电材料组成,其可为氧化物/Cu RDL或PI/Cu RDL用于倒装芯片连接到第一衬底200。替代地,在一些实施例中,第一互连层101由介电材料及导电材料组成,其可包含氧化物/Cu RDL粘合剂或PI/Cu RDL用于混合接合(图17A中未说明)到第一衬底200。在一些实施例中,第一互连层101的L/S可小于2μm/2μm且其厚度约为5μm。在一些实施例中,第一互连层101的L/S可小于1μm/1μm。在其中实施含焊料端子的一些实施例中,多个焊料凸块(例如微凸块103)在第一互连层101与第二互连层201之间形成电性连接。在一些实施例中,连接IC块100及第一衬底200的多个微凸块103的接合间距可为约40μm。
IC块100由第一衬底200支撑。在一些实施例中,第一衬底200在衬底的两侧上包含用于电性连接的两个互连层。如图17A中所说明,第一衬底200可包含面向第一互连层101的第二互连层201及与第二互连层201相对的第三互连层202。
在一些实施例中,第一衬底200是中介层。在一些实施例中,第二互连层201及第三互连层202中的每一者由介电材料及导电材料组成。在一些实施例中,第二互连层201或第三互连层202中的至少一者由与第一互连层101的对应介电材料及对应导电材料实质上相同的介电材料及导电材料(其可包含PI/Cu RDL或氧化物/Cu RDL)组成。在一些实施例中,第二互连层201及第三互连层202两者包含PI/Cu RDL或氧化物/Cu RDL。第三互连层202的PI/Cu RDL或氧化物/Cu RDL可通过多个焊料凸块203形成到第二衬底300的电性连接。在一些实施例中,第二互连层201的介电质可为沉积温度低于250℃的后段工艺(BEOL)氧化物或固化温度低于250℃且线宽/线间距(L/S)小于5μm/5μm的聚合物。在一些实施例中,第三互连层202的介电质可为L/S小于5μm/5μm的聚合物或BEOL氧化物。在一些实施例中,连接第一衬底200及第二衬底300的多个焊料凸块203的接合间距可为约100μm至400μm。
在一些实施例中,第一衬底200是扇出衬底。扇出衬底可参考与图16A到图16G相关联的先前描述,但不限于此。在一些实施例中,第二互连层201的介电质可为沉积温度低于250℃的后段工艺(BEOL)氧化物或固化温度低于250℃且线宽/线间距(L/S)小于5μm/5μm的聚合物。在一些实施例中,第三互连层202的介电质可为固化温度低于250℃且L/S小于5μm/5μm的聚合物或沉积温度低于250℃的BEOL氧化物。
在一些实施例中,一或多个有源装置(例如见图7)、无源装置(例如见图9)及/或光学装置(例如见图23A及图23B)可集成或嵌入于第一衬底200的第二互连层201及/或第三互连层202中或支撑IC块100的第一衬底内。类似地,当第一衬底200是扇出衬底时,一或多个有源装置(例如见图7)、无源装置(例如见图9)及/或光学装置(例如见图23A及图23B)可集成或嵌入于扇出衬底或第二互连层201与第三互连层202之间的结构(例如模制层)中。
在一些实施例中,第一衬底200可包含电性连接第二互连层201及第三互连层202的多个第二通孔204,其中第二通孔204的间距等于或不同于第一通孔107的间距。例如,第一通孔107可为图11到图15中所描述的通孔(954及954'),且第二通孔204可为图8中所描述的通孔935。在一些实施例中,个别IC裸片或IC结构中的第一通孔107的直径可为从2μm到6μm且其间距为从4μm到15μm且其深度为从25μm到30μm。在一些实施例中,第一衬底200的第二通孔204的直径可为从5μm到20μm且其间距为从10μm到40μm且其深度为从25μm到100μm。
仍参考图17A,半导体封装10进一步包含支撑第一衬底200的第二衬底300。在一些实施例中,第二衬底300是封装衬底,例如本文中所描述的层压衬底,例如图8、图25及图24中的层压衬底。第二衬底300可包含面向第三互连层202的第四互连层301。在一些实施例中,第四互连层301可包含ABF/Cu RDL,其在L/S/间距能力方面不同于用于形成第二互连层201及第三互连层202的ABF/Cu RDL。在一些实施例中,由ABF/CuRDL组成的第四互连层301的L/S可为约6μm/6μm且其厚度可为约20μm。
在一些实施例中,第二衬底300可进一步包含与第二衬底300中的第四互连层301相对的第五互连层302。在一些实施例中,第五互连层302可包含ABF/Cu RDL,其类似于第四互连层301中的ABF/Cu RDL,但具有不同L/S及间距。在一些实施例中,第五互连层302与用于进一步外部连接的多个BGA球303形成电性连接。
在一些实施例中,第二衬底300可包含电性连接第四互连层301及第五互连层302的多个第三通孔304,其中第一通孔107的间距及第二通孔204的间距等于或不同于第三通孔304的间距。在一些实施例中,第三通孔304的L/S可为约30μm,其厚度为60μm且其深度为400μm。在一些实施例中,第三通孔304是电镀通孔(PTH),如先前图8中所描述。
参考图17B,半导体封装11包含IC块100及支撑或承载IC块100的第一衬底200。图17B的IC块100中的相同元件符号与图17A中所描述的元件符号相同或等效且为简洁起见,此处不再重复。具体来说,IC块100与第一衬底200之间的连接通过混合接合实现。如图17B中所描绘,第一互连层101在裸片或IC结构(即,2裸片堆叠104及5裸片3D IC 105)下方。第一互连层101包含氧化物/Cu RDL/粘合剂或PI/Cu RDL/粘合剂结构用于与第一衬底200混合接合。对应地,第一衬底200的第二互连层201也包含类似氧化物/Cu RDL/粘合剂或PI/CuRDL/粘合剂结构。第一衬底200与第二衬底300之间的接合选项可基于微凸块、焊料凸块及甚至混合接合结构,取决于具体L/S及间距要求。标记图17B的第一衬底200及第二衬底300的元件符号与图17A中所描述的元件符号相同或等效且为简洁起见,此处不再重复。例如,图17B中的第一衬底200可为中介层或扇出衬底。
在一些实施例中,第二互连层201或第三互连层202中的至少一者由与第四互连层301的对应介电材料及对应导电材料基本上相同的介电材料及导电材料组成。例如,中介层及封装衬底(例如层压衬底)可通过混合接合来接合,如图18中所说明。
参考图18,在其它实施例中,半导体封装12中的第四互连层301可包含PI/Cu RDL/粘合剂(或LDT氧化物/Cu)结构用于与第一衬底200混合接合,且因此不仅使第一互连层101及第二互连层201无焊接合,而且使第三互连层202及第四互连层301无焊接合。
此外,图18中还展示,在一些实施例中,第三互连层202及第四互连层301经由有机导电或无机导电混合接合层来混合接合。
参考图19中所展示的半导体封装13,IC块100、第一衬底200及第二衬底300由第三衬底400支撑。在一些实施例中,第三衬底400是PCB。在一些实施例中,第三衬底400可包含电性连接第六互连层401及第七互连层402的多个第四通孔404,其中第一通孔107的间距、第二通孔204的间距及第三通孔304的间距等于或不同于第四通孔404的间距。在一些实施例中,当第三衬底400是PCB时,第四通孔404可为电镀通孔(PTH)。第六互连层401及第七互连层402位于第三衬底400的两个相对侧处。在一些实施例中,第六互连层401可包含PI/Cu(或LDT氧化物/Cu)结构用于混合接合到含有匹配PI/Cu结构的第二衬底300的第五互连层302。第七互连层402依赖多个BGA球403进行外部连接。
参考图20中所展示的半导体封装14,IC块100及第一衬底200(其可为本文中所描述的层压衬底)由第二衬底300(其可为本文中所描述的PCB)支撑。在此类实施例中,第一互连层101及第二互连层201可包含经配置用于混合接合的氧化物/Cu或PI/Cu,且第三互连层202及第四互连层301可包含ABF/Cu RDL以基于焊料凸块203形成电性连接。第五互连层302可包含ABF/Cu RDL以使用焊料凸块或BGA球303形成电性连接。
在其它实施例中,图20中的半导体封装14的第一衬底200(例如层压衬底)的第二互连层201的介电材料可由沉积温度低于250℃的后段工艺(BEOL)氧化物或固化温度低于250℃且线宽/线间距(L/S)小于5μm/5μm的聚合物组成,且第一衬底200(例如层压衬底)的第三互连层202的介电材料可由固化温度低于250℃且L/S小于5μm/5μm的聚合物或堆积膜组成。
在其它实施例中,图20中半导体封装14的第一衬底200是具有核心层601、堆积层(602及604)及再钝化层(603及608)的层压衬底,如随后图24及图25中所描述。所属领域的一般技术人员可参考图20的半导体封装14中所实施的层压衬底的细节。
参考图21中所展示的半导体封装15,替代地,在一些实施例中,IC块100及第一衬底200,第一衬底200可为层压衬底且通过混合接合安装于第二衬底300(例如PCB)上。在此实施例中,第一互连层101及第二互连层201可包含经配置用于混合接合的氧化物/Cu或PI/Cu,且第三互连层202及第四互连层301两者可包含用于将第一衬底200混合接合到第二衬底300的PI/Cu(或LDT氧化物/Cu)结构。第五互连层302可包含ABF/Cu RDL以使用焊料凸块或BGA球303形成到下一级衬底的电性连接。
类似于图20中所描述,图21中第一衬底200(例如层压衬底)的第二互连层201的介电材料可由沉积温度低于250℃的后段工艺(BEOL)氧化物或固化温度低于250℃且线宽/线间距(L/S)小于5μm/5μm的聚合物组成,且第一衬底200(例如层压衬底)的第三互连层202的介电材料(例如层压衬底)可由固化温度低于250℃且L/S小于5μm/5μm的聚合物或堆积膜组成。
在其它实施例中,图21的半导体封装15的第一衬底200是具有核心层601、堆积层(602及604)及再钝化层(603及608)的层压衬底,如随后图24及图25中所描述。所属领域的一般技术人员可参考图20的半导体封装14中所实施的层压衬底的细节。
参考图22中所展示的半导体封装16,在一些实施例中,IC块100可由第一衬底200支撑,第一衬底200可为PCB。在此类实施例中,IC块100的第一互连层101及第一衬底的第二互连层201可包含PI/Cu或LDT氧化物/Cu结构用于将IC块100混合接合到第一衬底200。第三互连层202可包含ABF/Cu RDL以使用焊料凸块或BGA球303形成到下一级衬底的电性连接。
在一些实施例中,图24中第一衬底200的第二互连层201的介电材料可由沉积温度低于250℃的后段工艺(BEOL)氧化物或固化温度低于250℃且线宽/线间距(L/S)小于5μm/5μm的聚合物组成。在一些实施例中,图24中第一衬底200的第三互连层202的介电材料可由固化温度低于250℃且L/S小于5μm/5μm的聚合物或作为第二介电质的堆积膜组成。
在与图17A到22相关联的前述实施例中,出于演示目的,关于第一衬底200、第二衬底300及第三衬底400的术语用于描述中介层、层压衬底(或封装衬底)及PCB。还存在衬底选项的其它组合。
本公开中所描述的方法、工艺及结构可适当应用于各种其它先进SiP式样。此应用的实例在图23A及23B中描绘,其中半导体封装17及18表示在以下两种不同封装配置中硅光子与专用IC(ASIC)/FPGA/CPU的共同封装:一种基于焊料接合(图23A)且另一种基于混合接合(图23B)。
如图23A中所展示,载体506(其可为层压衬底或硅中介层)安装有有源装置501,例如ASIC、FPGA、CPU或其类似者。除有源装置501之外,接合到硅中介层503或在接收本文中所描述的光子IC块的第一衬底上的光学模块502可安装于载体506上。在一些实施例中,将光学信号耦合至波导结构508中或从波导结构508耦合出的光纤504光学连接到光学模块502。尽管图23A中未说明,但至少一个电光转换组件或光电转换组件嵌入或集成于硅中介层503及/或波导结构508中。在一些实施例中,有源装置501及硅中介层503两者通过多个焊料凸块507(或根据需要,微凸块)安装于载体506上方。
参考图23B,类似于图23A中所描述的组件,有源装置501的一侧(例如侧501A)及硅中介层503的一侧(例如侧503A)可包含互连层,其具有LDT氧化物/Cu或PI/Cu结构用于混合接合到载体506的对应互连层(例如在侧506A处)。在一些实施例中,载体506的另一侧可包含用于外部连接的多个BGA球。
如图23A及23B中所公开,安装于含光波导的硅中介层上方的硅光子模块可接合到高密度层压衬底或另一硅中介层,而硅中介层503及层压衬底506使用氧化物对氧化物或PI对PI混合接合来接合在一起。
方法、工艺及结构还可扩展到包含嵌入无源装置,例如硅互连件及/或有源装置,以在层压衬底中嵌入无源装置或有源装置为例。参考图24中所展示的半导体封装,在一些实施例中,层压衬底19可包含核心601(或核心区段)及具有大于10μm/10μm的最小L/S的预浸布线层堆叠。核心601可通过围绕无源装置或有源装置606堆叠或层压预穿孔预浸(例如BT/玻璃)层来制备。在一些实施例中,光学装置可以与无源或有源装置606相同的方式嵌入核心601中。根据需要,可通过激光钻孔操作或机械钻孔操作在预浸层堆叠中形成通孔以形成连接核心601的顶面601A及底面601B的通孔607。通孔607及其接近顶面601A及底面601B的电性连接可通过以下操作中的至少一者来形成:去钻污、镀铜(电镀或无电镀)、光阻剂形成及移除、薄铜沉积及蚀刻。
参考图24,核心601的顶面601A上方的第一堆积布线层602可具有6μm/6μm到10μm/10μm之间的最小L/S。第一堆积布线层602的顶面602A上方的第一再钝化布线层603可具有等于或小于2μm/2μm的最小L/S。在一些实施例中,本公开中的再钝化布线层603可特征化超精细间距。第一堆积布线层602可通过采用以下操作中的至少一者来形成:ABF沉积、通过激光钻孔形成通孔、去钻污、薄铜沉积、光阻剂沉积、图案化及移除、镀铜(电镀或无电极)及薄铜蚀刻。可重复所阐述的操作以在第一堆积布线层602中实现期望层数或总厚度。同样,可制造第二堆积布线层604。接着,第二堆积布线层604的最外表面经由释放/粘合层附接到临时载体(例如玻璃载体)以随后制造第一再钝化布线层603。
在一些实施例中,第一再钝化布线层603由PI/Cu或氧化物/Cu组成以形成经配置以接合到IC块或衬底的第一互连层。在一些实施例中,第一再钝化布线层603包含有机导电混合接合层或无机导电混合接合层。当PI用作介电质时,第一再钝化布线层603的形成可包含以下操作中的至少一者:PI沉积、氧化物沉积、种子层沉积、导电迹线界定、铜电镀、光阻剂剥离及薄铜蚀刻。可重复所阐述的操作以在第一再钝化布线层603中实现得期望层数或总厚度。任选地,形成焊料掩模及金属表面处理(例如金、镍等)可在第一再钝化布线层603的最外表面处执行以促进随后与IC块或衬底组装。在嵌入式层压衬底形成的最后阶段形成第一再钝化布线层603之后,可移除临时载体(例如玻璃载体)。在一些实施例中,第一再钝化布线层603可用作本文中所描述的第二互连层、第三互连层、第四互连层或第五互连层,且层压衬底19可用作本文中所描述的第一衬底、第二衬底、第三衬底或第四衬底。
此外,关于核心601的另一侧,如图24中所展示,在一些实施例中,层压衬底19可进一步包含核心601的底面601B下方的第二堆积布线层604。第一及第二堆积布线层602、604可通过穿透核心601的PTH 607电性连接。
参考图24,沿层压衬底19的垂直方向变化的间距尺度允许容纳不同装置大小及配置以优化支持3D IC的整体设计及功能。在一些实施例中,多个预浸布线层可嵌入至少一无源装置、有源装置或光学组件处。
参考图25,在一些实施例中,核心601的两侧可具有其相应再钝化布线层,如层压衬底20中所展示。第二再钝化布线层608位于第二堆积布线层604的底面604B下方,且第二再钝化布线层608具有与第一再钝化布线层603的L/S相同或不同的L/S。用于形成图25中的衬底结构的制造工艺类似于针对图24所描述的制造工艺且为简洁起见,此处不再重复。对于图25的层压衬底20,第二临时载体(例如玻璃载体)可接合到在先前操作中形成的第一再钝化布线层603以提供机械支撑。在形成第二再钝化布线层608之后,从第二再钝化布线层608释放第二载体。
展望未来,传统互连缩放及特征大小小型化的趋势将在IC、中介层、IC衬底、IC封装及PCB行业中继续,正如自微电子学出现以来的过去几十年一样。随着时间推移,本公开中的方法、工艺及结构将使这些行业能够利用来自相邻行业的最精细及最先进能力。方法、工艺及结构将有助于加速3D IC堆叠、中介层、IC衬底及3D IC封装技术以比仅通过传统缩放方法可实现的节奏更快的节奏缩放且能够继续来自相邻行业的主流更精细L/S/间距技术的异质集成。
上文已概述若干实施例的结构,使得所属领域的技术人员可较佳理解本公开的方面。所属领域的技术人员应了解,其可容易地使用本公开作为设计或修改其它操作及结构的基础以实施本文中所介绍的实施例的相同目的及/或实现相同优点。所属领域的技术人员还应认识到,此类等效构造不应背离本公开的精神及范围,且在不背离本公开的精神及范围的情况下,其可对本文进行各种改变、替换及变更。
Claims (20)
1.一种半导体封装,其包括:
集成电路IC块,其具有第一互连层;及
第一衬底,其承载所述IC块,所述第一衬底包括:
第二互连层,其面向所述第一互连层;及
第三互连层,其与所述第二互连层相对,
其中所述第二互连层或所述第三互连层中的至少一者由与所述第一互连层的对应介电材料及对应导电材料基本上相同的介电材料及导电材料组成。
2.根据权利要求1所述的半导体封装,其进一步包括承载所述IC块及所述第一衬底的第二衬底,所述第二衬底包括面向所述第三互连层的第四互连层,其中所述第二互连层或所述第三互连层中的至少一者由与所述第四互连层的对应介电材料及对应导电材料基本上相同的介电材料及导电材料组成。
3.根据权利要求2所述的半导体封装,其中所述第一互连层及所述第二互连层经无焊接合,且其中所述第三互连层及所述第四互连层经无焊接合。
4.根据权利要求3所述的半导体封装,其中所述第三互连层及所述第四互连层经由有机导电混合接合层混合接合。
5.根据权利要求1所述的半导体封装,其中所述第一互连层是混合接合层,且所述第二互连层是混合接合层。
6.根据权利要求5所述的半导体封装,其中所述第一衬底是层压衬底或印刷电路板。
7.根据权利要求6所述的半导体封装,其中所述第一衬底包括:
预浸布线层;
堆积布线层,其堆叠于所述预浸布线层上方,具有比所述预浸布线层更精细的间距及更精细的线宽;及
再钝化布线层,其在所述堆积布线层上方,具有比所述堆积布线层更精细的间距及更精细的线宽,
其中所述再钝化布线层包括有机导电混合接合层或无机导电混合接合层。
8.根据权利要求7所述的半导体封装,其进一步包括嵌入至少一无源装置、有源装置或光学组件处的多个预浸布线层。
9.根据权利要求1所述的半导体封装,其进一步包括集成于所述第一衬底的所述第二互连层、所述第三互连层或所述第二与所述第三互连层之间的结构中的至少一者中的至少一有源装置、无源装置或光学组件。
10.根据权利要求1所述的半导体封装,其中所述IC块包括以多层扇出结构布置的多个IC,其中所述多层扇出结构包括:
至少一第一IC及第二IC,其在第一扇出载体中;及
至少一第二扇出载体,其包括所述第一扇出载体上方的至少一第三IC,
其中所述第一扇出载体的至少一侧或所述第二扇出载体的至少一侧包括混合接合层,所述混合接合层具有沉积温度低于250℃的后段工艺BEOL氧化物或固化温度低于250℃且线宽/线间距L/S小于5μm/5μm的聚合物作为电介质。
11.一种半导体封装,其包括:
第一衬底,其包含:
第一互连层,其经配置用于混合接合到集成电路IC块或第二衬底,其中所述
第一互连层包括第一电介质及第一线宽;及
第二互连层,其与所述第一互连层相对,其中所述第二互连层包括第二电介质及第二线宽,
其中所述第一电介质与所述第二电介质相同或不同,且所述第一线宽与所述第二线宽相同或不同。
12.根据权利要求11所述的半导体封装,其中所述第一衬底是中介层,所述中介层具有(1)后段工艺BEOL氧化物或线宽/线间距L/S小于5μm/5μm的聚合物作为所述第一电介质及(2)L/S小于5μm/5μm的聚合物或BEOL氧化物作为所述第二电介质。
13.根据权利要求11所述的半导体封装,其中所述第一衬底是层压衬底,所述层压衬底具有(1)沉积温度低于250℃的后段工艺BEOL氧化物或固化温度低于250℃且线宽/线间距L/S小于5μm/5μm的聚合物作为所述第一电介质及(2)固化温度低于250℃且L/S小于5μm/5μm的聚合物或堆积膜作为所述第二电介质。
14.根据权利要求11所述的半导体封装,其中所述第一衬底是扇出衬底,所述扇出衬底具有(1)沉积温度低于250℃的后段工艺BEOL氧化物或固化温度低于250℃且线宽/线间距L/S小于5μm/5μm的聚合物作为所述第一电介质及(2)固化温度低于250℃且L/S小于5μm/5μm的聚合物或沉积温度低于250℃的BEOL氧化物作为所述第二电介质。
15.根据权利要求13所述的半导体封装,其中所述第一衬底进一步包括:
核心区段,其允许容纳无源装置或有源装置;
堆积区段,其堆叠于所述核心区段上方,具有比所述核心区段更精细的间距及更精细的线宽;及
再钝化区段,其位于所述堆积区段上方,具有比所述堆积区段更精细的间距及更精细的线宽,
其中所述再钝化区段的最外层形成所述第一互连层。
16.根据权利要求15所述的半导体封装,其中所述第一衬底的所述核心区段进一步包括电性连接所述第一互连层及所述第二互连层的电镀通孔。
17.根据权利要求11所述的半导体封装,其中所述第一衬底是印刷电路板,所述印刷电路板具有(1)沉积温度低于250℃的后段工艺BEOL氧化物或固化温度低于250℃且线宽/线间距L/S小于5μm/5μm的聚合物作为所述第一电介质及(2)固化温度低于250℃且L/S小于5μm/5μm的聚合物或堆积膜作为所述第二电介质。
18.一种半导体封装,其包括:
第一衬底,其包括:
预浸布线层,其具有大于10μm/10μm的最小线宽/线间距L/S;
第一堆积布线层,其位于所述预浸布线层的顶面上方,具有6μm/6μm到10μm/10μm之间的最小L/S;及
第一再钝化布线层,其位于所述第一堆积布线层的顶面上方,具有等于或小于2μm/2μm的最小L/S,
其中所述第一再钝化布线层由聚酰亚胺或氧化物组成以形成经配置以接合到集成电路IC块或另一衬底的第一互连层。
19.根据权利要求18所述的半导体封装,其进一步包括:
第二堆积布线层,其位于所述预浸布线层的底面下方;及
第二再钝化布线层,其位于所述第二堆积布线层的底面下方,其中所述第二再钝化布线层具有与所述第一再钝化布线层的所述L/S相同或不同的L/S且形成经配置用于接合到另一衬底的第二互连层。
20.根据权利要求19所述的半导体封装,其中所述第一互连层及所述第二互连层两者是混合接合层。
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