CN117334643A - 用于形成堆叠式晶体管器件的方法 - Google Patents

用于形成堆叠式晶体管器件的方法 Download PDF

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CN117334643A
CN117334643A CN202310785856.3A CN202310785856A CN117334643A CN 117334643 A CN117334643 A CN 117334643A CN 202310785856 A CN202310785856 A CN 202310785856A CN 117334643 A CN117334643 A CN 117334643A
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fin
channel
fin structure
forming
sacrificial
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S·苏布兰马尼安
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Interuniversitair Microelektronica Centrum vzw IMEC
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Interuniversitair Microelektronica Centrum vzw IMEC
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Abstract

公开了一种用于形成堆叠式晶体管器件的方法，其中形成纳米片场效应晶体管FET结构和鳍FET结构。该方法包括从垂直堆叠来形成第一鳍结构(110)和第二鳍结构(120)，其中第二鳍结构被布置在第一鳍结构上方，并且其中该垂直堆叠包括布置在第一和第二鳍结构之间的中间层(115)。该方法还包括从上方形成跨第二鳍结构的沟道区的栅极结构(122)，从下方形成跨第一鳍结构的沟道区的栅极结构(112)，以及形成第一和第二鳍的源极区和漏极区(114，124)。

Description

用于形成堆叠式晶体管器件的方法
技术领域
本公开涉及一种用于在半导体基板上形成包括纳米片场效应晶体管结构和鳍式场效应晶体管结构的堆叠式晶体管器件的方法。
背景技术
现代半导体集成电路技术包括水平沟道晶体管，如鳍式场效应晶体管(FinFET)和水平或横向纳米片场效应晶体管(NSHFET)。此类器件通常包括源极、漏极、由鳍状沟道层(在FinFET的情况下)或一个或多个水平延伸沟道纳米片(在NSHFET的情况下)组成的沟道，以及包围该沟道的栅极堆叠。
为了促进更具面积效率的电路系统，开发了堆叠式晶体管器件结构。堆叠式晶体管器件的示例是互补场效应晶体管(CFET)器件。CFET器件包括一对互补的FET，诸如一对相互堆叠的互补的NSHFET(例如，pFET底部器件和nFET顶部器件，或反之)。与pFET和nFET的传统并排布置相比，CFET器件允许降低占地面积。
使用所谓的“序贯”工艺，可以通过首先加工底部器件来形成包括底部和顶部NSHFET器件的CFET器件。底部器件的沟道纳米片的堆叠随后使用晶片接合工艺被接合在底部器件的顶部上。在加工上部沟道纳米片上的源极区和漏极区(例如，包括源极和漏极外延)之后，可以向上部沟道纳米片提供电连接到底部器件的栅极堆叠的栅极堆叠。
发明内容
虽然已经开发了形成堆叠式晶体管器件(诸如CFET器件)的方法，但现有的工艺通常被设计以形成包括相同沟道几何形状的底部和顶部器件(诸如NSHFET底部和顶部器件)的器件结构。然而，如发明人所认识到的，在某些情况下，底部和顶部器件的不同沟道几何形状可能提供经改进的器件性能。
鉴于上述，本发明概念的目标是提供一种使得能够形成包括纳米片场效应晶体管结构和鳍式场效应晶体管结构的堆叠式晶体管器件的方法。
根据一方面，提供了一种用于在基板上形成包括纳米片场效应晶体管(NSHFET)结构和鳍式场效应晶体管(FinFET)结构的堆叠式晶体管器件的方法，该方法包括：
形成包括布置在基板上的第一沟道结构、布置在第一沟道结构上的中间层以及布置在牺牲中间层上的第二沟道结构的垂直堆叠；
形成第一沟道结构的第一鳍结构和第二沟道结构的第二鳍结构；
从上方形成跨第二鳍结构的沟道区的栅极结构；
从下方形成跨第一鳍结构的沟道区的栅极结构；以及
形成第一鳍结构和第二鳍结构的源极区和漏极区；
其中第一鳍结构和第二鳍结构中的第一者包括沟道纳米片的堆叠，从而形成NSHFET结构；以及
其中第一鳍结构和第二鳍结构中的另一者包括沟道鳍，从而形成FinFET结构。
通过该方法，形成了包括FinFET结构和NSHFET结构的堆叠式晶体管器件。
这两个鳍结构，即第一鳍结构和第二鳍结构，可以在共同的图案化工艺中由沟道结构的垂直堆叠形成，从而允许FinFET结构和NSHFET结构相对于彼此垂直对准。这与例如序贯地形成的CFET器件相比是有利的，在序贯地形成的CFET器件中，顶部器件是借助于晶片接合工艺提供在底部器件的顶部上，而由此两个FET之间的对准受到接合工艺的对准精度的限制。利用本发明的方法，顶部FET结构的沟道区可以与底部器件自对准。
中间绝缘层在包括第一沟道结构和第二沟道结构的堆叠中的存在提供了在所得到的NSHFET和FinFET结构的沟道纳米片和沟道鳍之间的电分离。此外，中间绝缘层在加工期间提供第一沟道结构和第二沟道结构之间的分离，从而提供诸如在形成栅极结构和/或源极区/漏极区时有利于沟道结构的单独处理的垂直裕度。这可以从下面更详细地列出的方法的各种实施例中更好地理解。
由于该方法包括从沟道结构的公共堆叠来加工第一和第二鳍结构，因此该方法有助于形成可以被称为“单片”堆叠式晶体管器件。然而，与其他“单片”工艺相比，本方法涉及从堆叠的相对侧来加工源极区/漏极区和栅极结构，其中第二沟道结构是从上方加工的，第一沟道结构是从下方加工的，类似于可称为“序贯”的工艺。因此，本方法可以被称为“混合”工艺，利用了单片工艺和序贯工艺的优点。
尽管该方法可有利地用于形成CFET器件，但设想了该方法也可被用于形成可受益于包括NSHFET结构和FinFET结构的组合的其他非CFET类型的堆叠式晶体管器件。
术语和定义
本文所使用的术语“鳍结构”是指具有沿基板取向并从基板垂直突出的纵向尺寸的、包括单层或层堆叠的细长半导体结构。
“层堆叠”在此意指在彼此顶部顺序地形成的层结构。
术语“第一沟道结构”和“第二沟道结构”被理解成指布置在基板上的层堆叠的层或子堆叠，由此可以形成第一和第二鳍结构。因此，从中形成堆叠式晶体管器件的垂直堆叠可以包括第一沟道结构、第二沟道结构和布置在它们之间的中间层。
诸如“垂直”、“上部”、“下部”、“顶部”、“底部”、“堆叠在……顶部上”之类的相对空间术语在此被理解成表示在堆叠式晶体管器件的参照系内的位置或方向。具体而言，这些术语可以相关于基板的法线方向来理解，或者等效地相关于器件层堆叠的自底向上方向来理解。相应地，诸如“横向”和“水平”等术语应理解成平行于基板的位置或方向，即平行于基板的上表面或主延伸平面。
第一和第二鳍结构可以通过使用硬掩模作为蚀刻掩模来图案化垂直堆叠来被形成。因此，诸鳍结构可以在共同的图案化工艺中被精确且高效地形成。
在一些实施例中，纳米片堆叠可包括与纳米片相交替的若干牺牲纳米片，并且该方法还可包括在形成源极区和漏极区之后，从沟道区选择性地去除牺牲纳米片部分并随后形成栅极结构。由此，沟道纳米片可以被“释放”，使得随后栅极结构也可以被形成在沟道纳米片之间的空间中。因此，栅极结构可形成相对于沟道纳米片的环绕栅极。
在一些实施例中，该方法还包括在选择性地去除牺牲纳米片部分之前，形成延伸跨过纳米片堆叠的至少一个锚结构，并且其中在去除牺牲纳米片部分时，纳米片被该锚结构锚定。锚结构可以通过在纳米片堆叠上沉积一层或多层的锚材料层结构并图案化锚材料层结构以形成锚结构来被形成。因此，锚材料层结构可被形成为与每个纳米片接触(即邻接)，在去除该堆叠的牺牲纳米片期间提供支撑。
在一些实施例中，在释放沟道纳米片之后，可以跨纳米片部分形成牺牲栅极结构。在形成源极区和漏极区之后，可以用最终栅极结构来替换牺牲栅极结构。因此，栅极结构可以根据替代金属栅极(RMG)工艺来形成。牺牲栅极结构使源极区/漏极区中的每一者以及最终功能栅极结构能够相对于沟道区自对准。
在一些实施例中，中间层可以是牺牲中间层，其由将第一和第二鳍结构分隔开的介电绝缘层来替换。初始的牺牲中间层可以与第一和第二沟道结构同时形成，例如使用Si和/或SiGe的外延生长，其成分允许相对于第一和/或第二沟沟道结构被选择性蚀刻。牺牲中间层可以被隔离氧化物(诸如SiO2)替换。
在一些实施例中，可以在“修整”工艺中减小沟道鳍的宽度，在该工艺中，沟道鳍的横向侧壁被蚀刻以提供更薄的沟道鳍。修整可以在牺牲中间层已经被介电绝缘层替换之后执行。此外，沟道鳍高度可以在蚀刻或CMP工艺中被降低。沟道鳍的修整可被执行以更改所得到的FinFET的电性能，并使该性能与NSHFET的性能相匹配。
在一些实施例中，该方法还可以包括将基板翻转以允许从基板的背面进行加工。因此，翻转基板允许从下方加工第一鳍结构的沟道区处的栅极结构。该方法可以包括在第二鳍结构上方形成接合层，并将载体晶片接合到接合层。载体晶片可以被用于翻转或转动基板。翻转可以例如在形成第二鳍结构处的源极区/漏极区和栅极结构之后执行。
因此将明白，在本公开的上下文中，可以根据基板的正面和背面来描述基板，其中第二晶体管结构可以至少部分地从正面加工，而第一晶体管结构可以至少部分地从背面加工。“从背面”加工也可以称为“从下方”，无论基板是否已翻转。
在一些实施例中，其中第一鳍结构包括沟道鳍且第二鳍结构包括沟道纳米片的堆叠，该方法还可包括：
形成加工层，所述加工层嵌入有第一鳍结构和第二鳍结构；
从下方蚀刻第一鳍结构以在加工层中形成槽；
在槽的相对侧表面上形成间隔物，以在间隔物之间形成经宽度减小的间隙；
通过使用间隔物作为保护第一鳍结构的下部的蚀刻掩模，在经宽度减小的间隙中回蚀第一鳍结构，来拆分第一鳍结构；以及
移除加工层及间隔物以暴露第一鳍结构的剩余部分，从而形成第一沟道鳍及第二沟道鳍。
通过该方法，可以提供双鳍FET结构。有益地，将鳍的数量从一增加到二可以是增大鳍高度以达到FinFET的所需电性能的替换方案。
通过将鳍结构嵌入在加工层中并随后将鳍结构开槽到加工层中，在加工层中形成的间隙可以相对于鳍结构自对准。在加工层中在间隙的相对侧表面上的间隔物层的随后形成允许(经自对准的)间隙的宽度被修整(即，沿跨鳍结构的方向所见)，使得鳍结构可以通过该鳍结构的上表面的所暴露出的中心部分的回蚀而被拆分成两个沟道鳍。相对于下方沟道纳米片，所述自对准也可相应地被赋予沟道鳍。间隔物层可以形成具有精确且均匀的厚度，例如使用共形侧壁间隔物沉积工艺，其中两个沟道鳍可被形成具有基本均匀的宽度。
在一些实施例中，第一鳍结构可包括蚀刻停止层，从而允许蚀刻第一鳍以形成槽，以在蚀刻停止层被暴露时停止。蚀刻停止层可以是布置在从中形成第一鳍结构的沟道堆叠中的单独层。另选地，蚀刻停止功能可以由在其上布置有第一鳍结构的中间层提供。
在一些实施例中，其中形成源极区和漏极区包括在沟道纳米片的相对端表面上形成第一导电类型的外延源极主体和漏极主体，以及在沟道鳍的相对端表面上形成第二导电类型的外延源极主体和漏极主体。这使得能够形成互补电导率类型的NSFET和FinFET。
在一些实施例中，沟道纳米片是由SiGey形成的，而沟道鳍是由SiGez形成的，其中y和z中的每一者都大于或等于0，并且其中y不同于z。因此可以形成基于Si和基于SiGe的堆叠式晶体管结构。
在一些实施例中，下部沟道纳米片可以是Si(y＝0)，而上部沟道层可以是SiGe的(z≥0.15)，其中该方法可包括在沟道区的沟道纳米片部分的相对端表面上形成n型外延源极主体和漏极主体，以及在沟道区的沟道鳍部分的相对端表面上形成p型外延源极主体和漏极主体。
在一些实施例中，牺牲纳米片由SiGex形成，其中x大于或等于0，并且y不同于x和z。
牺牲纳米片和下部沟道纳米片的不同锗含量(x≠y)使得能够进行牺牲纳米片部分从沟道区的上述选择性去除。
在一些实施例中，其中初始中间层是布置在第一和第二鳍结构之间的牺牲中间层，牺牲中间层可以是SiGe，其Ge成分不同于沟道鳍、沟道纳米片和牺牲纳米片中的至少一者，以允许选择性地去除牺牲中间层。在一些示例中，牺牲中间层可以具有与牺牲纳米片中的一者相类似的Ge成分，以允许在同一蚀刻工艺中去除牺牲中间层和牺牲纳米片。
附图说明
通过参考附图的说明性和非限制性的以下详细描述，可更好地理解以上以及其他目的、特征和优点。在附图中，除非另有说明，否则相似的附图标记将用于相似的元件。
图1a-i示出了根据一些实施例的用于形成布置在若干沟道纳米片上方的沟道鳍的方法。
图2a-d示出了根据一些实施例的用于形成布置在沟道鳍上方的若干沟道纳米片的方法。
图3a-h示出了根据一些实施例的用于形成在若干沟道纳米片上方的两个沟道鳍的方法。
具体实施方式
以下将参考附图描述根据若干实施例的用于形成包括NSHFET结构和FinFET结构的堆叠式晶体管器件(诸如CFET器件)的方法。
在图1a中，鳍结构已被形成在基板100上。基板100可以是适合于CMOS加工的常规半导体基板。基板100可以是单层半导体基板，例如由诸如Si基板、锗(Ge)基板或硅锗(SiGe)基板之类的块状基板形成。然而，多层/复合基板也是可能的，诸如在块状基板上的外延地生长的半导体层或绝缘体上半导体(SOI)基板，诸如绝缘体上Si基板、绝缘体上Ge基板或绝缘体上SiGe基板。
鳍结构由细长的鳍形层堆叠形成，该鳍形层堆叠具有沿基板100在第一水平方向上取向的纵向尺寸并在垂直方向上从基板100突出。鳍结构的宽度尺寸被取向在横向于第一水平方向的第二水平方向上。
鳍结构在自下而上的方向上包括下部鳍结构110(也称为第一鳍结构110)、布置在第一沟道结构上的牺牲中间层115’和布置在牺牲中间层115’上方的上部鳍结构120，所述牺牲中间层115’可以被下文将要讨论的最终介电隔离层115替换。上部鳍结构120也可以被称为第二鳍结构120。蚀刻停止层118和隔离层119可被设置在第一鳍结构110和基板100之间，以便于后续加工。
在图1a中，第一鳍结构110包括将从中形成FinFET结构的沟道鳍层116，而第二鳍结构120包括将从中形成NSHFET结构的沟道纳米片126的堆叠。沟道纳米片126的堆叠与牺牲纳米片127相交替地布置，如沿着垂直方向所见。如图所示，第二鳍结构120布置在第一鳍结构110上方，牺牲中间层115’位于第一鳍结构110和第二鳍结构120之间。然而，其他配置也是可能的，如下面结合图2a-d所讨论的。
第二上部鳍结构120的牺牲纳米片127由与沟道纳米片126的半导体材料(“纳米片沟道材料”)不同的半导体材料(“牺牲材料”)形成，并被选择成可相对于沟道材料被选择性地去除。如本文所使用的，与材料或特征(例如层或层部分)的去除相结合的术语“选择性”是指该材料或特征是使用蚀刻工艺以大于暴露于该蚀刻工艺的另一材料/特征的速率来蚀刻该材料/特征以被去除/可去除。下部第一鳍结构110的鳍116可以由不同于纳米片沟道材料的半导体材料(“鳍沟道材料”)形成。然而，设想了纳米片沟道材料和鳍沟道材料可以是相同的材料或不同的材料。
牺牲纳米片材料可以是SiGex，纳米片沟道材料可以是SiGey，且鳍沟道材料可以是SiGez，其中x、y、z中的每一者都≥0，y≠x，y≠z。例如，x≥y+d且z≥y+d，其中d＝0.15。牺牲材料和纳米片沟道材料的Ge含量的0.15差异可促进牺牲材料相对于纳米片沟道材料的选择性去除。例如，纳米片沟道材料的Ge含量可以是0(即Si，x＝0)，牺牲纳米片材料的Ge含量可以在0.15～0.45之间的范围，而鳍沟道材料的Ge含量可以在0.15～0.65之间的范围，诸如0.15到0.45。例如，可以使用基于HCl的干法蚀刻来选择性地(即，以更大的速率)蚀刻具有比另一Si或SiGe材料更大的Ge浓度的SiGe层。另一示例是包括过氧化氨混合物(APM)的蚀刻化学。然而，允许相对于较低Ge含量的SiGe(或Si层)材料来选择性地蚀刻较高Ge含量的SiGe材料的其他适当的蚀刻工艺(干法或湿法)本身是本领域已知的，并且也可以被用于此目的。
纳米片沟道材料Si和鳍沟道材料SiGe适用于包含n型NSHFET和p型FinFET的CFET器件。更一般而言，纳米片和鳍沟道材料的Ge含量来可被选择来优化NSHFET和FinFET器件的沟道特性。虽然Si作为纳米片沟道材料和SiGe作为鳍沟道材料可分别促进形成n型NSHFET结构和p型FinFET结构，但设想该方法也可应用于包括SiGe作为纳米片沟道材料、Si作为牺牲纳米片材料和Si作为鳍沟道材料的鳍结构。
沟道纳米片126和牺牲纳米片127可以各自形成宽度(在水平平面中)与厚度(沿垂直方向)之比大于1，诸如宽度在10nm至30nm的范围内，而厚度在3nm至10nm的范围内。沟道鳍116可被形成为厚度大于每一沟道纳米片126的厚度，诸如至少两倍于沟道纳米片116的厚度。沟道鳍116可被形成为具有在20至50nm范围内的厚度。
虽然图1a示出了包括三个沟道纳米片126的第二鳍结构120，但是沟道纳米板126的数量可以不同于所描绘的示例。例如，第二鳍结构120可包括与牺牲纳米片127相交替地布置的更多数量的沟道纳米片126，诸如四个或五个或更多个。具体而言，每一沟道纳米片126可以被布置在一对牺牲层127之间。
牺牲纳米片127、沟道纳米片126和沟道鳍116可以各自形成为外延层，即使用外延生长或沉积工艺形成的层。
初始中间层115’可以是由Si或Ge或其组合物形成的牺牲层，其Ge(或Si)含量允许相对于纳米片沟道材料或鳍沟道材料或这两者被选择性地去除。然后可以用绝缘层替换经去除的牺牲层，该绝缘层包括诸如氧化物或氮化物之类的绝缘材料。例如，中间绝缘层115可以由SiO2、SiN或SiCN形成。中间绝缘层115可被例如形成为具有在20至50nm范围内的厚度。
虽然被称为并解说为单个层，但中间层115也可被形成为包括例如两个或更多个不同绝缘层的堆叠的复合层结构。
第一鳍结构110和第二鳍结构120可以从初始垂直堆叠形成，该初始垂直堆叠可以在基板100上外延地生长并被图案化成鳍结构110、120。初始堆叠的图案化可以包括沉积并随后图案化硬掩模层以形成硬掩模(未示出)。可以使用传统的鳍图案化技术，例如诸如光刻和蚀刻(“litho-etch”)的单一图案化技术或者诸如(litho-etch)x、自对准双重或四重图案化(SADP或SAQP)的多重图案化技术)。然后可以通过使用硬掩模作为蚀刻掩模进行蚀刻来将由硬掩模限定的图案转移到初始堆叠中。
在图1b中，通过选择性地去除中间牺牲层115’并随后用绝缘材料填充所得到的细长空腔以形成中间绝缘层115，第一鳍结构110和第二鳍结构120之间的牺牲中间层115’已被替换成介电绝缘材料，诸如氧化物或氮化物，诸如SiO2或SiN，并且如图1b中的示例所示，加工层150嵌入有第一鳍结构110和第二鳍结构120。
图1c示出了在沟道纳米片126的沟道部处形成第二栅极结构122’之后的第二鳍结构120。第二栅极结构122’可以是在替换金属栅极(RMG)工艺中涉及的牺牲栅极结构122’，或者是最终栅极结构122。此外，栅极触点123已被经形成，从而允许从上方接触栅极结构122。
在形成牺牲栅极结构122’之前，牺牲纳米片127的一部分已被从沟道区去除，从而在沟道区中限定经释放或悬浮的沟道纳米片部分126。可以使用对牺牲纳米片127的牺牲材料具有选择性的蚀刻工艺。例如，可以使用HCl或APM来相对于Si纳米片沟道材料(或Ge含量低于SiGe牺牲材料的SiGe沟道材料)选择性地去除SiGe牺牲材料。包括延伸跨过第二鳍结构120的一个或多个细长支撑结构(例如，形成中间层116的一条或多条线或非晶Si或绝缘材料)的临时支撑结构可被用于在去除牺牲纳米片127期间支撑沟道纳米片126。临时支撑结构也可以被称为锚结构，并且牺牲纳米片127的去除是“鳍释放”过程。
通过释放纳米片的一部分，栅极结构122可以环绕沟道纳米片126。在采用RMG工艺的情况下，在加工的稍后阶段，诸如在形成源极区/漏极区之后，牺牲栅极结构122’被替换成最终栅极结构122。最终栅极结构122可以包括栅极介电层、一个或多个有效功函数金属(WFM)层和栅极填充金属。栅极介电层可以由常规高k电介质形成，例如HfO2、HfSiO、LaO、AlO或ZrO。WFM层可以由一个或多个有效WFM(例如，诸如TiAl或TiAlC之类的n型WFM和/或诸如TiN或TaN之类的p型WFM)形成。栅极填充金属可由常规栅极填充金属(例如W、Al、Co或Ru)形成。栅极介电层和第一WFM可以通过ALD来被沉积。栅极填充金属可以例如通过CVD或物理气相沉积(PVD)来被沉积。在沉积后，可以使用金属回蚀工艺将栅极堆叠开槽，以提供具有所需垂直尺寸的功能栅极结构。
在形成最终栅极结构122之前，以及在RMG工艺中形成牺牲栅极结构122’之后，源极区/漏极区124可以通过在沟道纳米片124的暴露于沟道区和牺牲栅极结构122’两侧处的部分的端表面上外延地生长半导体源极主体/漏极主体来被形成。形成在沟道纳米片126上的源极主体/漏极主体124可被原位掺杂，并且所得的结构如图1d所示，图1d是沿图1c中的线A-A’的截面。
为了允许从下方加工第一鳍结构110，载体晶片162可被接合到形成在第二鳍结构120上方的接合层161，基板100被翻转，如图1e所示。
在图1f中，基板100已被去除，例如借助于在CMP工艺中对基板100进行平坦化和开槽，并且沟道鳍116被回蚀到加工层150中。蚀刻可以在若干步骤中执行，使用一个或若干个蚀刻停止层118来实现更精确的工艺控制并降低过蚀刻的风险。之后，加工层150可以被回蚀以暴露出沟道鳍116，如图1g所示，沟道鳍116可以从加工层150的表面垂直突出。
现在可以对沟道鳍116进行修整(即，沿着跨沟道鳍的方向所见)，使得与沟道纳米片126的宽度相比，鳍的宽度被减小，如图1h所示。这可以通过使用蚀刻沟道116的侧表面的各向异性蚀刻工艺来蚀刻沟道鳍116来实现。
此后，牺牲栅极结构112’可被形成在沟道鳍116的沟道区上，从而允许通过在沟道鳍116的、在沟道区和牺牲栅极结构112’的两侧处暴露出的部分的端表面上外延地生长半导体源极主体/漏极主体来形成源极区/漏极区114。
图1i是沿图1h中线A-A’的截面，示出了如上所述的沟道鳍116的沟道区的源极区/漏极区114、124和沟道纳米片126。此外，牺牲栅极结构112’、122’已被替换成最终栅极结构112、122。
现在将参考图2a-d讨论替换配置。第一鳍结构110、第二鳍结构120和中介中间层115以及它们的加工可以类似于上面描述的。然而，在该替换配置中，沟道鳍116和沟道纳米片126的堆叠次序被反转。因此，最靠近基板100布置的第一鳍结构110包括沟道纳米片126的堆叠，而布置在第一鳍结构110和牺牲中间层115’上方(从基板来看)的第二鳍结构120包括沟道鳍116。
在图2b中，牺牲中间层115’已被替换成隔离材料层115和嵌入在加工层150中的鳍结构116、126，类似于上面参考图1b所描述的。然后可以在蚀刻工艺中从上方加工第二鳍结构120，其中加工层150被回蚀以暴露出沟道鳍116。结果如图2c所示，示出了从加工层150的表面突出的沟道鳍116。此后，可以对沟道鳍116进行类似于结合图1h所讨论的修整或减薄工艺的修整或减薄工艺，从而得到图2d所示的经减小的宽度。
在随后的加工步骤中，载体晶片可以被接合在第一鳍结构110上方，并且基板被翻转以允许从下方加工第二鳍结构120。在该加工中，沟道纳米片126可被释放，牺牲栅极结构被形成，并且源极区/漏极区以与上文参考图1c和图1d所述类似的方式生长。
现在将参考图3a-h讨论本发明方法的另一示例，其中包括多于一个沟道鳍116的FinFET结构从包括沟道纳米片126的堆叠的第一鳍结构110形成。第一鳍结构110、第二鳍结构120和中介中间层115以及它们的加工可以类似于上面描述的，除了下文讨论的一些差异之外。
图3a示出了叠层结构，类似于图1a中从中形成鳍结构110、120的叠层结构。然而，在本附图中，鳍图案化工艺已经停止在第一鳍结构110的诸层上方，使得仅限定第二上部鳍结构120。因此，第一鳍结构110和中间(牺牲)层115’在图案化工艺中被蚀刻，而下方的沟道鳍层116以及蚀刻停止层118基本上保持完整。
此外，间隔物材料层被共形地沉积在第二沟道结构120上并随后被蚀刻，使得离散的间隔物层182保留在牺牲中间层115’的相对侧表面上以及沟道纳米片126和牺牲纳米片127的堆叠上。间隔物材料层可以是例如ALD沉积的氮化物或碳化物，例如SiN、SiCO、SiOCN或SiC。可以使用各向异性蚀刻工艺(诸如反应性离子蚀刻)来将间隔物材料层回蚀(例如，自上而下，在垂直地朝向基板100)。
在图3b中，包括沟道鳍116和可选的上部蚀刻停止层118a的第一鳍结构110的各层已经通过在使用间隔物层180作为蚀刻掩模的同时回蚀沟道鳍层116的所暴露的上表面而被图案化。蚀刻可以停止在下部蚀刻停止层118b上。由此，在基板100上形成了两个垂直对准的鳍结构110、120，其中第一鳍结构110比第二上部鳍结构120宽。
在图3c中，牺牲中间层115’已被替换成介电绝缘层115和嵌入在加工艺层150中的鳍结构110、120，类似于上面参考图1b所描述的。此后，如在研究图3d时所明白的，沟道纳米片126可以在鳍释放工艺中被释放，并被设置有牺牲栅极122’，类似于上面参考图1c所描述的。该栅极限定工艺之后可以进行源极/漏极形成工艺，其结果类似于图1d中的结果。
在图3e中，基板100已被上下翻转，以允许从下方加工第一鳍结构110。类似于上文所描述的，翻转可以包括将载体晶片(未示出)接合在第二鳍结构120上方。基板100以及下部蚀刻停止层118b可以被去除以允许从下方暴露出沟道鳍116。基板100和下部蚀刻停止层118b可以例如被平坦化和开槽(例如通过CMP)，而对加工层150的选择性蚀刻可被采用来暴露出沟道鳍116。这种选择性蚀刻工艺的结果如图3f所示，其中鳍结构110的槽已经停止在隔离层116上。在图3g中，通过经由形成在加工层150中的间隙回蚀第一鳍结构层堆叠的所暴露的上表面，同时使用形成在加工层150中的间隙的相对侧表面上的间隔物层180，沟道鳍116已经被拆分。间隔物层180可以与上面结合图3a和b讨论的间隔物层182类似地配置。因此，两个子鳍结构已被形成在中间绝缘层115上，包括各自的沟道鳍116。可以使用各向异性蚀刻工艺并使用中间绝缘层115作为蚀刻停止层来回蚀第一鳍结构110。如可明白的，可以通过间隔物层180的厚度来控制沟道鳍116的最终宽度，其中较大的厚度导致加工层中的间隙的宽度较减小，并且沟道鳍180的宽度相应地增加。在图3h中，在拆分沟道鳍116之后，间隔物层180以及隔离材料119已经被去除，例如采用对其具有选择性的蚀刻工艺。图3h相应地描绘了所得到的经加工的半导体器件，包括第二鳍结构120、中间绝缘层115和包括两个上部沟道鳍116的第一鳍结构120。该器件随后可以被进一步加工以形成用于第二鳍结构120的栅极结构以及源极区和漏极区，以形成与NSHFET垂直对准的两个FinFET。在上文中，主要参考有限数量的示例描述了本发明构思。然而，如本领域技术人员容易理解的，在由所附权利要求书限定的本发明构思的范围内，除了上面公开的示例以外的其他示例同样是可能的。

Claims (12)

1.一种用于在基板(100)上形成包括纳米片场效应晶体管FET结构和鳍FET结构的堆叠式晶体管器件的方法，包括：
从布置在所述基板上的垂直堆叠来形成第一鳍结构(110)和第二鳍结构(120)，其中所述第一鳍结构被布置在所述基板上，并且所述第二鳍结构被布置在所述第一鳍结构上方，并且其中所述垂直堆叠包括布置在所述第一鳍结构和所述第二鳍结构之间的中间层(115)；
从上方形成跨所述第二鳍结构的沟道区的栅极结构(122)；
从下方形成跨所述第一鳍结构的沟道区的栅极结构(112)；以及
形成所述第一鳍结构和所述第二鳍结构的源极区和漏极区(114，124)；
其中所述第一鳍结构和所述第二鳍结构中的第一者包括沟道纳米片(126)的堆叠，从而形成所述纳米片FET结构；以及
其中所述第一鳍结构和所述第二鳍结构中的另一者包括沟道鳍(116)，从而形成所述鳍FET结构。
2.根据权利要求1所述的方法，其特征在于，所述纳米片堆叠还包括与所述纳米片相交替的若干牺牲纳米片(127)，并且所述方法还包括在形成所述源极区和所述漏极区之后，从所述沟道区选择性地去除牺牲纳米片部分并随后形成所述栅极结构。
3.根据权利要求2所述的方法，其特征在于，所述方法还包括在选择性地去除所述牺牲纳米片部分之前，形成延伸跨过所述纳米片堆叠的至少一个锚结构，并且其中在所述牺牲纳米片部分被去除时，所述纳米片被所述锚结构锚定。
4.根据权利要求2或3所述的方法，其特征在于，还包括在选择性地去除所述牺牲纳米片部分之后，形成跨所述纳米片部分的牺牲栅极结构，并且在形成所述源极区和所述漏极区之后，用所述栅极结构替换所述牺牲栅极结构。
5.根据前述权利要求中任一项所述的方法，其特征在于，所述中间层是牺牲中间层，并且其中所述方法还包括用将所述第一鳍结构和所述第二鳍结构分开的介电绝缘层来替换所述牺牲中间层。
6.根据前述权利要求中的任一项所述的方法，其特征在于，还包括：
在替换所述牺牲中间层之后，减小所述沟道鳍的宽度。
7.根据前述权利要求中的任一项所述的方法，其特征在于，还包括：
在所述第二鳍结构上方形成接合层(161)；
将载体晶片(162)接合到所述接合层；以及
翻转所述基板，以允许从所述基板的背面进行加工。
8.根据前述权利要求中任一项所述的方法，其特征在于，所述第一鳍结构包括所述沟道鳍，并且所述第二鳍结构包括沟道纳米片的堆叠，其中所述方法还包括：
形成加工层(150)，所述加工层嵌入有所述第一鳍结构和所述第二鳍结构；
从下方蚀刻所述第一鳍结构以在所述加工层中形成槽；
在所述槽的相对侧表面上形成间隔物(180)，以在所述间隔物之间形成经宽度减小的间隙；
通过使用所述间隔物作为保护所述第一鳍结构的下部的蚀刻掩模，在经宽度减小的间隙中回蚀所述第一鳍结构，来拆分所述第一鳍结构；以及
移除所述加工层及所述间隔物以暴露所述第一鳍结构的剩余部分，从而形成第一沟道鳍及第二沟道鳍。
9.根据权利要求8所述的方法，其特征在于，所述第一鳍结构还包括蚀刻停止层(118)，并且其中蚀刻所述第一鳍结构以形成所述槽包括回蚀所述第一鳍结构直到所述蚀刻停止层被暴露。
10.根据前述权利要求中的任一项所述的方法，其特征在于，形成所述源极区和所述漏极区包括在所述沟道纳米片的相对端表面上形成第一导电类型的外延源极主体和漏极主体，以及在所述沟道鳍的相对端表面上形成第二导电类型的外延源极主体和漏极主体。
11.根据前述权利要求中的任一项所述的方法，其特征在于，所述沟道纳米片是由SiGey形成的，且所述沟道鳍是由SiGez形成的，其中y和z中的每一者都大于或等于0，并且其中y不同于z。
12.根据权利要求11所述的方法，当引用权利要求2时，所述牺牲纳米片是由SiGex形成的，其中x大于或等于0并且y不同于x和z。
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