CN117334563A - Semiconductor device and method for manufacturing the same - Google Patents

Semiconductor device and method for manufacturing the same Download PDF

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Publication number
CN117334563A
CN117334563A CN202210718468.9A CN202210718468A CN117334563A CN 117334563 A CN117334563 A CN 117334563A CN 202210718468 A CN202210718468 A CN 202210718468A CN 117334563 A CN117334563 A CN 117334563A
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layer
semiconductor
region
isolation
gate
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黄猛
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Changxin Memory Technologies Inc
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Changxin Memory Technologies Inc
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Priority to CN202210718468.9A priority Critical patent/CN117334563A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/401—Multistep manufacturing processes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42356—Disposition, e.g. buried gate electrode

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

The embodiment of the disclosure provides a method for manufacturing a semiconductor device, which is characterized in that a first gap is formed in a first region of a stacked layer before a gate is formed, a gate material can be introduced from the side surface of the first gap (along a second direction and a third direction) and deposited on a gate dielectric layer of a semiconductor column, so that the uniformity of gate deposition can be improved, the occurrence of gate disconnection caused by insufficient introduction of the gate material is avoided, and the influence on the subsequent process and the reliability of the semiconductor device due to gate defects is avoided. In addition, in the method for manufacturing the semiconductor device provided by the embodiment of the disclosure, the spacer layer is formed on the semiconductor column first, and then the gate is formed, so that the width of the gate can be controlled by adjusting the width of the spacer layer, further the control of the length of the transistor channel region is realized, and the reliability of the semiconductor device is improved.

Description

Semiconductor device and method for manufacturing the same
Technical Field
The present disclosure relates to the field of integrated circuits, and more particularly, to a semiconductor device and a method of fabricating the same.
Background
A dynamic random access memory (Dynamic Random Access Memory, DRAM) is a semiconductor device commonly used in electronic equipment such as a computer, and is composed of a plurality of memory cells each typically including a transistor and a capacitor. The gate electrode of the transistor is electrically connected with the gate electrode, the source electrode is electrically connected with the bit line, the drain electrode is electrically connected with the capacitor, and the gate voltage on the gate electrode can control the on and off of the transistor, so that the data information stored in the capacitor can be read through the bit line or written into the capacitor.
With the continuous development of semiconductor chips, the critical dimensions thereof have been reduced, but the reduction of the dimensions of the photolithographic patterns on the semiconductor chips has a limit due to the limitations of the structures of the photolithographic tools themselves, and for this reason, semiconductor devices such as DRAMs having three-dimensional structures have been developed. However, since the performance such as stability of semiconductor devices such as DRAM having a three-dimensional structure cannot meet the requirements, how to improve the performance of semiconductor devices and expand the application field of semiconductor devices is a technical problem to be solved at present
Disclosure of Invention
The embodiment of the disclosure provides a semiconductor device and a preparation method thereof, which can improve the reliability of the semiconductor device.
The embodiment of the disclosure provides a method for manufacturing a semiconductor device, which comprises the following steps: forming a stacked layer on a surface of a substrate, wherein the stacked layer comprises a plurality of semiconductor layers and isolation layers which are stacked and arranged along a first direction, the semiconductor layers comprise a plurality of semiconductor columns which extend along a second direction and are arranged at intervals along a third direction, a part of surfaces of the semiconductor columns are exposed in a first area of the stacked layer, the other part of the surfaces of the semiconductor columns are covered by the isolation layers, a first gap is formed between the isolation layers adjacent to the surfaces of the semiconductor columns, the first direction is a direction vertical to the surface of the substrate, the second direction and the third direction are both directions parallel to the surface of the substrate, and the second direction is intersected with the third direction; introducing a gate material from the side surface of the first gap to form a gate electrode, wherein the gate material is deposited on the exposed surface of the semiconductor column, a second gap is formed between the gate electrodes deposited adjacent to the surface of the semiconductor column, the gate electrode extends along the third direction, and a semiconductor column region corresponding to the gate electrode is used as a channel region; and filling insulating materials in the first gap and the second gap to form an insulating layer.
In one embodiment, the step of forming a stacked layer on the surface of the substrate further comprises: forming an initial stacked layer on the surface of the substrate, wherein the initial stacked layer comprises a plurality of semiconductor layers and a sacrificial layer which are stacked and arranged along a first direction, a plurality of first sub-isolation layers vertically penetrating through the initial stacked layer along the first direction are arranged in the initial stacked layer, the first sub-isolation layers extend along the second direction, and the plurality of first sub-isolation layers are arranged at intervals along the third direction so as to divide the semiconductor layer into a plurality of semiconductor columns; removing a portion of the sacrificial layer from the side surface of the first region in the first region, the surface of the semiconductor pillar being exposed; forming the spacer layer, wherein the spacer layer covers the exposed surface of the semiconductor column; removing the sacrificial layer to form a groove, wherein the surface of the semiconductor column covered by the sacrificial layer is exposed in the first region; filling a second sub isolation layer in the groove; and removing the first sub-isolation layer and the second sub-isolation layer in the channel region, wherein the rest of the first sub-isolation layer and the second sub-isolation layer are used as the isolation layers together.
In one embodiment, the step of forming the initial stacked layer on the substrate surface further comprises: forming a plurality of initial semiconductor layers and sacrificial layers stacked and arranged along a first direction on the surface of the substrate; patterning the initial semiconductor layer and the sacrificial layer to form a plurality of isolation trenches, wherein the isolation trenches vertically penetrate through the initial stacked layer along the first direction, extend along the second direction and are arranged at intervals along the third direction; and filling isolation materials in the isolation trenches to form the first sub-isolation layers.
In an embodiment, in the step of filling the isolation trench with an isolation material to form the first sub-isolation layer, the first sub-isolation layer further covers a surface of the initial stacked layer, and in the step of removing a portion of the sacrificial layer from a side surface of the first region, the first sub-isolation layer covering the surface of the initial stacked layer is partially removed.
In an embodiment, the step of forming the spacer layer, the spacer layer covering the exposed surface of the semiconductor pillar further comprises: depositing a spacer material in the first region, wherein the spacer material covers the exposed surface of the semiconductor column and the end face of the sacrificial layer; the step of filling the second sub-isolation layer in the trench further comprises: in the first region, the second sub-isolation layer also fills the gaps between the spacer materials; the step of removing the first sub-isolation layer and the second sub-isolation layer in the channel region further comprises: removing the side wall of the spacer material to expose the second sub-isolation layer, and taking the rest spacer material as the spacer layer; and removing the second sub-isolation layers between the isolation layers to form the first gaps.
In an embodiment, in the step of passing gate material from the first void side at the first region, at least the first void is exposed at the first region side.
In one embodiment, the spacer layer is silicon nitride and the gate material is titanium nitride.
In an embodiment, further comprising: and forming a supporting layer in the stacking layer, wherein the supporting layer penetrates through the stacking layer along the first direction, is arranged at the edge of the first region and covers the semiconductor column.
In an embodiment, the stacked layer further includes a word line region, where the word line region and the first region are arranged along the third direction, the semiconductor pillars extend along the second direction and the third direction and are spaced apart along the first direction, and in the step of introducing the gate material from the side of the first space in the first region, the gate material covers the surface of the semiconductor pillars in the word line region, and has a third space between adjacent word lines as the word line; and filling insulating materials in the first gap and the second gap, wherein in the step of forming an insulating layer, the insulating materials are filled in the third gap in the word line region.
The embodiment of the disclosure also provides a semiconductor device prepared by adopting the preparation method, which comprises: a substrate; a stacked layer disposed on the substrate, the stacked layer including a plurality of semiconductor layers and isolation layers stacked and arranged along a first direction, the semiconductor layers including a plurality of semiconductor pillars extending along a second direction and arranged at intervals along a third direction, the semiconductor pillars also being isolated by the isolation layers in the third direction, the stacked layer including a first region, the first direction being a direction perpendicular to a surface of the substrate, the second direction and the third direction both being directions parallel to the surface of the substrate, and the second direction intersecting the third direction; a spacer layer disposed in the first region and covering a portion of a surface of the semiconductor pillar; a gate electrode arranged in the first region and covering the other part of the surface of the semiconductor column, wherein the semiconductor column region corresponding to the gate electrode is used as a channel region; and an insulating layer disposed between adjacent gates and between adjacent spacers.
In an embodiment, the semiconductor device further includes a supporting layer penetrating through the stacked layer along the first direction, and the supporting layer is disposed at an edge of the first region and wraps the semiconductor pillar.
In an embodiment, the gate is disposed at an end of the first region facing the support layer, and the spacer layer is disposed at an end of the first region facing away from the support layer.
In one embodiment, the thickness of the gate is 2-30 nm.
In an embodiment, the stacked layer further includes a word line region, where the word line region and the first region are arranged along the third direction, and the semiconductor pillars extend along the second direction and the third direction and are spaced apart in the first direction; and word lines covering the surfaces of the semiconductor columns, and the insulating layers are arranged between adjacent word lines.
In an embodiment, the supporting layer is in a grid shape, and the material of the supporting layer is silicon nitride.
According to the semiconductor device and the preparation method thereof, before the grid electrode is formed, the first gap is formed in the first region of the stacked layer, and the grid electrode material can be introduced from the side face of the first gap (along the second direction and the third direction) and deposited on the semiconductor column, so that the uniformity of grid electrode deposition can be improved, the occurrence of grid electrode broken lines caused by insufficient introduction of the grid electrode material is avoided, and the influence on the subsequent process and the reliability of the semiconductor device caused by grid electrode defects is avoided. If the first gap does not exist in the first region, the gate material can only be vertically introduced from the top surface of the stacked layer (along the first direction), after the gates of the upper layer are connected together, the gate material is blocked from entering the lower layer, so that the lower layer gate cannot be deposited continuously, the uniformity of the lower layer gate is poor, and the condition of broken lines of the lower layer gate may exist. In addition, in the method for manufacturing the semiconductor device provided by the embodiment of the disclosure, the spacer layer is formed on the semiconductor column first, and then the gate is formed, so that the width of the gate can be controlled by adjusting the width of the spacer layer, further control over the length of the transistor channel region is realized, and the reliability of the semiconductor device is improved.
Drawings
Fig. 1 is a schematic step diagram of a method for manufacturing a semiconductor device according to an embodiment of the present disclosure;
fig. 2A-2M are schematic process structures of embodiments of the present disclosure in the process of manufacturing a semiconductor device.
Detailed Description
Specific embodiments of a semiconductor device and a method for manufacturing the same provided by the present disclosure are described in detail below with reference to the accompanying drawings.
An embodiment of the disclosure provides a method for manufacturing a semiconductor device, fig. 1 is a schematic step diagram of the method for manufacturing a semiconductor device according to an embodiment of the disclosure, and fig. 2A to fig. 2M are schematic process structures of the semiconductor device according to the embodiment of the disclosure. In this embodiment, the semiconductor device may be, but is not limited to, a DRAM.
Referring to fig. 1 and 2J, where (a) in fig. 2J is a top view, (B) in fig. 2J is a cross-sectional view along A-A ' in (a), (C) in fig. 2J is a cross-sectional view along B-B ' in (a), and (d) in fig. 2J is a cross-sectional view along C-C ' in (a).
In step S10, a stacked layer 210 is formed on the surface of the substrate 200, where the stacked layer 210 includes a plurality of semiconductor layers and isolation layers stacked and arranged along a first direction D1, the semiconductor layers include a plurality of semiconductor pillars 221 extending along a second direction D2 and arranged at intervals along a third direction D3, a portion of the surface of the semiconductor pillars 221 is exposed in a first area E1 of the stacked layer 210, and another portion is covered by the isolation layers 240, and along the first direction D1, a first gap 241 is provided between the isolation layers 240 adjacent to the surface of the semiconductor pillars 221, the first direction D1 is a direction perpendicular to the surface of the substrate, the second direction D2 and the third direction D3 are both parallel to the surface of the substrate, and the second direction D2 intersects the third direction D3.
In this embodiment, the first direction D1 is a Z-axis direction in a cartesian coordinate system, the second direction D2 is an X-axis direction in the cartesian coordinate system, and the third direction D3 is a Y-axis direction in the cartesian coordinate system.
The substrate 200 is for supporting a semiconductor device thereon. Specifically, the substrate 200 may be, but is not limited to, a silicon substrate, and the present embodiment is described by taking the substrate 200 as a silicon substrate as an example. In other examples, the substrate 200 may be a semiconductor substrate such as gallium nitride, gallium arsenide, gallium carbide, silicon carbide, or SOI.
In this embodiment, the semiconductor layer is not a continuous structure, but is divided into a plurality of semiconductor pillars 221 by the isolation layer, in the same layer of semiconductor layer (i.e., a plane defined by the second direction D2 and the third direction D3), the plurality of semiconductor pillars 221 extend along the second direction D2 and are arranged at intervals along the third direction D3 (as shown in (a) of fig. 2J), in different layers of semiconductor layer arranged along the first direction D1 (i.e., arranged along a direction perpendicular to the plane defined by the second direction D2 and the third direction D3), the plurality of semiconductor pillars 221 extend along the second direction D2 and are arranged at intervals along the first direction D1 (as shown in (c) of fig. 2J).
The stacked layer 210 includes a first region E1, and in this embodiment, an end of the stacked layer 210 extends inward a set distance in the second direction D2 to form the first region E1. In this embodiment, the stacked layer 210 further includes a word line area E2, where the word line area E2 and the first area E1 are arranged along the third direction D3, and the semiconductor pillars 221 extend along the second direction D2 and the third direction D3 in the word line area E2 and are disposed at intervals in the first direction D1.
In the present embodiment, in the first region E1, the exposed area of the surface of the semiconductor pillar 221 is located on the inner side (i.e., a position far from the end of the stacked layer 210), and the area of the semiconductor pillar 221 covered by the spacer layer 240 is located on the outer side (i.e., a position near to the end of the stacked layer 210). The exposed area of the surface of the semiconductor pillar 221 forms a gate in a subsequent process, and thus, the area serves as a channel area CH of the transistor. In some embodiments, in the third direction D3, the word line region E2 corresponds to the channel region CH.
In this embodiment, the spacer layer 240 covers not only the surface of the semiconductor pillar 221 but also the surface of the isolation layer (as shown in (b) of fig. 2J), and the first void 241 extends inward of the stacked layer 210 to a fourth void 244 between exposed surfaces of adjacent semiconductor pillars 221 along the second direction D2 and communicates with the fourth void 244.
In some embodiments, a support layer 250 is formed within the stacked layer 210, the support layer 250 extending through the stacked layer 210 along the first direction D1, the support layer 250 being disposed at an edge of the first region E1 and encasing the semiconductor pillars 221. The supporting layer 250 is used for supporting the semiconductor device to avoid collapse when each process is performed, and the material of the supporting layer 250 is silicon nitride.
The support layer 250 is disposed at the edge of the first region E1, which means that the support layer 250 is disposed at a side of the first region E1 away from the end of the stacked layer 210, the exposed area of the surface of the semiconductor pillar 221 is adjacent to the support layer 250, and the area of the semiconductor pillar 221 covered by the spacer layer 240 is away from the support layer 250. The supporting layer 250 is in a grid shape and covers the semiconductor pillars 221 to support the semiconductor pillars 221 from collapsing.
As an example, the disclosed embodiments also provide a method of forming a stacked layer 210 on the substrate 200. The method comprises the following steps:
referring to fig. 2C, where (a) in fig. 2C is a top view, fig. 2C is a cross-sectional view along A-A ' in (a), fig. 2C is a cross-sectional view along B-B ' in (a), fig. 2C is a cross-sectional view along C-C ' in (a), an initial stacked layer 300 is formed on a surface of the substrate 200, the initial stacked layer 300 includes a plurality of semiconductor layers stacked along a first direction D1 and a sacrificial layer 320, a plurality of first sub-isolation layers 231 vertically penetrating the initial stacked layer 300 along the first direction D1 are provided in the initial stacked layer 300, the first sub-isolation layers 231 extend along the second direction D2 and the plurality of first sub-isolation layers 231 are spaced apart along the third direction D3 to divide the semiconductor layers into a plurality of the semiconductor pillars 221.
In the initial stacked layer 300, the sacrificial layer 320 serves as an isolation structure adjacent to the semiconductor pillars 221 in the first direction D1, and the first sub-isolation layer 231 serves as an isolation structure adjacent to the semiconductor pillars 221 in the third direction D3. In this step, in the first region E1, the surface of the semiconductor pillar 221 is not exposed.
In some embodiments, the material of the semiconductor layer is a silicon material including doped ions, and the material of the sacrificial layer 320 is silicon germanium. Wherein the dopant ions may be, but are not limited to, phosphorus ions. The semiconductor layer is formed by adopting a silicon material comprising doped ions, so that doping is not needed to be carried out in the process of forming a channel region, a source region and a drain region in the transistor, thereby simplifying the forming process of the semiconductor device. The silicon material including the doped ions has a high etching selectivity ratio to the silicon germanium material, thereby facilitating subsequent selective removal of the sacrificial layer 320 without damaging the semiconductor layer.
As an example, the disclosed embodiments also provide a method of forming an initial stacked layer 300 on the substrate 200, the method comprising the steps of:
Referring to fig. 2A, where (a) in fig. 2A is a top view, (B) in fig. 2A is a cross-sectional view along A-A ' in (a), (C) in fig. 2A is a cross-sectional view along B-B ' in (a), and (D) in fig. 2A is a cross-sectional view along C-C ' in (a), a plurality of initial semiconductor layers 310 and sacrificial layers 320 stacked along a first direction D1 are formed on a surface of the substrate 200. Specifically, on the surface of the substrate 200, the initial semiconductor layers 310 and the sacrificial layers 320 are alternately deposited along the first direction D1.
The specific number of layers of the semiconductor layer and the sacrificial layer 320 alternately deposited may be selected by those skilled in the art according to actual needs. The more the number of layers of the initial semiconductor layer 310 and the sacrificial layer 320 are alternately deposited, the greater the memory capacity of the semiconductor device formed.
Referring to fig. 2B, where (a) in fig. 2B is a top view, fig. 2B is a cross-sectional view along A-A ' in (a), fig. 2B is a cross-sectional view along B-B ' in (a), fig. 2B is a cross-sectional view along C-C ' in (a), the initial semiconductor layer 310 and the sacrificial layer 320 are patterned to form a plurality of isolation trenches 330, the isolation trenches 330 vertically penetrate the initial stacked layer 300 along the first direction D1, the isolation trenches 330 extend along the second direction D2, and the plurality of isolation trenches 330 are arranged at intervals along the third direction D3.
In this step, the initial semiconductor layer 310 and the sacrificial layer 320 may be patterned using photolithography and etching processes. In this embodiment, the isolation trench 330 penetrates the initial semiconductor layer 310 and the sacrificial layer 320 to the substrate 200. The initial semiconductor layer 320 is partitioned into a plurality of the semiconductor pillars 221.
With continued reference to fig. 2C, the isolation trench 330 is filled with an isolation material to form the first sub-isolation layer 231.
In this step, an isolation material is filled in the isolation trench 330, and the isolation material covers the surface of the initial stacked layer 300 in addition to filling the isolation trench 330; and thinning the isolation material on the surface of the initial stacked layer 300 by adopting a thinning process. The thinning process includes, but is not limited to, a chemical mechanical polishing process. In this embodiment, the isolation material on the surface of the initial stacked layer 300 is not completely removed, i.e., a layer of isolation material remains on the surface of the initial stacked layer 300 to protect the surface of the initial stacked layer 300 from damage in the subsequent process. In other embodiments, the isolation material on the surface of the initial stack 300 may also be completely removed, leaving only the isolation material within the isolation trenches 330. It will be appreciated that after the spacer material on the surface of the initial stacked layer 300 is thinned by a thinning process, the remaining spacer material serves as the first sub-spacer 231.
In this embodiment, after the first sub-spacer 231 is formed, the support layer 250 is also formed within the initial stacked layer 300.
Referring to fig. 2D, where (a) in fig. 2D is a top view, fig. 2D is a cross-sectional view along A-A ' in (a), fig. 2D is a cross-sectional view along B-B ' in (a), and fig. 2D is a cross-sectional view along C-C ' in (a), after the initial stacked layer 300 is formed, a portion of the sacrificial layer 320 is removed from the side of the first region E1, and the surface of the semiconductor pillar 221 is exposed.
In this step, since the side of the first region E1 is not blocked, a portion of the sacrificial layer 320 may be removed from the side of the first region E1. I.e. the sacrificial layer 320 is removed along the end of the initial stack 300. Methods of removing the sacrificial layer 320 include, but are not limited to, etching processes. It can be appreciated that after the sacrificial layer 320 is removed, the surface of the semiconductor pillars 221 at the original locations of the sacrificial layer 320 is exposed.
The removal depth (i.e., the distance extending along the second direction D2) of the sacrificial layer 320 may be determined according to the width of the subsequently formed gate, and the wider the subsequently formed gate is, the smaller the removal depth of the sacrificial layer 320 is, so that the width of the subsequently formed gate 260 may be controlled according to the removal depth of the sacrificial layer 320. The width of the gate 260 determines the length of the channel region CH of the transistor formed, and thus, the control of the length of the channel region CH of the transistor can be achieved by controlling the removal depth of the sacrificial layer 320.
In the step of removing the sacrificial layer 320, the first sub-isolation layer 231 covered on the surface of the initial stacked layer 300 is also partially removed, that is, the first sub-isolation layer 231 corresponding to the removed sacrificial layer 320 in the first direction D1 is removed. In some embodiments, an etching process is first used to remove a portion of the first sub-isolation layer 231 covered on the surface of the initial stacked layer 300, and then an etching process is used to remove the sacrificial layer 320.
The spacer layer 240 is formed, and the spacer layer 240 covers the exposed surface of the semiconductor pillars 221.
In some embodiments, the spacer layer 240 is formed directly on the exposed surface of the semiconductor pillars 221 after the sacrificial layer 320 is removed, whereas in this embodiment, a spacer material is deposited after the sacrificial layer 320 is removed.
Specifically, referring to fig. 2E, where (a) in fig. 2E is a top view, (B) in fig. 2E is a cross-sectional view along A-A ' in (a), fig. 2E is a cross-sectional view along B-B ' in (a), and fig. 2E is a cross-sectional view along C-C ' in (a), a spacer material 400 is deposited, and in the first region E1, the spacer material 400 covers the exposed surface of the semiconductor pillar 221 and the end surface of the sacrificial layer 320.
In this embodiment, the spacer material 400 also covers the end surfaces of the semiconductor pillars 221, the surface of the initial stacked layer 300, to protect the semiconductor pillars 221 and the initial stacked layer 300 during a subsequent process of removing the sacrificial layer 320. Among other methods of depositing the spacer material 400 include, but are not limited to, chemical Vapor Deposition (CVD), atomic Layer Deposition (ALD), and the spacer material 400 includes, but is not limited to, silicon nitride.
Referring to fig. 2F, where (a) in fig. 2F is a top view, (B) in fig. 2F is a cross-sectional view along A-A ' in (a), (C) in fig. 2F is a cross-sectional view along B-B ' in (a), and (d) in fig. 2F is a cross-sectional view along C-C ' in (a), after the spacer material 400 is deposited, the sacrificial layer 320 is removed to form a trench 500, and a surface of the semiconductor pillar 221 covered by the sacrificial layer 320 is exposed in the first region E1.
In this step, the sacrificial layer 320 is completely removed, the trench 500 is formed at the original position of the sacrificial layer 320, the trench 500 exposes the surface of the semiconductor pillar 221, and in the first region E1, the trench 500 also exposes the surface of the semiconductor pillar 221 covered by the sacrificial layer 320, i.e., the surface of the channel region CH. In some embodiments, the sacrificial layer 320 may be removed using a lateral etching process, forming a trench 500 between two adjacent layers of the semiconductor layer.
The second sub-isolation layer 232 is filled in the trench 500. In some embodiments, when the process of directly forming the spacer layers 240 at the exposed surfaces of the semiconductor pillars 221, rather than forming the spacer material 400, is performed, the second sub-isolation layer 232 does not fill the first voids 241 between the spacer layers 240, but only fills the trenches 500. In this embodiment, the second sub-isolation layer 232 also fills the gaps between the spacer materials 400, since the spacer materials 400 are deposited first after the sacrificial layer 320 is removed, instead of directly forming the spacer layer 240.
Specifically, referring to fig. 2G, where (a) in fig. 2G is a top view, fig. 2G is a cross-sectional view along A-A ' in (a), fig. 2G is a cross-sectional view along B-B ' in (a), and fig. 2G is a cross-sectional view along C-C ' in (a), the trench 500 is filled with a second sub-isolation layer 232, and the first region E1 is filled with the second sub-isolation layer 232 not only the trench 500 between the channel regions CH of the adjacent semiconductor pillars 221, but also fills the gap between the spacer materials 400.
Referring to fig. 2H, where (a) in fig. 2H is a top view, fig. 2H (B) is a cross-sectional view along A-A ' in (a), fig. 2H (C) is a cross-sectional view along B-B ' in (a), and fig. 2H (d) is a cross-sectional view along C-C ' in (a), the first sub-isolation layer 231 and the second sub-isolation layer 232 are removed in the channel region CH to expose the sidewalls of the spacer material 400. In this step, the second sub-isolation layer 232 filled in the void of the spacer material 400 is not removed, which can protect the spacer material 400 deposited on the semiconductor pillars 221 from being removed in a subsequent process, on the one hand, and can play a supporting role to prevent the ends of the semiconductor pillars 221 from collapsing, on the other hand. It will be appreciated that in this step, the spacer material covering the surface of the second sub-spacer 232 is also removed. For example, in the word line region E2, the spacer material 400, the second sub-isolation layer 232 and the support layer 250 on the surface of the stacked layer 210 are also removed.
In this step, the first and second sub-spacers 231 and 232 of the word line region E2 are also removed, and the surface of the semiconductor pillar 221 is exposed.
Referring to fig. 2I, where (a) in fig. 2I is a top view, fig. 2I (B) is a cross-sectional view along A-A ' in (a), fig. 2I (C) is a cross-sectional view along B-B ' in (a), fig. 2I (d) is a cross-sectional view along C-C ' in (a), sidewalls of the spacer material 400 are removed, the second sub-isolation layer 232 is exposed, and the remaining spacer material 400 serves as the spacer layer 240. In this step, the sidewall of the spacer material 400 is etched and removed by using the space formed after the second sub-isolation layer 232 is removed as an etching window, and when the second sub-isolation layer 232 filled in the space of the spacer material 400 is completely exposed, it is explained that the sidewall of the spacer material 400 is removed, forming a spacer layer covering only the surface of the semiconductor pillar 221. It will be appreciated that in this step, the spacer material attached to the ends of the semiconductor pillars 221, the spacer material covering the surface of the initial stacked layer 300, are also removed at the same time.
Referring to fig. 2J, the second sub-isolation layer 232 between the spacers 240 is removed to form the first gap 241. In this step, the second sub-isolation layer 232 may be removed using an etching process. After the second sub-spacer 232 is removed, the surface of the spacer 240 is exposed to the first void 241. In the first region E1, the space 244 between the semiconductor pillars 221 communicates with the outside through the first space 241.
With continued reference to fig. 1 and 2K, in which (a) in fig. 2K is a top view, (B) in fig. 2K is a cross-sectional view along A-A ' in (a), (C) in fig. 2K is a cross-sectional view along B-B ' in (a), and (d) in fig. 2K is a cross-sectional view along C-C ' in (a), in step S11, a gate dielectric layer 290 is formed on the exposed surface of the semiconductor pillar 221 in the first region E1. In some embodiments, the gate dielectric layer 290 is formed only in the channel region CH. The gate dielectric layer 290 may be a high K dielectric layer to reduce leakage current of the transistor and reduce impurity diffusion.
With continued reference to fig. 1 and 2L, where (a) in fig. 2L is a top view, and (B) in fig. 2L is a cross-sectional view along A-A ' in (a), and (C) in fig. 2L is a cross-sectional view along B-B ' in (a), and (D) in fig. 2L is a cross-sectional view along C-C ' in (a), in step S12, a gate material is introduced from a side of the first void 241 in the first region E1, the gate material is deposited on the gate dielectric layer 290 to form a gate 260, and in the first direction D1, a second void 242 is formed between the gates 260 deposited adjacent to the surface of the semiconductor pillar 221, and in the third direction D3, adjacent to the gate 260 is connected to form a word line structure extending in the third direction D3.
In the channel region CH, the distance between the semiconductor pillars 221 in the third direction D3 is L1, and the distance between the semiconductor pillars 221 in the first direction D1 is L2, wherein L2> L1, e.g., L2>4L1 in some embodiments. Because L1 is small, when gate material is deposited, the deposited gate material will be connected together in the third direction D3, thereby forming a word line structure extending in the third direction D3.
In this step, the gate material is not deposited on the surface of the spacer layer 240 and the surface of the support layer 250, but is deposited only on the surface of the gate dielectric layer 290, so that the width of the gate 260 formed along the second direction D2 can be controlled by adjusting the width of the spacer layer 240 along the second direction D2, and thus the length of the channel region CH along the second direction D2 can be controlled.
In some embodiments, the spacer layer 240 is made of silicon nitride, the surface of the semiconductor pillar 221 is made of silicon oxide, and the interface properties of the two are different, so that the gate material is selectively deposited on the surface of the semiconductor pillar 221, but not on the surface of the spacer layer 240, so that the gate 260 can be formed.
After forming the gate electrode 260, at least the first void 241 is exposed at the side of the first region E1. Since the gate electrode 260 is formed only on the surface of the gate dielectric layer 290, the spacer layer 240 is not covered by the gate material, and the first void 241 is still remained.
In the first direction D1, the gate electrode 260 deposited adjacent to the surface of the semiconductor pillar 221 does not contact, but has a second void 242, the second void 242 communicating with the first void 241.
In this step, in the word line region E2, the gate material covers the surface of the gate dielectric layer 290, and as the word line 280, a third gap 243 is formed between adjacent word lines 280 in the first direction D1, that is, in the first direction D1, the adjacent word lines 280 are not in contact with each other. In the third direction D3, adjacent word lines 280 are connected, and the word lines 280 are connected with the gate electrodes 260 to form a word line structure extending in the third direction.
Referring to fig. 1 and 2M, where (a) in fig. 2M is a top view, (B) in fig. 2M is a cross-sectional view along A-A ' in (a), (C) in fig. 2M is a cross-sectional view along B-B ' in (a), and (d) in fig. 2M is a cross-sectional view along C-C ' in (a), in step S13, insulating materials are filled in the first and second voids 241 and 242 to form the insulating layer 270.
In this step, the insulating layer 270 is disposed between adjacent gates 260, separating the adjacent gates 260 in the first direction D1 to electrically insulate the two, and supporting the gates 260 and the semiconductor pillars 221 from collapsing. The insulating layer 270 is further disposed between the spacers 240 to support the stack on the one hand and to close the ends of the stack on the other hand, thereby preventing damage to the gate 260 by materials used or generated in subsequent processes.
In this embodiment, in the word line region E2, the insulating material is filled in the third gap 243 to form the insulating layer 270. The insulating layer 270 is provided between the adjacent word lines 280, separates the adjacent word lines 280 in the first direction D1 to electrically insulate them, supports the word lines 280 and the semiconductor pillars 221,
in the method for manufacturing a semiconductor device provided in the embodiments of the present disclosure, before forming the gate, the first gap 241 is formed in the first region E1 of the stacked layer 210, and the gate material can be introduced from the side surface of the first gap 241 (along the second direction D2 and the third direction D3) and deposited on the gate dielectric layer 290 on the surface of the semiconductor pillar 221, so that the uniformity of depositing the gate 260 can be improved, and the occurrence of gate disconnection caused by insufficient introduction of the gate material is avoided, thereby avoiding the influence on the subsequent process and the reliability of the semiconductor device due to the gate defect. If the first gap does not exist in the first region E1, the gate material can only be vertically introduced from the top surface of the stacked layer 210 (along the first direction D1), and after the gates on the upper layer are connected together along the third direction D3, the gate material is blocked from entering the lower layer, so that the lower layer gate cannot be deposited continuously, the uniformity of the lower layer gate is poor, and the condition of the lower layer gate disconnection may exist.
In addition, in the method for manufacturing a semiconductor device provided in the embodiments of the present disclosure, the spacer layer 240 is formed on the semiconductor pillar 221 first, and then the gate 260 is formed, so that the width of the gate 260 can be controlled by adjusting the width of the spacer layer 240, thereby controlling the length of the channel region of the transistor, and improving the reliability of the semiconductor device.
The embodiment of the disclosure also provides a semiconductor device. Referring to fig. 2A-2M, the semiconductor device includes a substrate 200, a stacked layer 210, a spacer 240, a gate dielectric 290, a gate 260, and an insulating layer 270.
The substrate 200 is for supporting a semiconductor device thereon. In this embodiment, the substrate 200 is exemplified as a silicon substrate.
The stacked layer 210 is disposed on the substrate 200, the stacked layer 210 includes a plurality of semiconductor layers and isolation layers stacked and arranged along a first direction D1, the semiconductor layers include a plurality of semiconductor pillars 221 extending along a second direction D2 and arranged at intervals along a third direction D3, the semiconductor pillars 221 are also isolated by the isolation layers in the third direction D3, the stacked layer 210 includes a first region E1, the first direction D1 is a direction perpendicular to the surface of the substrate 200, the second direction D2 and the third direction D3 are both directions parallel to the surface of the substrate 200, and the second direction D2 intersects the third direction D3.
In this embodiment, the semiconductor layer is not a continuous structure, but is divided into a plurality of semiconductor pillars 221 by the isolation layer, the plurality of semiconductor pillars 221 extend in the second direction D2 and are spaced apart in the third direction D3 (as shown in fig. 2 a) in the same layer of semiconductor layer (i.e., a plane defined by the second direction D2 and the third direction D3), and the plurality of semiconductor pillars 221 extend in the second direction D2 and are spaced apart in the first direction D1 (as shown in fig. 2 c) in different layers of semiconductor layer arranged in the first direction D1 (i.e., in a direction perpendicular to the plane defined by the second direction D2 and the third direction D3).
The spacer 240 is disposed at the first region E1 and covers a portion of the surface of the semiconductor pillar 221. The gate dielectric layer 390 is disposed in the first region E1 and covers another portion of the surface of the semiconductor pillar 221, the gate 260 is disposed in the first region E1 and covers the surface of the gate dielectric layer 290, and the semiconductor pillar region corresponding to the gate 260 is used as a channel region CH, that is, in the first region E1, the region covered by the spacer 240 is not covered by the gate 260. In the first direction D1, adjacent gate electrodes 260 are not in contact with each other, and in the third direction D3, the gate electrodes 260 of the same layer are connected to form a word line structure extending along the third direction D3.
In this embodiment, the stacked layer 210 further includes a word line area E2, where the word line area E2 and the first area E1 are arranged along the third direction D3, and the word line area E2 is disposed corresponding to the channel area CH. In the word line region E2, the semiconductor pillars 221 extend along the second direction D2 and the third direction D3, and are spaced apart in the first direction D1.
The semiconductor device also includes a word line 280. In the word line region E2, the gate dielectric layer 290 covers the surface of the semiconductor pillar 221, and the word line 280 covers the surface of the gate dielectric layer 290. In the first direction D1, adjacent word lines 280 do not contact each other, and in the third direction D3, the word lines 280 are connected to the gate electrode 260 to form a word line structure extending in the third direction D3.
In the first region E1, the insulating layer 270 is disposed between adjacent gates 260 and between adjacent spacers 240, and in the word line region E2, the insulating layer 270 is disposed between adjacent word lines 280, so as to perform isolation and protection functions.
In this embodiment, the semiconductor device further includes a support layer 250 (see fig. 2J), the support layer 250 is disposed along the first direction D1 and penetrates through the stacked layers, and the support layer 250 is disposed at an edge of the first region E1 and wraps the semiconductor pillar 221. The gate electrode 260 is disposed at an end of the first region E1 facing the support layer, and the spacer layer 240 is disposed at an end of the first region E1 facing away from the support layer 250.
In this embodiment, the thickness of the gate 260 is 2-30 nm, which not only can meet the performance requirement of the gate 260, but also can avoid the connection of adjacent gates in the first direction D1.
The semiconductor device provided by the embodiment of the disclosure has the advantages that the uniformity of the thickness of the grid electrode is high, the condition of wire breakage does not exist, and the reliability of the semiconductor device is high.
The foregoing is merely a preferred embodiment of the present invention and it should be noted that modifications and adaptations to those skilled in the art may be made without departing from the principles of the present invention, which are intended to be comprehended within the scope of the present invention.

Claims (15)

1. A method of manufacturing a semiconductor device, comprising:
forming a stacked layer on a surface of a substrate, wherein the stacked layer comprises a plurality of semiconductor layers and isolation layers which are stacked and arranged along a first direction, the semiconductor layers comprise a plurality of semiconductor columns which extend along a second direction and are arranged at intervals along a third direction, a part of surfaces of the semiconductor columns are exposed in a first area of the stacked layer, the other part of the surfaces of the semiconductor columns are covered by the isolation layers, a first gap is formed between the isolation layers adjacent to the surfaces of the semiconductor columns, the first direction is a direction vertical to the surface of the substrate, the second direction and the third direction are both directions parallel to the surface of the substrate, and the second direction is intersected with the third direction;
Forming a gate dielectric layer on the exposed surface of the semiconductor column in the first region;
introducing a gate material from the side surface of the first gap in the first region, depositing the gate material on the surface of the gate dielectric layer to form a gate, wherein a second gap is formed between adjacent gates in the first direction, the adjacent gates are connected in the third direction, and a semiconductor column region corresponding to the gate is used as a channel region;
and filling insulating materials in the first gap and the second gap to form an insulating layer.
2. The method of manufacturing a semiconductor device according to claim 1, wherein the step of forming a stacked layer on the surface of the substrate further comprises:
forming an initial stacked layer on the surface of the substrate, wherein the initial stacked layer comprises a plurality of semiconductor layers and a sacrificial layer which are stacked and arranged along a first direction, a plurality of first sub-isolation layers vertically penetrating through the initial stacked layer along the first direction are arranged in the initial stacked layer, the first sub-isolation layers extend along the second direction, and the plurality of first sub-isolation layers are arranged at intervals along the third direction so as to divide the semiconductor layer into a plurality of semiconductor columns;
Removing a portion of the sacrificial layer from the side surface of the first region in the first region, the surface of the semiconductor pillar being exposed;
forming the spacer layer, wherein the spacer layer covers the exposed surface of the semiconductor column;
removing the sacrificial layer to form a groove, wherein the surface of the semiconductor column covered by the sacrificial layer is exposed in the first region;
filling a second sub isolation layer in the groove;
and removing the first sub-isolation layer and the second sub-isolation layer in the channel region, wherein the rest of the first sub-isolation layer and the second sub-isolation layer are used as the isolation layers together.
3. The method of manufacturing a semiconductor device according to claim 2, wherein the step of forming the initial stacked layer on the substrate surface further comprises:
forming a plurality of initial semiconductor layers and sacrificial layers stacked and arranged along a first direction on the surface of the substrate;
patterning the initial semiconductor layer and the sacrificial layer to form a plurality of isolation trenches, wherein the isolation trenches vertically penetrate through the initial stacked layer along the first direction, extend along the second direction and are arranged at intervals along the third direction;
And filling isolation materials in the isolation trenches to form the first sub-isolation layers.
4. The method of manufacturing a semiconductor device according to claim 3, wherein in the step of forming the first sub-spacer by filling the isolation trench with an isolation material, the first sub-spacer further covers a surface of the initial stacked layer, and in the step of removing a part of the sacrificial layer from a side surface of the first region, the first sub-spacer covering the surface of the initial stacked layer is partially removed.
5. The method of manufacturing a semiconductor device according to claim 2, wherein forming the spacer layer, the spacer layer covering the exposed surface of the semiconductor pillar, further comprises:
depositing a spacer material in the first region, wherein the spacer material covers the exposed surface of the semiconductor column and the end face of the sacrificial layer;
the step of filling the second sub-isolation layer in the trench further comprises: in the first region, the second sub-isolation layer also fills the gaps between the spacer materials;
the step of removing the first sub-isolation layer and the second sub-isolation layer in the channel region further comprises: removing the side wall of the spacer material to expose the second sub-isolation layer, and taking the rest spacer material as the spacer layer; and removing the second sub-isolation layers between the isolation layers to form the first gaps.
6. The method of manufacturing a semiconductor device according to claim 1, wherein in the step of introducing gate material from the first void side surface in the first region, at least the first void is exposed at the first region side surface.
7. The method of manufacturing a semiconductor device according to claim 1, wherein the spacer layer is silicon nitride and the gate material is titanium nitride.
8. The method for manufacturing a semiconductor device according to claim 1, further comprising: and forming a supporting layer in the stacking layer, wherein the supporting layer penetrates through the stacking layer along the first direction, is arranged at the edge of the first region and covers the semiconductor column.
9. The method of manufacturing a semiconductor device according to claim 1, wherein the stacked layer further includes a word line region, the word line region and the first region being arranged along the third direction, the semiconductor pillars extending along the second direction and the third direction in the word line region and being spaced apart in the first direction;
forming a gate dielectric layer on the exposed surface of the semiconductor column in the first region, and forming the gate dielectric layer on the surface of the semiconductor column in the word line region;
In the step of introducing gate materials from the side surfaces of the first gaps in the first region, in the word line region, the gate materials cover the surface of the gate dielectric layer and serve as word lines, and third gaps are formed between adjacent word lines;
and filling insulating materials in the first gap and the second gap, wherein in the step of forming an insulating layer, the insulating materials are filled in the third gap in the word line region.
10. A semiconductor device manufactured by the manufacturing method according to any one of claims 1 to 9, comprising:
a substrate;
a stacked layer disposed on the substrate, the stacked layer including a plurality of semiconductor layers and isolation layers stacked and arranged along a first direction, the semiconductor layers including a plurality of semiconductor pillars extending along a second direction and arranged at intervals along a third direction, the semiconductor pillars also being isolated by the isolation layers in the third direction, the stacked layer including a first region, the first direction being a direction perpendicular to a surface of the substrate, the second direction and the third direction both being directions parallel to the surface of the substrate, and the second direction intersecting the third direction;
A spacer layer disposed in the first region and covering a portion of a surface of the semiconductor pillar;
a gate dielectric layer arranged in the first region and covering the other part of the surface of the semiconductor column,
the grid electrode covers the surface of the grid dielectric layer, and a semiconductor column region corresponding to the grid electrode is used as a channel region;
and an insulating layer disposed between adjacent gates and between adjacent spacers.
11. The semiconductor device of claim 10, further comprising a support layer extending through the stack layer in the first direction, the support layer being disposed at an edge of the first region and surrounding the semiconductor pillars.
12. The semiconductor device of claim 11, wherein the gate is disposed at an end of the first region facing the support layer, and the spacer layer is disposed at an end of the first region facing away from the support layer.
13. The semiconductor device according to claim 10, wherein a thickness of the gate electrode is 2 to 30nm.
14. The semiconductor device of claim 10, wherein the stacked layer further comprises a word line region arranged along the third direction with the first region, the semiconductor pillars extending along the second and third directions in the word line region and being spaced apart in the first direction;
And word lines covering the surfaces of the semiconductor columns, and the insulating layers are arranged between adjacent word lines.
15. The semiconductor device according to claim 11, wherein the support layer has a mesh shape, and wherein a material of the support layer is silicon nitride.
CN202210718468.9A 2022-06-23 2022-06-23 Semiconductor device and method for manufacturing the same Pending CN117334563A (en)

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CN202210718468.9A CN117334563A (en) 2022-06-23 2022-06-23 Semiconductor device and method for manufacturing the same

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