WO2024041040A1

WO2024041040A1 - Semiconductor device and preparation method therefor

Info

Publication number: WO2024041040A1
Application number: PCT/CN2023/093819
Authority: WO
Inventors: 王弘; 李晓杰
Original assignee: 长鑫存储技术有限公司
Priority date: 2022-08-26
Filing date: 2023-05-12
Publication date: 2024-02-29
Also published as: CN117693188A

Abstract

A preparation method for a semiconductor device comprises: forming a substrate and a stack structure located on the substrate, wherein the stack structure comprises first semiconductor layers and second semiconductor layers, which are alternately stacked in a first direction, and the stack structure comprises a capacitor region, a wordline region and a bitline region; removing the second semiconductor layers to form first gaps; thinning the first semiconductor layers along the first gaps; removing part of the first semiconductor layers to form a plurality of semiconductor columns, wherein each semiconductor column extends in a third direction, and the plurality of semiconductor columns are arranged in an array in the first direction and a second direction; forming a gate structure layer on a surface of each semiconductor column; and removing the gate structure layers on the surfaces of the semiconductor columns in the capacitor region and forming capacitor structure layers, wherein the capacitor structure layers cover the surfaces of the semiconductor columns.

Description

Semiconductor device and preparation method thereof

Related application citations

This application claims priority to the Chinese patent application number 202211034211.8 and the application title "Semiconductor Device and Preparation Method thereof" submitted on August 26, 2022, the entire content of which is appended hereto by reference.

Technical field

The present disclosure relates to the field of integrated circuits, and in particular, to a semiconductor device and a manufacturing method thereof.

Background technique

Dynamic Random Access Memory (DRAM) is a semiconductor device commonly used in electronic equipment such as computers. It is composed of multiple storage units, and each storage unit usually includes a transistor and a capacitor. In order to meet the requirements of high storage density and high integration, memories such as DRAM are gradually developing from two-dimensional structures to three-dimensional structures. During the manufacturing process of semiconductor structures such as DRAM with a three-dimensional structure, a superlattice stack structure of semiconductor layers and sacrificial layers needs to be formed first through a deposition process. The superlattice stack structure usually uses an epitaxial process to form a SiG layer on the Si layer. Since SiGe There is a lattice mismatch between the SiGe layer and the Si layer, which limits the epitaxial thickness of the SiGe layer on the Si layer. The limited epitaxial thickness limits the spacing of semiconductor devices in the vertical direction, increasing the difficulty of the process. Conducive to the increase in integration density.

Contents of the invention

The technical problem to be solved by this disclosure is to provide a semiconductor device and a preparation method thereof, which can break through the limitations caused by the epitaxial thickness of the SiGe layer and facilitate an increase in integration density.

In order to solve the above problems, embodiments of the present disclosure provide a method for manufacturing a semiconductor device, including: forming a substrate and a stacked structure located on the substrate, the stacked structure including first semiconductors stacked alternately along a first direction. layer and a second semiconductor layer, the stacked structure includes a capacitor region, a word line region and a bit line region, the first direction is a direction perpendicular to the top surface of the substrate; remove the second semiconductor layer, to Forming a first gap; thinning the first semiconductor layer along the first gap; removing part of the first semiconductor layer to form a plurality of semiconductor pillars, each of the semiconductor pillars extending along a third direction and having a plurality of The semiconductor pillars are arranged in an array in the first direction and the second direction, the second direction is a direction parallel to the top surface of the substrate, and the third direction is parallel to the top surface of the substrate. direction of the surface, and the second direction intersects the third direction; forming a gate structure layer on the surface of the semiconductor pillar; in the capacitor region, removing the gate structure layer on the surface of the semiconductor pillar, and forming and a capacitor structure layer covering the surface of the semiconductor pillar.

Embodiments of the present disclosure also provide a semiconductor device, including: a substrate; a plurality of semiconductor pillars located on the substrate, the plurality of semiconductor pillars are arranged in an array in the first direction and the second direction and extend in the third direction. , the first direction is a direction perpendicular to the top surface of the substrate, the second direction is a direction parallel to the top surface of the substrate, and the third direction is parallel to the top surface of the substrate. The direction of the top surface, and the second direction intersects the third direction; the first distance between adjacent semiconductor pillars in the first direction is greater than the third distance between adjacent semiconductor pillars in the second direction. One spacing.

The method for manufacturing a semiconductor device provided by embodiments of the present disclosure utilizes thinning of the first semiconductor layer to increase the first spacing between adjacent first semiconductor layers (and semiconductor pillars), thereby breaking through the limitations caused by insufficient epitaxial thickness of the second semiconductor layer. , which is conducive to increasing the integration density of semiconductor devices; embodiments of the present disclosure also provide a new preparation method, which first forms a gate structure layer and then forms bit lines and capacitors, which is conducive to expanding the application of semiconductor devices.

Description of drawings

Figure 1 is a schematic diagram of the steps of a method for manufacturing a semiconductor device provided by an embodiment of the present disclosure;

2-20 are schematic diagrams of the main process structures in the process of preparing semiconductor devices according to embodiments of the present disclosure.

Detailed ways

Specific embodiments of the method for manufacturing a semiconductor device provided by the present disclosure will be described in detail below with reference to the accompanying drawings.

Embodiments of the present disclosure provide a method for manufacturing a semiconductor device. FIG. 1 is a schematic diagram of steps of a method for manufacturing a semiconductor device provided by an embodiment of the present disclosure. FIGS. 2-20 illustrate the main steps in the process of preparing a semiconductor device according to embodiments of the present disclosure. Schematic diagram of the process structure. In this embodiment, the semiconductor device may be but is not limited to DRAM.

Please refer to Figures 1 to 8, in which (a) is a top view, (b) is a schematic cross-sectional view along line A-A' in (a), (c) is a schematic cross-sectional view along line B-B' in (a) , (d) is a schematic cross-sectional view along line CC′ in (a), step S10 , forming a substrate 20 and a stacked structure 21 located on the substrate 20 . The stacked structure 21 includes first semiconductor layers 210 and second semiconductor layers 220 alternately stacked along a first direction D1. The stacked structure 21 includes a capacitor region A1, a word line region A2 and a bit line region A3. The first direction D1 is perpendicular to the substrate. The second direction D2 is a direction parallel to the top surface of the substrate 20 .

In this embodiment, the first direction D1 is the Z-axis direction in the Cartesian coordinate system, and the second direction D2 is the Y-axis direction in the Cartesian coordinate system.

The substrate 20 may be, but is not limited to, a silicon substrate. In this embodiment, the substrate 20 is a silicon substrate for description. In other examples, the substrate 20 may be a semiconductor such as gallium nitride, gallium arsenide, gallium carbide, silicon carbide, or SOI. The substrate 20 is used to support the stacked structure 21 on its top surface.

The first semiconductor layer 210 and the second semiconductor layer 220 are alternately stacked. This means that after forming a layer of the first semiconductor layer 210, a layer of the second semiconductor layer 220 is formed on the first semiconductor layer 210, and then the first semiconductor layer is formed in sequence. layer 210 and a second semiconductor layer 220 located on the first semiconductor layer 210 . In this embodiment, the first semiconductor layer 210 is a silicon layer, and the second semiconductor layer 220 is a silicon germanium layer. Since the substrate 20 is a silicon substrate, a second semiconductor layer 220 is epitaxially formed on the substrate 20. The first semiconductor layer 210 is deposited on the second semiconductor, and the second semiconductor layer 220 is epitaxially formed on the first semiconductor layer 210 . This process is repeated to form the stacked structure 21 . In this embodiment, the topmost layer of the stacked structure 21 is the second semiconductor layer 220 .

The capacitor area A1, the word line area A2 and the bit line area A3 are arranged along the third direction D3. In this embodiment, the stacked structure 21 includes two capacitor regions A1, two word line regions A2 and one bit line region A3. The bit line region A3 is disposed between the two word line regions A2. The two word line regions A2 It is arranged between the two capacitor regions A1, that is, a symmetrical structure is formed with the center line of the bit line region A3 as the symmetry axis. In other embodiments, it may only include one capacitor region A1, one word line region A2, and one bit line region A3 that are arranged in sequence.

In the bit line region A3, a plurality of first openings 230 arranged along the second direction D2 penetrate the first semiconductor layer 210 and the second semiconductor layer 220 along the first direction D1, that is, the first openings 230 expose the substrate 20, and the first opening 230 exposes the substrate 20. Partial side surfaces of the first semiconductor layer 210 and the second semiconductor layer 220 are exposed to the inner wall of the first opening 230 . In a region between adjacent first openings 230, a first support layer 400 is provided between the first semiconductor layers 210.

The area between adjacent first openings 230 refers to the area corresponding to the stacked structure 21 between the adjacent first openings 230 . In this area, the first support layer 400 partially replaces the second semiconductor layer 220 and is disposed between adjacent first semiconductor layers 210 . The side surfaces of the first support layer 400 are also exposed to the inner wall of the first opening 230 . Specifically, in the area between adjacent first openings 230, in the third direction D3, in the same layer, the first support layer 400 cuts the second semiconductor layer 220 into two parts, the first support layer 400 disposed between the two portions of the second semiconductor layer 220 .

As an example, the present disclosure provides a method of forming stack structure 21 on substrate 20 .

Please refer to Figure 2, in which (a) is a top view, (b) is a schematic cross-sectional view along line A-A' in (a), and (c) is a schematic cross-sectional view along line B-B' in (a). First semiconductor layers 210 and second semiconductor layers 220 alternately stacked along the first direction D1 are formed on the bottom 20 . Wherein, an epitaxial process may be used to form the second semiconductor layer 220 on the first semiconductor layer 210 .

Please refer to Figure 3, in which (a) is a top view, (b) is a schematic cross-sectional view along line A-A' in (a), (c) is a schematic cross-sectional view along line B-B' in (a), in place A plurality of first openings 230 arranged along the second direction D2 are formed in the line area A3. The first openings 230 penetrate the first semiconductor layer 210 and the second semiconductor layer 220 along the first direction D1. In this step, photolithography and etching processes can be used to form the first openings 230. The number of the first openings 230 can be specifically set according to the structural size of the semiconductor device, which is not limited in the embodiments of the present disclosure.

Please refer to Figure 6, in which (a) is a top view, (b) is a schematic cross-sectional view along line A-A' in (a), (c) is a schematic cross-sectional view along line B-B' in (a), (d) ) is a schematic cross-sectional view along line CC' in (a). Along the first opening 230, part of the second semiconductor layer 220 between the adjacent first openings 230 is removed. Between the adjacent first semiconductor layers 210 An initial gap 211 is formed between them.

Specifically, in this embodiment, the method of removing part of the second semiconductor layer 220 between adjacent first openings 230 along the first openings 230 includes:

Please refer to Figure 4, in which (a) is a top view, (b) is a schematic cross-sectional view along line A-A' in (a), and (c) is a schematic cross-sectional view along line B-B' in (a). After the first opening 230 , the insulating layer 231 is filled in the first opening 230 , and the insulating layer 231 covers the inner wall of the first opening 230 . The insulating layer 231 may be a silicon oxide layer.

Please refer to Figure 5, in which (a) is a top view, (b) is a schematic cross-sectional view along line A-A' in (a), (c) is a schematic cross-sectional view along line B-B' in (a), with parts removed. The insulating layer 231 and the remaining insulating layer 231 serve as the protective layer 234 to cover the opposite side walls of the first opening 230 in the third direction D3, and the remaining area of the first opening 230 serves as the second opening 232. Among them, a dry etching process can be used to remove part of the insulating layer 231 . In this step, the two side walls of the first opening 230 that are oppositely arranged in the second direction D2 are partially exposed, and the two side walls that are oppositely arranged in the third direction D3 are covered by the protective layer 234 , and the exposed side walls of the first opening 230 are partially exposed. The edges and the side surfaces of the protective layer 234 define the second opening 232 . It can be understood that due to the influence of the thickness of the protective layer 234 , the edges of the two side walls of the first opening 230 oppositely arranged in the second direction D2 are also covered by the protective layer 234 .

Referring to FIG. 6 , along the second opening 232 , the exposed second semiconductor layer 220 on the sidewall of the second opening 232 is removed, and an initial gap 211 is formed between adjacent first semiconductor layers 210 . In this step, the topmost second semiconductor layer 220 is removed, the top first semiconductor layer 210 is exposed as the topmost layer, and the protective layer 234 corresponding to the topmost second semiconductor layer 220 is also removed accordingly.

Please refer to Figure 7, in which (a) is a top view, (b) is a schematic cross-sectional view along line A-A' in (a), (c) is a schematic cross-sectional view along line B-B' in (a), (d) ) is a schematic cross-sectional view along line CC' in (a), where the first support layer 400 is formed in the initial gap 211. Specifically, the method of forming the first support layer 400 includes: depositing a support layer material in the stack structure 21; etching to remove the upper surface of the stack structure 21 (ie, the surface of the topmost first semiconductor layer 210) and the inside of the second opening 232. The support layer material remaining in the initial gap 211 serves as the first support layer 400 . The first support layer 400 may be a silicon nitride layer.

Referring to FIG. 8 , the protective layer 234 is removed, and the first semiconductor layer 210 and the second semiconductor layer 220 are exposed. In this step, a dry etching process may be used to remove the protective layer 234 .

Please refer to Figure 1 and Figure 9. In Figure 9, (a) is a top view, (b) is a schematic cross-sectional view along line A-A' in (a), and (c) is a schematic cross-sectional view along line B-B' in (a). (d) is a schematic cross-sectional view along line CC' in (a). In step S11, the second semiconductor layer 220 is removed to form the first gap 212. In this step, the second semiconductor layer 220 is completely removed, exposing the surface of the first semiconductor layer 210 . Specifically, in this embodiment, the second semiconductor layer 220 in the capacitor region A1, the word line region A2, and the bit line region A3 is removed along the first opening 230 to form the first gap 212. In this step, the second semiconductor layer 220 is completely removed, exposing the surface of the first semiconductor layer 210 .

In this embodiment, an epitaxial process is used to form the second semiconductor layer 220 on the first semiconductor layer 210. However, due to the lattice mismatch between the second semiconductor layer 220 and the first semiconductor layer 210, the second semiconductor layer 220 The epitaxial thickness on the first semiconductor layer 210 is limited, so after the second semiconductor layer 220 is removed, the first distance d1 between the two adjacent first semiconductor layers 210 in the first direction D1 is smaller, and The first distance d1 between two adjacent first semiconductor layers 210 is too small, so that in subsequent processes, the distance between the semiconductor structures in the first direction D1 is limited, for example, between the two adjacent first semiconductor layers 210 The first spacing d1 between the two adjacent bit lines can define the distance between the adjacent bit lines formed subsequently. If the first spacing d1 between the two adjacent first semiconductor layers 210 is too small, the distance between the adjacent bit lines will be affected. It may even affect the spacing of the subsequently formed word line structures, which increases the difficulty of the process and is not conducive to the increase in integration density. It may even make it impossible to connect word line structures on the same layer, affecting the reliability of semiconductor devices.

Therefore, the preparation method provided by the embodiment of the present disclosure increases the spacing between the first semiconductor layers 210 by thinning the first semiconductor layers 210 . Specifically, please refer to Figures 1 and 10. In Figure 10, (a) is a top view, (b) is a schematic cross-sectional view along line A-A' in (a), and (c) is a schematic cross-sectional view along line A-A' in (a). A schematic cross-sectional view along line BB', (d) is a schematic cross-sectional view along line CC' in (a), step S12, thinning the first semiconductor layer 210 along the first gap 212 to increase the size of the adjacent The first spacing d1 of the first semiconductor layer 210 in the first direction D1. In this step, a lateral etching process is used to etch the first semiconductor layer 210 through the first gap 212, that is, the first semiconductor layer 210 is thinned from the upper and lower surfaces of the first semiconductor layer 210, and is adjacent in the first direction D1. The first distance d1 between the first semiconductor layers 210 increases.

Please refer to Figure 1 and Figure 14. In Figure 14, (a) is a top view, (b) is a cross-sectional view along line A-A' in (a), and (c) is a cross-sectional view along line B- in (a). A schematic cross-sectional view of line B', (d) is a schematic cross-sectional view along line C-C' in (a), (e) is a schematic cross-sectional view along line D-D' in (a), step S13, remove part A semiconductor layer 210 forms a plurality of semiconductor pillars 240. Each semiconductor pillar 240 extends along the third direction D3 and the plurality of semiconductor pillars 240 are arranged in an array in the first direction D1 and the second direction D2. The third direction D3 is parallel. The second direction D2 intersects the third direction D3. In this embodiment, the third direction D3 is the X-axis direction in the Cartesian coordinate system as an example for explanation. Since the first semiconductor layer 210 is thinned, that is, the first distance d1 between adjacent semiconductor pillars 240 in the first direction D1 increases, for example, is greater than the distance d1 between adjacent semiconductor pillars 240 in the second direction D2. The second spacing d2 prevents the distance between adjacent bit lines from being affected and reduces the difficulty of the process.

As an example, embodiments of the present disclosure provide a method of removing part of the first semiconductor layer 210 to form a plurality of semiconductor pillars 240 . The method includes the following steps:

Please refer to Figure 11. In Figure 11, (a) is a top view, (b) is a schematic cross-sectional view along line A-A' in (a), and (c) is a cross-section along line BB' in (a). Schematic diagram, (d) is a schematic cross-sectional diagram along line CC′ in (a), in which the first isolation layer 213 is filled in the first gap 212 .

In this embodiment, the first isolation layer 213 is an oxide layer, which is filled in the first gap 212 between the first semiconductor layers 210 to support the first semiconductor layer 210 . Due to limitations of the semiconductor process, in some embodiments, the first isolation layer 213 also covers the top surface of the stacked structure 21. In this step, the step of removing the first isolation layer 213 on the top surface of the stacked structure 21 may also be included. The first semiconductor layer 210 on the top surface is exposed to avoid covering the first isolation layer 213 on the surface of the top semiconductor pillar 240 formed in the subsequent process, thereby affecting the contact between the gate structure layer formed in the subsequent process and the surface of the semiconductor pillar 240 .

Please refer to Figure 12. In Figure 12, (a) is a top view, (b) is a schematic cross-sectional view along line A-A' in (a), and (c) is a cross-section along line BB' in (a). Schematic diagram, (d) is a cross-sectional schematic diagram along line CC' in (a), a first mask layer 300 is formed on the stacked structure 21, the first mask layer 300 includes a plurality of first pattern windows 301, each The first graphics window 301 extends along the third direction D3, and the plurality of first graphics windows 301 are arranged along the second direction D2. Specifically, in this step, a layer of mask material is first coated, and then the mask material layer is patterned to form mask strips arranged at intervals, and the spaces between adjacent mask strips are First graphics window 301. In this embodiment, the first pattern window 301 exposes the first opening 230, and in subsequent processes, the first isolation layer 213 filled in the first opening 230 can be completely removed to avoid affecting the structure of the semiconductor pillar 240. In this embodiment, the first mask layer 300 may be a photoresist layer. In other embodiments, the first mask layer 300 may also be a hard mask layer. The projection of the first pattern window 301 on the substrate 20 covers the projection of the first opening 230 on the substrate 20 , that is, the first pattern window 301 exposes the first isolation layer 213 filled in the first opening 230 .

Please refer to Figure 13. In Figure 13, (a) is a top view, (b) is a schematic cross-sectional view along line A-A' in (a), and (c) is a cross-section along line BB' in (a). Schematic diagram, (d) is a schematic cross-sectional view along line C-C' in (a), (e) is a schematic cross-sectional view along line D-D' in (a), along the first graphics window 301, remove part of the first Semiconductor layer 210 forms semiconductor pillars 240. In this step, part of the first isolation layer 213 is removed, leaving the first isolation layer 213 between the semiconductor pillars 240 arranged in the first direction D1 to support the semiconductor pillars 240 . In this step, the first support layer 400 in the area corresponding to the first graphics window 301 is also removed.

After this step, it also includes: performing ion implantation on the semiconductor pillar 240 to form a doped semiconductor pillar 240 in preparation for subsequent formation of transistor and capacitor structures. In other embodiments of the present disclosure, ion implantation may also be performed when forming the first semiconductor layer 210 .

Referring to FIG. 14 , the first isolation layer 213 between the semiconductor pillars 240 arranged in the first direction D1 is removed, and the surfaces of the semiconductor pillars 240 are exposed. Specifically, an etching process may be used to remove the first isolation layer 213 . In this step, the first mask layer 300 is also removed.

Please refer to Figure 15. In Figure 15, (a) is a top view, (b) is a schematic cross-sectional view along line A-A' in (a), and (c) is a cross-section along line BB' in (a). Schematic diagram, (d) is a schematic cross-sectional view along the line CC' in (a), (e) is a schematic cross-sectional view along the line DD' in (a), step S14, forming a gate electrode on the surface of the semiconductor pillar 240 Structural layer 260. The gate structure layer 260 corresponding to the word line region A2 serves as the gate electrode, and the semiconductor pillar 240 corresponding to the gate electrode serves as the channel region. The gate structure layer 260 includes a gate dielectric layer 261 and a gate material layer 262.

As an example, the step of forming the gate structure layer 260 on the surface of the semiconductor pillar 240 includes:

A gate dielectric layer 261 is formed on the surface of the semiconductor pillar 240 , that is, the gate dielectric layer 261 covers the surface of the semiconductor pillar 240 . The gate dielectric layer 261 may be silicon oxide or a high-K dielectric layer. Among them, the gate dielectric layer 261 can be formed using processes such as chemical vapor deposition and atomic layer deposition.

A gate material layer 262 is formed on the surface of the gate dielectric layer 261 , that is, the gate material layer 262 covers the surface of the gate dielectric layer 261 . In the first direction D1, the gate material layers 262 located on the same layer are connected. Specifically, each semiconductor pillar 240 extends along the third direction D3. The semiconductor pillars 240 arranged in sequence in the second direction D2 are in the same layer, and the semiconductor pillars 240 arranged in sequence in the first direction D1 are in different layers. In this article, In the embodiment, the gate material layer 262 covering the surface of the semiconductor pillar 240 of the same layer is connected to form an overall structure. Gate material layer 262 may be a tungsten layer.

The second isolation layer 263 is filled in the gap between adjacent gate structure layers 260 in the first direction D1, and the second isolation layer 263 is filled with the stacked structure 21 to play a supporting role. In this embodiment, the second isolation layer 263 also covers the top surface of the stacked structure 21 . The second isolation layer 263 includes, but is not limited to, a silicon dioxide layer.

The preparation method also includes the step of forming bit lines. Specifically, please refer to Figure 18. In Figure 18, (a) is a top view, (b) is a schematic cross-sectional view along line A-A' in (a), and (c) is a schematic cross-sectional view along line B-B in (a). ' line schematic cross-sectional view, (d) is a schematic cross-sectional view along line C-C' in (a), (e) is a schematic cross-sectional view along line D-D' in (a), in bit line area A3, remove The first support layer 400, the gate structure layer 260 and the semiconductor pillar 240 form a plurality of bit lines 270. Each bit line 270 extends along the first direction D1 and the third direction D3, and the plurality of bit lines 270 extend along the second direction D1. Arranged at intervals in direction D2. In the semiconductor structure formed in this step, the semiconductor pillars 240 located on both sides of the bit line 270 are connected to the bit line 270, and both share the same bit line 270.

As an example, embodiments of the present disclosure also provide a method of forming multiple bit lines 270. The method includes the following steps:

Please refer to Figure 16. In Figure 16, (a) is a top view, (b) is a schematic cross-sectional view along line A-A' in (a), and (c) is a cross-section along line BB' in (a). Schematic diagram, (d) is a schematic cross-sectional view along the line C-C' in (a), (e) is a schematic cross-sectional view along the line D-D' in (a), in the bit line area A3, the first support layer is removed 400. The gate structure layer 260 and the semiconductor pillar 240 form a bit line trench 271. The bit line trench 271 penetrates the stack structure 21; continue to remove part of the gate structure layer 260 along the sidewall of the bit line trench 271 to form a groove 272. . In this step, when part of the gate structure layer 260 is continued to be removed along the sidewall of the bit line trench 271, the second isolation layer 263 is also partially removed. In the semiconductor structure formed in this step, the semiconductor pillar 240 is divided into two parts disposed on opposite sides of the bit line trench 271 , and the groove 272 is recessed in a direction away from the center of the bit line trench 271 . In this step, a dry etching process may be used to form the bit line trench 271, and a lateral etching process may be used to form the groove 272.

As an example, embodiments of the present disclosure provide a method of forming a bit line trench 271. The method includes: forming a second mask layer on the surface of the stacked structure 21, the second mask layer having a second pattern window, and the second pattern window is formed along the surface of the stack structure 21. The second direction D2 extends; along the second pattern window, the first support layer 400, the gate structure layer 260 and the semiconductor pillar 240 are removed to form a bit line trench 271. In this step, the second mask layer is a photoresist layer, and the bit line trench 271 is formed using photolithography and etching processes. In other embodiments, the second mask layer may also be a mask structure such as a hard mask.

Please refer to Figure 17. In Figure 17, (a) is a top view, (b) is a schematic cross-sectional view along line A-A' in (a), and (c) is a cross-section along line BB' in (a). Schematic diagram, (d) is a schematic cross-sectional view along line C-C' in (a), (e) is a schematic cross-sectional view along line D-D' in (a), forming the second support layer 250, the second support layer 250 fills between the exposed first semiconductor layer 210 of the groove 272 . The second support layer 250 is not only used to support the semiconductor pillar 240, but also is used to isolate the bit line 270 and the gate electrode. Specifically, in this embodiment, a silicon nitride layer is deposited and filled in the groove 272 as the second support layer 250 . In this step, the second mask layer used when forming the bit line trench 271 can be used as a mask layer when depositing the second support material.

Referring to FIG. 18, a bit line material layer is formed in the bit line trench; the bit line material layer is patterned to form bit lines 270 spaced apart along the second direction D2, and each bit line 270 is in contact with the bit line 270 along the first direction. The plurality of semiconductor pillars 240 arranged in D1 are connected; a third isolation layer 273 is formed between the bit lines 270, and the third isolation layer 273 is used to isolate adjacent bit lines 270 in the second direction D2. In this embodiment, the third isolation layer 273 includes but is not limited to silicon dioxide.

Please refer to Figure 19. In Figure 19, (a) is a top view, (b) is a schematic cross-sectional view along line A-A' in (a), and (c) is a cross-section along line BB' in (a). Schematic diagram, (d) is a schematic cross-sectional view along line C-C' in (a), (e) is a schematic cross-sectional view along line D-D' in (a), in this embodiment, when forming along the second After the step of arranging the bit lines 270 at intervals in the direction D2, the preparation method further includes: forming a third support layer 280 at the interface between the capacitor region A1 and the word line region A2, and the third support layer 280 supports the semiconductor pillar 240. The third support layer 280 is not only used to support the semiconductor pillar 240, but also is used to isolate the word line region A2 and the capacitor region A1 to prevent them from being electrically connected, thus affecting the reliability of the semiconductor device. The gate structure layer 260 located between the second support layer 250 and the third support layer 280 serves as the gate structure of the transistor, and its corresponding semiconductor pillar 240 serves as the channel region of the transistor.

As an example, embodiments of the present disclosure provide a method of forming the third support layer 280. The method includes: forming a third mask layer 281 on the surface of the stacked structure 21, the third mask layer 281 having a third pattern window 282, The three pattern windows 282 extend along the second direction D2 and correspond to the junction of the capacitor region A1 and the word line region A2; along the third pattern window 282, the gate structure layer 260 is removed; the support material is filled to form the third support layer 280. In this embodiment, the third mask layer 281 may be a photoresist layer, and the third support layer 280 may be a silicon nitride layer.

Please refer to Figure 20. In Figure 20, (a) is a top view, (b) is a schematic cross-sectional view along line A-A' in (a), and (c) is a cross-section along line C-C' in (a). Schematic diagram, (d) is a schematic cross-sectional view along the line D-D' in (a), (e) is a schematic cross-sectional view along the line EE' in (a), step S15, in the capacitor area A1, remove the semiconductor pillar The gate structure layer 260 on the surface of the semiconductor pillar 240 is formed, and the capacitance structure layer 290 is formed. The capacitance structure layer 290 covers the surface of the semiconductor pillar 240. In this embodiment, a capacitor structure layer 290 is formed in both capacitor regions A1. The capacitor structure layer 290 includes a lower electrode 291, a dielectric layer 292 and an upper electrode 293. The lower electrode 291 can be titanium nitride, and the dielectric layer 292 can be The high-K dielectric layer and the upper electrode 293 may be titanium nitride.

As an example, embodiments of the present disclosure provide a method of forming the capacitor structure layer 290 . The method includes: removing the gate structure layer 260 on the surface of the semiconductor pillar 240 in the capacitor area A1 to expose the surface of the semiconductor pillar 240 . A lower electrode 291 is formed, and the lower electrode 291 covers the surface of the semiconductor pillar 240; a dielectric layer 292 is formed, and the dielectric layer 292 covers the surface of the lower electrode 291; and an upper electrode 293 is formed, and the upper electrode 293 covers the surface of the dielectric layer 292.

In this embodiment, after forming the upper electrodes 293, the following steps are also included: forming a polysilicon layer 294, and the polysilicon layer 294 fills the gaps between the upper electrodes 293.

The method for manufacturing a semiconductor device provided by embodiments of the present disclosure increases the spacing between adjacent first semiconductor layers 210 in the first direction D1 by thinning the first semiconductor layer 210, thereby reducing the difficulty of the process and facilitating integration. The increase in density improves the reliability of semiconductor devices. At the same time, the preparation method provided by the embodiment of the present disclosure is a new method of preparing a semiconductor device, which forms the capacitor structure after forming the gate structure and the bit line 270, instead of forming the gate structure and the capacitor structure after forming the capacitor structure. Bit line 270.

In addition, in some embodiments of the present disclosure, the step of thinning the first semiconductor layer is performed before the step of forming the semiconductor pillars, which can better control the distance between semiconductor pillars on the same layer (adjacent in the second direction D2). spacing (such as the second spacing d2), so that the gate structure layers of the same layer can be bonded more easily. It can be understood that in other embodiments of the present disclosure, the step of thinning the semiconductor pillars may also be performed after the semiconductor pillars are formed.

An embodiment of the present disclosure also provides a semiconductor device prepared using the above preparation method. Please refer to FIGS. 1 to 20 . The semiconductor device includes a substrate 20 and a plurality of semiconductor pillars 240 located on the substrate 20 . The plurality of semiconductor pillars 240 are arranged in an array in the first direction D1 and the second direction D2 and extend along the third direction D3. The first direction D1 is a direction perpendicular to the top surface of the substrate 20 , the second direction D2 is a direction parallel to the top surface of the substrate 20 , the third direction D3 is a direction parallel to the top surface of the substrate 20 , and the third direction D1 is a direction perpendicular to the top surface of the substrate 20 . The second direction D2 intersects the third direction D3. In this embodiment, the first direction D1 is the Z-axis direction in the Cartesian coordinate system, the second direction D2 is the Y-axis direction in the Cartesian coordinate system, and the third direction D3 is the X-axis direction in the Cartesian coordinate system. Take the direction as an example to illustrate.

Referring to FIG. 14 , the first spacing d1 between adjacent semiconductor pillars 240 in the first direction D1 is greater than the second spacing d2 between adjacent semiconductor pillars 240 in the second direction D2, which can reduce the cost of manufacturing a semiconductor device. process difficulty.

In some embodiments, the semiconductor pillar 240 includes a capacitor area A1 and a word line area A2. The semiconductor device further includes a gate structure layer 260 located on the surface of the semiconductor pillar 240 in the word line area A2, and a gate structure layer 260 located on the surface of the semiconductor pillar 240 in the capacitor area A1. The capacitance structure layer 290, the gate structure layer 260 and the capacitance structure layer 290 are aligned through the same semiconductor pillar 240, which is beneficial to improving the reliability of the semiconductor device.

The above are only the preferred embodiments of the present invention. It should be noted that those skilled in the art can also make several improvements and modifications without departing from the principles of the present invention. These improvements and modifications should also be regarded as the present invention. protection scope of the invention.

Claims

A method for preparing a semiconductor device, including:

A substrate (20) and a stacked structure (21) located on the substrate (20) are formed. The stacked structure (21) includes first semiconductor layers (210) and first semiconductor layers (210) alternately stacked along a first direction (D1). Two semiconductor layers (220), the stacked structure (21) includes a capacitor region (A1), a word line region (A2) and a bit line region (A3), the first direction (D1) is perpendicular to the substrate The direction of the top surface of (20);

removing the second semiconductor layer (220) to form a first void (212);

Thinning the first semiconductor layer (210) along the first gap (212);

Part of the first semiconductor layer (210) is removed to form a plurality of semiconductor pillars (240). Each of the semiconductor pillars (240) extends along the third direction (D3) and the plurality of semiconductor pillars (240) are located therein. The arrays are arranged in the first direction (D1) and the second direction (D2), the second direction (D2) is a direction parallel to the top surface of the substrate (20), and the third direction (D3) ) is a direction parallel to the top surface of the substrate (20), and the second direction (D2) intersects the third direction (D3);

Form a gate structure layer (260) on the surface of the semiconductor pillar (240);

In the capacitance area (A1), the gate structure layer (260) on the surface of the semiconductor pillar (240) is removed, and a capacitance structure layer (290) is formed. The capacitance structure layer (290) covers the semiconductor pillar (240). 240) surface.
The method of manufacturing a semiconductor device according to claim 1, wherein the method of forming the stacked structure (21) located on the substrate (20) includes:

The first semiconductor layer (210) and the second semiconductor layer (220) alternately stacked along the first direction (D1) are formed on the substrate (20);

In the bit line area (A3), a plurality of first openings (230) arranged along the second direction (D2) are formed, and the first openings (230) penetrate along the first direction (D1). the first semiconductor layer (210) and the second semiconductor layer (220);

Remove a portion of the second semiconductor layer (220) between adjacent first openings (230) along the first opening (230), between the adjacent first semiconductor layers (210) Form initial void (211);

A first support layer (400) is formed within the initial gap (211).
The method of manufacturing a semiconductor device according to claim 2, wherein:

The method of removing part of the second semiconductor layer (220) between adjacent first openings (230) along the first opening (230) includes:

Fill the first opening (230) with an insulating layer (231);

Part of the insulating layer (231) is removed, and the remaining insulating layer (231) serves as a protective layer (234) to cover the opposite side walls of the first opening (230) in the third direction (D3), so The remaining area of the first opening (230) is used as the second opening (232);

The second semiconductor layer (220) exposed on the sidewall of the second opening (232) is removed along the second opening (232), and the second semiconductor layer (220) is formed between the adjacent first semiconductor layers (210). initial void(211);

After forming the first support layer (400), the protective layer (234) is removed to expose the first semiconductor layer (210) and the second semiconductor layer (220).
The method of manufacturing a semiconductor device according to claim 2 or 3, wherein the method of removing part of the first semiconductor layer (210) and forming a plurality of semiconductor pillars (240) includes:

A first mask layer (300) is formed on the stacked structure (21), the first mask layer (300) includes a plurality of first graphic windows (301), each of the first graphic windows (301 ) extends along the third direction (D3), and a plurality of the first graphics windows (301) are arranged along the second direction (D2);

Part of the first semiconductor layer (210) is removed along the first pattern window (301) to form the semiconductor pillar (240).
The method of manufacturing a semiconductor device according to claim 4, wherein the projection of the first pattern window (301) on the substrate (20) covers the first opening (230) on the substrate (20). 20); after the step of thinning the first semiconductor layer (210), it also includes: filling the first isolation layer (213) in the first gap (212);

The step of removing part of the first semiconductor layer (210) along the first pattern window (301) to form the semiconductor pillar (240) includes: removing part of the first isolation layer (213), leaving the first isolation layer (213) between the semiconductor pillars (240) arranged in the first direction (D1);

Perform ion implantation on the semiconductor pillar (240) to form a doped semiconductor pillar (240);

The first isolation layer (213) between the semiconductor pillars (240) arranged in the first direction (D1) is removed.
The method for manufacturing a semiconductor device according to any one of claims 1 to 5, wherein:

The method of forming the gate structure layer (260) on the surface of the semiconductor pillar (240) includes;

Form a gate dielectric layer (261) on the surface of the semiconductor pillar (240);

A gate material layer (262) is formed on the surface of the gate dielectric layer (261). In the first direction (D1), the gate material layer (262) located on the surface of the same layer of semiconductor pillars (240) is connected to ;

A second isolation layer (263) is filled between the adjacent gate structure layers (260) in the first direction (D1).
The method for manufacturing a semiconductor device according to any one of claims 2 to 5, wherein the method includes:

In the bit line area (A3), the first support layer (400), the gate structure layer (260) and the semiconductor pillar (240) are removed to form a bit line trench (271). Bit line trenches (271) penetrate the stacked structure (21);

Continue to remove part of the gate structure layer (260) along the sidewall of the bit line trench (271) to form a groove (272);

Forming a second support layer (250), the second support layer (250) filling between the first semiconductor layer (210) exposed by the groove (272);

forming a bit line material layer within the bit line trench (271);

The bit line material layer is patterned to form bit lines (270) spaced apart along the second direction (D2), and each of the bit lines (270) is consistent with the first direction (D1). A plurality of the arranged semiconductor pillars (240) are connected;

A third isolation layer (273) is formed between the bit lines (270).
The method of manufacturing a semiconductor device according to claim 7, wherein the step of forming the bit line trench (271) includes:

A second mask layer is formed on the surface of the stacked structure (21), the second mask layer has a second graphic window, and the second graphic window extends along the second direction (D2);

The first support layer (400), the gate structure layer (260) and the semiconductor pillar (240) are removed along the second pattern window to form the bit line trench (271).
The method for manufacturing a semiconductor device according to claim 7 or 8, wherein after the step of forming the bit lines (270) spaced apart along the second direction (D2), it further includes: in the capacitor region (A1 ) and the word line region (A2) form a third support layer (280), the third support layer (280) supports the semiconductor pillar (240).
The method of manufacturing a semiconductor device according to claim 9, wherein the method of forming the third support layer (280) includes:

A third mask layer (281) is formed on the surface of the stacked structure (21), the third mask layer (281) has a third graphic window (282), and the third graphic window (282) is along the second Extends in direction (D2) and corresponds to the junction of the capacitor area (A1) and the word line area (A2);

Remove the gate structure layer (260) along the third graphics window (282);

Fill the support material to form the third support layer (280).
The method for manufacturing a semiconductor device according to any one of claims 1 to 10, wherein in the capacitor region (A1), the gate structure layer (260) on the surface of the semiconductor pillar (240) is removed, and a capacitor is formed. Methods at the structural level (290) include:

In the capacitor area (A1), remove the gate structure layer (260) on the surface of the semiconductor pillar (240) to expose the surface of the semiconductor pillar (240);

Forming a lower electrode (291), the lower electrode (291) covering the exposed surface of the semiconductor pillar (240);

Form a dielectric layer (292), which covers the surface of the lower electrode (291);

An upper electrode (293) is formed, and the upper electrode (293) covers the surface of the dielectric layer (292).
The method of preparing a semiconductor device according to claim 11, wherein after forming the upper electrode (293), it further includes the following steps: forming a polysilicon layer (294), and the polysilicon layer (294) fills the upper electrode (293) ).
The method for manufacturing a semiconductor device according to any one of claims 1 to 12, wherein the capacitor region (A1), the word line region (A2) and the bit line (270) region (A3) are formed along the Arranged in the third direction (D3), the stacked structure (21) includes two of the capacitor regions (A1) and two of the word line regions (A2), and the bit line (270) region (A3) The two word line areas (A2) are arranged between the two word line areas (A2), and the two word line areas (A2) are arranged between the two capacitor areas (A1).
A semiconductor device, including:

substrate(20);

A plurality of semiconductor pillars (240) located on the substrate (20), the plurality of semiconductor pillars (240) are arranged in an array in the first direction (D1) and the second direction (D2) and along the third direction (D3) ) extends, the first direction (D1) is a direction perpendicular to the top surface of the substrate (20), and the second direction (D2) is a direction parallel to the top surface of the substrate (20) , the third direction (D3) is a direction parallel to the top surface of the substrate (20), and the second direction (D2) intersects the third direction (D3); in the first direction ( The first spacing (d1) between adjacent semiconductor pillars (240) in D1) is greater than the second spacing (d2) between adjacent semiconductor pillars (240) in the second direction (D2).
The semiconductor device according to claim 14, wherein the semiconductor pillar (240) includes a capacitor region (A1) and a word line region (A2), the semiconductor device further comprising:

The gate structure layer (260) located on the surface of the semiconductor pillar (240) in the word line region (A2);

A capacitor structure layer (290) located on the surface of the semiconductor pillar (240) of the capacitor region (A1).