WO2024041040A1 - Semiconductor device and preparation method therefor - Google Patents
Semiconductor device and preparation method therefor Download PDFInfo
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- WO2024041040A1 WO2024041040A1 PCT/CN2023/093819 CN2023093819W WO2024041040A1 WO 2024041040 A1 WO2024041040 A1 WO 2024041040A1 CN 2023093819 W CN2023093819 W CN 2023093819W WO 2024041040 A1 WO2024041040 A1 WO 2024041040A1
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 271
- 238000002360 preparation method Methods 0.000 title abstract description 11
- 239000000758 substrate Substances 0.000 claims abstract description 50
- 239000003990 capacitor Substances 0.000 claims abstract description 42
- 239000010410 layer Substances 0.000 claims description 318
- 238000000034 method Methods 0.000 claims description 63
- 238000002955 isolation Methods 0.000 claims description 25
- 238000004519 manufacturing process Methods 0.000 claims description 21
- 239000000463 material Substances 0.000 claims description 19
- 239000011241 protective layer Substances 0.000 claims description 10
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 4
- 229920005591 polysilicon Polymers 0.000 claims description 4
- 238000005468 ion implantation Methods 0.000 claims description 3
- 239000011800 void material Substances 0.000 claims 3
- 238000003491 array Methods 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 14
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 6
- 238000005530 etching Methods 0.000 description 6
- 230000010354 integration Effects 0.000 description 6
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 5
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 4
- 229910052710 silicon Inorganic materials 0.000 description 4
- 239000010703 silicon Substances 0.000 description 4
- 229910052581 Si3N4 Inorganic materials 0.000 description 3
- 238000001312 dry etching Methods 0.000 description 3
- 229920002120 photoresistant polymer Polymers 0.000 description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 3
- 238000003860 storage Methods 0.000 description 3
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- 235000012239 silicon dioxide Nutrition 0.000 description 2
- 239000000377 silicon dioxide Substances 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 1
- 229910002601 GaN Inorganic materials 0.000 description 1
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 description 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 description 1
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 1
- 238000000231 atomic layer deposition Methods 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 238000005137 deposition process Methods 0.000 description 1
- 229910052733 gallium Inorganic materials 0.000 description 1
- 230000015654 memory Effects 0.000 description 1
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 1
- 229910010271 silicon carbide Inorganic materials 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
Definitions
- the present disclosure relates to the field of integrated circuits, and in particular, to a semiconductor device and a manufacturing method thereof.
- DRAM Dynamic Random Access Memory
- DRAM Dynamic Random Access Memory
- each storage unit usually includes a transistor and a capacitor.
- memories such as DRAM are gradually developing from two-dimensional structures to three-dimensional structures.
- a superlattice stack structure of semiconductor layers and sacrificial layers needs to be formed first through a deposition process.
- the superlattice stack structure usually uses an epitaxial process to form a SiG layer on the Si layer.
- the technical problem to be solved by this disclosure is to provide a semiconductor device and a preparation method thereof, which can break through the limitations caused by the epitaxial thickness of the SiGe layer and facilitate an increase in integration density.
- embodiments of the present disclosure provide a method for manufacturing a semiconductor device, including: forming a substrate and a stacked structure located on the substrate, the stacked structure including first semiconductors stacked alternately along a first direction. layer and a second semiconductor layer, the stacked structure includes a capacitor region, a word line region and a bit line region, the first direction is a direction perpendicular to the top surface of the substrate; remove the second semiconductor layer, to Forming a first gap; thinning the first semiconductor layer along the first gap; removing part of the first semiconductor layer to form a plurality of semiconductor pillars, each of the semiconductor pillars extending along a third direction and having a plurality of The semiconductor pillars are arranged in an array in the first direction and the second direction, the second direction is a direction parallel to the top surface of the substrate, and the third direction is parallel to the top surface of the substrate.
- the second direction intersects the third direction; forming a gate structure layer on the surface of the semiconductor pillar; in the capacitor region, removing the gate structure layer on the surface of the semiconductor pillar, and forming and a capacitor structure layer covering the surface of the semiconductor pillar.
- Embodiments of the present disclosure also provide a semiconductor device, including: a substrate; a plurality of semiconductor pillars located on the substrate, the plurality of semiconductor pillars are arranged in an array in the first direction and the second direction and extend in the third direction.
- the first direction is a direction perpendicular to the top surface of the substrate
- the second direction is a direction parallel to the top surface of the substrate
- the third direction is parallel to the top surface of the substrate.
- the direction of the top surface, and the second direction intersects the third direction; the first distance between adjacent semiconductor pillars in the first direction is greater than the third distance between adjacent semiconductor pillars in the second direction.
- One spacing is
- the method for manufacturing a semiconductor device utilizes thinning of the first semiconductor layer to increase the first spacing between adjacent first semiconductor layers (and semiconductor pillars), thereby breaking through the limitations caused by insufficient epitaxial thickness of the second semiconductor layer. , which is conducive to increasing the integration density of semiconductor devices; embodiments of the present disclosure also provide a new preparation method, which first forms a gate structure layer and then forms bit lines and capacitors, which is conducive to expanding the application of semiconductor devices.
- Figure 1 is a schematic diagram of the steps of a method for manufacturing a semiconductor device provided by an embodiment of the present disclosure
- FIGS. 2-20 are schematic diagrams of the main process structures in the process of preparing semiconductor devices according to embodiments of the present disclosure.
- FIG. 1 is a schematic diagram of steps of a method for manufacturing a semiconductor device provided by an embodiment of the present disclosure.
- FIGS. 2-20 illustrate the main steps in the process of preparing a semiconductor device according to embodiments of the present disclosure. Schematic diagram of the process structure.
- the semiconductor device may be but is not limited to DRAM.
- FIG. 1 is a top view
- FIG. 1 is a schematic cross-sectional view along line A-A' in (a)
- (c) is a schematic cross-sectional view along line B-B' in (a)
- (d) is a schematic cross-sectional view along line CC′ in (a)
- step S10 forming a substrate 20 and a stacked structure 21 located on the substrate 20 .
- the stacked structure 21 includes first semiconductor layers 210 and second semiconductor layers 220 alternately stacked along a first direction D1.
- the stacked structure 21 includes a capacitor region A1, a word line region A2 and a bit line region A3.
- the first direction D1 is perpendicular to the substrate.
- the second direction D2 is a direction parallel to the top surface of the substrate 20 .
- the first direction D1 is the Z-axis direction in the Cartesian coordinate system
- the second direction D2 is the Y-axis direction in the Cartesian coordinate system.
- the substrate 20 may be, but is not limited to, a silicon substrate.
- the substrate 20 is a silicon substrate for description.
- the substrate 20 may be a semiconductor such as gallium nitride, gallium arsenide, gallium carbide, silicon carbide, or SOI.
- the substrate 20 is used to support the stacked structure 21 on its top surface.
- the first semiconductor layer 210 and the second semiconductor layer 220 are alternately stacked. This means that after forming a layer of the first semiconductor layer 210, a layer of the second semiconductor layer 220 is formed on the first semiconductor layer 210, and then the first semiconductor layer is formed in sequence. layer 210 and a second semiconductor layer 220 located on the first semiconductor layer 210 .
- the first semiconductor layer 210 is a silicon layer
- the second semiconductor layer 220 is a silicon germanium layer. Since the substrate 20 is a silicon substrate, a second semiconductor layer 220 is epitaxially formed on the substrate 20.
- the first semiconductor layer 210 is deposited on the second semiconductor, and the second semiconductor layer 220 is epitaxially formed on the first semiconductor layer 210 . This process is repeated to form the stacked structure 21 .
- the topmost layer of the stacked structure 21 is the second semiconductor layer 220 .
- the capacitor area A1, the word line area A2 and the bit line area A3 are arranged along the third direction D3.
- the stacked structure 21 includes two capacitor regions A1, two word line regions A2 and one bit line region A3.
- the bit line region A3 is disposed between the two word line regions A2.
- the two word line regions A2 It is arranged between the two capacitor regions A1, that is, a symmetrical structure is formed with the center line of the bit line region A3 as the symmetry axis. In other embodiments, it may only include one capacitor region A1, one word line region A2, and one bit line region A3 that are arranged in sequence.
- a plurality of first openings 230 arranged along the second direction D2 penetrate the first semiconductor layer 210 and the second semiconductor layer 220 along the first direction D1, that is, the first openings 230 expose the substrate 20, and the first opening 230 exposes the substrate 20. Partial side surfaces of the first semiconductor layer 210 and the second semiconductor layer 220 are exposed to the inner wall of the first opening 230 .
- a first support layer 400 is provided between the first semiconductor layers 210.
- the area between adjacent first openings 230 refers to the area corresponding to the stacked structure 21 between the adjacent first openings 230 .
- the first support layer 400 partially replaces the second semiconductor layer 220 and is disposed between adjacent first semiconductor layers 210 .
- the side surfaces of the first support layer 400 are also exposed to the inner wall of the first opening 230 .
- the first support layer 400 cuts the second semiconductor layer 220 into two parts, the first support layer 400 disposed between the two portions of the second semiconductor layer 220 .
- the present disclosure provides a method of forming stack structure 21 on substrate 20 .
- FIG. 2 Please refer to Figure 2, in which (a) is a top view, (b) is a schematic cross-sectional view along line A-A' in (a), and (c) is a schematic cross-sectional view along line B-B' in (a).
- First semiconductor layers 210 and second semiconductor layers 220 alternately stacked along the first direction D1 are formed on the bottom 20 . Wherein, an epitaxial process may be used to form the second semiconductor layer 220 on the first semiconductor layer 210 .
- FIG. 3 in which (a) is a top view, (b) is a schematic cross-sectional view along line A-A' in (a), (c) is a schematic cross-sectional view along line B-B' in (a), in place A plurality of first openings 230 arranged along the second direction D2 are formed in the line area A3.
- the first openings 230 penetrate the first semiconductor layer 210 and the second semiconductor layer 220 along the first direction D1.
- photolithography and etching processes can be used to form the first openings 230.
- the number of the first openings 230 can be specifically set according to the structural size of the semiconductor device, which is not limited in the embodiments of the present disclosure.
- the method of removing part of the second semiconductor layer 220 between adjacent first openings 230 along the first openings 230 includes:
- FIG. 4 Please refer to Figure 4, in which (a) is a top view, (b) is a schematic cross-sectional view along line A-A' in (a), and (c) is a schematic cross-sectional view along line B-B' in (a).
- the insulating layer 231 is filled in the first opening 230 , and the insulating layer 231 covers the inner wall of the first opening 230 .
- the insulating layer 231 may be a silicon oxide layer.
- FIG. 5 Please refer to Figure 5, in which (a) is a top view, (b) is a schematic cross-sectional view along line A-A' in (a), (c) is a schematic cross-sectional view along line B-B' in (a), with parts removed.
- the insulating layer 231 and the remaining insulating layer 231 serve as the protective layer 234 to cover the opposite side walls of the first opening 230 in the third direction D3, and the remaining area of the first opening 230 serves as the second opening 232.
- a dry etching process can be used to remove part of the insulating layer 231 .
- the two side walls of the first opening 230 that are oppositely arranged in the second direction D2 are partially exposed, and the two side walls that are oppositely arranged in the third direction D3 are covered by the protective layer 234 , and the exposed side walls of the first opening 230 are partially exposed.
- the edges and the side surfaces of the protective layer 234 define the second opening 232 . It can be understood that due to the influence of the thickness of the protective layer 234 , the edges of the two side walls of the first opening 230 oppositely arranged in the second direction D2 are also covered by the protective layer 234 .
- the exposed second semiconductor layer 220 on the sidewall of the second opening 232 is removed, and an initial gap 211 is formed between adjacent first semiconductor layers 210 .
- the topmost second semiconductor layer 220 is removed, the top first semiconductor layer 210 is exposed as the topmost layer, and the protective layer 234 corresponding to the topmost second semiconductor layer 220 is also removed accordingly.
- the method of forming the first support layer 400 includes: depositing a support layer material in the stack structure 21; etching to remove the upper surface of the stack structure 21 (ie, the surface of the topmost first semiconductor layer 210) and the inside of the second opening 232.
- the support layer material remaining in the initial gap 211 serves as the first support layer 400 .
- the first support layer 400 may be a silicon nitride layer.
- the protective layer 234 is removed, and the first semiconductor layer 210 and the second semiconductor layer 220 are exposed.
- a dry etching process may be used to remove the protective layer 234 .
- step S11 the second semiconductor layer 220 is removed to form the first gap 212.
- step S11 the second semiconductor layer 220 is completely removed, exposing the surface of the first semiconductor layer 210 .
- the second semiconductor layer 220 in the capacitor region A1, the word line region A2, and the bit line region A3 is removed along the first opening 230 to form the first gap 212.
- the second semiconductor layer 220 is completely removed, exposing the surface of the first semiconductor layer 210 .
- an epitaxial process is used to form the second semiconductor layer 220 on the first semiconductor layer 210.
- the second semiconductor layer 220 Due to the lattice mismatch between the second semiconductor layer 220 and the first semiconductor layer 210, the second semiconductor layer 220 The epitaxial thickness on the first semiconductor layer 210 is limited, so after the second semiconductor layer 220 is removed, the first distance d1 between the two adjacent first semiconductor layers 210 in the first direction D1 is smaller, and The first distance d1 between two adjacent first semiconductor layers 210 is too small, so that in subsequent processes, the distance between the semiconductor structures in the first direction D1 is limited, for example, between the two adjacent first semiconductor layers 210 The first spacing d1 between the two adjacent bit lines can define the distance between the adjacent bit lines formed subsequently.
- the distance between the adjacent bit lines will be affected. It may even affect the spacing of the subsequently formed word line structures, which increases the difficulty of the process and is not conducive to the increase in integration density. It may even make it impossible to connect word line structures on the same layer, affecting the reliability of semiconductor devices.
- the preparation method provided by the embodiment of the present disclosure increases the spacing between the first semiconductor layers 210 by thinning the first semiconductor layers 210 .
- Figure 10 (a) is a top view, (b) is a schematic cross-sectional view along line A-A' in (a), and (c) is a schematic cross-sectional view along line A-A' in (a).
- a lateral etching process is used to etch the first semiconductor layer 210 through the first gap 212, that is, the first semiconductor layer 210 is thinned from the upper and lower surfaces of the first semiconductor layer 210, and is adjacent in the first direction D1.
- the first distance d1 between the first semiconductor layers 210 increases.
- FIG 14 (a) is a top view, (b) is a cross-sectional view along line A-A' in (a), and (c) is a cross-sectional view along line B- in (a).
- a schematic cross-sectional view of line B' (d) is a schematic cross-sectional view along line C-C' in (a)
- (e) is a schematic cross-sectional view along line D-D' in (a)
- step S13 remove part
- a semiconductor layer 210 forms a plurality of semiconductor pillars 240.
- Each semiconductor pillar 240 extends along the third direction D3 and the plurality of semiconductor pillars 240 are arranged in an array in the first direction D1 and the second direction D2.
- the third direction D3 is parallel.
- the second direction D2 intersects the third direction D3.
- the third direction D3 is the X-axis direction in the Cartesian coordinate system as an example for explanation. Since the first semiconductor layer 210 is thinned, that is, the first distance d1 between adjacent semiconductor pillars 240 in the first direction D1 increases, for example, is greater than the distance d1 between adjacent semiconductor pillars 240 in the second direction D2.
- the second spacing d2 prevents the distance between adjacent bit lines from being affected and reduces the difficulty of the process.
- embodiments of the present disclosure provide a method of removing part of the first semiconductor layer 210 to form a plurality of semiconductor pillars 240 .
- the method includes the following steps:
- Figure 11 (a) is a top view, (b) is a schematic cross-sectional view along line A-A' in (a), and (c) is a cross-section along line BB' in (a). Schematic diagram, (d) is a schematic cross-sectional diagram along line CC′ in (a), in which the first isolation layer 213 is filled in the first gap 212 .
- the first isolation layer 213 is an oxide layer, which is filled in the first gap 212 between the first semiconductor layers 210 to support the first semiconductor layer 210 . Due to limitations of the semiconductor process, in some embodiments, the first isolation layer 213 also covers the top surface of the stacked structure 21. In this step, the step of removing the first isolation layer 213 on the top surface of the stacked structure 21 may also be included. The first semiconductor layer 210 on the top surface is exposed to avoid covering the first isolation layer 213 on the surface of the top semiconductor pillar 240 formed in the subsequent process, thereby affecting the contact between the gate structure layer formed in the subsequent process and the surface of the semiconductor pillar 240 .
- FIG 12 (a) is a top view, (b) is a schematic cross-sectional view along line A-A' in (a), and (c) is a cross-section along line BB' in (a).
- Schematic diagram, (d) is a cross-sectional schematic diagram along line CC' in (a)
- a first mask layer 300 is formed on the stacked structure 21, the first mask layer 300 includes a plurality of first pattern windows 301, each The first graphics window 301 extends along the third direction D3, and the plurality of first graphics windows 301 are arranged along the second direction D2.
- a layer of mask material is first coated, and then the mask material layer is patterned to form mask strips arranged at intervals, and the spaces between adjacent mask strips are First graphics window 301.
- the first pattern window 301 exposes the first opening 230, and in subsequent processes, the first isolation layer 213 filled in the first opening 230 can be completely removed to avoid affecting the structure of the semiconductor pillar 240.
- the first mask layer 300 may be a photoresist layer. In other embodiments, the first mask layer 300 may also be a hard mask layer.
- the projection of the first pattern window 301 on the substrate 20 covers the projection of the first opening 230 on the substrate 20 , that is, the first pattern window 301 exposes the first isolation layer 213 filled in the first opening 230 .
- FIG. 13 (a) is a top view, (b) is a schematic cross-sectional view along line A-A' in (a), and (c) is a cross-section along line BB' in (a).
- Schematic diagram (d) is a schematic cross-sectional view along line C-C' in (a)
- (e) is a schematic cross-sectional view along line D-D' in (a)
- the first graphics window 301 remove part of the first Semiconductor layer 210 forms semiconductor pillars 240.
- part of the first isolation layer 213 is removed, leaving the first isolation layer 213 between the semiconductor pillars 240 arranged in the first direction D1 to support the semiconductor pillars 240 .
- the first support layer 400 in the area corresponding to the first graphics window 301 is also removed.
- this step also includes: performing ion implantation on the semiconductor pillar 240 to form a doped semiconductor pillar 240 in preparation for subsequent formation of transistor and capacitor structures.
- ion implantation may also be performed when forming the first semiconductor layer 210 .
- the first isolation layer 213 between the semiconductor pillars 240 arranged in the first direction D1 is removed, and the surfaces of the semiconductor pillars 240 are exposed. Specifically, an etching process may be used to remove the first isolation layer 213 . In this step, the first mask layer 300 is also removed.
- FIG 15 (a) is a top view, (b) is a schematic cross-sectional view along line A-A' in (a), and (c) is a cross-section along line BB' in (a).
- the gate structure layer 260 corresponding to the word line region A2 serves as the gate electrode, and the semiconductor pillar 240 corresponding to the gate electrode serves as the channel region.
- the gate structure layer 260 includes a gate dielectric layer 261 and a gate material layer 262.
- the step of forming the gate structure layer 260 on the surface of the semiconductor pillar 240 includes:
- a gate dielectric layer 261 is formed on the surface of the semiconductor pillar 240 , that is, the gate dielectric layer 261 covers the surface of the semiconductor pillar 240 .
- the gate dielectric layer 261 may be silicon oxide or a high-K dielectric layer. Among them, the gate dielectric layer 261 can be formed using processes such as chemical vapor deposition and atomic layer deposition.
- a gate material layer 262 is formed on the surface of the gate dielectric layer 261 , that is, the gate material layer 262 covers the surface of the gate dielectric layer 261 .
- the gate material layers 262 located on the same layer are connected.
- each semiconductor pillar 240 extends along the third direction D3.
- the semiconductor pillars 240 arranged in sequence in the second direction D2 are in the same layer, and the semiconductor pillars 240 arranged in sequence in the first direction D1 are in different layers.
- the gate material layer 262 covering the surface of the semiconductor pillar 240 of the same layer is connected to form an overall structure.
- Gate material layer 262 may be a tungsten layer.
- the second isolation layer 263 is filled in the gap between adjacent gate structure layers 260 in the first direction D1, and the second isolation layer 263 is filled with the stacked structure 21 to play a supporting role. In this embodiment, the second isolation layer 263 also covers the top surface of the stacked structure 21 .
- the second isolation layer 263 includes, but is not limited to, a silicon dioxide layer.
- the preparation method also includes the step of forming bit lines.
- bit lines Specifically, please refer to Figure 18.
- (a) is a top view
- (b) is a schematic cross-sectional view along line A-A' in (a)
- (c) is a schematic cross-sectional view along line B-B in (a).
- ' line schematic cross-sectional view is a schematic cross-sectional view along line C-C' in (a)
- (e) is a schematic cross-sectional view along line D-D' in (a)
- bit line area A3 remove The first support layer 400, the gate structure layer 260 and the semiconductor pillar 240 form a plurality of bit lines 270.
- Each bit line 270 extends along the first direction D1 and the third direction D3, and the plurality of bit lines 270 extend along the second direction D1. Arranged at intervals in direction D2. In the semiconductor structure formed in this step, the semiconductor pillars 240 located on both sides of the bit line 270 are connected to the bit line 270, and both share the same bit line 270.
- embodiments of the present disclosure also provide a method of forming multiple bit lines 270.
- the method includes the following steps:
- FIG 16 (a) is a top view, (b) is a schematic cross-sectional view along line A-A' in (a), and (c) is a cross-section along line BB' in (a).
- the gate structure layer 260 and the semiconductor pillar 240 form a bit line trench 271.
- the bit line trench 271 penetrates the stack structure 21; continue to remove part of the gate structure layer 260 along the sidewall of the bit line trench 271 to form a groove 272. .
- the second isolation layer 263 is also partially removed.
- the semiconductor pillar 240 is divided into two parts disposed on opposite sides of the bit line trench 271 , and the groove 272 is recessed in a direction away from the center of the bit line trench 271 .
- a dry etching process may be used to form the bit line trench 271
- a lateral etching process may be used to form the groove 272.
- embodiments of the present disclosure provide a method of forming a bit line trench 271.
- the method includes: forming a second mask layer on the surface of the stacked structure 21, the second mask layer having a second pattern window, and the second pattern window is formed along the surface of the stack structure 21.
- the second direction D2 extends; along the second pattern window, the first support layer 400, the gate structure layer 260 and the semiconductor pillar 240 are removed to form a bit line trench 271.
- the second mask layer is a photoresist layer, and the bit line trench 271 is formed using photolithography and etching processes.
- the second mask layer may also be a mask structure such as a hard mask.
- FIG 17 (a) is a top view, (b) is a schematic cross-sectional view along line A-A' in (a), and (c) is a cross-section along line BB' in (a).
- the second support layer 250 is not only used to support the semiconductor pillar 240, but also is used to isolate the bit line 270 and the gate electrode.
- a silicon nitride layer is deposited and filled in the groove 272 as the second support layer 250 .
- the second mask layer used when forming the bit line trench 271 can be used as a mask layer when depositing the second support material.
- bit line material layer is formed in the bit line trench; the bit line material layer is patterned to form bit lines 270 spaced apart along the second direction D2, and each bit line 270 is in contact with the bit line 270 along the first direction.
- the plurality of semiconductor pillars 240 arranged in D1 are connected; a third isolation layer 273 is formed between the bit lines 270, and the third isolation layer 273 is used to isolate adjacent bit lines 270 in the second direction D2.
- the third isolation layer 273 includes but is not limited to silicon dioxide.
- Figure 19 (a) is a top view, (b) is a schematic cross-sectional view along line A-A' in (a), and (c) is a cross-section along line BB' in (a).
- the third support layer 280 is not only used to support the semiconductor pillar 240, but also is used to isolate the word line region A2 and the capacitor region A1 to prevent them from being electrically connected, thus affecting the reliability of the semiconductor device.
- the gate structure layer 260 located between the second support layer 250 and the third support layer 280 serves as the gate structure of the transistor, and its corresponding semiconductor pillar 240 serves as the channel region of the transistor.
- embodiments of the present disclosure provide a method of forming the third support layer 280.
- the method includes: forming a third mask layer 281 on the surface of the stacked structure 21, the third mask layer 281 having a third pattern window 282,
- the three pattern windows 282 extend along the second direction D2 and correspond to the junction of the capacitor region A1 and the word line region A2; along the third pattern window 282, the gate structure layer 260 is removed; the support material is filled to form the third support layer 280.
- the third mask layer 281 may be a photoresist layer
- the third support layer 280 may be a silicon nitride layer.
- FIG 20 Please refer to Figure 20.
- (a) is a top view
- (b) is a schematic cross-sectional view along line A-A' in (a)
- (c) is a cross-section along line C-C' in (a).
- Schematic diagram (d) is a schematic cross-sectional view along the line D-D' in (a)
- (e) is a schematic cross-sectional view along the line EE' in (a)
- step S15, in the capacitor area A1 remove the semiconductor pillar
- the gate structure layer 260 on the surface of the semiconductor pillar 240 is formed, and the capacitance structure layer 290 is formed.
- the capacitance structure layer 290 covers the surface of the semiconductor pillar 240.
- a capacitor structure layer 290 is formed in both capacitor regions A1.
- the capacitor structure layer 290 includes a lower electrode 291, a dielectric layer 292 and an upper electrode 293.
- the lower electrode 291 can be titanium nitride
- the dielectric layer 292 can be The high-K dielectric layer and the upper electrode 293 may be titanium nitride.
- embodiments of the present disclosure provide a method of forming the capacitor structure layer 290 .
- the method includes: removing the gate structure layer 260 on the surface of the semiconductor pillar 240 in the capacitor area A1 to expose the surface of the semiconductor pillar 240 .
- a lower electrode 291 is formed, and the lower electrode 291 covers the surface of the semiconductor pillar 240; a dielectric layer 292 is formed, and the dielectric layer 292 covers the surface of the lower electrode 291; and an upper electrode 293 is formed, and the upper electrode 293 covers the surface of the dielectric layer 292.
- the following steps are also included: forming a polysilicon layer 294, and the polysilicon layer 294 fills the gaps between the upper electrodes 293.
- the method for manufacturing a semiconductor device increases the spacing between adjacent first semiconductor layers 210 in the first direction D1 by thinning the first semiconductor layer 210, thereby reducing the difficulty of the process and facilitating integration.
- the increase in density improves the reliability of semiconductor devices.
- the preparation method provided by the embodiment of the present disclosure is a new method of preparing a semiconductor device, which forms the capacitor structure after forming the gate structure and the bit line 270, instead of forming the gate structure and the capacitor structure after forming the capacitor structure. Bit line 270.
- the step of thinning the first semiconductor layer is performed before the step of forming the semiconductor pillars, which can better control the distance between semiconductor pillars on the same layer (adjacent in the second direction D2). spacing (such as the second spacing d2), so that the gate structure layers of the same layer can be bonded more easily. It can be understood that in other embodiments of the present disclosure, the step of thinning the semiconductor pillars may also be performed after the semiconductor pillars are formed.
- the semiconductor device includes a substrate 20 and a plurality of semiconductor pillars 240 located on the substrate 20 .
- the plurality of semiconductor pillars 240 are arranged in an array in the first direction D1 and the second direction D2 and extend along the third direction D3.
- the first direction D1 is a direction perpendicular to the top surface of the substrate 20
- the second direction D2 is a direction parallel to the top surface of the substrate 20
- the third direction D3 is a direction parallel to the top surface of the substrate 20
- the third direction D1 is a direction perpendicular to the top surface of the substrate 20 .
- the second direction D2 intersects the third direction D3.
- the first direction D1 is the Z-axis direction in the Cartesian coordinate system
- the second direction D2 is the Y-axis direction in the Cartesian coordinate system
- the third direction D3 is the X-axis direction in the Cartesian coordinate system. Take the direction as an example to illustrate.
- the first spacing d1 between adjacent semiconductor pillars 240 in the first direction D1 is greater than the second spacing d2 between adjacent semiconductor pillars 240 in the second direction D2, which can reduce the cost of manufacturing a semiconductor device. process difficulty.
- the semiconductor pillar 240 includes a capacitor area A1 and a word line area A2.
- the semiconductor device further includes a gate structure layer 260 located on the surface of the semiconductor pillar 240 in the word line area A2, and a gate structure layer 260 located on the surface of the semiconductor pillar 240 in the capacitor area A1.
- the capacitance structure layer 290, the gate structure layer 260 and the capacitance structure layer 290 are aligned through the same semiconductor pillar 240, which is beneficial to improving the reliability of the semiconductor device.
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Abstract
A preparation method for a semiconductor device comprises: forming a substrate and a stack structure located on the substrate, wherein the stack structure comprises first semiconductor layers and second semiconductor layers, which are alternately stacked in a first direction, and the stack structure comprises a capacitor region, a wordline region and a bitline region; removing the second semiconductor layers to form first gaps; thinning the first semiconductor layers along the first gaps; removing part of the first semiconductor layers to form a plurality of semiconductor columns, wherein each semiconductor column extends in a third direction, and the plurality of semiconductor columns are arranged in an array in the first direction and a second direction; forming a gate structure layer on a surface of each semiconductor column; and removing the gate structure layers on the surfaces of the semiconductor columns in the capacitor region and forming capacitor structure layers, wherein the capacitor structure layers cover the surfaces of the semiconductor columns.
Description
相关申请引用说明Related application citations
本申请要求于2022年08月26日递交的中国专利申请号202211034211.8、申请名为“半导体器件及其制备方法”的优先权,其全部内容以引用的形式附录于此。This application claims priority to the Chinese patent application number 202211034211.8 and the application title "Semiconductor Device and Preparation Method thereof" submitted on August 26, 2022, the entire content of which is appended hereto by reference.
本公开涉及集成电路领域,尤其涉及一种半导体器件及其制备方法。The present disclosure relates to the field of integrated circuits, and in particular, to a semiconductor device and a manufacturing method thereof.
动态随机存储器(Dynamic Random Access Memory,DRAM)是计算机等电子设备中常用的半导体器件,其由多个存储单元构成,每个存储单元通常包括晶体管和电容器。为了满足高的存储密度和高的集成度的要求,DRAM等存储器逐渐由二维结构向三维结构发展。具有三维结构的DRAM等半导体结构在制造过程中需要先通过沉积工艺形成半导体层和牺牲层的超晶格堆栈结构,超晶格堆栈结构通常采用外延工艺在Si层上形成SiG层,而由于SiGe层与Si层之间存在晶格失配,导致SiGe层在Si层上的外延厚度受到限制,而有限的外延厚度使得半导体器件在竖直方向的间距受限,增大了工艺制程难度,不利于集成密度的增加。Dynamic Random Access Memory (DRAM) is a semiconductor device commonly used in electronic equipment such as computers. It is composed of multiple storage units, and each storage unit usually includes a transistor and a capacitor. In order to meet the requirements of high storage density and high integration, memories such as DRAM are gradually developing from two-dimensional structures to three-dimensional structures. During the manufacturing process of semiconductor structures such as DRAM with a three-dimensional structure, a superlattice stack structure of semiconductor layers and sacrificial layers needs to be formed first through a deposition process. The superlattice stack structure usually uses an epitaxial process to form a SiG layer on the Si layer. Since SiGe There is a lattice mismatch between the SiGe layer and the Si layer, which limits the epitaxial thickness of the SiGe layer on the Si layer. The limited epitaxial thickness limits the spacing of semiconductor devices in the vertical direction, increasing the difficulty of the process. Conducive to the increase in integration density.
发明内容Contents of the invention
本公开所要解决的技术问题是,提供一种半导体器件及其制备方法,其能够突破SiGe层外延厚度带来的限制,有利于集成密度的增加。The technical problem to be solved by this disclosure is to provide a semiconductor device and a preparation method thereof, which can break through the limitations caused by the epitaxial thickness of the SiGe layer and facilitate an increase in integration density.
为了解决上述问题,本公开实施例提供了一种半导体器件的制备方法,包括:形成衬底以及位于所述衬底上的堆叠结构,所述堆叠结构包括沿第一方向交替堆叠的第一半导体层和第二半导体层,所述堆叠结构包括电容区、字线区及位线区,所述第一方向为垂直于所述衬底的顶面的方向;去除所述第二半导体层,以形成第一空隙;沿所述第一空隙减薄所述第一半导体层;去除部分所述第一半导体层,形成多个半导体柱,每一所述半导体柱沿第三方向延伸且多个所述半导体柱在所述第一方向及第二方向上阵列排布,所述第二方向为平行于所述衬底的顶面的方向,所述第三方向为平行于所述衬底的顶面的方向,且所述第二方向与所述第三方向相交;在所述半导体柱表面形成栅极结构层;在所述电容区,去除所述半导体柱表面的栅极结构层,并形成电容结构层,所述电容结构层覆盖所述半导体柱表面。In order to solve the above problems, embodiments of the present disclosure provide a method for manufacturing a semiconductor device, including: forming a substrate and a stacked structure located on the substrate, the stacked structure including first semiconductors stacked alternately along a first direction. layer and a second semiconductor layer, the stacked structure includes a capacitor region, a word line region and a bit line region, the first direction is a direction perpendicular to the top surface of the substrate; remove the second semiconductor layer, to Forming a first gap; thinning the first semiconductor layer along the first gap; removing part of the first semiconductor layer to form a plurality of semiconductor pillars, each of the semiconductor pillars extending along a third direction and having a plurality of The semiconductor pillars are arranged in an array in the first direction and the second direction, the second direction is a direction parallel to the top surface of the substrate, and the third direction is parallel to the top surface of the substrate. direction of the surface, and the second direction intersects the third direction; forming a gate structure layer on the surface of the semiconductor pillar; in the capacitor region, removing the gate structure layer on the surface of the semiconductor pillar, and forming and a capacitor structure layer covering the surface of the semiconductor pillar.
本公开实施例还提供一种半导体器件,包括:衬底;位于衬底上的多个半导体柱,多个所述半导体柱在第一方向及第二方向上阵列排布且沿第三方向延伸,所述第一方向为垂直于所述衬底的顶面的方向,所述第二方向为平行于所述衬底的顶面的方向,所述第三方向为平行于所述衬底的顶面的方向,且所述第二方向与所述第三方向相交;在第一方向上相邻的半导体柱之间的第一间距大于在第二方向上相邻的半导体柱之间的第一间距。Embodiments of the present disclosure also provide a semiconductor device, including: a substrate; a plurality of semiconductor pillars located on the substrate, the plurality of semiconductor pillars are arranged in an array in the first direction and the second direction and extend in the third direction. , the first direction is a direction perpendicular to the top surface of the substrate, the second direction is a direction parallel to the top surface of the substrate, and the third direction is parallel to the top surface of the substrate. The direction of the top surface, and the second direction intersects the third direction; the first distance between adjacent semiconductor pillars in the first direction is greater than the third distance between adjacent semiconductor pillars in the second direction. One spacing.
本公开实施例提供的半导体器件的制备方法利用减薄第一半导体层增加相邻第一半导体层(及半导体柱)之间的第一间距,突破了第二半导体层外延厚度不足带来的限制,有利于半导体器件集成密度的增加;本公开实施例还提供一种新的制备方法,其先形成栅极结构层再形成位线及电容,有利于扩大半导体器件的应用。The method for manufacturing a semiconductor device provided by embodiments of the present disclosure utilizes thinning of the first semiconductor layer to increase the first spacing between adjacent first semiconductor layers (and semiconductor pillars), thereby breaking through the limitations caused by insufficient epitaxial thickness of the second semiconductor layer. , which is conducive to increasing the integration density of semiconductor devices; embodiments of the present disclosure also provide a new preparation method, which first forms a gate structure layer and then forms bit lines and capacitors, which is conducive to expanding the application of semiconductor devices.
图1是本公开一实施例提供的半导体器件的制备方法的步骤示意图;Figure 1 is a schematic diagram of the steps of a method for manufacturing a semiconductor device provided by an embodiment of the present disclosure;
图2-图20是本公开实施例在制备半导体器件的过程中主要的工艺结构示意图。2-20 are schematic diagrams of the main process structures in the process of preparing semiconductor devices according to embodiments of the present disclosure.
下面结合附图对本公开提供的半导体器件的制备方法的具体实施方式做详细说明。Specific embodiments of the method for manufacturing a semiconductor device provided by the present disclosure will be described in detail below with reference to the accompanying drawings.
本公开实施例提供一种半导体器件的制备方法,图1是本公开一实施例提供的半导体器件的制备方法的步骤示意图,图2-图20是本公开实施例在制备半导体器件的过程中主要的工艺结构示意图。在本实施例中,半导体器件可以是但不限于DRAM。
Embodiments of the present disclosure provide a method for manufacturing a semiconductor device. FIG. 1 is a schematic diagram of steps of a method for manufacturing a semiconductor device provided by an embodiment of the present disclosure. FIGS. 2-20 illustrate the main steps in the process of preparing a semiconductor device according to embodiments of the present disclosure. Schematic diagram of the process structure. In this embodiment, the semiconductor device may be but is not limited to DRAM.
请参阅图1至图8,其中(a)为俯视图,(b)为沿(a)中A-A’线的截面示意图,(c)为沿(a)中B-B’线的截面示意图,(d)为沿(a)中C-C’线的截面示意图,步骤S10,形成衬底20以及位于衬底20上的堆叠结构21。堆叠结构21包括沿第一方向D1交替堆叠的第一半导体层210和第二半导体层220,堆叠结构21包括电容区A1、字线区A2及位线区A3,第一方向D1为垂直于衬底20的顶面的方向,第二方向D2为平行于衬底20的顶面的方向。Please refer to Figures 1 to 8, in which (a) is a top view, (b) is a schematic cross-sectional view along line A-A' in (a), (c) is a schematic cross-sectional view along line B-B' in (a) , (d) is a schematic cross-sectional view along line CC′ in (a), step S10 , forming a substrate 20 and a stacked structure 21 located on the substrate 20 . The stacked structure 21 includes first semiconductor layers 210 and second semiconductor layers 220 alternately stacked along a first direction D1. The stacked structure 21 includes a capacitor region A1, a word line region A2 and a bit line region A3. The first direction D1 is perpendicular to the substrate. The second direction D2 is a direction parallel to the top surface of the substrate 20 .
在本实施例中,以第一方向D1为笛卡尔坐标系中的Z轴方向,第二方向D2为笛卡尔坐标系中的Y轴方向为例进行说明。In this embodiment, the first direction D1 is the Z-axis direction in the Cartesian coordinate system, and the second direction D2 is the Y-axis direction in the Cartesian coordinate system.
衬底20可以是但不限于硅衬底,本实施例以衬底20为硅衬底为例进行说明。在其他示例中,衬底20可以为氮化镓、砷化镓、碳化镓、碳化硅或SOI等半导体。衬底20用于支撑位于其顶面上的堆叠结构21。The substrate 20 may be, but is not limited to, a silicon substrate. In this embodiment, the substrate 20 is a silicon substrate for description. In other examples, the substrate 20 may be a semiconductor such as gallium nitride, gallium arsenide, gallium carbide, silicon carbide, or SOI. The substrate 20 is used to support the stacked structure 21 on its top surface.
第一半导体层210和第二半导体层220交替堆叠是指:形成一层第一半导体层210后,在第一半导体层210上形成一层第二半导体层220,然后依次循环进行形成第一半导体层210和位于第一半导体层210上的第二半导体层220的步骤。本实施例中,第一半导体层210为硅层,第二半导体层220为硅锗层,由于衬底20为硅衬底,则在衬底20上外延形成一层第二半导体层220,在第二半导体上沉积第一半导体层210,再在第一半导体层210上外延形成第二半导体层220,如此重复,形成堆叠结构21。在本实施例中,堆叠结构21最顶层为第二半导体层220。The first semiconductor layer 210 and the second semiconductor layer 220 are alternately stacked. This means that after forming a layer of the first semiconductor layer 210, a layer of the second semiconductor layer 220 is formed on the first semiconductor layer 210, and then the first semiconductor layer is formed in sequence. layer 210 and a second semiconductor layer 220 located on the first semiconductor layer 210 . In this embodiment, the first semiconductor layer 210 is a silicon layer, and the second semiconductor layer 220 is a silicon germanium layer. Since the substrate 20 is a silicon substrate, a second semiconductor layer 220 is epitaxially formed on the substrate 20. The first semiconductor layer 210 is deposited on the second semiconductor, and the second semiconductor layer 220 is epitaxially formed on the first semiconductor layer 210 . This process is repeated to form the stacked structure 21 . In this embodiment, the topmost layer of the stacked structure 21 is the second semiconductor layer 220 .
电容区A1、字线区A2及位线区A3沿第三方向D3排布。在本实施例中,堆叠结构21包括两个电容区A1、两个字线区A2及一个位线区A3,位线区A3设置在两个字线区A2之间,两个字线区A2设置在两个电容区A1之间,即形成以位线区A3中心线为对称轴的对称结构。在另一些实施例中,也可仅包括依次设置的一个电容区A1、一个字线区A2及一个位线区A3。The capacitor area A1, the word line area A2 and the bit line area A3 are arranged along the third direction D3. In this embodiment, the stacked structure 21 includes two capacitor regions A1, two word line regions A2 and one bit line region A3. The bit line region A3 is disposed between the two word line regions A2. The two word line regions A2 It is arranged between the two capacitor regions A1, that is, a symmetrical structure is formed with the center line of the bit line region A3 as the symmetry axis. In other embodiments, it may only include one capacitor region A1, one word line region A2, and one bit line region A3 that are arranged in sequence.
在位线区A3,多个沿第二方向D2排布的第一开口230沿第一方向D1贯穿第一半导体层210及第二半导体层220,即第一开口230暴露出衬底20,第一半导体层210及第二半导体层220的部分侧面暴露于第一开口230的内壁。在相邻的第一开口230之间的区域,在第一半导体层210之间设置有第一支撑层400。In the bit line region A3, a plurality of first openings 230 arranged along the second direction D2 penetrate the first semiconductor layer 210 and the second semiconductor layer 220 along the first direction D1, that is, the first openings 230 expose the substrate 20, and the first opening 230 exposes the substrate 20. Partial side surfaces of the first semiconductor layer 210 and the second semiconductor layer 220 are exposed to the inner wall of the first opening 230 . In a region between adjacent first openings 230, a first support layer 400 is provided between the first semiconductor layers 210.
相邻的第一开口230之间的区域是指在相邻的第一开口230之间的堆叠结构21所对应的区域。在该区域,第一支撑层400部分替代第二半导体层220,设置在相邻的第一半导体层210之间,第一支撑层400的侧面也暴露于第一开口230的内壁。具体地说,在相邻的第一开口230之间的区域,在第三方向D3上,在同一层中,第一支撑层400将第二半导体层220截断为两部分,第一支撑层400设置在该两部分第二半导体层220之间。The area between adjacent first openings 230 refers to the area corresponding to the stacked structure 21 between the adjacent first openings 230 . In this area, the first support layer 400 partially replaces the second semiconductor layer 220 and is disposed between adjacent first semiconductor layers 210 . The side surfaces of the first support layer 400 are also exposed to the inner wall of the first opening 230 . Specifically, in the area between adjacent first openings 230, in the third direction D3, in the same layer, the first support layer 400 cuts the second semiconductor layer 220 into two parts, the first support layer 400 disposed between the two portions of the second semiconductor layer 220 .
作为示例,本公开实施提供一种在衬底20上形成堆叠结构21的方法。As an example, the present disclosure provides a method of forming stack structure 21 on substrate 20 .
请参阅图2,其中(a)为俯视图,(b)为沿(a)中A-A’线的截面示意图,(c)为沿(a)中B-B’线的截面示意图,在衬底20上形成沿第一方向D1交替堆叠的第一半导体层210和第二半导体层220。其中,可采用外延工艺在第一半导体层210上形成第二半导体层220。Please refer to Figure 2, in which (a) is a top view, (b) is a schematic cross-sectional view along line A-A' in (a), and (c) is a schematic cross-sectional view along line B-B' in (a). First semiconductor layers 210 and second semiconductor layers 220 alternately stacked along the first direction D1 are formed on the bottom 20 . Wherein, an epitaxial process may be used to form the second semiconductor layer 220 on the first semiconductor layer 210 .
请参阅图3,其中(a)为俯视图,(b)为沿(a)中A-A’线的截面示意图,(c)为沿(a)中B-B’线的截面示意图,在位线区A3,形成多个沿第二方向D2排布的第一开口230,第一开口230沿第一方向D1贯穿第一半导体层210及第二半导体层220。在该步骤中,可采用光刻及刻蚀工艺形成第一开口230,第一开口230的数量可根据半导体器件的结构尺寸进行具体设置,本公开实施例对此不进行限定。Please refer to Figure 3, in which (a) is a top view, (b) is a schematic cross-sectional view along line A-A' in (a), (c) is a schematic cross-sectional view along line B-B' in (a), in place A plurality of first openings 230 arranged along the second direction D2 are formed in the line area A3. The first openings 230 penetrate the first semiconductor layer 210 and the second semiconductor layer 220 along the first direction D1. In this step, photolithography and etching processes can be used to form the first openings 230. The number of the first openings 230 can be specifically set according to the structural size of the semiconductor device, which is not limited in the embodiments of the present disclosure.
请参阅图6,其中(a)为俯视图,(b)为沿(a)中A-A’线的截面示意图,(c)为沿(a)中B-B’线的截面示意图,(d)为沿(a)中C-C’线的截面示意图,沿第一开口230,去除相邻的第一开口230之间的部分第二半导体层220,在相邻的第一半导体层210之间形成初始空隙211。Please refer to Figure 6, in which (a) is a top view, (b) is a schematic cross-sectional view along line A-A' in (a), (c) is a schematic cross-sectional view along line B-B' in (a), (d) ) is a schematic cross-sectional view along line CC' in (a). Along the first opening 230, part of the second semiconductor layer 220 between the adjacent first openings 230 is removed. Between the adjacent first semiconductor layers 210 An initial gap 211 is formed between them.
具体地说,在本实施例中,沿第一开口230,去除相邻的第一开口230之间的部分第二半导体层220的方法包括:
Specifically, in this embodiment, the method of removing part of the second semiconductor layer 220 between adjacent first openings 230 along the first openings 230 includes:
请参阅图4,其中(a)为俯视图,(b)为沿(a)中A-A’线的截面示意图,(c)为沿(a)中B-B’线的截面示意图,在形成第一开口230后,在第一开口230内填充绝缘层231,绝缘层231覆盖第一开口230的内壁。绝缘层231可为氧化硅层。Please refer to Figure 4, in which (a) is a top view, (b) is a schematic cross-sectional view along line A-A' in (a), and (c) is a schematic cross-sectional view along line B-B' in (a). After the first opening 230 , the insulating layer 231 is filled in the first opening 230 , and the insulating layer 231 covers the inner wall of the first opening 230 . The insulating layer 231 may be a silicon oxide layer.
请参阅图5,其中(a)为俯视图,(b)为沿(a)中A-A’线的截面示意图,(c)为沿(a)中B-B’线的截面示意图,去除部分绝缘层231,剩余的绝缘层231作为保护层234覆盖第一开口230在第三方向D3上相对设置的两侧壁,第一开口230的剩余区域作为第二开口232。其中,可采用干法刻蚀工艺去除部分绝缘层231。在该步骤中,第一开口230在第二方向D2上相对设置的两侧壁被部分暴露,在第三方向D3上相对设置的两侧壁被保护层234覆盖,第一开口230暴露的侧边及保护层234的侧面围成第二开口232。可以理解的是,受到保护层234厚度的影响,第一开口230在第二方向D2上相对设置的两侧壁的边缘也被保护层234覆盖。Please refer to Figure 5, in which (a) is a top view, (b) is a schematic cross-sectional view along line A-A' in (a), (c) is a schematic cross-sectional view along line B-B' in (a), with parts removed. The insulating layer 231 and the remaining insulating layer 231 serve as the protective layer 234 to cover the opposite side walls of the first opening 230 in the third direction D3, and the remaining area of the first opening 230 serves as the second opening 232. Among them, a dry etching process can be used to remove part of the insulating layer 231 . In this step, the two side walls of the first opening 230 that are oppositely arranged in the second direction D2 are partially exposed, and the two side walls that are oppositely arranged in the third direction D3 are covered by the protective layer 234 , and the exposed side walls of the first opening 230 are partially exposed. The edges and the side surfaces of the protective layer 234 define the second opening 232 . It can be understood that due to the influence of the thickness of the protective layer 234 , the edges of the two side walls of the first opening 230 oppositely arranged in the second direction D2 are also covered by the protective layer 234 .
请参阅图6,沿第二开口232,去除第二开口232侧壁暴露的第二半导体层220,在相邻的第一半导体层210之间形成初始空隙211。在该步骤中,最顶层的第二半导体层220被去除,顶部的第一半导体层210被暴露作为最顶层,与最顶层的第二半导体层220对应的保护层234也被对应去除。Referring to FIG. 6 , along the second opening 232 , the exposed second semiconductor layer 220 on the sidewall of the second opening 232 is removed, and an initial gap 211 is formed between adjacent first semiconductor layers 210 . In this step, the topmost second semiconductor layer 220 is removed, the top first semiconductor layer 210 is exposed as the topmost layer, and the protective layer 234 corresponding to the topmost second semiconductor layer 220 is also removed accordingly.
请参阅图7,其中(a)为俯视图,(b)为沿(a)中A-A’线的截面示意图,(c)为沿(a)中B-B’线的截面示意图,(d)为沿(a)中C-C’线的截面示意图,在初始空隙211内形成第一支撑层400。具体地说,形成第一支撑层400的方法包括:在堆叠结构21中沉积支撑层材料;刻蚀去除堆叠结构21上表面(即最顶层的第一半导体层210表面)及第二开口232内的支撑层材料,初始空隙211内保留的支撑层材料作为第一支撑层400。第一支撑层400可为氮化硅层。Please refer to Figure 7, in which (a) is a top view, (b) is a schematic cross-sectional view along line A-A' in (a), (c) is a schematic cross-sectional view along line B-B' in (a), (d) ) is a schematic cross-sectional view along line CC' in (a), where the first support layer 400 is formed in the initial gap 211. Specifically, the method of forming the first support layer 400 includes: depositing a support layer material in the stack structure 21; etching to remove the upper surface of the stack structure 21 (ie, the surface of the topmost first semiconductor layer 210) and the inside of the second opening 232. The support layer material remaining in the initial gap 211 serves as the first support layer 400 . The first support layer 400 may be a silicon nitride layer.
请参阅图8,去除保护层234,第一半导体层210及第二半导体层220被暴露。在该步骤中,可采用干法刻蚀工艺去除保护层234。Referring to FIG. 8 , the protective layer 234 is removed, and the first semiconductor layer 210 and the second semiconductor layer 220 are exposed. In this step, a dry etching process may be used to remove the protective layer 234 .
请参阅图1及图9,在图9中,(a)为俯视图,(b)为沿(a)中A-A’线的截面示意图,(c)为沿(a)中B-B’线的截面示意图,(d)为沿(a)中C-C’线的截面示意图,步骤S11,去除第二半导体层220,形成第一空隙212。在该步骤中,第二半导体层220被全部去除,暴露出第一半导体层210的表面。具体地说,在本实施例中,沿第一开口230,去除电容区A1、字线区A2及位线区A3的第二半导体层220,形成第一空隙212。在该步骤中,第二半导体层220被全部去除,暴露出第一半导体层210的表面。Please refer to Figure 1 and Figure 9. In Figure 9, (a) is a top view, (b) is a schematic cross-sectional view along line A-A' in (a), and (c) is a schematic cross-sectional view along line B-B' in (a). (d) is a schematic cross-sectional view along line CC' in (a). In step S11, the second semiconductor layer 220 is removed to form the first gap 212. In this step, the second semiconductor layer 220 is completely removed, exposing the surface of the first semiconductor layer 210 . Specifically, in this embodiment, the second semiconductor layer 220 in the capacitor region A1, the word line region A2, and the bit line region A3 is removed along the first opening 230 to form the first gap 212. In this step, the second semiconductor layer 220 is completely removed, exposing the surface of the first semiconductor layer 210 .
在本实施例中,采用外延工艺在第一半导体层210上形成第二半导体层220,而由于第二半导体层220与第一半导体层210之间存在晶格失配,导致第二半导体层220在第一半导体层210上的外延厚度受到限制,则在去除第二半导体层220后,在第一方向D1上相邻的两个第一半导体层210之间的第一间距d1较小,而相邻的两个第一半导体层210之间的第一间距d1过小使得在后续工艺中,半导体结构在第一方向D1上的间距受到限制,例如相邻的两个第一半导体层210之间的第一间距d1可定义后续形成的相邻位线之间的距离,则相邻的两个第一半导体层210之间的第一间距d1过小使得相邻位线之间的距离受到影响,甚至也会影响后续形成的字线结构的间距,增大了工艺制程难度,不利于集成密度的增加,甚至可能会使得同一层的字线结构无法连接,影响半导体器件的可靠性。In this embodiment, an epitaxial process is used to form the second semiconductor layer 220 on the first semiconductor layer 210. However, due to the lattice mismatch between the second semiconductor layer 220 and the first semiconductor layer 210, the second semiconductor layer 220 The epitaxial thickness on the first semiconductor layer 210 is limited, so after the second semiconductor layer 220 is removed, the first distance d1 between the two adjacent first semiconductor layers 210 in the first direction D1 is smaller, and The first distance d1 between two adjacent first semiconductor layers 210 is too small, so that in subsequent processes, the distance between the semiconductor structures in the first direction D1 is limited, for example, between the two adjacent first semiconductor layers 210 The first spacing d1 between the two adjacent bit lines can define the distance between the adjacent bit lines formed subsequently. If the first spacing d1 between the two adjacent first semiconductor layers 210 is too small, the distance between the adjacent bit lines will be affected. It may even affect the spacing of the subsequently formed word line structures, which increases the difficulty of the process and is not conducive to the increase in integration density. It may even make it impossible to connect word line structures on the same layer, affecting the reliability of semiconductor devices.
因此,本公开实施例提供的制备方法通过减薄第一半导体层210的方式增大第一半导体层210之间的间距。具体地说,请参阅图1及图10,在图10中,(a)为俯视图,(b)为沿(a)中A-A’线的截面示意图,(c)为沿(a)中B-B’线的截面示意图,(d)为沿(a)中C-C’线的截面示意图,步骤S12,沿第一空隙212,减薄第一半导体层210,以增大相邻的第一半导体层210在第一方向D1上的第一间距d1。在该步骤中,采用侧向刻蚀工艺,通过第一空隙212刻蚀第一半导体层210,即自第一半导体层210的上下表面减薄第一半导体层210,在第一方向D1相邻的第一半导体层210之间的第一间距d1增大。Therefore, the preparation method provided by the embodiment of the present disclosure increases the spacing between the first semiconductor layers 210 by thinning the first semiconductor layers 210 . Specifically, please refer to Figures 1 and 10. In Figure 10, (a) is a top view, (b) is a schematic cross-sectional view along line A-A' in (a), and (c) is a schematic cross-sectional view along line A-A' in (a). A schematic cross-sectional view along line BB', (d) is a schematic cross-sectional view along line CC' in (a), step S12, thinning the first semiconductor layer 210 along the first gap 212 to increase the size of the adjacent The first spacing d1 of the first semiconductor layer 210 in the first direction D1. In this step, a lateral etching process is used to etch the first semiconductor layer 210 through the first gap 212, that is, the first semiconductor layer 210 is thinned from the upper and lower surfaces of the first semiconductor layer 210, and is adjacent in the first direction D1. The first distance d1 between the first semiconductor layers 210 increases.
请参阅图1及请参阅图14,在图14中,(a)为俯视图,(b)为沿(a)中A-A’线的截面示意图,(c)为沿(a)中B-B’线的截面示意图,(d)为沿(a)中C-C’线的截面示意图,(e)为沿图(a)中D-D’线的截面示意图,步骤S13,去除部分第一半导体层210,形成多个半导体柱240,每一半导体柱240沿第三方向D3延伸且多个半导体柱240在第一方向D1及第二方向D2上阵列排布,第三方向D3为平行于衬底20的顶面的方向,且第二方向D2与第三方向D3相交。在本实施例中,以第三方向D3为笛卡尔坐标系中的X轴方向为例进行说明。由于第一半导体层210被减薄,即在第一方向D1上相邻的半导体柱240之间的第一间距d1增大,例如大于在第二方向D2上相邻的半导体柱240之间的第二间距d2,从而避免相邻位线之间的距离受到影响,降低了工艺制程难度。Please refer to Figure 1 and Figure 14. In Figure 14, (a) is a top view, (b) is a cross-sectional view along line A-A' in (a), and (c) is a cross-sectional view along line B- in (a). A schematic cross-sectional view of line B', (d) is a schematic cross-sectional view along line C-C' in (a), (e) is a schematic cross-sectional view along line D-D' in (a), step S13, remove part A semiconductor layer 210 forms a plurality of semiconductor pillars 240. Each semiconductor pillar 240 extends along the third direction D3 and the plurality of semiconductor pillars 240 are arranged in an array in the first direction D1 and the second direction D2. The third direction D3 is parallel. The second direction D2 intersects the third direction D3. In this embodiment, the third direction D3 is the X-axis direction in the Cartesian coordinate system as an example for explanation. Since the first semiconductor layer 210 is thinned, that is, the first distance d1 between adjacent semiconductor pillars 240 in the first direction D1 increases, for example, is greater than the distance d1 between adjacent semiconductor pillars 240 in the second direction D2. The second spacing d2 prevents the distance between adjacent bit lines from being affected and reduces the difficulty of the process.
作为示例,本公开实施例提供一种去除部分第一半导体层210,形成多个半导体柱240的方法。方法包括如下步骤:As an example, embodiments of the present disclosure provide a method of removing part of the first semiconductor layer 210 to form a plurality of semiconductor pillars 240 . The method includes the following steps:
请参阅图11,在图11中,(a)为俯视图,(b)为沿(a)中A-A’线的截面示意图,(c)为沿(a)中B-B’线的截面示意图,(d)为沿(a)中C-C’线的截面示意图,在第一空隙212内填充第一隔离层213。Please refer to Figure 11. In Figure 11, (a) is a top view, (b) is a schematic cross-sectional view along line A-A' in (a), and (c) is a cross-section along line BB' in (a). Schematic diagram, (d) is a schematic cross-sectional diagram along line CC′ in (a), in which the first isolation layer 213 is filled in the first gap 212 .
在本实施例中,第一隔离层213为氧化物层,其填充在第一半导体层210之间的第一空隙212内,以支撑第一半导体层210。受到半导体工艺的限制,在一些实施例中,第一隔离层213还覆盖堆叠结构21的顶面,则在该步骤中,还可以包括去除堆叠结构21顶面的第一隔离层213的步骤,以暴露出顶面的第一半导体层210,避免在后续工艺形成的顶层的半导体柱240表面覆盖第一隔离层213,进而影响后续工艺形成的栅极结构层与半导体柱240表面的接触。In this embodiment, the first isolation layer 213 is an oxide layer, which is filled in the first gap 212 between the first semiconductor layers 210 to support the first semiconductor layer 210 . Due to limitations of the semiconductor process, in some embodiments, the first isolation layer 213 also covers the top surface of the stacked structure 21. In this step, the step of removing the first isolation layer 213 on the top surface of the stacked structure 21 may also be included. The first semiconductor layer 210 on the top surface is exposed to avoid covering the first isolation layer 213 on the surface of the top semiconductor pillar 240 formed in the subsequent process, thereby affecting the contact between the gate structure layer formed in the subsequent process and the surface of the semiconductor pillar 240 .
请参阅图12,在图12中,(a)为俯视图,(b)为沿(a)中A-A’线的截面示意图,(c)为沿(a)中B-B’线的截面示意图,(d)为沿(a)中C-C’线的截面示意图,在堆叠结构21上形成第一掩膜层300,第一掩膜层300包括多个第一图形窗口301,每一第一图形窗口301沿第三方向D3延伸,且多个第一图形窗口301沿第二方向D2排布。具体地说,在该步骤中,首先涂覆一层掩膜材料层,然后对掩膜材料层进行图案化,形成间隔排布的掩膜条,相邻的掩膜条之间的空格即为第一图形窗口301。在本实施例中,第一图形窗口301暴露出第一开口230,则在后续工艺中,第一开口230内填充的第一隔离层213可被完全去除,避免影响半导体柱240的结构。在本实施例中,第一掩膜层300可为光刻胶层,在其他实施例中,第一掩膜层300也可为硬掩膜层。第一图形窗口301在衬底20上的投影覆盖第一开口230在衬底20上的投影,即第一图形窗口301暴露出第一开口230中填充的第一隔离层213。Please refer to Figure 12. In Figure 12, (a) is a top view, (b) is a schematic cross-sectional view along line A-A' in (a), and (c) is a cross-section along line BB' in (a). Schematic diagram, (d) is a cross-sectional schematic diagram along line CC' in (a), a first mask layer 300 is formed on the stacked structure 21, the first mask layer 300 includes a plurality of first pattern windows 301, each The first graphics window 301 extends along the third direction D3, and the plurality of first graphics windows 301 are arranged along the second direction D2. Specifically, in this step, a layer of mask material is first coated, and then the mask material layer is patterned to form mask strips arranged at intervals, and the spaces between adjacent mask strips are First graphics window 301. In this embodiment, the first pattern window 301 exposes the first opening 230, and in subsequent processes, the first isolation layer 213 filled in the first opening 230 can be completely removed to avoid affecting the structure of the semiconductor pillar 240. In this embodiment, the first mask layer 300 may be a photoresist layer. In other embodiments, the first mask layer 300 may also be a hard mask layer. The projection of the first pattern window 301 on the substrate 20 covers the projection of the first opening 230 on the substrate 20 , that is, the first pattern window 301 exposes the first isolation layer 213 filled in the first opening 230 .
请参阅图13,在图13中,(a)为俯视图,(b)为沿(a)中A-A’线的截面示意图,(c)为沿(a)中B-B’线的截面示意图,(d)为沿(a)中C-C’线的截面示意图,(e)为沿图(a)中D-D’线的截面示意图,沿第一图形窗口301,去除部分第一半导体层210,形成半导体柱240。在该步骤中,去除部分第一隔离层213,保留在第一方向D1上排布的半导体柱240之间的第一隔离层213,以支撑半导体柱240。在该步骤中,第一图形窗口301对应区域的第一支撑层400也被去除。Please refer to Figure 13. In Figure 13, (a) is a top view, (b) is a schematic cross-sectional view along line A-A' in (a), and (c) is a cross-section along line BB' in (a). Schematic diagram, (d) is a schematic cross-sectional view along line C-C' in (a), (e) is a schematic cross-sectional view along line D-D' in (a), along the first graphics window 301, remove part of the first Semiconductor layer 210 forms semiconductor pillars 240. In this step, part of the first isolation layer 213 is removed, leaving the first isolation layer 213 between the semiconductor pillars 240 arranged in the first direction D1 to support the semiconductor pillars 240 . In this step, the first support layer 400 in the area corresponding to the first graphics window 301 is also removed.
在该步骤之后,还包括:对半导体柱240执行离子注入,形成掺杂的半导体柱240,以为后续形成的晶体管、电容结构做准备。在本公开其他实施例中,也可在形成第一半导体层210时进行离子注入。After this step, it also includes: performing ion implantation on the semiconductor pillar 240 to form a doped semiconductor pillar 240 in preparation for subsequent formation of transistor and capacitor structures. In other embodiments of the present disclosure, ion implantation may also be performed when forming the first semiconductor layer 210 .
请参阅图14,去除在第一方向D1上排布的半导体柱240之间的第一隔离层213,半导体柱240的表面被暴露。具体地说,可采用刻蚀工艺去除第一隔离层213。在该步骤中,第一掩膜层300也被去除。Referring to FIG. 14 , the first isolation layer 213 between the semiconductor pillars 240 arranged in the first direction D1 is removed, and the surfaces of the semiconductor pillars 240 are exposed. Specifically, an etching process may be used to remove the first isolation layer 213 . In this step, the first mask layer 300 is also removed.
请参阅图15,在图15中,(a)为俯视图,(b)为沿(a)中A-A’线的截面示意图,(c)为沿(a)中B-B’线的截面示意图,(d)为沿(a)中C-C’线的截面示意图,(e)为沿图(a)中D-D’线的截面示意图,步骤S14,在半导体柱240表面形成栅极结构层260。字线区A2对应的栅极结构层260作为栅极,栅极对应的半导体柱240作为沟道区域。栅极结构层260包括栅介质层261及栅极材料层262。Please refer to Figure 15. In Figure 15, (a) is a top view, (b) is a schematic cross-sectional view along line A-A' in (a), and (c) is a cross-section along line BB' in (a). Schematic diagram, (d) is a schematic cross-sectional view along the line CC' in (a), (e) is a schematic cross-sectional view along the line DD' in (a), step S14, forming a gate electrode on the surface of the semiconductor pillar 240 Structural layer 260. The gate structure layer 260 corresponding to the word line region A2 serves as the gate electrode, and the semiconductor pillar 240 corresponding to the gate electrode serves as the channel region. The gate structure layer 260 includes a gate dielectric layer 261 and a gate material layer 262.
作为示例,在半导体柱240表面形成栅极结构层260的步骤包括:As an example, the step of forming the gate structure layer 260 on the surface of the semiconductor pillar 240 includes:
在半导体柱240表面形成栅介质层261,即栅介质层261覆盖半导体柱240表面。栅介质层261可为氧化硅或者高K介质层。其中,可采用化学气相沉积、原子层沉积等工艺形成栅介质层261。A gate dielectric layer 261 is formed on the surface of the semiconductor pillar 240 , that is, the gate dielectric layer 261 covers the surface of the semiconductor pillar 240 . The gate dielectric layer 261 may be silicon oxide or a high-K dielectric layer. Among them, the gate dielectric layer 261 can be formed using processes such as chemical vapor deposition and atomic layer deposition.
在栅介质层261表面形成栅极材料层262,即栅极材料层262覆盖栅介质层261的表面。在第一方向D1上,位于同一层的栅极材料层262连接。具体地说,每一半导体柱240沿第三方向D3延伸,在第 二方向D2上依次排列的半导体柱240为同一层,在第一方向D1上依次排列的半导体柱240为不同层,在本实施例中,覆盖在同一层的半导体柱240表面的栅极材料层262连接,形成整体结构。栅极材料层262可为钨层。A gate material layer 262 is formed on the surface of the gate dielectric layer 261 , that is, the gate material layer 262 covers the surface of the gate dielectric layer 261 . In the first direction D1, the gate material layers 262 located on the same layer are connected. Specifically, each semiconductor pillar 240 extends along the third direction D3. The semiconductor pillars 240 arranged in sequence in the second direction D2 are in the same layer, and the semiconductor pillars 240 arranged in sequence in the first direction D1 are in different layers. In this article, In the embodiment, the gate material layer 262 covering the surface of the semiconductor pillar 240 of the same layer is connected to form an overall structure. Gate material layer 262 may be a tungsten layer.
在第一方向D1上相邻的栅极结构层260的间隙内填充第二隔离层263,第二隔离层263充满堆叠结构21,以起到支撑作用。在本实施例中,第二隔离层263还覆盖堆叠结构21的顶面。第二隔离层263包括但不限于二氧化硅层。The second isolation layer 263 is filled in the gap between adjacent gate structure layers 260 in the first direction D1, and the second isolation layer 263 is filled with the stacked structure 21 to play a supporting role. In this embodiment, the second isolation layer 263 also covers the top surface of the stacked structure 21 . The second isolation layer 263 includes, but is not limited to, a silicon dioxide layer.
制备方法还包括形成位线的步骤。具体地说,请参阅图18,在图18中,(a)为俯视图,(b)为沿(a)中A-A’线的截面示意图,(c)为沿(a)中B-B’线的截面示意图,(d)为沿(a)中C-C’线的截面示意图,(e)为沿图(a)中D-D’线的截面示意图,在位线区A3,去除第一支撑层400、栅极结构层260及半导体柱240,并形成多个位线270,每一位线270沿第一方向D1及第三方向D3延伸,且多个位线270沿第二方向D2间隔排布。在该步骤形成的半导体结构中,位于位线270两侧的半导体柱240与位线270连接,两者共用同一位线270。The preparation method also includes the step of forming bit lines. Specifically, please refer to Figure 18. In Figure 18, (a) is a top view, (b) is a schematic cross-sectional view along line A-A' in (a), and (c) is a schematic cross-sectional view along line B-B in (a). ' line schematic cross-sectional view, (d) is a schematic cross-sectional view along line C-C' in (a), (e) is a schematic cross-sectional view along line D-D' in (a), in bit line area A3, remove The first support layer 400, the gate structure layer 260 and the semiconductor pillar 240 form a plurality of bit lines 270. Each bit line 270 extends along the first direction D1 and the third direction D3, and the plurality of bit lines 270 extend along the second direction D1. Arranged at intervals in direction D2. In the semiconductor structure formed in this step, the semiconductor pillars 240 located on both sides of the bit line 270 are connected to the bit line 270, and both share the same bit line 270.
作为示例,本公开实施例还提供形成多个位线270的方法,方法包括如下步骤:As an example, embodiments of the present disclosure also provide a method of forming multiple bit lines 270. The method includes the following steps:
请参阅图16,在图16中,(a)为俯视图,(b)为沿(a)中A-A’线的截面示意图,(c)为沿(a)中B-B’线的截面示意图,(d)为沿(a)中C-C’线的截面示意图,(e)为沿图(a)中D-D’线的截面示意图,在位线区A3,去除第一支撑层400、栅极结构层260及半导体柱240,形成位线沟槽271,位线沟槽271贯穿堆叠结构21;沿位线沟槽271侧壁继续去除部分栅极结构层260,形成凹槽272。在该步骤中,沿位线沟槽271侧壁继续去除部分栅极结构层260时,第二隔离层263也被部分去除。在该步骤形成的半导体结构中,半导体柱240被分为设置在位线沟槽271相对两侧的两部分,凹槽272朝向远离位线沟槽271中心的方向凹陷。在该步骤中,可采用干法刻蚀工艺形成位线沟槽271,采用侧向刻蚀工艺形成凹槽272。Please refer to Figure 16. In Figure 16, (a) is a top view, (b) is a schematic cross-sectional view along line A-A' in (a), and (c) is a cross-section along line BB' in (a). Schematic diagram, (d) is a schematic cross-sectional view along the line C-C' in (a), (e) is a schematic cross-sectional view along the line D-D' in (a), in the bit line area A3, the first support layer is removed 400. The gate structure layer 260 and the semiconductor pillar 240 form a bit line trench 271. The bit line trench 271 penetrates the stack structure 21; continue to remove part of the gate structure layer 260 along the sidewall of the bit line trench 271 to form a groove 272. . In this step, when part of the gate structure layer 260 is continued to be removed along the sidewall of the bit line trench 271, the second isolation layer 263 is also partially removed. In the semiconductor structure formed in this step, the semiconductor pillar 240 is divided into two parts disposed on opposite sides of the bit line trench 271 , and the groove 272 is recessed in a direction away from the center of the bit line trench 271 . In this step, a dry etching process may be used to form the bit line trench 271, and a lateral etching process may be used to form the groove 272.
作为示例,本公开实施例提供一种形成位线沟槽271的方法,方法包括:在堆叠结构21表面形成第二掩膜层,第二掩膜层具有第二图形窗口,第二图形窗口沿第二方向D2延伸;沿第二图形窗口,去除第一支撑层400、栅极结构层260及半导体柱240,形成位线沟槽271。在该步骤中,第二掩膜层为光刻胶层,采用光刻及刻蚀工艺形成位线沟槽271。在其他实施例中,第二掩膜层也可为硬掩膜等掩膜结构。As an example, embodiments of the present disclosure provide a method of forming a bit line trench 271. The method includes: forming a second mask layer on the surface of the stacked structure 21, the second mask layer having a second pattern window, and the second pattern window is formed along the surface of the stack structure 21. The second direction D2 extends; along the second pattern window, the first support layer 400, the gate structure layer 260 and the semiconductor pillar 240 are removed to form a bit line trench 271. In this step, the second mask layer is a photoresist layer, and the bit line trench 271 is formed using photolithography and etching processes. In other embodiments, the second mask layer may also be a mask structure such as a hard mask.
请参阅图17,在图17中,(a)为俯视图,(b)为沿(a)中A-A’线的截面示意图,(c)为沿(a)中B-B’线的截面示意图,(d)为沿(a)中C-C’线的截面示意图,(e)为沿图(a)中D-D’线的截面示意图,形成第二支撑层250,第二支撑层250填充凹槽272露出的第一半导体层210之间。第二支撑层250不仅用于支撑半导体柱240,还用于隔离位线270与栅极。具体地说,在本实施例中,沉积氮化硅层,氮化硅层填充在凹槽272内,作为第二支撑层250。在该步骤中,形成位线沟槽271时采用的第二掩膜层可作为沉积第二支撑材料时的掩膜层。Please refer to Figure 17. In Figure 17, (a) is a top view, (b) is a schematic cross-sectional view along line A-A' in (a), and (c) is a cross-section along line BB' in (a). Schematic diagram, (d) is a schematic cross-sectional view along line C-C' in (a), (e) is a schematic cross-sectional view along line D-D' in (a), forming the second support layer 250, the second support layer 250 fills between the exposed first semiconductor layer 210 of the groove 272 . The second support layer 250 is not only used to support the semiconductor pillar 240, but also is used to isolate the bit line 270 and the gate electrode. Specifically, in this embodiment, a silicon nitride layer is deposited and filled in the groove 272 as the second support layer 250 . In this step, the second mask layer used when forming the bit line trench 271 can be used as a mask layer when depositing the second support material.
请参阅图18,在位线沟槽内形成位线材料层;对位线材料层进行图案化,形成沿第二方向D2间隔排列的位线270,且每一位线270与沿第一方向D1排列的多个半导体柱240连接;在位线270之间形成第三隔离层273,第三隔离层273用于隔离在第二方向D2上相邻的位线270。在本实施例中,第三隔离层273包括但不限于二氧化硅。Referring to FIG. 18, a bit line material layer is formed in the bit line trench; the bit line material layer is patterned to form bit lines 270 spaced apart along the second direction D2, and each bit line 270 is in contact with the bit line 270 along the first direction. The plurality of semiconductor pillars 240 arranged in D1 are connected; a third isolation layer 273 is formed between the bit lines 270, and the third isolation layer 273 is used to isolate adjacent bit lines 270 in the second direction D2. In this embodiment, the third isolation layer 273 includes but is not limited to silicon dioxide.
请参阅图19,在图19中,(a)为俯视图,(b)为沿(a)中A-A’线的截面示意图,(c)为沿(a)中B-B’线的截面示意图,(d)为沿(a)中C-C’线的截面示意图,(e)为沿图(a)中D-D’线的截面示意图,在本实施例中,在形成沿第二方向D2间隔排列的位线270的步骤之后,制备方法还包括:在电容区A1与字线区A2的交界处形成第三支撑层280,第三支撑层280支撑半导体柱240。第三支撑层280不仅用于支撑半导体柱240,还用于隔离字线区A2与电容区A1,避免两者电连接,从而影响半导体器件的可靠性。位于第二支撑层250与第三支撑层280之间的栅极结构层260作为晶体管的栅极结构,其对应的半导体柱240为晶体管的沟道区域。
Please refer to Figure 19. In Figure 19, (a) is a top view, (b) is a schematic cross-sectional view along line A-A' in (a), and (c) is a cross-section along line BB' in (a). Schematic diagram, (d) is a schematic cross-sectional view along line C-C' in (a), (e) is a schematic cross-sectional view along line D-D' in (a), in this embodiment, when forming along the second After the step of arranging the bit lines 270 at intervals in the direction D2, the preparation method further includes: forming a third support layer 280 at the interface between the capacitor region A1 and the word line region A2, and the third support layer 280 supports the semiconductor pillar 240. The third support layer 280 is not only used to support the semiconductor pillar 240, but also is used to isolate the word line region A2 and the capacitor region A1 to prevent them from being electrically connected, thus affecting the reliability of the semiconductor device. The gate structure layer 260 located between the second support layer 250 and the third support layer 280 serves as the gate structure of the transistor, and its corresponding semiconductor pillar 240 serves as the channel region of the transistor.
作为示例,本公开实施例提供了一种形成第三支撑层280的方法,方法包括:在堆叠结构21表面形成第三掩膜层281,第三掩膜层281具有第三图形窗口282,第三图形窗口282沿第二方向D2延伸,且对应电容区A1与字线区A2的交界处;沿第三图形窗口282,去除栅极结构层260;填充支撑材料,形成第三支撑层280。在本实施例中,第三掩膜层281可为光刻胶层,第三支撑层280可为氮化硅层。As an example, embodiments of the present disclosure provide a method of forming the third support layer 280. The method includes: forming a third mask layer 281 on the surface of the stacked structure 21, the third mask layer 281 having a third pattern window 282, The three pattern windows 282 extend along the second direction D2 and correspond to the junction of the capacitor region A1 and the word line region A2; along the third pattern window 282, the gate structure layer 260 is removed; the support material is filled to form the third support layer 280. In this embodiment, the third mask layer 281 may be a photoresist layer, and the third support layer 280 may be a silicon nitride layer.
请参阅图20,在图20中,(a)为俯视图,(b)为沿(a)中A-A’线的截面示意图,(c)为沿(a)中C-C’线的截面示意图,(d)为沿(a)中D-D’线的截面示意图,(e)为沿图(a)中E-E’线的截面示意图,步骤S15,在电容区A1,去除半导体柱240表面的栅极结构层260,并形成电容结构层290,电容结构层290覆盖半导体柱240表面。在本实施例中,在两个电容区A1均形成电容结构层290,电容结构层290包括下电极291、介质层292及上电极293,下电极291可为氮化钛,介质层292可为高K介质层,上电极293可为氮化钛。Please refer to Figure 20. In Figure 20, (a) is a top view, (b) is a schematic cross-sectional view along line A-A' in (a), and (c) is a cross-section along line C-C' in (a). Schematic diagram, (d) is a schematic cross-sectional view along the line D-D' in (a), (e) is a schematic cross-sectional view along the line EE' in (a), step S15, in the capacitor area A1, remove the semiconductor pillar The gate structure layer 260 on the surface of the semiconductor pillar 240 is formed, and the capacitance structure layer 290 is formed. The capacitance structure layer 290 covers the surface of the semiconductor pillar 240. In this embodiment, a capacitor structure layer 290 is formed in both capacitor regions A1. The capacitor structure layer 290 includes a lower electrode 291, a dielectric layer 292 and an upper electrode 293. The lower electrode 291 can be titanium nitride, and the dielectric layer 292 can be The high-K dielectric layer and the upper electrode 293 may be titanium nitride.
作为示例,本公开实施例提供一种形成电容结构层290的方法,方法包括:在电容区A1,去除半导体柱240表面的栅极结构层260,暴露出半导体柱240表面。形成下电极291,下电极291覆盖半导体柱240表面;形成介质层292,介质层292覆盖下电极291表面;形成上电极293,上电极293覆盖介质层292表面。As an example, embodiments of the present disclosure provide a method of forming the capacitor structure layer 290 . The method includes: removing the gate structure layer 260 on the surface of the semiconductor pillar 240 in the capacitor area A1 to expose the surface of the semiconductor pillar 240 . A lower electrode 291 is formed, and the lower electrode 291 covers the surface of the semiconductor pillar 240; a dielectric layer 292 is formed, and the dielectric layer 292 covers the surface of the lower electrode 291; and an upper electrode 293 is formed, and the upper electrode 293 covers the surface of the dielectric layer 292.
在本实施例中,在形成上电极293后还包括如下步骤:形成多晶硅层294,多晶硅层294填充上电极293之间的空隙。In this embodiment, after forming the upper electrodes 293, the following steps are also included: forming a polysilicon layer 294, and the polysilicon layer 294 fills the gaps between the upper electrodes 293.
本公开实施例提供的半导体器件的制备方法通过减薄第一半导体层210增大在第一方向D1上相邻的第一半导体层210之间的间距,进而降低了工艺制程难度,有利于集成密度的增加,提高半导体器件的可靠性。同时,本公开实施例提供的制备方法为一种新的制备半导体器件的方法,其在形成栅极结构及位线270之后形成电容结构,而并非是在形成电容结构之后再形成栅极结构及位线270。The method for manufacturing a semiconductor device provided by embodiments of the present disclosure increases the spacing between adjacent first semiconductor layers 210 in the first direction D1 by thinning the first semiconductor layer 210, thereby reducing the difficulty of the process and facilitating integration. The increase in density improves the reliability of semiconductor devices. At the same time, the preparation method provided by the embodiment of the present disclosure is a new method of preparing a semiconductor device, which forms the capacitor structure after forming the gate structure and the bit line 270, instead of forming the gate structure and the capacitor structure after forming the capacitor structure. Bit line 270.
另外,在本公开一些实施例中,减薄第一半导体层的步骤在形成半导体柱的步骤之前执行,能够较好地控制处于同一层的半导体柱(在第二方向D2上相邻)之间的间距(例如第二间距d2),以使得同一层的栅极结构层更容易粘合。可以理解的是,在本公开另一些实施例中,也可在形成半导体柱之后再执行减薄半导体柱的步骤。In addition, in some embodiments of the present disclosure, the step of thinning the first semiconductor layer is performed before the step of forming the semiconductor pillars, which can better control the distance between semiconductor pillars on the same layer (adjacent in the second direction D2). spacing (such as the second spacing d2), so that the gate structure layers of the same layer can be bonded more easily. It can be understood that in other embodiments of the present disclosure, the step of thinning the semiconductor pillars may also be performed after the semiconductor pillars are formed.
本公开实施例还提供一种采用上述制备方法制备的半导体器件,请参阅图1~图20,半导体器件包括衬底20、位于衬底20上的多个半导体柱240。多个半导体柱240在第一方向D1及第二方向D2上阵列排布且沿第三方向D3延伸。第一方向D1为垂直于衬底20的顶面的方向,第二方向D2为平行于衬底20的顶面的方向,第三方向D3为平行于衬底20的顶面的方向,且第二方向D2与第三方向D3相交。在本实施例中,以第一方向D1为笛卡尔坐标系中的Z轴方向,第二方向D2为笛卡尔坐标系中的Y轴方向,第三方向D3为笛卡尔坐标系中的X轴方向为例进行说明。An embodiment of the present disclosure also provides a semiconductor device prepared using the above preparation method. Please refer to FIGS. 1 to 20 . The semiconductor device includes a substrate 20 and a plurality of semiconductor pillars 240 located on the substrate 20 . The plurality of semiconductor pillars 240 are arranged in an array in the first direction D1 and the second direction D2 and extend along the third direction D3. The first direction D1 is a direction perpendicular to the top surface of the substrate 20 , the second direction D2 is a direction parallel to the top surface of the substrate 20 , the third direction D3 is a direction parallel to the top surface of the substrate 20 , and the third direction D1 is a direction perpendicular to the top surface of the substrate 20 . The second direction D2 intersects the third direction D3. In this embodiment, the first direction D1 is the Z-axis direction in the Cartesian coordinate system, the second direction D2 is the Y-axis direction in the Cartesian coordinate system, and the third direction D3 is the X-axis direction in the Cartesian coordinate system. Take the direction as an example to illustrate.
请参阅图14,在第一方向D1上相邻的半导体柱240之间的第一间距d1大于在第二方向D2上相邻的半导体柱240之间的第二间距d2,能够降低制备半导体器件的工艺难度。Referring to FIG. 14 , the first spacing d1 between adjacent semiconductor pillars 240 in the first direction D1 is greater than the second spacing d2 between adjacent semiconductor pillars 240 in the second direction D2, which can reduce the cost of manufacturing a semiconductor device. process difficulty.
在一些实施例中,半导体柱240包括电容区A1和字线区A2,半导体器件还包括位于字线区A2的半导体柱240表面的栅极结构层260、位于电容区A1的半导体柱240表面的电容结构层290,栅极结构层260与电容结构层290通过同一半导体柱240对准,有利于提高半导体器件的可靠性。In some embodiments, the semiconductor pillar 240 includes a capacitor area A1 and a word line area A2. The semiconductor device further includes a gate structure layer 260 located on the surface of the semiconductor pillar 240 in the word line area A2, and a gate structure layer 260 located on the surface of the semiconductor pillar 240 in the capacitor area A1. The capacitance structure layer 290, the gate structure layer 260 and the capacitance structure layer 290 are aligned through the same semiconductor pillar 240, which is beneficial to improving the reliability of the semiconductor device.
以上仅是本发明的优选实施方式,应当指出,对于本技术领域的普通技术人员,在不脱离本发明原理的前提下,还可以做出若干改进和润饰,这些改进和润饰也应视为本发明的保护范围。
The above are only the preferred embodiments of the present invention. It should be noted that those skilled in the art can also make several improvements and modifications without departing from the principles of the present invention. These improvements and modifications should also be regarded as the present invention. protection scope of the invention.
Claims (15)
- 一种半导体器件的制备方法,包括:A method for preparing a semiconductor device, including:形成衬底(20)以及位于所述衬底(20)上的堆叠结构(21),所述堆叠结构(21)包括沿第一方向(D1)交替堆叠的第一半导体层(210)和第二半导体层(220),所述堆叠结构(21)包括电容区(A1)、字线区(A2)及位线区(A3),所述第一方向(D1)为垂直于所述衬底(20)的顶面的方向;A substrate (20) and a stacked structure (21) located on the substrate (20) are formed. The stacked structure (21) includes first semiconductor layers (210) and first semiconductor layers (210) alternately stacked along a first direction (D1). Two semiconductor layers (220), the stacked structure (21) includes a capacitor region (A1), a word line region (A2) and a bit line region (A3), the first direction (D1) is perpendicular to the substrate The direction of the top surface of (20);去除所述第二半导体层(220),以形成第一空隙(212);removing the second semiconductor layer (220) to form a first void (212);沿所述第一空隙(212)减薄所述第一半导体层(210);Thinning the first semiconductor layer (210) along the first gap (212);去除部分所述第一半导体层(210),形成多个半导体柱(240),每一所述半导体柱(240)沿第三方向(D3)延伸且多个所述半导体柱(240)在所述第一方向(D1)及第二方向(D2)上阵列排布,所述第二方向(D2)为平行于所述衬底(20)的顶面的方向,所述第三方向(D3)为平行于所述衬底(20)的顶面的方向,且所述第二方向(D2)与所述第三方向(D3)相交;Part of the first semiconductor layer (210) is removed to form a plurality of semiconductor pillars (240). Each of the semiconductor pillars (240) extends along the third direction (D3) and the plurality of semiconductor pillars (240) are located therein. The arrays are arranged in the first direction (D1) and the second direction (D2), the second direction (D2) is a direction parallel to the top surface of the substrate (20), and the third direction (D3) ) is a direction parallel to the top surface of the substrate (20), and the second direction (D2) intersects the third direction (D3);在所述半导体柱(240)表面形成栅极结构层(260);Form a gate structure layer (260) on the surface of the semiconductor pillar (240);在所述电容区(A1),去除所述半导体柱(240)表面的栅极结构层(260),并形成电容结构层(290),所述电容结构层(290)覆盖所述半导体柱(240)表面。In the capacitance area (A1), the gate structure layer (260) on the surface of the semiconductor pillar (240) is removed, and a capacitance structure layer (290) is formed. The capacitance structure layer (290) covers the semiconductor pillar (240). 240) surface.
- 根据权利要求1所述的半导体器件的制备方法,其中,形成位于所述衬底(20)上的堆叠结构(21)的方法包括:The method of manufacturing a semiconductor device according to claim 1, wherein the method of forming the stacked structure (21) located on the substrate (20) includes:所述衬底(20)上形成沿所述第一方向(D1)交替堆叠的所述第一半导体层(210)和所述第二半导体层(220);The first semiconductor layer (210) and the second semiconductor layer (220) alternately stacked along the first direction (D1) are formed on the substrate (20);在所述位线区(A3),形成多个沿所述第二方向(D2)排布的第一开口(230),所述第一开口(230)沿所述第一方向(D1)贯穿所述第一半导体层(210)及所述第二半导体层(220);In the bit line area (A3), a plurality of first openings (230) arranged along the second direction (D2) are formed, and the first openings (230) penetrate along the first direction (D1). the first semiconductor layer (210) and the second semiconductor layer (220);沿所述第一开口(230)去除相邻的所述第一开口(230)之间的部分所述第二半导体层(220),在相邻的所述第一半导体层(210)之间形成初始空隙(211);Remove a portion of the second semiconductor layer (220) between adjacent first openings (230) along the first opening (230), between the adjacent first semiconductor layers (210) Form initial void (211);在所述初始空隙(211)内形成第一支撑层(400)。A first support layer (400) is formed within the initial gap (211).
- 根据权利要求2所述的半导体器件的制备方法,其中,The method of manufacturing a semiconductor device according to claim 2, wherein:沿所述第一开口(230)去除相邻的所述第一开口(230)之间的部分所述第二半导体层(220)的方法包括:The method of removing part of the second semiconductor layer (220) between adjacent first openings (230) along the first opening (230) includes:在所述第一开口(230)内填充绝缘层(231);Fill the first opening (230) with an insulating layer (231);去除部分所述绝缘层(231),剩余的绝缘层(231)作为保护层(234)覆盖所述第一开口(230)在所述第三方向(D3)上相对设置的两侧壁,所述第一开口(230)的剩余区域作为第二开口(232);Part of the insulating layer (231) is removed, and the remaining insulating layer (231) serves as a protective layer (234) to cover the opposite side walls of the first opening (230) in the third direction (D3), so The remaining area of the first opening (230) is used as the second opening (232);沿所述第二开口(232)去除所述第二开口(232)侧壁暴露的所述第二半导体层(220),在相邻的所述第一半导体层(210)之间形成所述初始空隙(211);The second semiconductor layer (220) exposed on the sidewall of the second opening (232) is removed along the second opening (232), and the second semiconductor layer (220) is formed between the adjacent first semiconductor layers (210). initial void(211);在形成所述第一支撑层(400)的步骤之后,去除所述保护层(234),以露出所述第一半导体层(210)及所述第二半导体层(220)。After forming the first support layer (400), the protective layer (234) is removed to expose the first semiconductor layer (210) and the second semiconductor layer (220).
- 根据权利要求2或3所述的半导体器件的制备方法,其中,去除部分所述第一半导体层(210),形成多个半导体柱(240)的方法包括:The method of manufacturing a semiconductor device according to claim 2 or 3, wherein the method of removing part of the first semiconductor layer (210) and forming a plurality of semiconductor pillars (240) includes:在所述堆叠结构(21)上形成第一掩膜层(300),所述第一掩膜层(300)包括多个第一图形窗口(301),每一所述第一图形窗口(301)沿所述第三方向(D3)延伸,且多个所述第一图形窗口(301)沿所述第二方向(D2)排布;A first mask layer (300) is formed on the stacked structure (21), the first mask layer (300) includes a plurality of first graphic windows (301), each of the first graphic windows (301 ) extends along the third direction (D3), and a plurality of the first graphics windows (301) are arranged along the second direction (D2);沿所述第一图形窗口(301)去除部分所述第一半导体层(210),以形成所述半导体柱(240)。Part of the first semiconductor layer (210) is removed along the first pattern window (301) to form the semiconductor pillar (240).
- 根据权利要求4所述的半导体器件的制备方法,其中,所述第一图形窗口(301)在所述衬底(20)上的投影覆盖所述第一开口(230)在所述衬底(20)上的投影;在减薄所述第一半导体层(210)的步骤之后还包括:在所述第一空隙(212)内填充第一隔离层(213); The method of manufacturing a semiconductor device according to claim 4, wherein the projection of the first pattern window (301) on the substrate (20) covers the first opening (230) on the substrate (20). 20); after the step of thinning the first semiconductor layer (210), it also includes: filling the first isolation layer (213) in the first gap (212);在沿所述第一图形窗口(301)去除部分所述第一半导体层(210),以形成所述半导体柱(240)的步骤中包括:去除部分所述第一隔离层(213),保留在所述第一方向(D1)上排布的半导体柱(240)之间的所述第一隔离层(213);The step of removing part of the first semiconductor layer (210) along the first pattern window (301) to form the semiconductor pillar (240) includes: removing part of the first isolation layer (213), leaving the first isolation layer (213) between the semiconductor pillars (240) arranged in the first direction (D1);对所述半导体柱(240)执行离子注入,形成掺杂的半导体柱(240);Perform ion implantation on the semiconductor pillar (240) to form a doped semiconductor pillar (240);去除在所述第一方向(D1)上排布的所述半导体柱(240)之间的第一隔离层(213)。The first isolation layer (213) between the semiconductor pillars (240) arranged in the first direction (D1) is removed.
- 根据权利要求1~5任意一项所述的半导体器件的制备方法,其中,The method for manufacturing a semiconductor device according to any one of claims 1 to 5, wherein:在所述半导体柱(240)表面形成栅极结构层(260)的方法包括;The method of forming the gate structure layer (260) on the surface of the semiconductor pillar (240) includes;在所述半导体柱(240)表面形成栅介质层(261);Form a gate dielectric layer (261) on the surface of the semiconductor pillar (240);在所述栅介质层(261)表面形成栅极材料层(262),在所述第一方向(D1)上,位于同一层半导体柱(240)表面的所述栅极材料层(262)连接;A gate material layer (262) is formed on the surface of the gate dielectric layer (261). In the first direction (D1), the gate material layer (262) located on the surface of the same layer of semiconductor pillars (240) is connected to ;在所述第一方向(D1)上相邻的所述栅极结构层(260)之间填充第二隔离层(263)。A second isolation layer (263) is filled between the adjacent gate structure layers (260) in the first direction (D1).
- 根据权利要求2~5任意一项所述的半导体器件的制备方法,其中,所述方法包括:The method for manufacturing a semiconductor device according to any one of claims 2 to 5, wherein the method includes:在所述位线区(A3),去除所述第一支撑层(400)、所述栅极结构层(260)及所述半导体柱(240),形成位线沟槽(271),所述位线沟槽(271)贯穿所述堆叠结构(21);In the bit line area (A3), the first support layer (400), the gate structure layer (260) and the semiconductor pillar (240) are removed to form a bit line trench (271). Bit line trenches (271) penetrate the stacked structure (21);沿所述位线沟槽(271)侧壁继续去除部分所述栅极结构层(260),形成凹槽(272);Continue to remove part of the gate structure layer (260) along the sidewall of the bit line trench (271) to form a groove (272);形成第二支撑层(250),所述第二支撑层(250)填充所述凹槽(272)露出的所述第一半导体层(210)之间;Forming a second support layer (250), the second support layer (250) filling between the first semiconductor layer (210) exposed by the groove (272);在所述位线沟槽(271)内形成位线材料层;forming a bit line material layer within the bit line trench (271);对所述位线材料层进行图案化,形成沿所述第二方向(D2)间隔排列的位线(270),且每一所述位线(270)与沿所述第一方向(D1)排列的多个所述半导体柱(240)连接;The bit line material layer is patterned to form bit lines (270) spaced apart along the second direction (D2), and each of the bit lines (270) is consistent with the first direction (D1). A plurality of the arranged semiconductor pillars (240) are connected;在所述位线(270)之间形成第三隔离层(273)。A third isolation layer (273) is formed between the bit lines (270).
- 根据权利要求7所述的半导体器件的制备方法,其中,形成所述位线沟槽(271)的步骤包括:The method of manufacturing a semiconductor device according to claim 7, wherein the step of forming the bit line trench (271) includes:在所述堆叠结构(21)表面形成第二掩膜层,所述第二掩膜层具有第二图形窗口,所述第二图形窗口沿第二方向(D2)延伸;A second mask layer is formed on the surface of the stacked structure (21), the second mask layer has a second graphic window, and the second graphic window extends along the second direction (D2);沿所述第二图形窗口去除所述第一支撑层(400)、所述栅极结构层(260)及所述半导体柱(240),形成所述位线沟槽(271)。The first support layer (400), the gate structure layer (260) and the semiconductor pillar (240) are removed along the second pattern window to form the bit line trench (271).
- 根据权利要求7或8所述的半导体器件的制备方法,其中,在形成沿所述第二方向(D2)间隔排列的位线(270)的步骤之后,还包括:在所述电容区(A1)与所述字线区(A2)的交界处形成第三支撑层(280),所述第三支撑层(280)支撑所述半导体柱(240)。The method for manufacturing a semiconductor device according to claim 7 or 8, wherein after the step of forming the bit lines (270) spaced apart along the second direction (D2), it further includes: in the capacitor region (A1 ) and the word line region (A2) form a third support layer (280), the third support layer (280) supports the semiconductor pillar (240).
- 根据权利要求9所述的半导体器件的制备方法,其中,形成所述第三支撑层(280)的方法包括:The method of manufacturing a semiconductor device according to claim 9, wherein the method of forming the third support layer (280) includes:在所述堆叠结构(21)表面形成第三掩膜层(281),所述第三掩膜层(281)具有第三图形窗口(282),所述第三图形窗口(282)沿第二方向(D2)延伸,且对应所述电容区(A1)与所述字线区(A2)的交界处;A third mask layer (281) is formed on the surface of the stacked structure (21), the third mask layer (281) has a third graphic window (282), and the third graphic window (282) is along the second Extends in direction (D2) and corresponds to the junction of the capacitor area (A1) and the word line area (A2);沿所述第三图形窗口(282)去除所述栅极结构层(260);Remove the gate structure layer (260) along the third graphics window (282);填充支撑材料,形成所述第三支撑层(280)。Fill the support material to form the third support layer (280).
- 根据权利要求1~10任意一项所述的半导体器件的制备方法,其中,在所述电容区(A1),去除所述半导体柱(240)表面的栅极结构层(260),并形成电容结构层(290)的方法包括:The method for manufacturing a semiconductor device according to any one of claims 1 to 10, wherein in the capacitor region (A1), the gate structure layer (260) on the surface of the semiconductor pillar (240) is removed, and a capacitor is formed. Methods at the structural level (290) include:在所述电容区(A1),去除所述半导体柱(240)表面的栅极结构层(260),暴露出所述半导体柱(240)表面;In the capacitor area (A1), remove the gate structure layer (260) on the surface of the semiconductor pillar (240) to expose the surface of the semiconductor pillar (240);形成下电极(291),所述下电极(291)覆盖暴露出的所述半导体柱(240)表面;Forming a lower electrode (291), the lower electrode (291) covering the exposed surface of the semiconductor pillar (240);形成介质层(292),所述介质层(292)覆盖所述下电极(291)表面;Form a dielectric layer (292), which covers the surface of the lower electrode (291);形成上电极(293),所述上电极(293)覆盖所述介质层(292)表面。 An upper electrode (293) is formed, and the upper electrode (293) covers the surface of the dielectric layer (292).
- 根据权利要求11所述的半导体器件的制备方法,其中,形成所述上电极(293)后还包括如下步骤:形成多晶硅层(294),所述多晶硅层(294)填充所述上电极(293)之间的空隙。The method of preparing a semiconductor device according to claim 11, wherein after forming the upper electrode (293), it further includes the following steps: forming a polysilicon layer (294), and the polysilicon layer (294) fills the upper electrode (293) ).
- 根据权利要求1~12任意一项所述的半导体器件的制备方法,其中,所述电容区(A1)、所述字线区(A2)及所述位线(270)区(A3)沿所述第三方向(D3)排布,所述堆叠结构(21)包括两个所述电容区(A1)及两个所述字线区(A2),所述位线(270)区(A3)设置在两个所述字线区(A2)之间,两个所述字线区(A2)设置在两个所述电容区(A1)之间。The method for manufacturing a semiconductor device according to any one of claims 1 to 12, wherein the capacitor region (A1), the word line region (A2) and the bit line (270) region (A3) are formed along the Arranged in the third direction (D3), the stacked structure (21) includes two of the capacitor regions (A1) and two of the word line regions (A2), and the bit line (270) region (A3) The two word line areas (A2) are arranged between the two word line areas (A2), and the two word line areas (A2) are arranged between the two capacitor areas (A1).
- 一种半导体器件,其中,包括:A semiconductor device, including:衬底(20);substrate(20);位于衬底(20)上的多个半导体柱(240),多个所述半导体柱(240)在第一方向(D1)及第二方向(D2)上阵列排布且沿第三方向(D3)延伸,所述第一方向(D1)为垂直于所述衬底(20)的顶面的方向,所述第二方向(D2)为平行于所述衬底(20)的顶面的方向,所述第三方向(D3)为平行于所述衬底(20)的顶面的方向,且所述第二方向(D2)与所述第三方向(D3)相交;在第一方向(D1)上相邻的半导体柱(240)之间的第一间距(d1)大于在第二方向(D2)上相邻的半导体柱(240)之间的第二间距(d2)。A plurality of semiconductor pillars (240) located on the substrate (20), the plurality of semiconductor pillars (240) are arranged in an array in the first direction (D1) and the second direction (D2) and along the third direction (D3) ) extends, the first direction (D1) is a direction perpendicular to the top surface of the substrate (20), and the second direction (D2) is a direction parallel to the top surface of the substrate (20) , the third direction (D3) is a direction parallel to the top surface of the substrate (20), and the second direction (D2) intersects the third direction (D3); in the first direction ( The first spacing (d1) between adjacent semiconductor pillars (240) in D1) is greater than the second spacing (d2) between adjacent semiconductor pillars (240) in the second direction (D2).
- 根据权利要求14所述的半导体器件,其中,所述半导体柱(240)包括电容区(A1)和字线区(A2),所述半导体器件还包括:The semiconductor device according to claim 14, wherein the semiconductor pillar (240) includes a capacitor region (A1) and a word line region (A2), the semiconductor device further comprising:位于所述字线区(A2)的所述半导体柱(240)表面的栅极结构层(260);The gate structure layer (260) located on the surface of the semiconductor pillar (240) in the word line region (A2);位于所述电容区(A1)的所述半导体柱(240)表面的电容结构层(290)。 A capacitor structure layer (290) located on the surface of the semiconductor pillar (240) of the capacitor region (A1).
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