CN112071838A - Memory and forming method thereof - Google Patents

Memory and forming method thereof Download PDF

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Publication number
CN112071838A
CN112071838A CN201910496280.2A CN201910496280A CN112071838A CN 112071838 A CN112071838 A CN 112071838A CN 201910496280 A CN201910496280 A CN 201910496280A CN 112071838 A CN112071838 A CN 112071838A
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substrate
layer
bit line
forming
isolation
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不公告发明人
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Changxin Memory Technologies Inc
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Changxin Memory Technologies Inc
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells

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Abstract

The invention relates to a memory and a forming method thereof, wherein the forming method of the memory comprises the following steps: providing a substrate; forming a drain electrode doped layer, a channel doped layer and a source electrode doped layer which are sequentially stacked from the inside of the substrate to the surface of the substrate in the substrate; forming a bit line which is positioned below the channel doping layer and at least partially positioned in the drain doping layer, and a first isolation structure which penetrates through the bit line, wherein the bit line and the first isolation structure extend along a first direction; forming third isolation structures extending along the first direction and located on two sides of the bit line in the substrate; and forming a word line structure in the channel doping layer and a second isolation structure penetrating through the word line structure in the substrate, wherein the word line structure and the second isolation structure extend along a second direction. The memory formed by the method has improved storage density.

Description

Memory and forming method thereof
Technical Field
The invention relates to the technical field of memories, in particular to a memory and a forming method thereof.
Background
In the development of DRAM technology, it is an important subject to reduce the area of memory cells and to increase the density of memory cells. Based on the existing memory forming process, the area of the memory cell is difficult to further reduce due to the limitation of the process node.
In a DRAM memory, each memory cell includes a storage capacitor and an access transistor, by which writing or reading of data to or from the memory cell is controlled. In the increasingly difficult situation of reducing the area of the memory cell, the structure of the access transistor can be changed to be one of important methods for improving the storage density of the memory.
How to change the structure of the access transistor to improve the storage density of the memory is a problem to be solved.
Disclosure of Invention
The invention provides a memory and a forming method thereof, which can improve the storage density of the memory.
In order to solve the above problems, the present invention provides a method for forming a memory, including: providing a substrate; forming a drain electrode doped layer, a channel doped layer and a source electrode doped layer which are sequentially stacked from the inside of the substrate to the surface of the substrate in the substrate; forming a bit line which is positioned below the channel doping layer and at least partially positioned in the drain doping layer, and a first isolation structure which penetrates through the bit line, wherein the bit line and the first isolation structure extend along a first direction; forming third isolation structures extending along the first direction and located on two sides of the bit line in the substrate; and forming a word line structure in the channel doping layer and a second isolation structure penetrating through the word line structure in the substrate, wherein the word line structure and the second isolation structure extend along a second direction.
Optionally, the method for forming the bit line and the first isolation structure includes: forming a plurality of first trenches extending along a first direction in the substrate, wherein each first trench comprises a bit line trench and a first dividing trench, the bit line trench is located below the channel doping layer and at least partially located in the drain doping layer, the first dividing trench is located above the bit line trench and is communicated with the bit line trench, and the width of the bit line trench is greater than that of the first dividing trench; forming a bit line in the bit line slot; deepening the first dividing groove, forming a first isolation groove which penetrates through the bit line to the position below the drain electrode doped layer, and forming a first isolation structure in the first isolation groove.
Optionally, the forming method of the first trench includes: etching the substrate by adopting an anisotropic etching process to form a plurality of first dividing grooves extending along a first direction; forming a first protective layer on the side wall of the first dividing groove; and etching the substrate along the bottom of the first dividing groove by adopting an isotropic etching process to form the position line groove.
Optionally, the method for forming the word line structure and the second isolation structure includes: forming a plurality of second grooves extending along a second direction in the substrate, wherein each second groove comprises a word line groove located in the channel doping layer and a second dividing groove located above the word line groove and communicated with the word line groove, and the width of the word line groove is larger than that of the second dividing groove; forming a gate dielectric layer at least covering the inner wall of the word line groove part and a word line positioned on the surface of the gate dielectric layer in the word line groove; deepening the bottom of the second dividing groove, forming a second isolation groove penetrating through the word line, and forming a second isolation structure in the second isolation groove.
Optionally, the forming method of the second trench includes: etching the substrate by adopting an anisotropic etching process to form a plurality of second dividing grooves extending along a second direction; forming a second protective layer on the side wall of the second dividing groove; and etching the substrate along the bottom of the second dividing groove by adopting an isotropic etching process to form the word line groove.
Optionally, the method further includes: forming an isolation doping layer below the drain doping layer in the substrate; and part of the bit lines are positioned in the isolation doped layer.
Optionally, the method further includes: and forming a doped region between the bottom of the word line structure and the bit line, wherein the doping concentration of the doped region is greater than that of the drain doped layer, and the doped region and the drain doped layer have the same doping type.
In order to solve the above problem, an embodiment of the present invention further provides a memory, including: the substrate is internally provided with a drain electrode doped layer, a channel doped layer and a source electrode doped layer which are sequentially stacked from the inside of the substrate to the surface of the substrate; the bit line is positioned below the channel doping layer and at least partially positioned in the drain doping layer, and the first isolation structure penetrates through the bit line, and the bit line and the first isolation structure extend along a first direction; the third isolation structures are positioned in the substrate and extend along the first direction and positioned on two sides of the bit line; the word line structure is positioned in the substrate and in the channel doping layer, the second isolation structure penetrates through the word line structure, and the word line structure and the second isolation structure extend along a second direction.
Optionally, the method further includes: the isolation doping layer is positioned below the drain doping layer; and part of the bit lines are positioned in the isolation doped layer.
Optionally, the method further includes: and the doping region is positioned between the bottom of the word line structure and the bit line, the doping concentration of the doping region is greater than that of the drain doping layer, and the doping region and the drain doping layer have the same doping type.
According to the forming method of the memory, the transistor with the ring gate structure is formed in the substrate, the source electrode, the channel region and the drain electrode of the transistor are vertically arranged in the substrate, the word line is arranged around the channel region, and the bit line is located below the drain electrode doped layer, so that the size of the access transistor can be reduced, and the storage density of the memory is improved.
Drawings
Fig. 1 to 18E are schematic structural diagrams illustrating a formation process of a memory according to an embodiment of the invention.
Detailed Description
The following describes in detail a specific embodiment of the memory and the forming method thereof according to the present invention with reference to the accompanying drawings.
Please refer to fig. 1 to 18E, which are schematic structural diagrams illustrating a memory formation process according to an embodiment of the present invention.
Referring to fig. 1, a substrate 100 is provided, and a drain doping layer 103, a channel doping layer 104 and a source doping layer 105 are formed in the substrate 100 and sequentially stacked from the inside of the substrate 100 to the surface of the substrate 100.
The substrate 100 is a semiconductor substrate, and may be a single crystal silicon substrate, a single crystal germanium substrate, a germanium-silicon substrate, or the like. The substrate 100 may also be doped N-type or P-type. In this embodiment, the substrate 100 is a P-type doped monocrystalline silicon substrate.
The drain doping layer 103, the channel doping layer 104, and the source doping layer 105 are sequentially formed by an ion implantation or diffusion process. The drain doped layer 103 is used for forming a drain of the transistor, the channel doped layer 104 is used for forming a channel region of the transistor, and the source doped layer 105 is used for forming a source of the transistor. The remaining portion of the substrate 100 under the drain doping layer 103 serves as a base 101.
In this embodiment, each doped layer is formed by ion implantation. The substrate 101 is doped P-type, an N-type doped drain doping layer 103 is formed by N-type ion implantation, a P-type doped channel doping layer 104 is formed by P-type ion implantation, and an N-type doped source doping region 105 is formed by N-type ion implantation. By adjusting the ion energy of each ion implantation process, a corresponding doped layer is formed at each depth of the substrate 100. Particularly, the source doping layer 105 is formed by low-energy ion implantation, so that the source doping layer 105 is distributed on the surface of the substrate 100, thereby facilitating the subsequent formation of a memory cell connected to the source on the surface of the source doping layer 105.
In this embodiment, before forming the drain doped layer 103, forming an isolation doped layer 102 between the substrate 101 and the drain doped layer 103. The isolation doped layer 102 and the drain doped layer 103 have the same doping type, and the doping concentration of the isolation doped layer 102 is less than that of the drain doped layer 103. The isolation doping layer 102 is used for blocking metal atoms of a bit line formed in the substrate 100 from diffusing into the base 101.
After forming the respective doped layers, a bit line is formed below the channel doped layer 104 and at least partially within the drain doped layer 103, and a first isolation structure extends through the bit line, the bit line and the first isolation structure extending in a first direction.
In one embodiment, first trenches extending along a first direction are formed in the substrate 100, and the first trenches include a bit line trench located below the channel doping layer 104 and at least partially located in the drain doping layer 103, and a first dividing trench located above the bit line trench and communicating with the bit line trench; and forming the bit line in the bit line groove.
Fig. 2A to 10B are schematic structural diagrams illustrating a process of forming a bit line according to this embodiment.
Referring to fig. 2A and fig. 2B, a bit line mask layer having an opening is formed on the surface of the substrate 100, and fig. 2A is a cross-sectional view along a cut line AA' in fig. 2B.
In this embodiment, the bit line mask layer includes a mask layer 201 and a sidewall protection layer 202 covering both sides of the mask layer 201. The first direction is the x-direction.
Referring to fig. 3, the substrate 100 is etched by using the bit line mask layer as a mask and an anisotropic etching process to form a plurality of first dividing grooves 301 extending along a first direction.
The first dividing groove 301 may be formed by etching the substrate 100 using a plasma etching process. Then, a bit line is formed below the first dividing groove 301, so that the bottom surface of the first dividing groove 301 is located in the drain doped layer 103, so that an electrical connection is formed between the subsequently formed bit line and the drain doped layer 103.
Referring to fig. 4, a first passivation layer 401 is formed on the sidewall of the first dividing groove 301.
The forming method of the first protective layer 401 includes: forming a first protective material layer on the inner wall surface of the first dividing groove 301, the mask layer 201 and the side wall protective layer 202; and etching the first protective material layer by adopting an anisotropic etching process along the direction vertical to the surface of the substrate 100, removing the first protective material layer positioned at the bottom of the first dividing groove 301, forming a first protective layer 401 covering the side wall of the first dividing groove 301, and exposing the substrate material at the bottom of the first dividing groove 301. The first protective layer 401 may also cover the sidewalls (not shown) of the sidewall protection layer 202.
Referring to fig. 5, an etching process is performed to etch the substrate 100 along the bottom of the first dividing groove 301 to form the bit line groove 501.
The etching process may be a wet etching process or a dry etching process. In this embodiment, a wet etching process is used to etch the substrate at the bottom of the first dividing groove 301, and the etching solution used in the wet etching process may be a solution with high etching selectivity to silicon, such as HNA, TMAH, NaOH, or the like. The bit line slots 501 may be formed with arc, sigma, vertical or inclined sidewalls, and the topography of the bit line slots 501 in fig. 5 is merely an example and does not represent the actual topography of the bit line slots 501 in an actual process.
In other embodiments, the substrate 100 may be dry etched by using an etching gas having a high etching selectivity to silicon, so as to form the bit line trench 501. The etching gas molecules react with the substrate 100 material to achieve anisotropic etching. The etching gas may be XeF2、CF4、CH2F2And the like. In order to improve the etching efficiency, the etching gas may be also plasmatized to increase the energy of the etching gas, thereby increasing the reaction rate of the reaction with the material of the substrate 100.
The isotropic etching process can simultaneously etch the substrate at the bottom of the first dividing groove 301 in the vertical direction and the horizontal direction, so that the width of the formed bit line groove 501 is greater than the width of the first dividing groove 301. The bit line channel 501 is located in the drain doping layer 103 and the isolation doping layer 102, and a certain distance is reserved between the top of the bit line channel 501 and the channel doping layer 104, so that the problem of leakage caused by connection between a subsequently formed bit line and the channel doping layer 104 is avoided.
Referring to fig. 6, a bit line 601 is formed within the bit line trench 501 (see fig. 5).
The bit line 601 may be made of a metal material, such as tungsten, copper, silver, or the like. Before filling the bit line material, a diffusion-prevention barrier layer, such as a TiN layer or TaN, may also be formed on the inner wall surface of the bit line trench 501 to prevent the metal atoms of the bit line 601 from diffusing outward. In this embodiment, a chemical vapor deposition process may be used to deposit a bit line material in the bit line trench 501 to form the bit line 601. During the deposition process, a portion of the bit line material may also be deposited in the first dividing groove 301, and the bit line material outside the bit line groove 501 may be removed through an etching process.
Referring to fig. 7, the first protection layer 401 is removed (see fig. 6), and etching is continued along the first split trench 301 to deepen the first split trench, so as to form a first isolation trench 701 penetrating through the bit line 601 to a position below the drain doping layer 103.
And sequentially etching the bit line 601 and the doped layer positioned at the bottom of the bit line 601 into the substrate 101 by adopting an anisotropic etching process to form the first isolation groove 701.
The substrate 100 is divided into a plurality of active regions extending in the x direction by the first isolation trenches 701, and the bit line 601 is divided into two sub-bit lines in different active regions.
In order to avoid the leakage problem between the active regions on both sides of the first isolation trench 701, the depth of the first isolation trench 701 is sufficient to isolate the doped layer between the active regions. Since the isolation doping layer 102 is also formed below the drain doping layer 103, the bottom of the first isolation trench 701 needs to be located below the isolation doping layer 102. In other embodiments, if the isolation doping layer 102 is not formed, the bottom of the first isolation trench 701 only needs to be located below the drain doping layer 103.
Referring to fig. 8, a first isolation structure 801 is formed in the first isolation trench 701.
The first isolation structure 801 is made of insulating dielectric materials such as silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, and the like. The first isolation structure 801 may be formed by filling an insulating dielectric material in the first isolation trench 701 by using a chemical vapor deposition process, a plasma enhanced chemical vapor deposition process, or the like.
Preferably, the material of the first isolation structure 801 is different from the material of the mask layer 201, so that the first isolation structure 801 is prevented from being over-etched in the process of removing the mask layer 201. In other specific embodiments, the material of the first isolation structure 801 may be the same as the material of the mask layer 201, and the height of the mask layer 201 is lower, so that even when the mask layer 201 is removed, the first isolation structure 801 is etched at the same time, as long as the etched first isolation structure 801 is not lower than the surface of the substrate 100.
Referring to fig. 9, the mask layer 201 is removed, and the substrate 100 is etched using the sidewall protection layer 202 as a mask, so as to form a third isolation trench 901. The third isolation trench 901 extends in the first direction.
And etching the substrate 100 into the base 101 by using an anisotropic etching process to form the third isolation groove 901. The third isolation trench 901 divides a single active region between adjacent first isolation structures 801 into two sub-active regions extending along the first direction.
Referring to fig. 10A and 10B, a third isolation structure 1001 is formed in the third isolation trench 901.
Third isolation structures 1001 extending along the first direction and located on two sides of the bit line are formed in the substrate 100, and a certain distance is formed between the third isolation structures 1001 and the bit line 601, or sidewalls of the third isolation structures 1001 are connected with the bit line 601. Fig. 10B is a schematic top view of the first isolation structure 801 and the third isolation structure 1001 after being formed. The substrate 100 is divided into a plurality of sub-active regions extending along the first direction by the isolation structures 801 and the third isolation structures 1001, and each sub-active region has a sub-bit line 601a or a sub-bit line 601b formed therein.
After forming a word line and dividing the substrate 100 into a plurality of sub-active regions extending along a first direction, a word line structure located in the channel doping layer 104 and a second isolation structure penetrating the word line structure are formed in the substrate 100, wherein the word line structure and the second isolation structure extend along a second direction.
Referring to fig. 11A and 11B, a wordline mask layer 1101 is formed on the substrate 100, where the wordline mask layer 1101 has an opening exposing a region to be formed with a wordline in the substrate 100. Fig. 11B is a top view of the word line mask layer 1101 after being formed, and fig. 11A is a cross-sectional view along a cut line BB' in fig. 11B. The openings of the word line mask layer 1101 extend in a second direction. In this embodiment, the second direction is a Y direction and is perpendicular to the first direction X direction. In other embodiments, the second direction may intersect the first direction, but is not perpendicular.
The material of the word line mask layer 1101 may be a photoresist layer, silicon nitride, silicon oxide, or the like, and is different from the material of the substrate 100, the first isolation structure 801, and the third isolation structure 1001, so that in the subsequent process of removing the word line mask layer 1101, damage to the substrate 100, the first isolation structure 801, and the third isolation structure 1001 is reduced.
Referring to fig. 12, the substrate 100 is etched by using the word line mask layer 1101 as a mask and an anisotropic etching process to form a plurality of second dividing grooves 1201 extending along a second direction.
The bottom of the second split trench 1201 is located in the channel doping layer 104, so that a word line trench is formed in the channel doping layer 104 subsequently. Preferably, the bottom surface of the second split trench 1201 is located in the channel doping layer 104, near the source doping layer 105. In one embodiment, the depth of the second split 1201 is about 1/3 times the depth of the bit line 601.
Referring to fig. 13, the substrate 100 is etched along the bottom of the second split groove 1201 to form the word line groove 1301.
The substrate 100 may be continuously etched along the bottom of the second split groove 1201 by using an etching process to form the word line groove 1301.
Before etching, a second protective layer may be formed on sidewalls of the second split trench 1201 to protect the sidewalls of the second split trench 1201. The method for forming the second protective layer comprises the following steps: forming a second protective material layer on the surface of the inner wall of the second dividing groove and the surface of the word line mask layer; and etching the second protective material layer by adopting an anisotropic etching process along a direction vertical to the surface of the substrate 100, removing the second protective material layer at the bottom of the second split groove 1201, forming a second protective layer covering the side wall of the second split groove 1201, and exposing the substrate material at the bottom of the second split groove 1201. The second protection layer may also cover sidewalls of the wordline mask layer 1101.
The material of the second protection layer may be silicon oxide, silicon nitride, silicon oxynitride, or the like, and different from the material of the substrate 100, the material of the substrate 100 and the material of the second protection layer have a larger etching selection ratio so as to protect the sidewalls of the second dividing groove 1201.
The etching process may be a wet etching process or a dry etching process. In this embodiment, a wet etching process is used to etch the substrate at the bottom of the second dividing groove 1201, and the etching solution used in the wet etching process may be a solution with high etching selectivity to silicon, such as HNA, TMAH, NaOH, or the like. The word line groove 1301 may be formed with arc, sigma, vertical or inclined sidewalls, and the shape of the word line groove 1301 in fig. 13 is only an example and does not represent the actual shape of the word line groove 1301 in an actual process.
In other specific embodiments, the substrate 100 may be dry etched by using an etching gas having a high etching selectivity to silicon, so as to form the word line groove 1301. The etching gas molecules react with the substrate 100 material to achieve anisotropic etching. The etching gas may be XeF2、CF4、CH2F2And the like. In order to improve the etching efficiency, the etching gas may be also plasmatized to increase the energy of the etching gas, thereby increasing the reaction rate of the reaction with the material of the substrate 100.
The etching process can simultaneously etch the substrate at the bottom of the second dividing groove 1201 in the vertical direction and the horizontal direction, so that the width of the formed word line groove 1301 is greater than that of the second dividing groove 1201. The word line groove 1301 is located in the channel doping layer 104, and a word line structure is formed in the channel doping layer 104 as a gate structure of an access transistor.
Referring to fig. 14A and 14B, a doped region 1401 is formed between the bottom of the word line trench 1301 and the bit line 601, wherein the doped region 1401 has a doping concentration greater than that of the drain doped layer 103 and has the same doping type as the drain doped layer 103; and filling a dielectric layer 1402 in the second split groove 1201 and the word line groove 1301. Fig. 14B is a top view of the dielectric layer 1402 after formation, and fig. 14A is a cross-sectional view along a cut line BB' in fig. 14B.
By using an ion implantation process, the substrate at the bottom of the word line groove 1301 is ion implanted with the word line mask layer 1101 as a mask, so as to form the doped region 1401. The doped region 1401 is connected to the bit line 601, and forms an ohmic contact with the bit line 601, thereby reducing the contact resistance between the drain doped layer 103 and the bit line 601.
The dielectric layer 1402 is used for protecting the sidewalls of the word line trench 1301 and the second dividing trench 1201 in subsequent processes such as subsequent removal of the word line mask layer 1101. In this embodiment, the material of the dielectric layer 1402 is silicon oxide. In other embodiments, the material of the dielectric layer 1402 may also be other dielectric materials such as silicon nitride, silicon oxynitride, and the like.
In other embodiments, the doped region 1401 may not be formed, and the doping concentration of the drain doped layer 103 may be increased to reduce the contact resistance between the drain doped layer 103 and the bit line 601.
Referring to fig. 15, the word line mask layer 1101 is removed; the dielectric layer 1402 is removed to expose the word line trench 1301 and the second split groove 1201.
The word line mask layer 1101 may be removed by a wet etching process to expose the source doping layer 105, the first isolation structure 801, and the third isolation structure 1001.
And continuously removing the dielectric layer 1402 by using an etching process which is isotropic and has higher selectivity on the dielectric layer 1402. In this embodiment, the dielectric layer 1402 may be removed by a wet etching process. Since the material of the dielectric layer 1402 is the same as the material of the first isolation structure 801 and the third isolation structure 1001, a part of the thickness of the first isolation structure 801 and the third isolation structure 1001 is also removed during the process of removing the dielectric layer 1402.
Referring to fig. 16, a gate dielectric layer 1601 covering at least a portion of an inner wall of a word line groove 1301 is formed, and then a word line 1602 located on a surface of the gate dielectric layer 1601 is formed in the word line groove 1301.
The gate dielectric layer 1601 may be made of a dielectric material such as silicon oxide, silicon oxynitride, hafnium oxide, or zirconium oxide. The gate dielectric layer 1601 may be formed using a thermal oxidation process, a chemical vapor deposition process, or the like.
The material of the word lines 1602 may be polysilicon or a metal material, such as tungsten, copper, silver, etc. A chemical vapor deposition process or a physical vapor deposition process may be used to deposit a word line material in the second split groove 1201 and the word line groove 1301, and then remove the word line material in the second split groove 1201 to form a word line 1602 in the word line groove 1301. Trench doped layers 104 between adjacent word lines 1602 serve as channel regions for the transistors.
In this embodiment, a gate dielectric layer 1601 and a word line 1602 are sequentially formed on top of the first isolation structure 801 and the third isolation structure 1001, so that the word line 1602 surrounds the periphery of the source doping layer 105.
Referring to fig. 17, a patterned mask layer 1702 is formed on the surface of the substrate 100 to expose the bottom of the second split trench 1201, the word line 1602 and the substrate 100 are etched to deepen the bottom of the second split trench, and a second isolation trench 1701 penetrating the word line 1602 to the surface of the bit line 601 is formed.
The second isolation trench 1701 is formed using an anisotropic etching process.
Referring to fig. 18A to 18E, a second isolation structure 1801 is formed in the second isolation trench 1701, and then the patterned mask layer 1702 is removed.
The second isolation structures 1801 extend along a second direction, and divide the sub-active regions along the second direction to form a plurality of access transistors 1800 arranged in an array. The second isolation structure 1801 may be made of an insulating dielectric material such as silicon oxide, silicon nitride, or silicon oxynitride. While filling the second isolation trench 1701 with a dielectric material to form a second isolation structure, in the step of fig. 16, during the process of removing the dielectric layer 1402, filling an insulating dielectric material above the word line 1602 in the recess formed after the first isolation structure 801 and the third isolation structure 1001 are etched, and performing a planarization process such as chemical mechanical polishing to make the insulating dielectric material flush with the surface of the source doped layer 105.
The first isolation structure 801, the second isolation structure 1801, and the third isolation structure 1001 divide the substrate 100 into a plurality of access transistors 1800 arranged in an array.
The cross-sectional view of the access transistor 1800 along the BB ' direction is shown in FIG. 18A, the cross-sectional view along CC ' is shown in FIG. 18C, and the cross-sectional view along DD ' is shown in FIG. 18D. A schematic cross-sectional view along direction AA' is shown in FIG. 18E.
Access cells, such as capacitors, may be subsequently formed on the source doped layer 105 of each access transistor 1800 and the bit line 601 is pulled out by forming contact vias in the substrate that connect to the bit line 601.
According to the method, the transistor with the ring-gate structure is formed in the substrate, the source electrode, the channel region and the drain electrode of the transistor are vertically arranged in the substrate, the word line is arranged around the channel region, and the bit line is positioned below the drain electrode doped layer, so that the size of the access transistor can be reduced, and the storage density of the memory is improved.
The embodiment of the invention also provides a memory.
Please refer to fig. 10A, fig. 18B, fig. 18C, and fig. 18D in combination, wherein fig. 18A is a schematic top view of the memory; FIG. 10A is a schematic sectional view taken along section line AA' in FIG. 18A; FIG. 18B is a schematic sectional view taken along the cut line BB' in FIG. 18A; FIG. 18C is a schematic sectional view taken along section line CC' in FIG. 18A; FIG. 18D is a schematic sectional view taken along the cut line DD' in FIG. 18A.
The memory comprises a substrate 100, wherein a drain doping layer 103, a channel doping layer 104 and a source doping layer 105 are sequentially stacked from the inside of the substrate 100 to the surface of the substrate 100 and are formed in the substrate 100. The remaining portion of the substrate 100 under the drain doping layer 103 serves as a base 101. In one embodiment, the substrate 101 is doped P-type, the drain doping layer 103 is doped N-type, the channel doping layer 104 is doped P-type, and the source doping layer 105 is doped N-type.
In this embodiment, an isolation doped layer 102 is further formed between the drain doped layer 103 and the substrate 101. The isolation doped layer 102 and the drain doped layer 103 have the same doping type, and the doping concentration of the isolation doped layer 102 is less than that of the drain doped layer 103. The isolation doping layer 102 is used for blocking metal atoms of a subsequent bit line 601 from diffusing into the substrate 101.
The bit line 601 of the memory is located below the channel doped layer 104 and at least partially within the drain doped layer 103, the bit line 601 extending along a first direction. The bit line is connected to the drain doped layer 103. A portion of the bit line 601 is also located within the isolating doped layer 102.
The memory further comprises a first isolation structure 801 extending through the bit line 601, the first isolation structure 801 extending in a first direction.
The memory further comprises third isolation structures 1001 located within the substrate 100 extending in a first direction and located on both sides of the bit line 601. The third isolation structure 1001 and the first isolation structure 801 divide the substrate 100 into a plurality of sub-active regions extending along the first direction.
The word line structures of the memory are located in the substrate 100 and in the channel doping layer 104, and a part of the channel doping layer 104 is arranged between adjacent word line structures to serve as a channel region. A second isolation structure 1402 extends through the wordline structure, the wordline structure and the second isolation structure 1402 extending in a second direction. In this embodiment, the second direction is perpendicular to the first direction. The word line structure includes a gate dielectric layer 1601 and a word line 1602.
The semiconductor structure in the region surrounded by the third isolation structure 1001, the second isolation structure 1402 and the first isolation structure 801 is an access transistor 1800 of a memory.
In this embodiment, the memory further includes a doped region 1401 located between the bottom of the word line structure and the bit line 601, where a doping concentration of the doped region 1401 is greater than a doping concentration of the drain doped layer 103 and has the same doping type as the drain doped layer 103. The doped region 1401 is connected to the bit line 601, and forms an ohmic contact with the bit line 601, thereby reducing the contact resistance between the drain doped layer 103 and the bit line 601.
The memory also includes memory cells, such as capacitors, located at the surface of the source doped layer 105 of each access transistor 1800.
The access transistor 1800 of the memory has a gate-all-around structure, and the size of the access transistor can be effectively reduced compared with transistors of other structures under the condition of the same channel length, so that the storage density of the memory can be improved.
The foregoing is only a preferred embodiment of the present invention, and it should be noted that, for those skilled in the art, various modifications and decorations can be made without departing from the principle of the present invention, and these modifications and decorations should also be regarded as the protection scope of the present invention.

Claims (10)

1. A method for forming a memory, comprising:
providing a substrate;
forming a drain electrode doped layer, a channel doped layer and a source electrode doped layer which are sequentially stacked from the inside of the substrate to the surface of the substrate in the substrate;
forming a bit line which is positioned below the channel doping layer and at least partially positioned in the drain doping layer, and a first isolation structure which penetrates through the bit line, wherein the bit line and the first isolation structure extend along a first direction;
forming third isolation structures extending along the first direction and located on two sides of the bit line in the substrate;
and forming a word line structure in the channel doping layer and a second isolation structure penetrating through the word line structure in the substrate, wherein the word line structure and the second isolation structure extend along a second direction.
2. The method for forming a memory according to claim 1, wherein the method for forming the bit line and the first isolation structure comprises: forming a plurality of first trenches extending along a first direction in the substrate, wherein each first trench comprises a bit line trench and a first dividing trench, the bit line trench is located below the channel doping layer and at least partially located in the drain doping layer, the first dividing trench is located above the bit line trench and is communicated with the bit line trench, and the width of the bit line trench is greater than that of the first dividing trench; forming a bit line in the bit line slot; deepening the first dividing groove, forming a first isolation groove which penetrates through the bit line to the position below the drain electrode doped layer, and forming a first isolation structure in the first isolation groove.
3. The method of claim 2, wherein the first trench is formed by a method comprising: etching the substrate by adopting an anisotropic etching process to form a plurality of first dividing grooves extending along a first direction; forming a first protective layer on the side wall of the first dividing groove; and etching the substrate along the bottom of the first dividing groove by adopting an isotropic etching process to form the position line groove.
4. The method for forming a memory according to claim 1, wherein the method for forming the word line structure and the second isolation structure comprises: forming a plurality of second grooves extending along a second direction in the substrate, wherein each second groove comprises a word line groove located in the channel doping layer and a second dividing groove located above the word line groove and communicated with the word line groove, and the width of the word line groove is larger than that of the second dividing groove; forming a gate dielectric layer at least covering the inner wall of the word line groove part and a word line positioned on the surface of the gate dielectric layer in the word line groove; deepening the bottom of the second dividing groove, forming a second isolation groove penetrating through the word line, and forming a second isolation structure in the second isolation groove.
5. The method of claim 4, wherein the second trench is formed by a method comprising: etching the substrate by adopting an anisotropic etching process to form a plurality of second dividing grooves extending along a second direction; forming a second protective layer on the side wall of the second dividing groove; and etching the substrate along the bottom of the second dividing groove by adopting an isotropic etching process to form the word line groove.
6. The method of claim 1, further comprising: forming an isolation doping layer below the drain doping layer in the substrate; and part of the bit lines are positioned in the isolation doped layer.
7. The method of claim 1, further comprising: and forming a doped region between the bottom of the word line structure and the bit line, wherein the doping concentration of the doped region is greater than that of the drain doped layer, and the doped region and the drain doped layer have the same doping type.
8. A memory, comprising:
the substrate is internally provided with a drain electrode doped layer, a channel doped layer and a source electrode doped layer which are sequentially stacked from the inside of the substrate to the surface of the substrate;
the bit line is positioned below the channel doping layer and at least partially positioned in the drain doping layer, and the first isolation structure penetrates through the bit line, and the bit line and the first isolation structure extend along a first direction;
the third isolation structures are positioned in the substrate and extend along the first direction and positioned on two sides of the bit line;
the word line structure is positioned in the substrate and in the channel doping layer, the second isolation structure penetrates through the word line structure, and the word line structure and the second isolation structure extend along a second direction.
9. The memory of claim 8, further comprising: the isolation doping layer is positioned below the drain doping layer; and part of the bit lines are positioned in the isolation doped layer.
10. The memory of claim 8, further comprising: and the doping region is positioned between the bottom of the word line structure and the bit line, the doping concentration of the doping region is greater than that of the drain doping layer, and the doping region and the drain doping layer have the same doping type.
CN201910496280.2A 2019-06-10 2019-06-10 Memory and forming method thereof Pending CN112071838A (en)

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Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN115312519A (en) * 2021-05-08 2022-11-08 芯盟科技有限公司 Dynamic random access memory and forming method thereof
CN116209281A (en) * 2022-09-30 2023-06-02 北京超弦存储器研究院 Memory forming method and memory
WO2023240972A1 (en) * 2022-06-15 2023-12-21 北京超弦存储器研究院 Memory and preparation method therefor, and electronic device
CN115312519B (en) * 2021-05-08 2024-06-11 芯盟科技有限公司 Dynamic random access memory and forming method thereof

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN115312519A (en) * 2021-05-08 2022-11-08 芯盟科技有限公司 Dynamic random access memory and forming method thereof
CN115312519B (en) * 2021-05-08 2024-06-11 芯盟科技有限公司 Dynamic random access memory and forming method thereof
WO2023240972A1 (en) * 2022-06-15 2023-12-21 北京超弦存储器研究院 Memory and preparation method therefor, and electronic device
CN116209281A (en) * 2022-09-30 2023-06-02 北京超弦存储器研究院 Memory forming method and memory
CN116209281B (en) * 2022-09-30 2024-02-23 北京超弦存储器研究院 Memory forming method and memory

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