CN116209281A

CN116209281A - Memory forming method and memory

Info

Publication number: CN116209281A
Application number: CN202211213559.3A
Authority: CN
Inventors: 李辉辉; 张云森; 王桂磊; 赵超
Original assignee: Beijing Superstring Academy of Memory Technology
Current assignee: Beijing Superstring Academy of Memory Technology
Priority date: 2022-09-30
Filing date: 2022-09-30
Publication date: 2023-06-02
Anticipated expiration: 2042-09-30
Also published as: CN116209281B

Abstract

The disclosure provides a forming method of an MRAM memory and the MRAM memory, and relates to the technical field of semiconductors, wherein the forming method of the MRAM memory comprises the following steps: providing a silicon substrate and a plurality of patterned composite layers, wherein a first trench penetrates through the composite layers and extends to a first depth in the silicon substrate; forming a protective layer, wherein the protective layer forms a slit in the first groove; forming grooves in the silicon substrate based on the slits respectively, and forming source lines in each groove respectively; forming an isolation layer based on the slit; forming a plurality of vertical gate-all-around transistors based on the patterned composite layer; a bottom contact electrode is formed on each vertical gate-all-around transistor on the metal contact pad connected to the drain electrode, the bottom contact electrode being smaller than the top surface size of the metal contact pad. In the present disclosure, by reducing the contact area of the bottom contact electrode and the vertical gate-all-around transistor, a magnetic tunnel junction of a smaller area size can be formed, and the density of the magnetic tunnel junction is relatively increased, thereby improving the storage capacity of the chip.

Description

Memory forming method and memory

Technical Field

The disclosure relates to the technical field of memories, and in particular relates to a memory forming method and a memory.

Background

Magnetic random access memory (Magnetic Random Access Memory, MRAM) is a non-volatile memory with the advantages of low power consumption, etc., and is considered a good candidate for replacing semiconductor charge based memory technologies. While the core memory cells of MRAM (magnetic random access memory) are MTJ (Magnetic Tunnel Junction ), with the rapid development of semiconductor manufacturing technology, semiconductor devices are being developed toward higher element density and higher integration, and the development trend of the semiconductor process nodes following moore's law is continuously decreasing, and the spacing between magnetic tunnel junctions is still further to be simplified, so as to reduce the size of the memory cells and increase the memory density.

Disclosure of Invention

The following is a summary of the subject matter of the detailed description of the present disclosure. This summary is not intended to limit the scope of the claims.

The present disclosure provides a method for forming an MRAM memory and an MRAM memory.

A first aspect of the present disclosure provides a method for forming an MRAM memory, the MRAM memory including a plurality of memory cells distributed in an array, the memory cells including a vertical gate-all-around transistor including a source, a gate and a drain stacked from bottom to top, and a magnetic tunnel junction electrically connected to the drain of the vertical gate-all-around transistor through a bottom contact electrode; the method comprises the following steps:

Providing a silicon substrate and a plurality of patterned composite layers arranged on the silicon substrate, wherein the composite layers comprise a first doping layer, a SiGe layer and a second doping layer which are sequentially laminated from bottom to top; the first groove penetrates through the composite layer and extends into the silicon substrate, wherein the depth from the top surface of the silicon substrate to the bottom wall of the first groove, which extends into the silicon substrate, is a first depth which is smaller than or equal to the thickness of a source line to be formed in the silicon substrate, and the bottom of the first groove exposes part of the surface of the silicon substrate;

forming a protective layer covering the composite layer and the surface of the first groove, wherein the protective layer forms a slit in the first groove;

removing a protective layer between the bottom of the first doping layer and the bottom wall of the first groove based on the slit, exposing the side wall of the silicon substrate, respectively forming grooves in the silicon substrate at two sides of the bottom of the first groove, and respectively forming source lines in each groove; adjacent source lines are separated by a second groove and are not connected with each other, and the side walls of the source lines are flush with the side walls of the slits;

forming a dielectric layer in the slit and the second groove, etching the protective layer and the dielectric layer to be level with the upper surface of the first doping layer, and forming an isolation layer by the reserved protective layer and the dielectric layer;

Forming a third groove on the composite layer along the direction perpendicular to the first groove based on the patterned composite layer, wherein a plurality of columnar semiconductor layers are formed by surrounding the first groove and the third groove;

forming a grid electrode surrounding and covering the side surface of the columnar semiconductor layer, and forming a plurality of vertical gate-all-around transistors;

forming a plurality of bottom contact electrodes, each of the bottom contact electrodes being formed on a metal contact pad of a drain electrode of each of the vertical gate-all-around transistors to connect the magnetic tunnel junction; the projection area of the top surface of the bottom contact electrode on the silicon substrate is smaller than the projection area of the top surface of the metal contact pad on the silicon substrate.

Wherein, the preparation material of the bottom contact electrode comprises: one or more of tantalum, titanium, tantalum nitride, titanium nitride.

Wherein, the method for forming the bottom contact electrode comprises the following steps:

forming an unpatterned metal layer on the surface of the vertical gate-all-around transistor, wherein the metal layer covers the top surface of the metal contact pad;

patterning the metal layer, forming the bottom contact electrode on the metal contact pad, wherein the bottom contact electrode is electrically connected with the metal contact pad;

The diameter size of the top surface of the bottom contact electrode is smaller than that of the bottom surface of the bottom contact electrode, and the diameter size of the bottom surface of the bottom contact electrode is smaller than that of the top surface of the metal contact pad.

and forming an insulating medium layer on the surface of the bottom contact electrode by utilizing an atomic layer deposition process.

Wherein the forming method further comprises:

a magnetic tunnel junction is formed on each of the bottom contact electrodes using a self-aligned process, the magnetic tunnel junction including a reference layer, a barrier layer, and a free layer.

Forming grooves in the silicon substrate at two sides of the bottom of the first groove respectively, forming a source line in each groove, and comprising:

patterning the side wall of the silicon substrate exposed in the first groove to form two grooves which are arranged in opposite directions, wherein the grooves are provided with arc surfaces which are concave in the side wall of the silicon substrate, and the grooves expose partial areas of the first doping layer at the bottom of each composite layer on the silicon substrate;

filling a first metal material at the bottom of each first groove and in each groove, and performing high-temperature annealing treatment on the first metal material to form a source wire material layer;

And etching the source material layer based on the slits and extending into the silicon substrate to form a second groove and a source line, wherein the source line is connected with the bottom of the first doping layer of each composite layer.

The depth extending into the silicon substrate from the bottom surface of the source line material layer to the etching stop position is a second depth, and the second depth is smaller than the thickness of the source line.

Wherein the forming method comprises the following steps:

and forming an unpatterned composite layer on the silicon substrate by adopting an epitaxial process, and patterning the unpatterned composite layer by adopting a self-aligned etching process so as to form a plurality of first grooves on the silicon substrate.

A second aspect of the present disclosure provides an MRAM memory, the MRAM memory comprising:

the memory cell array comprises a vertical gate-all-around transistor and a magnetic tunnel junction, wherein the vertical gate-all-around transistor comprises a source electrode, a grid electrode and a drain electrode which are overlapped from bottom to top, and the magnetic tunnel junction is connected with a metal contact pad of the drain electrode of the vertical gate-all-around transistor through a bottom contact electrode;

the source lines are positioned in two grooves which are oppositely arranged and concave in the side wall of the silicon substrate and extend along the column direction parallel to the silicon substrate;

The top surface of the isolation layer is flush with the top surface of the first doped layer and is used for isolating source lines between adjacent storage units, and the cross section of the isolation layer is of a T-shaped structure in the row direction parallel to the silicon substrate;

a plurality of bottom contact electrodes respectively connected with the metal contact pad of the drain electrode of each vertical gate-all-around transistor; the projection area of the top surface of the bottom contact electrode on the silicon substrate is smaller than the projection area of the top surface of the metal contact pad on the silicon substrate.

Wherein a cross-sectional width of the isolation layer located above the top surface of the source line is larger than a cross-sectional width of the isolation layer located between the source line sidewalls in a row direction in a plane parallel to the silicon substrate.

According to the forming method of the memory and the memory, the bottom contact electrode which is used for being connected with the magnetic tunnel junction and provided with the smaller top surface is formed on the metal contact pad through each vertical gate-all-around transistor, so that the magnetic tunnel junction with the smaller area size is formed through reducing the contact area between the magnetic tunnel junction and the vertical gate-all-around transistor, the distance between two adjacent magnetic tunnel junctions is relatively reduced, namely the density of the magnetic tunnel junction is relatively increased, and the effect of improving the storage capacity of a chip while the area of a silicon substrate is unchanged is achieved.

Other aspects will become apparent upon reading and understanding the accompanying drawings and detailed description.

Drawings

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments of the disclosure and together with the description, serve to explain the principles of the embodiments of the disclosure. In the drawings, like reference numerals are used to identify like elements. The drawings, which are included in the description, are some, but not all embodiments of the disclosure. Other figures can be obtained from these figures without inventive effort for a person skilled in the art.

Fig. 1 is a flow chart illustrating a method of forming a memory according to an exemplary embodiment.

Fig. 2 is a schematic diagram illustrating the structure of an MRAM memory according to an exemplary embodiment.

Fig. 3 is a schematic diagram illustrating a structure of a composite layer patterned during formation of an MRAM memory according to an exemplary embodiment.

Fig. 4 is a schematic diagram illustrating a structure of forming a trench during formation of an MRAM memory according to an exemplary embodiment.

Fig. 5 is a schematic diagram illustrating a structure of forming a source line material layer during formation of an MRAM memory according to an exemplary embodiment.

Fig. 6 is a schematic diagram illustrating a structure of forming a source electrode during formation of an MRAM memory according to an exemplary embodiment.

Fig. 7 is a schematic diagram illustrating a structure of an MRAM memory after a dielectric layer is formed during formation of the MRAM memory according to an exemplary embodiment.

Fig. 8 is a schematic diagram illustrating a structure of forming an isolation layer during formation of an MRAM memory according to an exemplary embodiment.

Fig. 9 is a schematic diagram illustrating a structure of forming a trench region during formation of an MRAM memory according to an exemplary embodiment.

Fig. 10 is a schematic diagram illustrating a structure after forming an epitaxial layer during the formation of an MRAM memory according to an exemplary embodiment.

Fig. 11 is a schematic diagram illustrating a structure of an MRAM memory after a channel layer is formed in accordance with an exemplary embodiment.

Fig. 12 is a pattern distribution diagram of a second mask layer in an X direction during formation of an MRAM memory according to an exemplary embodiment.

Fig. 13 is a schematic diagram illustrating a structure of an MRAM memory after etching to a surface of an isolation layer based on a first recess in a forming process according to an exemplary embodiment.

Fig. 14 is a schematic diagram showing a pattern distribution of a second mask layer in a Y direction during formation of an MRAM memory according to another exemplary embodiment.

Fig. 15 is a schematic diagram illustrating a structure of an MRAM memory after etching to a surface of a silicon substrate based on a second recess in a forming process according to an exemplary embodiment.

Fig. 16 is a schematic diagram illustrating a structure of an insulating layer formed on a source line during formation of an MRAM memory according to an exemplary embodiment.

Fig. 17 is a schematic diagram illustrating a structure of an MRAM memory after a third mask layer is formed during formation of the MRAM memory according to an exemplary embodiment.

Fig. 18 is a schematic diagram illustrating a gate structure during formation of an MRAM memory according to an exemplary embodiment.

Fig. 19 is a schematic diagram illustrating a structure of forming vertical gate-around transistors and metal contact pads during formation of an MRAM memory according to an example embodiment.

Fig. 20 is a schematic diagram illustrating a structure after forming a metal layer during the formation of an MRAM memory according to an exemplary embodiment.

Fig. 21 is a schematic diagram illustrating a structure of forming a bottom contact electrode during formation of an MRAM memory according to an example embodiment.

Fig. 22 is a schematic diagram illustrating a structure of forming an insulating dielectric layer during formation of an MRAM memory according to an exemplary embodiment.

Reference numerals:

10. a storage unit; 100. a substrate; 110. a substrate; 120. a composite layer; 121. a first doped layer; 122. a SiGe layer; 123. a second doped layer; 124. a sacrificial semiconductor layer; 125. a channel region; 1251. a first recess; 1252. a second notch; 126. a first sidewall; 127. a second sidewall; 130. a first trench; 131. a slit; 132. a second trench; 140. a third trench; 150. a groove;

20. A second mask layer; 21. spin-coating a hard mask layer; 22. a photoresist layer; 210. a third groove; 30. a bit line; 300. an isolation layer; 310. a protective layer; 320. a dielectric layer; 40. a square pattern; 400. a source line; 410. a first metal material; 420. a metal silicide; 430. a source material layer; 50. a first mask layer; 510. a first groove; 520. a second groove; 60. a dielectric layer; 61. a filling layer; 62. a second filler layer; 600. a channel layer; 610. a first channel layer; 620. a second channel layer; 70. an epitaxial layer;

700. a magnetic tunnel junction; 710. a metal layer; 720. a bottom contact electrode; 721. an insulating dielectric layer; 730. a magnetic tunnel junction multilayer film; 740. a hard mask layer; 750. a sidewall protection layer; 760. a third filler layer; 770. a fourth filler layer; 80. a vertical gate-all-around transistor; 800. a gate; 810. a second metal material; 820. a gate insulating layer; 90. an insulating layer; 900. a columnar semiconductor layer; 910. and a metal contact pad.

Detailed Description

For the purpose of making the objects, technical solutions and advantages of the embodiments of the present disclosure more apparent, the technical solutions in the disclosed embodiments will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present disclosure, and it is apparent that the described embodiments are some embodiments of the present disclosure, but not all embodiments. Based on the embodiments in this disclosure, all other embodiments that a person skilled in the art would obtain without making any inventive effort are within the scope of protection of this disclosure. It should be noted that, without conflict, the embodiments of the present disclosure and features of the embodiments may be arbitrarily combined with each other.

In an exemplary embodiment of the present disclosure, a method for forming an MRAM memory is provided, as shown in fig. 1, fig. 1 is a flowchart illustrating a method for forming an MRAM memory according to an exemplary embodiment of the present disclosure, fig. 2 to 22 are schematic diagrams illustrating various stages of the method for forming an MRAM memory, and the method for forming an MRAM memory is described below with reference to fig. 2 to 22. The MRAM memory formed in this embodiment is not configured as a complete memory, but is merely a process of forming memory cells of the MRAM memory.

The present embodiment is not limited to the memory, in which the transistor in the MRAM memory is a vertical gate-all-around transistor, and the vertical gate-all-around transistor can be applied to a logic device and a driving transistor of a memory device of MRAM (Magnetic Random Access Memory). The MRAM memory includes a plurality of memory cells distributed in an array, as shown in fig. 2, which exemplarily illustrates an MRAM memory having two memory cells, each of which includes an access transistor for reading and writing data, and a Magnetic Tunnel Junction (MTJ) for storing data. The following embodiments are described using transistors as vertical gate-all-around transistors. The vertical gate-around transistor includes a source, a gate and a drain sequentially stacked from bottom to top, as shown in fig. 2, the vertical gate-around transistor includes a pillar-shaped semiconductor layer 900 and a gate 800, the source of the vertical gate-around transistor 80 is formed by the first doped layer 121, the drain of the vertical gate-around transistor 80 is formed by the second doped layer 123, and the magnetic tunnel junction 700 is electrically connected to the drain of the vertical gate-around transistor 80 through the bottom contact electrode 720.

As shown in fig. 1, an exemplary embodiment of the present disclosure provides a method for forming an MRAM memory, which includes the following steps:

step S110: providing a substrate, wherein the substrate comprises a silicon substrate and a plurality of patterned composite layers arranged on the silicon substrate, and the composite layers comprise a first doping layer, a SiGe layer and a second doping layer which are sequentially laminated from bottom to top; the first trench penetrates the composite layer and extends to a first depth in the silicon substrate, wherein the depth from the top surface of the silicon substrate to the bottom wall of the first trench, which extends into the silicon substrate, is the first depth.

Illustratively, the substrate serves as a support member for supporting other components disposed thereon as a platform for subsequent processing. As shown in fig. 3, the base 100 includes a silicon substrate 110, and the silicon substrate 110 may be made of a semiconductor material, which may be one or more of silicon, germanium, a silicon germanium compound, and a silicon carbon compound. The base 100 further includes a composite layer 120 composed of a plurality of patterned material layers on the silicon substrate 110, and the composite layer 120 includes a first doping layer 121, a SiGe layer, and a second doping layer 123 stacked in this order from bottom to top. The first doped layer 121 may be a material layer of a source of the vertical gate-all-around transistor, the second doped layer 123 may be a material layer of a drain of the vertical gate-all-around transistor, and the SiGe layer may be a placeholder layer of a channel of the vertical gate-all-around transistor.

In some exemplary embodiments, the formation of the plurality of patterned composite layers is as follows: and forming an unpatterned first doping layer, a semiconductor layer and a second doping layer on the silicon substrate in sequence by adopting an epitaxial process to form an unpatterned composite layer, and carrying out patterning treatment on the unpatterned composite layer by adopting a self-aligned etching process to form a plurality of first grooves. Referring to fig. 3, in a row direction X parallel to the silicon substrate, a plurality of first trenches 130 are spaced apart, each first trench 130 extending through the thickness of the composite layer 120 and into the silicon substrate until the bottom wall of the first trench 130 reaches a first depth H1 in the silicon substrate 110, wherein the first depth H1 is the distance of the bottom wall of the first trench 130 from the top surface of the silicon substrate 110. As shown in fig. 3, the first depth H1 is less than or equal to the thickness H3 of a source line formed in a silicon substrate by a subsequent process (refer to fig. 6).

Illustratively, the first doped layer and the second doped layer are both N-type doped material layers (n+si layers) formed by doping N impurities with monocrystalline silicon, and the doping concentration may be doped according to actual requirements. Illustratively, the N-type impurity may be phosphorus or arsenic.

In this embodiment, the composite layer is grown by adopting an epitaxial process, so that the forming process of VGAA is simplified, and the epitaxial flatness of each layer and the thickness of each layer can be uniformly controlled, so that the channel length and the thickness of the channel of the vertical gate-all-around transistor formed by the subsequent process are controlled, the uniformity of the channel is improved, the process precision of the vertical gate-all-around transistor is further improved, and the performance of each storage unit in the MRAM memory is improved.

In addition, in the embodiment, under the condition of defining smaller feature sizes by adopting a self-aligned etching process, the condition that the feature sizes become smaller can be reduced, the etching precision can be ensured, and the process precision of the MRAM memory can be improved.

Step S120: and forming a protective layer covering the composite layer and the surface of the first groove, wherein the protective layer forms a slit in the first groove.

As shown in fig. 4, in order to enable etching of the silicon substrate at two positions of the bottom of the first trench in a subsequent process without affecting the surfaces of the plurality of patterned composite layers, before etching, a protective layer 310 may be formed on the surfaces of the composite layers by using an ALD (Atomic Layer Deposition ) process, and the protective layer 310 may also cover the surfaces of the bottom of the first trench 130, that is, the surfaces of the silicon substrate exposed by the first trench 130. The protection layer 310 protects the top surface of the composite layer 120 and the sidewalls of the first trench 130. The protective layer 310 does not fill the first trench 130, and a slit 131 is formed in the first trench 130. Illustratively, the protective layer comprises at least one of silicon oxide, silicon oxynitride, silicon nitride, for example, the protective layer is silicon oxide.

Step S130: removing a protective layer between the bottom of the first doping layer and the bottom wall of the first groove based on the slit, exposing the side wall of the silicon substrate, forming grooves in the silicon substrate on two sides of the bottom of the first groove respectively, forming source lines in each groove respectively, separating adjacent source lines by the second groove, and not connecting the adjacent source lines with each other, wherein the side wall of the source lines is level with the side wall of the slit.

Referring to fig. 4 to 6, the protective layer 310 covering the surface of the silicon substrate in the first trench 130 is removed based on the opening of the slit 131, i.e., the protective layer between the bottom of the first doping layer to the bottom wall of the first trench is removed to expose the sidewall surface of the silicon substrate 110. Based on the exposed sidewalls of the silicon substrate 110, to form a source line 400 within the silicon substrate.

Wherein, the trenches are respectively formed in the silicon substrate at both sides of the bottom of the first trench, and the process of respectively forming the source lines in each trench may comprise the following steps:

step S121: patterning the side wall of the silicon substrate exposed by the first groove to form two grooves which are arranged in opposite directions, wherein the grooves are provided with arc surfaces which are concave on the side wall of the silicon substrate, and the grooves expose partial areas of the first doping layer at the bottom of each composite layer on the silicon substrate;

Step S122: forming a first metal material at the bottom of each first groove and in each groove, and performing high-temperature annealing treatment on the first metal material to form a source material layer;

step S123: and etching the source material layer based on the slit and extending into the silicon substrate, wherein the depth from the bottom surface of the source material layer to the etching stop position, extending into the silicon substrate, is a second depth, forming a second groove and a source line, and connecting the source line with the bottom of the first doping layer of each composite layer.

As shown in fig. 4, after removing the protective layer 310 covering the surface of the silicon substrate in the first trench 130, etching is performed along the exposed bottom of the first doped layer 121 and the surface of the sidewall of the silicon substrate 110 in the direction of retracting the sidewall of the silicon substrate 110 to form a trench 150 retracting into the silicon substrate 110 toward the sidewall of the first trench 130, the surface of the trench 150 is recessed in the sidewall of the silicon substrate, and the trench 150 extends in the column direction (the direction perpendicular to the paper surface, i.e., the direction parallel to the plane of the silicon substrate and perpendicular to the X direction) in the plane parallel to the silicon substrate 110.

As shown in conjunction with fig. 3 and 4, the openings of the trenches 150 located under the composite layer 120 are oppositely directed, and the openings of the trenches 150 on both sides of the first trench 130 are oppositely disposed, each trench 150 having an arc-shaped surface recessed from the sidewall of the silicon substrate 110 in a row direction X in a plane parallel to the silicon substrate, each trench 150 exposing a portion of the surface area of the bottom of the first doped layer 121 of the composite layer of the silicon substrate 110.

Illustratively, referring to fig. 3 and 4, two trenches 150 under the composite layer 120 in a row direction X in a plane parallel to the silicon substrate respectively expose both ends of the first doping layer 121 adjacent to the bottom regions of the first trenches 130. And the two trenches 150 under the same composite layer 120 are isolated from each other and not communicated with each other by the silicon substrate 110. In other embodiments, the surface of the groove may have other shapes, such as a semicircle, a rectangle, etc., which are not particularly limited herein.

Referring to fig. 5, the trench 150 is filled with a first metal material 410 using atomic layer deposition (Atomic Layer Deposition, ALD) or other deposition process, the first metal material 410 being in contact with the surface of the trench 150, i.e., the first metal material 410 being in contact with the surface of the silicon substrate 110 where the trench 150 is exposed. Then, the first metal material 410 is annealed at a high temperature, and the first metal material 410 in contact connection with the surface of the silicon substrate 110 is subjected to a high-temperature heating, annealing and other processes to react with the surface of the silicon substrate 110 to generate a metal silicide 420, wherein the unreacted first metal material 410 and the metal silicide 420 share the source material layer 430; the metal silicide 420 is a hard compound formed by the first metal material 410 and silicon, has stable chemical components and good oxidation resistance, and can reduce interface resistance.

Illustratively, the first metallic material includes, for example, any one including titanium (Ti), tantalum (Ta), hafnium (Hf), nickel (Ni), ruthenium (Ru), iridium (Ir), platinum (Pt), aluminum (Al), cobalt (Co), tungsten (W), molybdenum (Mo), or any one of alloys thereof.

As shown in fig. 5, the source material layer 430 located in the trench 150 is integrally connected with the source material layer 430 located in the slit 131, and thus, it is necessary to divide it and remove the source material layer 430 in the slit 131 to form the independent source line 400.

As shown in fig. 4 to 6, an opening is formed based on the slit 131, the source material layer 430 located in the middle region of the first trench 130 is etched, and the etching is stopped by extending into the silicon substrate 110 to the second depth H2 through the source material layer 430, thereby forming the second trench 132 directly under the slit 131, the source material layer 430 divided by the second trench 132, and the source line 400 capable of independent operation is formed in the trench 150.

As shown in fig. 5 and 6, the second depth H2 is a distance from the position where etching is stopped to the bottom surface of the source line material layer 430, that is, a distance from the bottom wall of the second trench 132 to the bottom surface of the source line 400, and in order to save process time on the basis of effective isolation, the second depth H2 is within a range smaller than the thickness of the source line 400, and can also completely isolate the adjacent source line 400. Referring to fig. 6, the bottom wall of the second trench 132 is located below the bottom surface of the source line 400, and the second depth H2 is not greater than the thickness H3 of the source line 400.

As shown in fig. 6, two source lines 400 are disposed under each of the composite layers 120, and the two source lines 400 are electrically connected to both ends of the bottom of the first doped layer 121 of the corresponding composite layer.

With continued reference to fig. 4 and 6, the sidewall of the source line 400 located in the trench 150 protrudes from the sidewall of the first trench 130 (refer to fig. 3) and is flush with the sidewall of the slit 131. The protective layer 310 on the top surface of the source line 400 extends the distance between the source line 400 and the gate electrode 800 (refer to fig. 19) formed later, and the protective layer 310 also plays a role of isolation and insulation between the source line 400 and the gate electrode 800.

Step S140: and forming a dielectric layer in the slit and the second groove, etching the protective layer and the dielectric layer to be level with the upper surface of the first doping layer, and forming an isolation layer by the reserved protective layer and the dielectric layer.

As shown in fig. 5 to 7, in order to form effective isolation between the source lines 400 of adjacent two composite layers 120 and the first doping layer 121, a CVD (Chemical Vapor Deposition ) process may be used to form the dielectric layer 320 in the areas of the slits 131 where the first trenches 130 are not filled and in the second trenches 132. Illustratively, the dielectric layer 320 includes at least one of silicon oxide, silicon oxynitride, silicon nitride, for example, the dielectric layer is silicon oxide. Illustratively, the dielectric layer and the protective layer are the same material.

Referring to fig. 7 and 8, the dielectric layer 320 covers the surface of the protective layer 310, fills the region of the slit 131, and the second trench 132 communicating with the slit 131 up and down, and the dielectric layer 320 also covers the sidewall surface of the exposed source line 400. And performing back etching treatment on the protective layer 310 and the dielectric layer 320 until the top surfaces of the protective layer 310 and the dielectric layer 320 are flush with the top surface of the first doped layer 121, and forming an isolation layer 300 by remaining part of the protective layer 310 and part of the dielectric layer 320, wherein the upper surface of the isolation layer 300 is flush with the upper surface of the first doped layer 121.

As shown in fig. 8, on top of the isolation layer 300, the protection layer 310 is located at two sides of the dielectric layer 320 and covers the sidewalls of the first doped layer 121. In the row direction X in a plane parallel to the silicon substrate, the cross section of the isolation layer 300 has a T-shape, and the cross section width of the isolation layer above the top surface of the source lines is larger than the cross section width of the isolation layer between the source lines, thereby effectively isolating the isolation layer of the gate and the source.

Step S150: forming a third groove on the composite layer along the direction perpendicular to the first groove based on the patterned composite layer, wherein the first groove and the third groove are surrounded to form a plurality of columnar semiconductor layers.

As shown in fig. 8 and 9, after the isolation layer 300 is formed, the unfilled first trench exposes the sidewalls of the second doped layer 123 and the sidewalls of the SiGe layer 122. As shown in fig. 8 and 9, the SiGe layer is etched back laterally along the exposed sidewalls of the SiGe layer 122, and etched to a set width to form a channel region 125 between the first doped layer 121, the SiGe layer 122, and the second doped layer 123, the channel region 125 being a region for forming a channel layer 600 (refer to fig. 11) in a subsequent process.

As shown in fig. 8 and 9, the cross-sectional width of the etched SiGe layer is smaller than the cross-sectional width of the second doped layer 123, the remaining SiGe layer 122 forms a sacrificial semiconductor layer 124, the cross-sectional width of the sacrificial semiconductor layer 124 is denoted as D2 and the cross-sectional width of the second doped layer 123 is denoted as D3 in a row direction X in a plane parallel to the silicon substrate, wherein D3X 2/5 < D2 < D3X 4/5. Illustratively, the sacrificial semiconductor layer 124 is located in the middle of the composite layer 120, with the sacrificial semiconductor layer 124 extending in a column direction Y (shown in fig. 2) in a plane parallel to the silicon substrate.

Referring to fig. 9, a channel region 125 is formed between the sidewall of the sacrificial semiconductor layer 124 and the first and second

doped layers

121 and 123, and the sacrificial semiconductor layer 124 has first and

second sidewalls

126 and 127 opposite to each other in a row direction X in a plane parallel to the silicon substrate. Wherein the first sidewall 126 forms a first recess 1251 with the top surface of the first doped layer 121 and the bottom surface of the second doped layer 123; the second sidewall 127 forms a second recess 1252 with the top surface of the first doped layer 121 and the bottom surface of the second doped layer 123, the opening of the first recess 1251 facing opposite to the opening of the second recess 1252; the first recess 1251 and the second recess 1252 together form a channel region 125, thereby forming a multi-channel region structure within the composite layer 120, which facilitates the fabrication of high performance vertical gate-all-around transistors.

As shown in fig. 10, an epitaxial layer 70 of silicon is formed on the surfaces of the first doped layer 121, the sacrificial semiconductor layer 124, and the second doped layer 123 using an epitaxial process; epitaxial layer 70 covers the surface of the non-channel region, including the surface area of second doped layer 123, as well as the surface of channel region 125. A portion of the epitaxial layer 70 covering the non-channel region is selectively etched, leaving the epitaxial layer 70 between the first doped layer 121 and the second doped layer 123, and referring to fig. 11, a channel layer 600 is formed, the channel layer 600 extending in a column direction parallel to the silicon substrate 110. Illustratively, the channel layer 600 may also be recessed inwardly from the sidewalls of the composite layer 120.

As shown in fig. 11 and in combination with fig. 9, a first channel layer 610 is formed at the first recess 1251; forming a second channel layer 620 at the second recess 1252; wherein the first channel layer 610 and the second channel layer 620 together constitute the channel layer 600. In this step, a vertical gate-all-around transistor structure having multiple channels is formed by forming multiple channels in the multiple channel region, thereby improving the driving capability and the turn-on speed of the vertical gate-all-around transistor.

Illustratively, the silicon material is selected as an epitaxial layer to form a silicon epitaxial layer as a channel layer, and the silicon epitaxial layer is used as the channel layer to facilitate controlling the thickness of the channel layer and the channel length, so that a gate with uniform thickness is formed on the surface of the channel layer in a subsequent process, and control of the transistor is facilitated.

And then, etching the composite layer and the channel layer to the top surface of the silicon substrate by adopting a self-aligned etching process. Referring to fig. 11 to 15, a filling layer 61 is formed in advance on the surface of the composite layer 120 and in the first trench 130, so that an unfilled region is filled with the filling layer 61, a patterned first mask layer 50 is formed on the surface of the filling layer 61, the first mask layer 50 is positioned over each composite layer, and as shown in fig. 12 and 13, the patterned first mask layer 50 defines a plurality of first grooves 510 and a plurality of second grooves 520, respectively, in a row direction X and a column direction Y in a plane parallel to the silicon substrate.

Referring to fig. 12 and 13, a plurality of first grooves 510 are arranged at intervals in a row direction X in a plane parallel to the silicon substrate and extend in a column direction (direction perpendicular to the paper surface) in the plane parallel to the silicon substrate, and the extending direction of the first grooves 510 is the same as the extending direction of the first grooves 130. The first groove 510 is located directly above the isolation layer 300, and the opening cross-sectional size of the first groove 510 is identical to the opening cross-sectional size of the first trench 130. The first trenches 130, which can expose sidewalls of the channel layer 600, are etched based on the plurality of first grooves 510 to be in a row direction X in a plane parallel to the silicon substrate, to be exposed again.

As shown in fig. 14, a plurality of second grooves 520 are arranged at intervals in a column direction Y in a plane parallel to the silicon substrate and extend in a row direction (direction perpendicular to the paper surface) in the plane parallel to the silicon substrate, and the extending direction of the second grooves 520 perpendicularly intersects with the first groove direction. To form a plurality of trenches exposing sidewalls of the channel layer 600 in a column direction Y in a plane parallel to the silicon substrate based on the plurality of second grooves 520.

As shown in fig. 14 and 15, the filling layer 61, the second doping layer 123, the channel layer 600, and the first doping layer 121 are sequentially etched along the second groove 520, exposing a portion of the surface of the source line 400, forming a plurality of third trenches 140. During etching along the second grooves 520, the filling layer 61 located above the surface of the isolation layer 300 may be simultaneously removed along the first grooves 510, thereby dividing the composite layer 120 into composite layers distributed in an array using the first grooves 130 and the third grooves 140.

As shown in fig. 16, the sacrificial semiconductor layer 124 in the composite layer may be removed by a selective etching process, and the remaining second doped layer 123, channel layer 600 and first doped layer 121 form a pillar-shaped semiconductor layer 900, and the pillar-shaped semiconductor layer 900 is arranged in an array on the silicon substrate 110.

Step S160: and forming a grid electrode surrounding and covering the side surface of the columnar semiconductor layer to form a vertical gate-all-around transistor.

Before forming the gate electrode, referring to fig. 16, in order to isolate the source line 400 from the gate electrode formed in the subsequent process, after removing the sacrificial semiconductor layer (blocked by the channel layer 600), referring to fig. 17, before removing the sacrificial semiconductor layer, an insulating layer 90 is formed on the surface of the exposed source line 400, the insulating layer 90 covers the surface of the exposed source line 400, and then the insulating layer 90 is planarized, the insulating layer 90 functioning as an insulating isolation between the adjacent first doping layers 121, and between the gate electrode and the source line.

As shown in fig. 18, after the pillar-shaped semiconductor layers 900 are formed, the gate electrode 800 is formed around the channel layer 600 of each pillar-shaped semiconductor layer 900, the gate electrode 800 surrounds the surfaces of the first channel layer 610 and the second channel layer 620 covering each pillar-shaped semiconductor layer 900, and fills up the region surrounded by the first channel layer 610, the first doping layer 121, the second channel layer 620, and the second doping layer 123 within the pillar-shaped semiconductor layer 900.

The process of forming the gate electrode will be described in detail with reference to fig. 17 to 19. First, a deposition process may be used to cover the gate insulating layer 820 on the surface of the channel layer 600 in a conformal manner, where the gate insulating layer 820 also covers the regions surrounded by the first doped layer 121, the second doped layer 123 and the channel layer 600. An unpatterned second metal material 810 is formed on the surface of the gate insulating layer 820, and the second metal material 810 serves as a material layer of a gate electrode formed later.

As shown in fig. 17 and 18, patterning the second metal material 810 to form the individual gate electrodes 800 around the pillar-shaped semiconductor layer 900, the step of forming the individual gate electrodes 800 includes: as shown in fig. 17, a patterned second mask layer 20 is formed over the pillar-shaped semiconductor layer 900 and over the second metal material 810, wherein the second mask layer 20 includes a spin-on hard mask layer 21, a photoresist layer 22, and a plurality of third recesses 210 spaced apart in the Y-direction, each third recess 210 extending in a row direction in a plane parallel to the silicon substrate 110.

As shown in fig. 17 and 18, the second metal material 810 and the insulating layer 90 are etched along the plurality of third grooves 210, so that the second metal material 810 is divided into a plurality of gates 800 in a column direction Y in a plane parallel to the silicon substrate, and the columnar semiconductor layer 900 and the gates 800 together form the vertical gate-all-around transistor 80 in the same direction perpendicular to the silicon substrate 110. As shown in fig. 19, the second doped layer 123 in the columnar semiconductor layer 900 is the drain of the vertical gate-all-around transistor 80, the first doped layer 121 is the source of the vertical gate-all-around transistor 80, and the gate insulating layer 820 further insulates the gate 800 from the source and drain, respectively.

In this embodiment, as shown in fig. 19, the gate 800 surrounds the region where the channel of the vertical gate-all-around transistor is located, and the channel control capability is stronger, so that the short channel effect can be better suppressed. The gate 800 may be a ring gate structure, and a projected area of the gate 800 on the substrate 110 is larger than a projected area of the channel layer 600 on the substrate 110.

Exemplary, the exemplary method of this embodiment further comprises: a metal contact pad is formed on the drain of each vertical gate-all-around transistor for connection to other device structures.

As shown in fig. 19, a process of forming a metal contact pad on the second doping layer 123 as a drain electrode is as follows: a second filling layer 62 is formed over the columnar semiconductor layers 900 and on the surface of the gate electrode 800 to fill the semiconductor structure in preparation for subsequent processing, the second filling layer 62 serving as an isolation and insulation between the columnar semiconductor layers 900.

Illustratively, after forming the gate, a filling layer on the top surface of the columnar semiconductor layer may be retained, so as to reduce the time of forming the dielectric layer by the subsequent process and reduce the time cost. Referring to fig. 19, the filler layer 61 and the second filler layer 62, which are not removed, together form a dielectric layer 60. Then, a contact hole may be formed in the dielectric layer 60 using conventional development, exposure, or the like, the contact hole exposing a portion of the surface of the second doped layer (drain electrode). And continuing to deposit a third metal material in the contact hole, filling the contact hole with the third metal material, and forming the metal contact pad 910 after high-temperature annealing the deposited third metal material. The third metal material includes: tungsten, cobalt, aluminum.

In this process, by performing high-temperature degradation treatment on the third metal material, the interface resistance between the metal contact pad 910 and the drain electrode can be reduced, and the conductivity between the metal contact pad and the vertical gate-all-around transistor can be improved.

Step S170: forming bottom contact electrodes, each bottom contact electrode being formed on a metal contact pad of the drain of each vertical gate-all-around transistor to connect to the magnetic tunnel junction; wherein, along the direction from the bottom surface of the silicon substrate to the top surface of the silicon substrate, the projection area of the upper surface of the bottom contact electrode is smaller than the projection area of the lower surface of the bottom contact electrode.

As shown in fig. 19, after forming the vertical gate-all-around transistors 80, in this step, by forming a bottom contact electrode for connection with the magnetic tunnel junction on the metal contact pad at each vertical gate-all-around transistor, and by reducing the contact area between the magnetic tunnel junction and the vertical gate-all-around transistor, it is possible to form a magnetic tunnel junction of a smaller area size, the distance between the adjacent two magnetic tunnel junctions is relatively reduced, that is, the density of the magnetic tunnel junctions is relatively increased, thereby achieving the effect of increasing the memory capacity of the chip while the area of the silicon substrate is unchanged.

Wherein, the process of forming the bottom contact electrode on each vertical gate-all-around transistor can comprise the following steps:

Step S210: an unpatterned metal layer is formed on the vertical gate-around transistor surface, the metal layer covering the top surface of the metal contact pad.

After forming the metal contact pad 910, as shown in fig. 20, a polishing process may be performed on the dielectric layer 60 and the metal contact pad 910 to expose the metal contact pad 910 and form a flat surface, and an unpatterned metal layer 710 may be formed on the dielectric layer 60 and the surface of the metal contact pad 910. The metal layer 710 is a material layer for forming a bottom contact electrode in a subsequent process. The unpatterned metal layer may be achieved by physical vapor deposition (PVD, physical Vapor Deposition), chemical vapor deposition (CVD, chemical Vapor Deposition), or atomic layer deposition (ALD, atomic LayerDeposition).

As shown in fig. 20, the metal contact pad 910 is not the optimal material for connection with the magnetic tunnel junction formed later, and thus, may be prepared from a material that is more stable for connection with the magnetic tunnel junction in the process of preparing the bottom contact electrode, and thus, a material different from the preparation material of the metal contact pad is selected as the preparation material of the bottom contact electrode, thereby improving the selectivity of the preparation material of the bottom contact electrode.

Illustratively, the material of the metal layer 710 may be selected to be easily combined with the magnetic tunnel junction to improve the connection stability between the bottom contact electrode and the magnetic tunnel junction, and illustratively, the metal layer includes: one or more of tantalum and titanium are combined, and a bottom contact electrode formed by a metal layer prepared by the materials and the surface of the metal contact pad can be connected stably.

Step S220: patterning the metal layer, forming a bottom contact electrode on the metal contact pad, wherein the bottom contact electrode is electrically connected with the metal contact pad; wherein, along the direction from the top surface of the silicon substrate to the bottom surface of the silicon substrate, the projection area of the top surface of the bottom contact electrode is smaller than the projection area of the bottom surface of the bottom contact electrode.

As shown in fig. 20, a patterned photoresist layer may be formed on the surface of the metal layer 710, where the patterned photoresist layer is, for example, an array of square patterns 40, and the projected area of the square patterns 40 on the silicon substrate is smaller than the projected area of the top surface of the metal contact pad 910 on the silicon substrate 110, and the area covered by the photoresist layer is the formation position of the bottom contact electrode, so as to form the bottom contact electrode with a diameter smaller than the diameter of the top surface of the metal contact pad 910.

Referring to fig. 20 and 21, the etching is stopped by etching an uncovered region of the photoresist layer to a plane where the top surface of the metal contact pad is located, based on the photoresist layer as a mask, to form a bottom contact electrode 720 (BEC, bottom ElectrodeContact) on the top surface of the metal contact pad. As shown in fig. 21, the bottom contact electrode 720 has a trapezoidal columnar structure, wherein the diameter size of the top of the bottom contact electrode is smaller than the diameter size of the lower portion of the bottom contact electrode. The bottom contact electrode may also be of a straight cylindrical structure, with the top surface of the bottom contact electrode having a diameter equal to the diameter of the lower surface of the bottom contact electrode.

In this embodiment, the metal layer is directly etched by using the photolithography layer as a mask, so that the process of forming the bottom contact electrode on the metal contact pad is simplified, compared with the prior art, the steps of defining the bottom contact electrode pattern, etching the bottom contact electrode pattern to form a bottom contact electrode hole, filling the bottom electrode material, and the like are saved, and the process of forming the bottom contact electrode is simplified.

Step S230: and forming an insulating medium layer on the surface of the bottom contact electrode by utilizing an atomic layer deposition process.

As shown in fig. 21 and 22, the surface of the bottom contact electrode 720 is exposed to air, and in order to prevent the surface of the bottom contact electrode from being oxidized, the surface of the bottom contact electrode is conformally covered with an insulating dielectric layer 721 to isolate oxygen in the air from contacting the surface of the bottom contact electrode.

The exemplary embodiment of the present disclosure illustrates a method for forming an MRAM memory, and the method provided in the present embodiment is added with a method for forming a magnetic tunnel junction on the basis of the method illustrated in fig. 1, and the method of the present embodiment may include:

a magnetic tunnel junction is formed on the top surface of the bottom contact electrode, and a bit line is formed on the top surface of the magnetic tunnel junction, the bit line being electrically connected to the magnetic tunnel junction.

As shown in fig. 2 and 22, a third filling layer 760 is formed on the surface of the insulating dielectric layer 721, the third filling layer 760 is planarized to expose the top surface of the bottom contact electrode 720, a magnetic tunnel junction 700 is formed on the top surface of the bottom contact electrode 720, and the magnetic tunnel junction 700 is electrically connected to the bottom contact electrode 720.

As shown with reference to fig. 2, the magnetic tunnel junction 700 includes a magnetic tunnel junction multilayer film 730, which may include a reference layer, a barrier layer, and a free layer, and a hard mask layer 740. The hard mask layer 740 has a certain conductivity, and can be used as a hard mask for etching the magnetic tunnel junction and also can be used as a top electrode conductive channel.

As shown in fig. 2, a sidewall protection layer 750 is formed on the surface of the magnetic tunnel junction 700, and the sidewall protection layer 750 plays a role in isolating external oxygen, water, etc. from the sidewalls of the magnetic tunnel junction multilayer film 730 and the hard mask layer 740, so as to avoid corrosion of the magnetic tunnel junction by external water, oxygen, etc.

As shown in fig. 2, a fourth filling layer 770 is formed on the surface of the sidewall protection layer 750, the sidewall protection layer 750 and the fourth filling layer 770 are patterned over the surface of the hard mask layer 740, openings are formed in the hard mask layer 740 exposing the hard mask layer 740 to extend, and a bit line material is filled based on the openings to form bit lines 30 in the openings in contact with the magnetic tunnel junctions 700, so that a plurality of array distributed memory cells 10 are formed.

An exemplary embodiment of the present disclosure provides an MRAM memory, as shown in fig. 2, which shows a schematic diagram of the MRAM memory provided according to an exemplary embodiment of the present disclosure, the MRAM memory including:

a plurality of memory cells 10, the plurality of memory cells 10 being arranged in an array on the silicon substrate 110, each memory cell 10 comprising a vertical gate-all-around transistor 80 and a magnetic tunnel junction 700, the vertical gate-all-around transistor 80 comprising a source, a gate and a drain stacked from bottom to top, the magnetic tunnel junction 700 being connected to a metal contact pad 910 on the drain of the vertical gate-all-around transistor 80 by a bottom contact electrode 720;

a source line 400 located in two oppositely disposed trenches 150 (refer to fig. 4) recessed in the sidewall of the silicon substrate, extending in a column direction parallel to the silicon substrate;

An isolation layer 300, wherein the top surface of the isolation layer 300 is flush with the top surface of the first doped layer 121, and is used for isolating the source line 400 between the adjacent memory cells 10, and the cross section of the isolation layer is of a T-shaped structure in the row direction parallel to the silicon substrate;

a plurality of bottom contact electrodes 720 respectively connected to the metal contact pads 910 of the drain electrode of each vertical gate-all-around transistor 80; wherein, the projection area of the top surface of the bottom contact electrode 720 on the silicon substrate is smaller than the projection area of the top surface of the metal contact pad on the silicon substrate.

Illustratively, the spacer 300 above the top surface of the source line 400 has a cross-sectional width greater than the spacer 300 between the sidewalls of the source line 400 in a row direction in a plane parallel to the silicon substrate.

In this specification, each embodiment or implementation is described in a progressive manner, and each embodiment focuses on a difference from other embodiments, and identical and similar parts between the embodiments are all enough to refer to each other.

In the description of the present specification, descriptions of the terms "example," "exemplary embodiment," "some embodiments," "illustrative embodiments," "examples," and the like are intended to mean that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the present disclosure.

In this specification, schematic representations of the above terms do not necessarily refer to the same embodiments or examples. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.

In the description of the present disclosure, it should be noted that the directions or positional relationships indicated by the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc. are based on the directions or positional relationships shown in the drawings, are merely for convenience of describing the present disclosure and simplifying the description, and do not indicate or imply that the devices or elements referred to must have a specific orientation, be configured and operated in a specific orientation, and thus should not be construed as limiting the present disclosure.

It will be understood that the terms "first," "second," and the like, as used in this disclosure, may be used to describe various structures, but these structures are not limited by these terms. These terms are only used to distinguish one structure from another structure.

In one or more of the drawings, like elements are referred to by like reference numerals. For clarity, the various parts in the drawings are not drawn to scale. Furthermore, some well-known portions may not be shown. The structure obtained after several steps may be depicted in one figure for simplicity. Numerous specific details of the present disclosure, such as device structures, materials, dimensions, processing techniques and technologies, are set forth in the following description in order to provide a more thorough understanding of the present disclosure. However, as will be understood by those skilled in the art, the present disclosure may be practiced without these specific details.

Finally, it should be noted that: the above embodiments are only for illustrating the technical solution of the present disclosure, and not for limiting the same; although the present disclosure has been described in detail with reference to the foregoing embodiments, those skilled in the art will appreciate that: the technical scheme described in the foregoing embodiments can be modified or some or all of the technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit of the corresponding technical solutions from the scope of the technical solutions of the embodiments of the present disclosure.

Claims

1. The method for forming the MRAM memory is characterized by comprising a plurality of memory cells distributed in an array, wherein each memory cell comprises a vertical gate-all-around transistor and a magnetic tunnel junction, the vertical gate-all-around transistor comprises a source electrode, a gate electrode and a drain electrode which are overlapped from bottom to top, and the magnetic tunnel junction is electrically connected with the drain electrode of the vertical gate-all-around transistor through a bottom contact electrode; the method comprises the following steps:

2. The method of forming an MRAM memory of claim 1, wherein,

the preparation materials of the bottom contact electrode comprise: one or more of tantalum, titanium, tantalum nitride, titanium nitride.

3. The method of forming an MRAM memory according to claim 1 or 2, wherein the method of forming a bottom contact electrode comprises:

4. The method of forming an MRAM memory of claim 1, wherein the method of forming a bottom contact electrode comprises:

5. The method of forming an MRAM memory of claim 1, further comprising:

A magnetic tunnel junction is formed on each of the bottom contact electrodes, the magnetic tunnel junction including a reference layer, a barrier layer, and a free layer.

6. The method of forming an MRAM memory of claim 1, wherein forming trenches in the silicon substrate on both sides of the bottom of the first trench, respectively, and forming a source line in each of the trenches, comprises:

7. The method of claim 6, wherein a depth extending into the silicon substrate from a bottom surface of the source line material layer to an etch stop position is a second depth, the second depth being less than a thickness of the source line.

8. The method of forming an MRAM memory of claim 1, wherein the method comprises:

9. An MRAM memory, the MRAM memory comprising:

10. The MRAM memory of claim 9, wherein a cross-sectional width of the isolation layer above the source line top surface is greater than a cross-sectional width of the isolation layer between the source line sidewalls in a row direction in a plane parallel to the silicon substrate.