CN117334237A

CN117334237A - Shifting register, silicon-based display panel and display device

Info

Publication number: CN117334237A
Application number: CN202311280996.1A
Authority: CN
Inventors: 刘炳麟; 吴桐
Original assignee: Shanghai Shiya Technology Co ltd
Current assignee: Shanghai Shiya Technology Co ltd
Priority date: 2023-09-28
Filing date: 2023-09-28
Publication date: 2024-01-02

Abstract

The invention discloses a shift register, a silicon-based display panel and a display device, wherein the shift register comprises: a plurality of shift register units in cascade; in the shift register unit, a latch module latches an upper shift signal of an upper shift signal input end in response to a clock signal input by a clock signal input end, and outputs a lower shift signal through a lower shift signal output end; the level conversion module responds to a lower-stage shift signal output by the lower-stage shift signal output end and controls the voltage of an effective pulse of a grid driving signal provided for the output module; the output module controls the polarity of the grid driving signal and outputs the grid driving signal to the grid of the switching transistor in one row of pixel circuits through the driving signal output end; the width of the effective pulse of the grid driving signal is N.H; n is a positive integer, h=1/(f×l), F is the refresh frequency of the silicon-based display panel, and L is the number of rows of pixel circuits in the silicon-based display panel.

Description

Shifting register, silicon-based display panel and display device

Technical Field

The present invention relates to the field of display technologies, and in particular, to a shift register, a silicon-based display panel, and a display device.

Background

Currently, a pixel of a silicon-based display panel includes a light emitting element and a pixel circuit, the pixel circuit can provide a driving current for the light emitting element to drive the light emitting element to emit light, and the magnitude and/or duration of the driving current provided for the light emitting element can control the brightness level presented by the light emitting element.

In the prior art, a pixel circuit includes a switching transistor to which gate driving signals having different duty ratios are supplied through a shift register so that the switching transistor has different on-times to control the duration of a driving current supplied to a light emitting element.

However, the structure and the working process of the shift register in the prior art are limited, so that the on-time of the switching transistor cannot be controlled finely, the time of the driving current provided to the light-emitting element cannot be controlled accurately, the light-emitting element is not smooth enough, flicker occurs even when the brightness is adjusted, the brightness of the light-emitting element cannot be adjusted accurately and flexibly, and the application of the silicon-based display panel is limited.

Disclosure of Invention

The invention provides a shift register, a silicon-based display panel and a display device, which are used for improving the accuracy and the flexibility of the display brightness adjustment of a light-emitting element, so as to improve the display effect of the silicon-based display panel.

According to an aspect of the present invention, there is provided a shift register applied to a silicon-based display panel including a plurality of pixel circuits arranged in an array; the pixel circuit includes a switching transistor, and the shift register includes: a plurality of shift register units in cascade;

each shift register unit comprises a latch module, a level conversion module, an output module, an upper level shift signal input end, a clock signal input end, a lower level shift signal output end and a driving signal output end; the upper-stage shifting signal input end is electrically connected with the lower-stage shifting signal output end of the shifting register unit of the upper stage, and the lower-stage shifting signal output end is electrically connected with the upper-stage shifting signal input end of the shifting register unit of the lower stage;

the latch module is respectively and electrically connected with the clock signal input end, the upper level shift signal input end and the lower level shift signal output end; the latch module is used for responding to the clock signal input by the clock signal input end, latching the upper-stage shift signal of the upper-stage shift signal input end and outputting the lower-stage shift signal through the lower-stage shift signal output end;

The level conversion module is coupled between the lower level shift signal output end and the output module; the level conversion module is used for responding to the lower-stage shift signal output by the lower-stage shift signal output end and controlling the voltage of the effective pulse of the grid driving signal provided to the output module;

the output module is also electrically connected with the driving signal output end; the output module is used for controlling the polarity of the grid driving signal and outputting the grid driving signal to the grid of the switching transistor in one row of pixel circuits through the driving signal output end;

the width of the effective pulse of the grid driving signal is N x H; n is a positive integer, h=1/(f×l), F is the refresh frequency of the silicon-based display panel, and L is the number of rows of pixel circuits in the silicon-based display panel.

According to another aspect of the present invention, there is provided a silicon-based display panel including: a plurality of pixel circuits, a plurality of gate signal lines, a start signal line and the shift register which are arranged in an array;

the pixel circuit includes a switching transistor; the grid electrodes of the switching transistors of the pixel circuits positioned in the same row are electrically connected with the same grid electrode signal line;

In the shift register, a superior shift signal input end of the first stage shift register unit is electrically connected with the starting signal line;

and the driving signal output ends of the shifting register units are respectively and electrically connected with the grid signal lines.

According to another aspect of the present invention, there is provided a display device including: the silicon-based display panel.

The technical proposal of the invention is that the latch module responds to the clock signal to latch the upper level shift signal and output the lower level shift signal, the level conversion module responds to the lower level shift signal to control the voltage of the effective pulse of the grid driving signal provided to the output module, the output module controls the polarity of the grid driving signal and outputs the grid driving signal to the grid of the switch transistor in one row of pixel circuits through the driving signal output end, so that the width of the effective pulse of the grid driving signal provided to the grid of the switch transistor in one row of pixel circuits is an integer multiple of the refreshing time of one row of pixel circuits, namely the width of the effective pulse of the grid driving signal can be an odd multiple or an even multiple of the refreshing time of one row of pixel circuits, therefore, the width of the effective pulse of the gate driving signal output by the shift register can be flexibly controlled according to the requirement of the on time of the switch transistor, and when the switch transistor is a transistor for controlling the light emitting time of the light emitting element, the corresponding gate driving signal is accurately output by controlling the width of the effective pulse of the gate driving signal output by the shift register, so that the silicon-based display panel can accurately present corresponding brightness when the light emitting element emits light, the silicon-based display panel has a finer brightness adjusting mode, the brightness adjustment is smoother, display flickering caused by the frustration of the brightness adjustment is avoided, the display effect of the silicon-based display panel can be improved, and the application scene of the silicon-based display panel is widened.

It should be understood that the description in this section is not intended to identify key or critical features of the embodiments of the invention or to delineate the scope of the invention. Other features of the present invention will become apparent from the description that follows.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for the description of the embodiments will be briefly described below, and it is apparent that the drawings in the following description are only some embodiments of the present invention, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.

Fig. 1 is a schematic structural diagram of a pixel circuit according to an embodiment of the present invention;

FIG. 2 is a schematic diagram of a shift register according to an embodiment of the present invention;

FIG. 3 is a timing diagram of a shift register according to an embodiment of the present invention;

FIG. 4 is a timing diagram illustrating another embodiment of a shift register according to the present invention;

FIG. 5 is a schematic diagram of a shift register unit according to an embodiment of the present invention;

FIG. 6 is a timing diagram of driving a shift register according to another embodiment of the present invention;

FIG. 7 is a timing diagram of driving a shift register according to another embodiment of the present invention;

FIG. 8 is a schematic diagram of a specific circuit structure of a shift register unit according to an embodiment of the present invention;

fig. 9 is a driving timing chart of a shift register unit corresponding to fig. 8;

FIG. 10 is a schematic diagram of another shift register according to an embodiment of the present invention;

FIG. 11 is a timing diagram of driving a shift register according to another embodiment of the present invention;

FIG. 12 is a timing diagram of driving a shift register according to another embodiment of the present invention;

FIG. 13 is a schematic diagram showing a specific circuit configuration of another shift register unit according to an embodiment of the present invention;

fig. 14 is a driving timing chart of a shift register unit corresponding to fig. 13;

fig. 15 is a driving timing chart of another shift register unit corresponding to fig. 13;

FIG. 16 is a schematic view of a silicon-based display panel according to an embodiment of the present invention;

fig. 17 is a schematic structural diagram of a display device according to an embodiment of the present invention.

Detailed Description

In order that those skilled in the art will better understand the present invention, a technical solution in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in which it is apparent that the described embodiments are only some embodiments of the present invention, not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the present invention without making any inventive effort, shall fall within the scope of the present invention.

It should be noted that the terms "first," "second," and the like in the description and the claims of the present invention and the above figures are used for distinguishing between similar objects and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used may be interchanged where appropriate such that the embodiments of the invention described herein may be implemented in sequences other than those illustrated or otherwise described herein. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.

The shift register provided by the embodiment of the invention can be applied to a silicon-based display panel, wherein the silicon-based display panel comprises a plurality of pixel circuits which are arranged in an array manner, and the pixel circuits at least comprise switching transistors. Fig. 1 is a schematic structural diagram of a pixel circuit according to an embodiment of the present invention, and as shown in fig. 1, the pixel circuit P may further include a driving module P1, a data writing module P2, and a light emitting element D0, in addition to the switching transistor M1. The DATA writing module P2 may provide the DATA signal DATA to the driving module P1, the driving module P1 may generate the corresponding driving current Id in response to the received DATA signal DATA, and the switching transistor M1 is used for controlling the transmission time of the driving current Id to the light emitting element D0.

In an alternative embodiment, the driving module P1 may include a driving transistor M0, and the data writing module P2 may include a data writing transistor M2, where the gate of the switching transistor M1 receives the gate driving signal Gout, and the gate of the data writing transistor M2 receives the gate driving signal Gout'; the first pole of the DATA writing transistor M2 can receive the DATA signal DATA, the second pole of the DATA writing transistor M2 can be electrically connected with the grid electrode of the driving transistor M0, the first pole of the driving transistor M0 receives the positive power supply signal VP+, the second pole of the driving transistor is electrically connected with the first pole of the switching transistor M1, the second pole of the switching transistor M1 is electrically connected with the anode electrode of the light emitting element D0, and the cathode electrode of the light emitting element D0 receives the negative power supply signal VP-; at this time, the DATA writing transistor M2 may be turned on or off under the control of the gate driving signal Gout' received by the gate thereof, the switching transistor M1 may be turned on or off under the control of the gate driving signal Gout received by the gate thereof, and the DATA signal DATA may be provided to the gate of the driving transistor M0 when the DATA writing transistor M2 is turned on, so that the driving transistor M0 may generate the corresponding driving current Id according to the DATA signal DATA received by the gate thereof; the switching transistor M1 may control the time when the driving current Id is supplied to the light emitting element D0 to control the light emitting time of the light emitting element D0.

It is understood that the channel types of the driving transistor M0, the data writing transistor M2, and the switching transistor M1 may be the same or different, i.e., the channel types of the transistors may be P-type or N-type; if the channel type of the data writing transistor M2 and/or the switching transistor M1 is P-type, the data writing transistor is turned on when the gate driving signal received by the gate thereof is at a low level, and turned off when the gate driving signal received by the gate thereof is at a high level; if the channel type of the data writing transistor M2 and/or the switching transistor M1 is N-type, the data writing transistor is turned on when the gate driving signal received by the gate thereof is at a high level, and turned off when the gate driving signal received by the gate thereof is at a low level; for the case that the channel type of the driving transistor M0 is P-type, the smaller the voltage of the data signal received by the gate thereof, the larger the driving current generated by the driving transistor M0; in the case where the channel type of the driving transistor is N-type, the larger the voltage of the data signal received by the gate thereof, the larger the driving current generated by the driving transistor M0. The signal levels and the signal levels are relative concepts, and can be designed according to actual needs, which is not particularly limited in the embodiment of the invention.

For convenience of description, the embodiments of the present invention take the driving transistor M0, the data writing transistor M2, and the switching transistor M1, which have the same channel types and are all N-channel transistors, as examples, to describe the technical solution of the embodiments of the present invention.

With continued reference to fig. 1, when the voltages of the data signals provided by the data writing module P2 to the driving module P1 are different, the driving currents generated by the driving module P1 are different, and when the different driving currents are transmitted to the light emitting element D0 through the on switch transistor M1, the light emitting element D0 can present different display light-emitting brightness, and when the different light emitting elements present different brightness and different colors of light, the silicon-based display panel can realize color display with rich colors; meanwhile, when the silicon-based display panel displays pictures, the display luminous brightness observed by human eyes is the integral of the actual luminous brightness of the silicon-based display panel in one frame of picture time, so that the longer the luminous element D0 displays and emits light, the higher the display brightness of the silicon-based display panel is perceived by human eyes, so that the purpose of controlling the display brightness of the silicon-based display panel can be achieved by controlling the luminous time of the luminous element D0, namely controlling the on time of the switching transistor M1, and the silicon-based display panel can have different display brightness under different application scenes, for example, in darker environments, the silicon-based display panel can have lower display brightness by controlling the switching transistor M1 to have shorter on time, thereby preventing high-brightness display from stimulating human eyes and improving the comfort level of the human eyes to watch the display pictures; in a brighter environment, the silicon-based display panel can have higher display brightness by controlling the switch transistor M1 to have longer on-time, so that the human eyes can not watch clear pictures in the brighter environment.

It should be noted that, the required display brightness of the silicon-based display panel has a difference in different application scenarios, and the display light-emitting brightness requirement of the silicon-based display panel in different application scenarios can be realized by controlling the on-time of the switching transistor M1, so that the silicon-based display panel meets the display light-emitting brightness requirement of more application scenarios on the premise of higher display quality, and the switching transistor M1 is required to have finer adjustment of the on-time.

In view of this, an embodiment of the present invention provides a shift register, including: a plurality of shift register units in cascade; each shift register unit comprises a latch module, a level conversion module, an output module, an upper level shift signal input end, a clock signal input end, a lower level shift signal output end and a driving signal output end; the upper-stage shift signal input end is electrically connected with the lower-stage shift signal output end of the upper-stage shift register unit, and the lower-stage shift signal output end is electrically connected with the upper-stage shift signal input end of the lower-stage shift register unit; the latch module is respectively and electrically connected with the clock signal input end, the upper level shift signal input end and the lower level shift signal output end; the latch module is used for responding to the clock signal input by the clock signal input end, latching the upper-stage shift signal of the upper-stage shift signal input end and outputting the lower-stage shift signal through the lower-stage shift signal output end; the level conversion module is coupled between the lower level shift signal output end and the output module; the level conversion module is used for responding to the lower-stage shift signal output by the lower-stage shift signal output end and controlling the voltage of the effective pulse of the grid driving signal provided to the output module; the output module is also electrically connected with the driving signal output end; the output module is used for controlling the polarity of the grid driving signal and outputting the grid driving signal to the grid of the switching transistor in one row of pixel circuits through the driving signal output end; the width of the effective pulse of the grid driving signal is N.H; n is a positive integer, h=1/(f×l), F is the refresh frequency of the silicon-based display panel, and L is the number of rows of pixel circuits in the silicon-based display panel.

By adopting the technical scheme, the width of the effective pulse of the gate driving signal provided to the gate electrode of the switching transistor in one row of pixel circuits is an integral multiple of the refreshing time of the one row of pixel circuits, namely, the width of the effective pulse of the gate driving signal can be an odd multiple or an even multiple of the refreshing time of the one row of pixel circuits, so that the width of the effective pulse of the gate driving signal output by the shift register can be flexibly controlled according to the requirement of the on time of the switching transistor, and when the switching transistor is a transistor for controlling the light emitting time of the light emitting element, the corresponding gate driving signal is accurately output by controlling the width of the effective pulse of the gate driving signal output by the shift register, the silicon-based display panel can accurately present corresponding brightness when the light emitting element emits light, the silicon-based display panel has a finer brightness adjusting mode, the brightness adjustment is smoother, the display effect of the silicon-based display panel is prevented from being caused by the sense of the brightness adjustment, and the application scene of the silicon-based display panel is widened.

The above is the core idea of the invention, and based on the embodiments of the invention, all other embodiments obtained by a person skilled in the art without making any inventive effort are within the scope of the invention. The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention.

Fig. 2 is a schematic structural diagram of a shift register according to an embodiment of the present invention, and as shown in fig. 2, the shift register 100 includes a plurality of shift register units G in cascade connection; each shift register unit G includes a latch module 10, a level shift module 20, an output module 30, an upper shift signal input terminal IN, a clock signal input terminal CK, a lower shift signal output terminal Next, and a driving signal output terminal OUT; the upper shift signal input end Next i-1 of the current shift register unit G is electrically connected to the lower shift signal output end Next of the upper shift register unit G, and the lower shift signal output end Next of the current shift register unit G is electrically connected to the upper shift signal input end IN of the lower shift register unit G.

Fig. 3 is a driving timing chart of a shift register according to an embodiment of the present invention, and fig. 4 is a driving timing chart of another shift register according to an embodiment of the present invention, referring to fig. 2-4, an upper shift signal input terminal IN of a first stage shift register unit G1 receives a start signal STV; the upper-stage shift signal input end IN of the second-stage shift register unit G2 is electrically connected with the lower-stage shift signal output end Next of the first-stage shift register unit G1, the lower-stage shift signal output end Next of the second-stage shift register unit G2 is electrically connected with the upper-stage shift signal input end IN of the third-stage shift register unit G3, and the lower-stage shift signal output end Next of the third-stage shift register unit G3 is electrically connected with the upper-stage shift signal input end Next-1 of the fourth-stage shift register unit G4; similarly, the upper stage shift signal input IN of the M-1 stage shift register unit GM-1 is electrically connected with the lower stage shift signal output Next of the M-2 stage shift register unit G, and the lower stage shift signal output IN of the M-1 stage shift register unit GM-1 is electrically connected with the upper stage shift signal input IN of the M stage shift register unit GM. At this time, the first stage shift register unit G1 may supply the lower stage shift signal v_next1 to the second stage shift register unit G2 under the control of the start signal STV as an upper stage shift signal of the second stage shift register unit, the second stage shift register unit G2 may supply the lower stage shift signal v_next2 to the third stage shift register unit G3 under the control of the upper stage shift signal v_next1 received by the second stage shift register unit G3 as an upper stage shift signal of the third stage shift register unit G3, and the third stage shift register unit G3 may supply the lower stage shift signal v_next3 to the fourth stage shift register unit G4 under the control of the upper stage shift signal v_next1 received by the third stage shift register unit G3 as an upper stage shift signal of the fourth stage shift register unit G4, and so on, the M-1 stage shift register unit GM-1 may supply the lower stage shift signal v_next2 to the third stage shift register unit GM-1 under the control of the lower stage shift signal v_next2 received by the third stage shift register unit GM-1 as an upper stage shift signal v_next1 received by the third stage shift register unit GM-1, and the fourth stage shift unit GM-1 may sequentially output the lower stage shift signal v_next1 as a lower stage shift signal to the fourth stage shift unit G4.

Referring to fig. 1 and 2 IN combination, IN the same shift register unit G, the latch module 10 is electrically connected to the clock signal input terminal CK, the upper shift signal input terminal IN, and the lower shift signal output terminal Next, respectively; the latch module 10 is configured to latch an upper shift signal v_next i-1 of the upper shift signal input terminal IN response to the clock signal CLK input by the clock signal input terminal CK, and output a lower shift signal v_next through the lower shift signal output terminal Next; the level conversion module 20 is coupled between the Next level shift signal output terminal Next and the output module 30; the level conversion module 20 is configured to control a voltage of an active pulse of the gate driving signal Gout provided to the output module 30 in response to the lower level shift signal v_next output from the lower level shift signal output terminal Next; the output module 30 is also electrically connected with the driving signal output terminal OUT; the output module 30 is used for controlling the polarity of the gate driving signal Gout and outputting the gate driving signal Gout to the gate of the switching transistor M1 in one row of the pixel circuits P through the driving signal output terminal OUT.

The latch module 10 may have any structure with a latch function, and is capable of implementing a latch function on the upper level shift signal v_next i-1 received by the upper level shift signal input terminal IN, and responding to the clock signal CLK of the clock signal terminal CK to control the shift amount of the lower level shift signal v_next output by the lower level shift signal output terminal Next compared with the upper level shift signal v_next i-1 received by the lower level shift signal output terminal Next under the control of the clock signal CLK. In an alternative embodiment, the clock period of the clock signal CLK may be an integer multiple of the refresh time H of a row of pixel circuits P, such that the lower-level shift signal v_next output by the lower-level shift signal output terminal Next is also an integer multiple of H compared to the upper-level shift signal v_next-1 received by the lower-level shift signal output terminal Next.

The level conversion module 20 may perform level conversion on the lower level shift signal v_next output by the lower level shift signal output terminal Next, for example, the amplitude of an effective pulse in the lower level shift signal v_next may be increased or decreased, so that the lower level shift signal v_next is converted into a corresponding gate driving signal Gout by the level conversion module 20, so that the amplitude of the effective pulse of the gate driving signal Gout is an amplitude capable of controlling the switching transistor to be turned on or off, that is, the amplitude of the effective pulse of the gate driving signal Gout may be related to the threshold voltage of the switching transistor M1, and the amplitude of the level conversion performed by the level conversion module 20 is not specifically limited on the premise of controlling the switching transistor M1 to be turned on when the gate driving signal Gout is an effective pulse. In an alternative embodiment, the level shifter module 20 may include a level shifter having an input terminal coupled to the Next level shift signal output terminal Next, and an output terminal electrically connected to the output module 30, and the level shifter may be capable of level-shifting the Next level shift signal v_next input to its input terminal.

The output module 30 may control the polarity of the gate driving signal Gout after the level conversion by the level conversion module 20, for example, when the switching transistor M1 is an N-channel transistor and the effective pulse of the gate driving signal provided to the output module 30 after the level conversion by the level conversion module 20 is a low level, the effective pulse of the gate driving signal is converted from the low level to the high level by the output module 30, so that the effective pulse may control the switching transistor M1 of the N channel to be turned on; conversely, the output module 30 may also switch the active pulse of the gate driving signal from high level to low level, so that the active pulse may control the P-channel switching transistor M1 to be turned on.

It is understood that the high and low levels of the active pulse described herein may refer to the polarity of the active pulse, e.g., the high level may be positive and the low level may be negative. In other alternative embodiments, when the effective pulse of the gate driving signal provided to the output module 30 after the level conversion by the level conversion module 20 can control the switch transistor M1 to be turned on, the output module 30 does not need to perform polarity conversion on the gate driving signal, and at this time, the output module 30 can improve the driving capability of the gate driving signal, so that the switch transistor M1 has a better on state. In an alternative embodiment, the output module 30 may include at least one buffer connected in series between the driving signal output terminal OUT and the level conversion module 20, which is capable of improving the driving capability of the gate driving signal. Wherein each buffer may include at least one inverter, and the number of inverters and the number of buffers are related to the polarity of the gate driving signal supplied to the switching transistor M1 and the driving capability required to be improved.

Referring to fig. 1 to 4, under the combined action of the latch module 10, the level shift 20, the output module 30, the clock signal CLK and the upper level shift signal v_next-1, the width T10 of the effective pulse of the gate driving signal Gout is n×h; n is a positive integer, namely N can be an odd number or an even number; h=1/(f×l), F is the refresh frequency of the silicon-based display panel, and L is the number of rows of the pixel circuits P in the silicon-based display panel.

The number of rows L of the pixel circuits P in the silicon-based display panel may be the same as or different from the number M of the shift register units G in the shift register, which is not particularly limited in the embodiment of the present invention, and in an alternative embodiment, the number M of the shift register units G may be greater than or equal to L, so as to ensure that each row of the pixel circuits P can receive the gate driving signals Gout output by the shift register units G at different stages.

It can be understood that the refresh frequency F of the silicon-based display panel may represent the number of frames of the frame that the silicon-based display panel can present in a unit time, and the refresh frequency of the silicon-based display panel may be selected according to needs, for example, may be 240Hz, 120Hz, 60Hz or 30Hz, etc., which is not limited in particular in the embodiment of the present invention. After knowing the refresh frequency F of the silicon-based display panel, the time required for the silicon-based display panel to display a frame of picture can be determined to be 1/F, and at this time, the length of the refresh time H of each row of pixel circuits P can be determined to be 1/(f×l) by the silicon-based display panel including L rows of pixel circuits P. The duration of each stage in the driving process of each row of pixel circuits P is performed in units of H, so that the driving of each row of pixel circuits P can be completed within the time of one frame of picture of the silicon-based display panel.

For example, taking the number M of the shift register units G as L as an example, in a frame of time, each row of pixel circuits P of the silicon-based display panel may be sequentially driven, for example, a first period of time may be a DATA writing stage of the first row of pixel circuits P, and the DATA writing module P1 in the first row of pixel circuits P may be controlled to be turned on, so that the DATA signal DATA of the first row of pixel circuits P may be correspondingly written into the driving module P1 of the first row of pixel circuits P, while the DATA writing modules of the other rows of pixel circuits P are in an off state, and after the first period of time is over, the light emitting stage of the first row of pixel circuits P may be entered, where the length of the light emitting stage is controlled by the turn-on period of the switching transistor M1, that is, the width T10 of the effective pulse of the gate driving signal Gout1 outputted by the first stage of the shift register unit G1; after the data writing phase of the first row of pixel circuits P is finished, entering the light emitting phase of the first row of pixel circuits P, and entering the data writing phase of the second row of pixel circuits P, wherein the duration of the data writing phase of the second row of pixel circuits P can be H as well; after the data writing phase of the second row of pixel circuits P is finished, the second stage shift register unit G2 outputs an effective pulse of the gate driving signal Gout 2; after the data writing phase of the second row of pixel circuits P is finished, the data writing phase of the third row of pixel circuits P is also entered while the light emitting phase of the second row of pixel circuits P is entered, and after the data writing phase of the third row of pixel circuits P is finished, the light emitting phase of the third row of pixel circuits P is entered, and at this time, the third stage shift register unit G3 outputs an effective pulse of the gate driving signal Gout 2; by analogy, after the data writing stage of the pixel circuit P of the M-1 row is finished, the light emitting stage of the pixel circuit P of the M row and the data writing stage of the pixel circuit P of the M row are entered, and at the moment, the M-1 shift register unit GM-1 outputs the effective pulse of the gate driving signal GoutM-1; after the data writing phase of the M-th row pixel circuit is finished, the M-th row pixel circuit enters the light emitting phase of the M-th row pixel circuit P, and at this time, the M-th shift register unit GM outputs an effective pulse of the gate driving signal GoutM. In this way, by sequentially shifting the effective pulses of the gate driving signals Gout (Gout 1, gout2, gout3, gout4, …, gout m-2, gout m-1, gout m) outputted from the respective stages of the shift register units G, the progressive scanning of the respective rows of the pixel circuits P can be realized, so that the light emitting elements D0 of the respective rows of the pixel circuits P can sequentially emit light.

Meanwhile, since the width T10 of the effective pulse of the gate driving signal Gout outputted by each stage of the shift register unit G is an integer multiple of the refresh time H of one row of the pixel circuits P, i.e., as shown in fig. 3, the width T10 of the effective pulse of the gate driving signal Gout may be an even multiple of the refresh time H of one row of the pixel circuits P, or as shown in fig. 4, the width T10 of the effective pulse of the gate driving signal Gout may be an odd multiple of the refresh time H of one row of the pixel circuits P, so that the width T10 of the effective pulse of the gate driving signal Gout outputted by the shift register unit G may be adjusted in units of H1*H to (L-1), so that the width T10 of the effective pulse of the gate driving signal Gout has a larger selection, and when the gate driving signal Gout outputted by each stage of the shift register unit G is used to control the on duration of the switching transistor M1 in the pixel circuits P, the on duration of the switching transistor M1 may be adjusted in units of 1*H to (L-1) H, so that the luminance level of the silicon-based display panel may not be adapted to the luminance level of the silicon-based display panel (i.e., the silicon-based display panel may be displayed.

According to the embodiment, the width of the effective pulse of the gate driving signal output by each level of shift register unit is an integer multiple of H, so that the width of the effective pulse of the gate driving signal output by the shift register can be adjusted in a more flexible mode, the shift register can accurately output the corresponding gate driving signal corresponding to the luminous brightness requirement of the luminous element in the pixel circuit, the luminous element can be provided with a finer brightness adjusting mode, brightness adjustment is smoother, display flickering caused by the frustration of brightness adjustment is avoided, the display effect of the silicon-based display panel can be improved, and the application scene of the silicon-based display panel is widened.

The above description is given by way of example only of the functions of the latch module, the level shift module, and the output module in each shift register unit, and the configuration of each module may be designed according to actual needs on the premise that the width of the effective pulse of the gate driving signal output by each shift register unit can be controlled to be an integer multiple of the refresh time of one row of pixel circuits, which is not particularly limited in the embodiment of the present invention, and the following description is given by way of example of typical examples of each module.

Optionally, fig. 5 is a schematic diagram of a shift register unit according to an embodiment of the present invention, as shown in fig. 5, the clock signal input terminal CK may include a first clock signal terminal CK1 for receiving the first clock signal CLK and a second clock signal terminal CK2 for receiving the second clock signal XCLK, and at the same time, polarities of the first clock signal CLK and the second clock signal XCLK may be opposite, i.e. when the first clock signal CLK is an in-phase clock signal, the second clock signal XCLK is an opposite-phase clock signal; at this time, the latch module may include a D flip-flop DS; the input end D of the D trigger DS is electrically connected with the upper level shift signal input end IN, the control end CL of the D trigger is electrically connected with the first clock signal end CK1, the reset end SET of the D trigger is electrically connected with the second clock signal end CK2, and the output end Q of the D trigger is electrically connected with the lower level shift signal output end Next; the width of the effective pulse of the upper level shift signal v_next-1 and the width of the effective pulse of the lower level shift signal v_next are the same as the width T10 of the effective pulse of the gate driving signal Gout.

Specifically, taking the active pulse of each signal as a high level as an example, the D flip-flop DS is usually triggered by a falling edge, and at this time, if the upper level shift signal v_nexti-1 received by the input end D of the D flip-flop DS is an active pulse, when the first clock signal CLK received by the control end CL of the D flip-flop DS transitions from a high level to a low level, the lower level shift signal v_nexti output by the output end Q of the D flip-flop DS transitions from a low level to a high level; similarly, if the upper level shift signal v_next_1 received by the input terminal D of the D flip-flop DS is at an inactive level, the lower level shift signal v_next outputted by the output terminal Q of the D flip-flop DS will transition from a high level to a low level when the first clock signal CLK received by the control terminal CL of the D flip-flop DS transitions from a high level to a low level. In this way, the shift amount of the lower shift signal v_next of the outputs of the adjacent two-stage shift register units is equal to one clock cycle of the first clock signal CLK.

It can be appreciated that since the lower level shift signal v_next i is controlled by the time when the upper level shift signal v_next i-1 and the first clock signal CLK received at the input terminal D of the D flip-flop DS transition from the high level to the low level, the control of the width of the effective pulse of the lower level shift signal v_next i can be achieved by controlling the width of the effective pulse of the upper level shift signal v_next i-1 and the period of the first clock signal CLK. Meanwhile, the lower level shift signal v_next i output by the D flip-flop may be provided to the output module 30 after level conversion by the level conversion module 20, so that the amplitude of the gate driving signal Gout received by the output module 30 may be different from the amplitude of the lower level shift signal v_next i, and the width of the effective pulse is the same; the output module 30 adjusts the polarity of the received gate driving signal Gout and provides the signal Gout to the switching transistors of one row of pixel circuits, that is, the gate driving signal Gout of the switching transistors of the pixel circuits may be different from the effective pulse of the lower level shift signal v_next in amplitude and polarity, but the width of the effective pulse of the gate driving signal Gout may be the same as the width of the effective pulse of the lower level shift signal v_next; in this way, the width of the effective pulse of the gate driving signal Gout outputted from the shift register unit G is also controlled by the upper level shift signal v_next-1 and the first clock signal CLK.

It will be appreciated that the above description is given by taking the first clock signal and the upper shift signal as the active pulse phases of the first clock signal and the upper shift signal as examples, and that in other embodiments of the present invention, the first clock signal and the upper shift signal may be reduced to the low level time as the active pulse phases of the first clock signal and the upper shift signal. On the premise of realizing the core invention point of the embodiment of the invention, the embodiment of the invention does not limit the level of the effective pulse. For convenience of description, the embodiment of the present invention takes the active pulse as the high level as an example, and the technical solution of the embodiment of the present invention is described in an exemplary manner without special limitation.

In an alternative embodiment, fig. 6 is a driving timing diagram of a shift register according to an embodiment of the present invention, fig. 7 is a driving timing diagram of a shift register according to an embodiment of the present invention, and referring to fig. 2 and fig. 5-7, when the clock signal input terminal CK includes a first clock signal terminal CK1 receiving the first clock signal CLK and a second clock signal terminal CK2 receiving the second clock signal XCLK, the clock signals may include the first clock signal CLK and the second clock signal XCLK with clock periods T being H; at the same time, the polarities of the first clock signal CLK and the second clock signal XCLK are opposite, and when the first clock signal CLK is positive, the second clock signal XCLK is negative and when the first clock signal CLK is negative, the second clock signal XCLK is positive.

Specifically, taking the operation of the first stage shift register unit IN the shift register as an example, when the width of the effective pulse of the gate driving signal Gout outputted from each stage shift register unit needs to be an even multiple of H, as an example, the width of the effective pulse of the gate driving signal Gout to be outputted is 2*H, the start signal STV having the width of the effective pulse 2*H may be supplied to the upper stage shift signal input terminal IN of the first stage shift register unit G1, and the start timing of the effective pulse of the start signal STV may overlap with the period when the first clock signal CLK is at the inactive level and the period when the second clock signal XCLK is at the active level, or may overlap with the time when the first clock signal CLK transitions from the high level to the low level and the time when the second clock signal XCLK transitions from the level to the high level, IN conjunction with fig. 2, 5 and 6. During the period when the start signal STV is an active pulse, the first clock signal CLK transitions from high to low for the first time, and the second clock signal XCLK transitions from low to high, the first stage shift register unit G1 starts outputting the low stage shift signal v_next1 and the gate driving signal Gout1 at the high level, that is, the start time of the active pulse of the low stage shift signal v_next1 and the gate driving signal Gout1 output by the first stage shift register unit G1, and the low stage shift signal v_next1 and the gate driving signal Gout1 output by the first stage shift register unit G1 are continuously maintained at the high level after that. After the termination time of the effective pulse of the start signal STV, when the first clock signal CLK transitions from high to low for the first time and the second clock signal XCLK transitions from low to high, the first stage shift register unit G1 stops outputting the low stage shift signal v_next1 and the gate driving signal Gout1, and the time is the termination time of the effective pulse of the low stage shift signal v_next1 and the gate driving signal Gout1 output by the first stage shift register unit G1. Thus, the width of the effective pulse of the lower shift signal v_next1 output by the first shift register unit G1 is an integer multiple of the clock period, and is influenced by the width T30 of the effective pulse of the start signal STV, the shift amount of the effective pulse of the lower shift signal v_next1 output by the first shift register unit G1 may be approximately equal to H, the width T21 of the effective pulse of the lower shift signal v_next1 output by the first shift register unit G1 is 2*H, and the width T11 of the effective pulse of the gate driving signal Gout1 output by the first shift register unit G1 is 2*H.

Since the upper shift signal received at the upper shift signal input terminal IN of the second stage shift register unit G2 is the lower shift signal v_next1 outputted from the first stage shift register unit G1, the first clock signal CLK transitions from high to low for the first time and the second clock signal XCLK transitions from low to high for the first time during the period when the lower shift signal v_next1 outputted from the first stage shift register unit G1 is an active pulse, and the second stage shift register unit G2 starts outputting the lower shift signal v_next2 and the gate driving signal Gout2 at high levels, that is, the start time of the active pulse of the lower shift signal v_next2 and the gate driving signal Gout2 outputted from the second stage shift register unit G2 is the start time of the active pulse of the lower shift signal v_next2 and the gate driving signal Gout2 outputted from the second stage shift register unit G2. After the termination time of the valid pulse of the lower shift signal v_next1 output by the first stage shift register unit G1, when the first clock signal CLK transitions from high level to low level for the first time and the second clock signal XCLK transitions from low level to high level, the second stage shift register unit G2 stops outputting the lower shift signal v_next2 and the gate driving signal Gout2 of high level, which is the termination time of the valid pulse of the lower shift signal v_next2 and the gate driving signal Gout2 output by the second stage shift register unit G2; in this way, the length between the start time and the end time of the effective pulse of the lower shift signal v_next2 output by the second shift register unit G2 is an integer multiple of the clock period, and is influenced by the width T21 of the effective pulse of the lower shift signal v_next1 output by the first shift register unit G1, so that the shift amount of the effective pulse of the lower shift signal v_next2 output by the second shift register unit G2 is H, the width T22 of the effective pulse of the lower shift signal v_next2 output by the second shift register unit G2 is 2*H, and the width T12 of the effective pulse of the gate driving signal Gout2 output by the second shift register unit G2 is 2*H, as compared with the effective pulse of the lower shift signal v_next1 output by the first shift register unit G1.

Based on the same principle as the gate driving signal Gout2 and the lower shift signal v_next2 outputted from the second stage shift register unit G2, the width T13 of the effective pulse of the gate driving signal Gout3 and the width T23 of the effective pulse of the lower shift signal v_next3 outputted from the third stage shift register unit G2 are both the same as the width T22 of the effective pulse of the lower shift signal v_next2 outputted from the second stage shift register unit G2, and the shift amount is H; the gate driving signal gout and the lower level shift signal v_next outputted to the other level shift register units G may be the same as the width of the effective pulse of the upper level shift signal v_next-1 received at the upper level shift signal input terminal, so that the level shift register units G can both output the gate driving signal gout and the lower level shift signal v_next having the width of the effective pulse equal to the width T30 of the effective pulse of the start signal STV.

It is understood that, for the case where the width of the effective pulse of the gate driving signal Gout outputted from each stage of the shift register unit is odd multiple of H, the case is similar to the case where the width of the effective pulse of the start signal STV is even multiple of H, as shown in fig. 7, only the odd multiple of H is needed, and the same points are described above, and the description thereof is omitted.

In an alternative embodiment, fig. 8 is a schematic diagram of a specific circuit structure of a shift register unit according to an embodiment of the present invention, and as shown in fig. 8, a D flip-flop DS may include a first latch 110 and a second latch 120; the input end of the first latch 110 is electrically connected with the upper level shift signal input end IN, the enabling end of the first latch 110 is electrically connected with the first clock signal end CK1, and the output end of the first latch 110 is electrically connected with the input end of the second latch 120; the enable terminal of the second latch 120 is electrically connected to the second clock signal terminal CK2, and the output terminal of the second latch 120 is electrically connected to the Next lower shift signal output terminal Next. At this time, the first latch 110 may latch the upper shift signal v_nexti-1 received by the upper shift signal input terminal IN response to the first clock signal CLK of the first clock signal terminal CK1 and provide a latch signal to the second latch 120; and the second latch 120 may latch the latch signal output from the first latch 110 in response to the second clock signal XCLK of the second clock signal terminal CK2 and supply the lower shift signal v_next to the lower shift signal output terminal Next.

Specifically, taking the output signal of the i-th stage shift register unit as 3 times of the refresh time H of a row of pixel circuits as an example, fig. 9 is a driving timing chart of a shift register unit corresponding to fig. 8, and referring to fig. 8 and 9 IN combination, the width of the effective pulse of the upper stage shift signal v_next-1 received by the upper stage shift signal input terminal IN is 3*H; before time T1, the upper level shift signal v_next-1 of the upper level shift signal input IN is at a low level, so that the upper level shift signal v_next-1 latched by the first latch 110 is at a low level, the latch signal v_lack output by the first latch 110 to the second latch 120 is also at a low level, and the lower level shift signal v_next provided by the second latch 120 to the lower level shift signal output Next is also at an inactive level.

IN a period between time T1 and time T2, the upper shift signal v_next-1 of the upper shift signal input terminal IN is at a high level, the first clock signal CLK is at a low level, and the first latch 110 latches the upper shift signal v_next-1 but is controlled by the low level of the first clock signal CLK such that the latch signal v_lach provided from the first latch 110 to the second latch 120 remains at a low level, and the lower shift signal v_next provided from the second latch 120 to the lower shift signal output terminal Next remains at a low level.

At time T2, the upper level shift signal v_next-1 of the upper level shift signal input terminal IN is still at a high level, the first clock signal CLK transitions from a low level to a high level, and the first latch 110 starts outputting the high level of the upper level shift signal v_next-1 latched by the first latch to the second latch 120; and IN a period from the time T2 to the time T4, the first latch 110 continuously supplies the latch signal v_lack of the high level to the second latch 120 because the upper level shift signal v_next-1 of the upper level shift signal input IN is continuously maintained at the high level.

In a period between the time T2 and the time T3, although the input terminal of the second latch 120 receives the latch signal v_lack to be at a high level, since the enable terminal of the second latch 120 receives the second clock signal XCLK to be at a low level, the second latch 120 can latch only the latch signal v_lack received thereto, and the lower shift signal v_next of a high level is not supplied to the lower shift signal output terminal Next, so that the lower shift signal v_next continues to be at a low level.

At time T3, the second clock signal XCLK received by the enable terminal of the second latch 120 transitions from low level to high level, so that the second latch 120 starts to control the latch signal v_lack output of the high level latched by the second latch, i.e., the second latch 120 starts to provide the lower shift signal v_next of high level to the lower shift signal output terminal Next, so that time T3 is the start time of the valid pulse of the lower shift signal v_next; and in a period from the time T3 to the time T4, the first latch 110 continuously provides the high-level latch signal v_lack to the second latch 120, so that the second latch 120 continuously provides the high-level lower-level shift signal v_next to the lower-level shift signal output terminal Next.

The upper shift signal v_next1 of the upper shift signal input terminal IN becomes low IN a period from the time T4 to the time T5, but the first latch 110 continues to supply the latch signal v_lack of the high level to the second latch 120 due to the first clock signal CLK being low IN the period, and the second latch 120 continues to supply the lower shift signal v_next of the high level to the lower shift signal output terminal Next.

At time T5, the upper shift signal v_nexti-1 of the upper shift signal input terminal IN is low, the first clock signal CLK transitions from low to high, and the first latch 110 starts outputting the latch signal v_lack of low to the second latch 120 IN response to the first clock signal CLK; and the first latch 110 continues to supply the latch signal v_lack of the low level to the second latch 120 for a period of time between the transition time of the next upper level shift signal v_next after the time T5.

At time T6, the latch signal v_lack is low, the second clock signal XCLK transitions from high to low, and the second latch 120 starts to supply the low lower-level shift signal v_next to the lower-level shift signal output Next in response to the second clock signal CLK, i.e., the time at which the lower-level shift signal v_next transitions from high to low.

In this way, by making the D flip-flop include two latches connected in series, and setting the clock period of the clock signal received by the two latches to be equal to the refresh time H of one row of pixel circuits, and the polarities of the clock periods of the clock signals received by the two latches at the same time are opposite, the lower shift signal output by the lower shift signal output terminal can be an integer multiple of the clock period of the clock signal.

It will be appreciated that the foregoing exemplary description is given by taking the example that the width of the effective pulse of the lower level shift signal is 3 times the refresh time H of one row of pixel circuits as an example, and the cases that the width of the effective pulse of the lower level shift signal is 1, 2, or 4 times the refresh time H of one row of pixel circuits are similar to the foregoing operation procedures, and will not be repeated here.

It should be noted that the structure of the first latch may be the same as or different from that of the second latch, and may be designed according to actual needs, which is not particularly limited in the embodiment of the present invention. In an exemplary embodiment, as shown in fig. 8, the first latch 110 may include a first inverter U11, a second inverter U12, a first tri-state gate U13, and a second tri-state gate U14; the input end of the first inverter U11 is electrically connected with the first clock signal end CK1, the input end of the first inverter U11 is also electrically connected with the negative signal control end of the first tri-state gate U13 and the positive signal control end of the second tri-state gate U14, and the output end of the first inverter U11 is electrically connected with the positive signal control end of the first tri-state gate U13 and the negative signal control end of the second tri-state gate U14; the input end of the first tri-state gate U13 is electrically connected with the input end IN of the upper level shift signal, and the output end of the first tri-state gate U13 is electrically connected with the input end of the second inverter U12; the output end of the second inverter U12 is electrically connected with the input end of the second tri-state gate U14, and the output end of the second tri-state gate U14 is electrically connected with the input end of the second inverter U12; the output terminal of the second inverter U12 is the output terminal of the first latch 110.

Accordingly, the second latch 120 may include a third inverter U21, a fourth inverter U22, a third tri-state gate U23, and a fourth tri-state gate U24; the input end of the third inverter U11 is electrically connected to the second clock signal end CK2, the input end of the third inverter U21 is also electrically connected to the negative signal control end of the third tri-state gate U23 and the positive signal control end of the fourth tri-state gate U24, and the output end of the third inverter U21 is electrically connected to the positive signal control end of the third tri-state gate U23 and the negative signal control end of the fourth tri-state gate U24, respectively; the input end of the third tri-state gate U23 is electrically connected with the output end of the first latch 110, and the output end of the third tri-state gate U23 is electrically connected with the input end of the fourth inverter U22; the output end of the fourth inverter U22 is electrically connected with the input end of the fourth three-state gate U24, and the output end of the fourth three-state gate U24 is electrically connected with the input end of the fourth inverter U22; the output terminal of the fourth inverter U22 is the output terminal of the second latch 120.

It will be appreciated that the above exemplary description is given of the clock signal having a clock period of H, and that in alternative embodiments the clock signal may have a clock period greater than H, for example, the clock signal may have a clock period of 2*H.

Optionally, fig. 10 is a schematic structural diagram of another shift register provided in the embodiment of the present invention, fig. 11 is a driving timing diagram of another shift register provided in the embodiment of the present invention, fig. 12 is a driving timing diagram of another shift register provided in the embodiment of the present invention, and referring to fig. 10 to fig. 12, a clock period T of the clock signal CLK may be 2*H, where the clock period T may include a first phase T01 and a second phase T02 each having a duration H; the clock signal CLK may include a first clock signal CLK1 and a second clock signal CLK2; in one clock period T, the time of the active pulse of the first clock signal CLK1 is in the first phase T1, and the time of the active pulse of the second clock signal CLK2 is in the second phase T2; at this time, in one clock period T, the duration between the start time of the active pulse of the first clock signal CLK1 and the start time of the active pulse of the second clock signal CLK2 may be H; at this time, the clock signal terminal CK of the odd-numbered stage shift register unit G (G1, G3 …) receives the first clock signal CLK1, and the clock signal terminal CK of the even-numbered stage shift register unit G (G2, G4 …) receives the second clock signal CLK2.

In this way, the latch module 10 of the odd-numbered stage shift register unit G (G1, G3 …) latches the upper stage shift signal v_next i-1 received by the latch module in response to the first clock signal CLK1 and controls the start time and the end time of the valid pulse of the lower stage shift signal v_next provided to the lower stage shift signal output terminal Next thereof; the latch module 10 of the even-numbered stage shift register unit G (G2, G2 …) may latch the upper-stage shift signal v_next i-1 received thereto in response to the second clock signal CLK2 and control the start timing and the end timing of the valid pulse of the lower-stage shift signal v_next provided to the lower-stage shift signal output terminal Next thereof.

IN an alternative embodiment, fig. 13 is a schematic diagram of a specific circuit structure of another shift register unit according to an embodiment of the present invention, where the latch module 10 may include a latch 101, an input terminal of the latch 101 is electrically connected to the upper level shift signal input terminal IN, an enable terminal of the latch 101 is electrically connected to the clock signal terminal CK, and an output terminal of the latch 101 is electrically connected to the lower level shift signal output terminal Next.

In an exemplary embodiment, the latch 101 may include two inverters U1 and U2 and two tri-state gates U3 and U4, and the connection manners of the inverters U1 and U2 and the tri-state gates U3 and U4 in the latch 101 may be similar to the connection manners of the inverters and the tri-state gates in the first latch and the second latch described above, and the same reference is made to the description above, and the details are not repeated here.

IN this manner, the latch 101 may respond to the clock signal CLK of the clock signal terminal CK IN a period IN which the upper shift signal v_next-1 at the upper shift signal input terminal IN is at a high level, so that the latch 101 starts outputting the lower shift signal v_next of the high level to the lower shift signal output terminal Next when the clock signal terminal CLK transitions to the high level; until the upper shift signal v_next-1 at the upper shift signal input terminal IN becomes low level and the clock signal CLK of the clock signal terminal CK jumps again to high level, the lower shift signal v_next outputted by the lower shift signal output terminal Next becomes low level, so that the effective pulse width of the lower shift signal v_next is an integer multiple of the clock period T of the clock signal CLK (the first clock signal CLK1 or the second clock signal CLK 2) received by the clock signal terminal CK, that is, when the clock period T of the clock signal CLK (the first clock signal CLK1 or the second clock signal CLK 2) is 2*H, the effective pulse width of the lower shift signal v_next may be only an even multiple of H.

On the basis of the above embodiment, IN order to make the gate driving signal Gout outputted from the driving signal output terminal OUT be an arbitrary integer multiple of H, referring to fig. 10 and 13, each shift register unit of the shift register 100 may be further provided with a logic module 40, an enable control terminal EN, and a lower shift signal input terminal IN'; the lower shift signal input terminal IN 'of the current shift register unit G is electrically connected to the lower shift signal output terminal Next of the Next shift register unit G, for example, the lower shift signal input terminal IN' of the first shift register unit G1 is electrically connected to the lower shift signal output terminal Next of the second shift register unit G2, the lower shift signal input terminal IN 'of the second shift register unit G2 is electrically connected to the lower shift signal output terminal Next of the third shift register unit G3, and so on, the lower shift signal input terminal IN' of the M-1 shift register unit G2 is electrically connected to the lower shift signal output terminal Next of the M-th shift register unit G3, and the lower shift signal input terminal IN 'of the M-th shift register unit G3 may receive the end signal STV'.

The logic module 40 is electrically connected between the level conversion module 20 and the Next level shift signal output terminal Next, and the logic module 40 is also electrically connected with the IN' level shift signal input terminal and the enable control terminal EN; the logic module 40 is configured to provide the level conversion control signal v_cl to the level conversion module 20 IN response to the lower level shift signal v_next output by the lower level shift signal output terminal Next, the lower level shift signal v_next+1 input by the lower level shift signal input terminal IN', and the enable control signal v_en of the enable control terminal EN; when N is an odd number, the enable control signal V_EN is an active level; when N is an even number, the enable control signal v_en is an inactive level; at this time, the level shift module 20 is specifically configured to control the voltage of the gate driving signal Gout and the width of the effective pulse supplied to the output module 30 in response to the level shift control signal v_cl; the width of the effective pulse of the upper level shift signal V_Nexti-1 is I.H, and the width of the effective pulse of the lower level shift signal V_Nexti is J.H; n-1 is less than or equal to I is less than or equal to N, N-1 is less than or equal to J is less than or equal to N, and I is more than or equal to J.

It is understood that when the width of the effective pulse of the upper level shift signal v_next I-1 is i×h, the width of the effective pulse of the lower level shift signal v_next I is j×h, and N-1 is n.ltoreq.i.ltoreq.n, N-1 is j.ltoreq.n, the width of the effective pulse of the upper level shift signal v_next I-1 may be the same as or different from the width of the effective pulse of the lower level shift signal v_next I, that is, when the width of the effective pulse of the upper level shift signal v_next I-1 is n×h, the width of the effective pulse of the lower level shift signal v_next I may be greater than or equal to (N-1) ×h and less than or equal to n×h, and when the enable control signal EN is an inactive level, N is an even number, that is the width of the effective pulse of the gate drive signal Gout is an even number of the time H of one row of the pixel circuits, and when the enable control signal is an odd number of the gate, that is an odd number of the effective pulse of the gate Gout.

In an alternative embodiment, with continued reference to fig. 13, logic module 40 may include a first nand gate 410 and a second nand gate 420; the first input terminal of the first nand gate 410 is electrically connected to the lower shift signal input terminal IN', the second input terminal of the first nand gate 410 is electrically connected to the enable control terminal EN, and the output terminal of the first nand gate EN is electrically connected to the first input terminal of the second nand gate 420; the second input terminal of the second nand gate 420 is electrically connected to the Next shift signal output terminal, and the output terminal of the second nand gate 420 is electrically connected to the level shift module 20.

Specifically, since the two input terminals of the first nand gate 410 are electrically connected to the lower shift signal input terminal IN' and the enable control terminal EN, respectively, when the lower shift signal v_next+1 and the enable control signal v_en are both at high level, the first nand gate 410 outputs a low-level signal to the first input terminal of the second nand gate, and when at least one of the lower shift signal v_next+1 and the clock control signal v_en is at low level, the first nand gate 410 outputs a high-level signal to the first input terminal of the second nand gate; similarly, since the two input terminals of the second nand gate 420 are electrically connected to the output terminal of the first nand gate 410 and the Next-level shift signal output terminal Next, respectively, when the signal output by the first nand gate 410 and the Next-level shift signal v_next of the Next-level shift signal output terminal Next are both at the high level, the second nand gate 420 outputs the high-level shift control signal v_cl to the level shift module 20, and when at least one of the signal output by the first nand gate 410 and the Next-level shift signal v_next of the Next-level shift signal output terminal Next is at the low level, the second nand gate 420 outputs the low-level shift control signal v_cl to the level shift module 20. At this time, the polarity of the active pulse of the level shift control signal v_cl provided by the logic module 40 to the level shift module 20 is opposite to the polarity of the lower level shift signal v_next, i.e., the active pulse of the level shift control signal v_cl is a low level signal.

In this way, if the enable control signal v_en of the enable control terminal EN is at a low level, the level shift control signal v_cl output by the second nand gate 420 is at a low level when the lower shift signal v_next of the lower shift signal output terminal Next is at a high level; when the lower-level shift signal v_next of the lower-level shift signal output terminal Next is at a low level, the level shift control signal v_cl output by the second nand gate 420 is at a high level, so that the duration of the level shift control signal v_cl provided to the level shift module 20 is the same as the width of the effective pulse of the lower-level shift signal v_next; at this time, the level conversion module 20 may perform level conversion on the low level conversion control signal v_cl received by the level conversion module and provide the level conversion control signal v_cl to the output module 30; the output module 30 performs polarity adjustment on the received signal and outputs a gate driving signal Gout having an effective pulse width identical to the effective pulse width of the next level shift signal v_next.

If the enable control signal v_en of the enable control terminal EN is at a high level, the level shift control signal v_cl output by the second nand gate 420 is at a low level when at least one of the lower shift signal v_next of the lower shift signal output terminal Next and the lower shift signal v_next+1 of the lower shift signal input terminal IN' is at a high level; when the lower shift signal v_next of the lower shift signal output terminal Next and the lower shift signal v_next+1 of the lower shift signal input terminal IN' are both at low level, the level shift control signal v_cl output by the second nand gate 420 is at high level; so that the duration of the level conversion control signal v_cl supplied to the level conversion module 20 is low may be equal to a period between the start time of the effective pulse of the lower level shift signal v_next and the end time of the effective pulse of the lower level shift signal v_next+1, and is supplied to the output module 30 after the level conversion module 20 level-converts the level conversion control signal v_cl of the low level received thereto, and the gate driving signal Gout having an effective pulse width greater than the width of the effective pulse of the lower level shift signal v_next may be outputted after the polarity adjustment of the signal received thereto by the output module 30.

It can be understood that the start time of the valid pulse of the lower-stage shift signal v_next i is located before the start time of the valid pulse of the lower-stage shift signal v_next i+1, and the end time of the valid pulse of the lower-stage shift signal v_next i is located after the end time of the valid pulse of the lower-stage shift signal v_next i, so that when the duration of the level shift control signal v_cl being low is equal to the period of time between the start time of the valid pulse of the lower-stage shift signal v_next i to the end time of the valid pulse of the lower-stage shift signal v_next i+1, the start time of the valid pulse of the gate drive signal Gout output by the drive signal output terminal OUT and the start time of the valid pulse of the lower-stage shift signal v_next output terminal Next are the same time in the same shift register unit G; the termination time of the effective pulse of the gate driving signal Gout outputted from the driving signal output terminal OUT is the same time as the termination time of the effective pulse of the lower shift signal v_next+1 inputted from the lower shift signal input terminal IN'.

IN an exemplary embodiment, fig. 14 is a driving timing diagram of a shift register unit corresponding to fig. 13, referring to fig. 14 and 13 IN combination, when the gate driving signal gout with the effective pulse width 2*H needs to be outputted, the enable control signal v_en of the enable control terminal EN is continuously low, the effective pulse width of the upper shift signal v_next i-1 inputted by the upper shift signal input terminal IN may be 2*H, and the start time of the effective pulse of the upper shift signal v_next-1 overlaps with the time of the ineffective pulse of the clock signal CLK received by the clock signal terminal CK.

Before time T1', the upper level shift signal v_next i-1 is low, so that the lower level shift signal v_next provided to the lower level shift signal output terminal Next by the latch 101 is continuously low. At this time, since one of the input terminals of the second nand gate 420 of the logic module 40 receives the lower level shift signal v_next which is continuously low, the level shift control signal v_cl output from the second nand gate 420 to the level shift module 20 is kept at a high level, and the gate driving signal Gout provided from the level shift module 20 to the output module 30 by the level shift control signal v_cl controlled by the high level is kept at an inactive level, and the gate driving signal Gout at the inactive level is still kept at the inactive level after the polarity of the gate driving signal Gout is shifted by the output module 30.

At time T1', the upper level shift signal v_next i-1 transitions from low level to high level, but therefore the clock signal CLK of the clock signal terminal CK is low level, so that the latch 101 latches only the upper level shift signal v_next i-1 of the high level and continues to provide the lower level shift signal v_next of the low level to the lower level shift signal output terminal Next; at this time, the lower shift signal v_next received by one of the input terminals of the second nand gate 420 of the logic module 40 is still at a low level, so that the level shift control signal v_cl output from the second nand gate 420 to the level shift module 20 is still at a high level, and further, the gate driving signal Gout provided by the level shift module 20 to the output module 30 is at an inactive level, and the gate driving signal Gout at the inactive level is still at an inactive level after the polarity of the gate driving signal Gout is converted by the output module 30.

At time T2', the upper level shift signal v_next i-1 remains at a high level, and the clock signal CLK transitions from a low level to a high level, so that the latch 101 starts outputting the lower level shift signal v_next i at a high level; the second input terminal of the second nand gate 420 of the logic module 40 starts to receive the low-level lower-level shift signal v_next; meanwhile, since the enable control signal v_en of the enable control terminal EN is continuously low, one of the input terminals of the first nand gate 410 receives a low level signal, and at this time, no matter the level of the lower level shift signal v_next+1 input by the lower level shift signal input terminal IN', the first nand gate 410 keeps outputting a high level signal to the first input terminal of the second nand gate 420, so that the second input terminal of the second nand gate 420 receives the high level lower level shift signal v_next, the second nand gate 420 provides a low level shift control signal v_cl to the level shift module 20, so that the level shift module 20 is controlled by the low level shift control signal v_cl to provide the gate driving signal Gout to the output module 30, and the valid level gate driving signal Gout is still kept at a valid level after being subjected to polarity shift by the output module 30; in this way, at time T2', supply of the active level of the gate drive signal gout to the gates of the switching transistors of the one row of pixel circuits is started.

At time T3', the upper level shift signal v_next-1 transitions to a low level, but the clock signal remains low, so that the lower level shift signal v_next outputted by the latch 101 remains high; accordingly, the second nand gate 420 continues to provide the low level shift control signal v_cl to the level shift module 20, so that the gate driving signal gout provided by the level shift module 20 to the output module 30 is still at the active level, and the active level of the gate driving signal gout is still at the active level after the polarity of the active level driving signal gout is shifted by the output module 30.

At time T4', the upper level shift signal v_next i-1 is low level, and the clock signal CLK transitions from low level to high level, so that the latch 101 starts to provide the lower level shift signal v_next to the lower level shift signal output Next in response to the clock signal CLK, the time being the termination time of the valid pulse of the lower level shift signal v_next, and the duration from the termination time T2' of the valid pulse of the lower level shift signal v_next to the termination time T4' of the valid pulse thereof being one clock period T of the clock signal, i.e. the width of the valid pulse of the lower level shift signal v_next is 2*H; meanwhile, since the lower shift signal v_next received by the second input terminal of the second nand gate 420 starts to become low level, the second nand gate 420 starts to provide the level shift control signal v_cl of high level to the level shift module 20, so that the gate driving signal gout provided by the level shift module 20 to the output module 30 becomes inactive level, and the inactive level of the gate driving signal gout is still kept at inactive level after the polarity conversion of the gate driving signal gout by the output module 30.

After time T4', the lower shift signal v_next and the gate driving signal gout remain at the inactive level until the next driving period. The next level shift signal v_next is the same as the effective pulse width of the gate driving signal Gouti in this way, so that the shift register unit G can output an effective pulse width of 2*H.

IN another exemplary embodiment, fig. 15 is a driving timing diagram of another shift register unit corresponding to fig. 13, referring to fig. 15 and 13 IN combination, when it is required to output a gate driving signal gout having a valid pulse width of 3*H, an enable control signal v_en of an enable control terminal EN is continuously high, a valid pulse width of a higher shift signal v_nexti-1 input from a higher shift signal input terminal IN may be 3*H, and a start time of the valid pulse of the higher shift signal v_nexti-1 overlaps with a time of the invalid pulse of the clock signal CLK received by the clock signal terminal CK, and a termination time of the valid pulse of the higher shift signal v_nexti-1 overlaps with a time of the valid pulse of the clock signal CLK received by the clock signal terminal CK.

At time T2', the upper level shift signal v_next i-1 remains at a high level, and the clock signal CLK transitions from a low level to a high level, so that the latch 101 starts outputting the lower level shift signal v_next i at a high level; the second input terminal of the second nand gate 420 of the logic module 40 starts to receive the low-level lower-level shift signal v_next; meanwhile, the enable control signal v_en of the enable control terminal EN is continuously high, so that the signal received by the second input terminal of the first nand gate 410 is high, at this time, the lower level shift signal v_next+1 input by the lower level shift signal input terminal IN' is low, the first nand gate 410 outputs a high level signal to the first input terminal of the second nand gate 420, the first input terminal of the second nand gate 420 is high, the second input terminal is also high, the second nand gate 420 outputs a low level shift control signal v_cl to the level shift module 20, so that the level shift module 20 is controlled by the low level shift control signal v_cl to provide the gate driving signal Gout to the output module 30, and the gate driving signal Gout of the effective level is still kept at the effective level after being subjected to polarity shift by the output module 30; in this way, at time T2', supply of the active level of the gate drive signal gout to the gates of the switching transistors of the one row of pixel circuits is started.

At time T3', the upper level shift signal v_next i-1 is still at a high level, so that the lower level shift signal v_next i output by the latch 101 will continue to be kept at a high level; meanwhile, the lower level shift signal v_next+1 transitions from low level to high level, and the first input terminal of the first nand gate 410 starts to receive the lower level shift signal v_next+1 at high level, so that the first nand gate 410 outputs a low level signal to the first input terminal of the second nand gate 420, and the second nand gate 420 provides a high level shift control signal v_cl to the level shift module 20; at this time, since the high level shift control signal v_cl is an inactive level, the level shift module 20 may combine other signals (e.g., clock signal, control signal, etc.) to continue the active level of the gate driving signal gout provided to the output module 30, and the active level of the gate driving signal gout is maintained at the active level after the polarity of the gate driving signal gout is shifted by the output module 30.

At time T4', the upper level shift signal v_next i-1 transitions to a low level and the clock signal CLK is high level, so that the latch 101 also starts to provide the lower level shift signal v_next to the lower level shift signal output Next in response to the clock signal CLK, the time being the termination time of the valid pulse of the lower level shift signal v_next, and the duration from the termination time T2' of the valid pulse of the lower level shift signal v_next to the termination time T4' of the valid pulse thereof being greater than one clock period T of the clock signal, i.e. the width of the valid pulse of the lower level shift signal v_next being greater than 2*H; meanwhile, the lower shift signal v_next received by the second input terminal of the second nand gate 420 starts to be changed to a low level, so that the second nand gate 420 continues to provide the high level shift control signal v_cl to the level shift module 20, at this time, the level shift module 20 may combine other signals (such as a clock signal, a control signal, etc.) with the high level shift control signal v_cl, and the active level of the gate driving signal gout provided to the output module 30 is still maintained after the polarity of the gate driving signal gout is converted by the output module 30.

At time T5', the lower level shift signal v_next+1 transitions from high level to low level, the first input terminal of the first nand gate 410 starts to receive the low level signal, so that the first nand gate 410 outputs the high level signal to the first input terminal of the second nand gate 420, and the second nand gate 420 continues to provide the high level shift control signal v_c to the level shift module 20 because the lower level shift signal v_next received by the first input terminal of the second nand gate 420 is still low level; at this time, since the high level conversion control signal v_cl is an inactive level, the level conversion module 20 may combine other signals (for example, a clock signal, a control signal, etc.), and stop the active level of the gate driving signal gout provided to the output module 30, so that the output module 30 receives the inactive circuit of the gate driving signal gout, and the inactive level of the gate driving signal gout is still kept at the inactive level after the polarity conversion of the output module 30, that is, the time T5' is the termination time of the active pulse of the gate driving signal gout.

In this way, the width of the effective pulse of the gate driving signal gout is a duration from the start time of the lower level shift signal v_next to the end time of the lower level shift signal v_next+1, that is, the width of the effective pulse of the gate driving signal gout is 3*H.

It will be appreciated that the foregoing exemplary cases where the effective pulse width of the gate driving signal gout is 2*H and 3*H are illustrated, respectively, and that the other cases where the gate driving signal gout is other are similar to the foregoing cases, and the same points are referred to in the foregoing description.

Based on the same inventive concept, the embodiment of the present invention further provides a silicon-based display panel, which includes the shift register provided by any embodiment of the present invention, so that the silicon-based display panel provided by the embodiment of the present invention includes the technical features of the shift register provided by any embodiment of the present invention, and can achieve the beneficial effects of the shift register provided by any embodiment of the present invention, and the same points can be referred to the above description of the shift register provided by any embodiment of the present invention, and are not repeated herein.

In an alternative embodiment, fig. 16 is a schematic structural diagram of a silicon-based display panel according to an embodiment of the present invention, and referring to fig. 1 and 16, a silicon-based display panel 001 includes a plurality of pixel circuits P, a plurality of gate signal lines S11 and S12, a start signal line S20, and a shift register 100 arranged in an array; the pixel circuit P includes a switching transistor M1; the gate of the switching transistor M1 of the pixel circuit P located in the same row is electrically connected to the same gate signal line S11; IN the shift register 100, a superior shift signal input terminal IN of a first-stage shift register unit is electrically connected to a start signal line S20; the driving signal output ends of the shifting register units are respectively and electrically connected with the gate signal lines S11, and the shifting register units sequentially shift the gate driving signals provided by the gate signal lines S11, so that the switching transistors M1 of the pixel circuits P can control the light emitting elements D0 to sequentially emit light.

Meanwhile, the pixel circuit P may further include a data writing module P2, the data writing module P2 may include a data writing transistor M2, and a gate of the data writing transistor P2 of the pixel circuit P located in the same row may be electrically connected to the same gate signal line S12; accordingly, the silicon-based display panel 001 may further include a shift register 200, and each stage of shift register unit of the shift register 200 can sequentially supply an effective pulse of a driving signal for controlling the data writing transistor M2 to be turned on to each gate signal line S12, so that the data writing transistor M2 of each row of pixel circuits P can be turned on in a time-sharing manner.

In addition, the silicon-based display panel 001 may further include a plurality of data signal lines S40 and clock signal lines S30, the clock signal lines S30 being capable of transmitting clock signals to each stage of shift register units; the data signal lines S40 may transmit data signals, and each pixel circuit P located in the same column may be electrically connected to the same data signal line S40, so that the data signal lines S40 may transmit data signals of each pixel circuit P located in the same column in a time-sharing manner, so that the data signals of each pixel circuit P may be written into their respective driving modules P1 in a one-to-one correspondence manner, and thus, when the switching transistor M1 is turned on, the driving modules P1 of each pixel circuit P may accurately provide a driving current to their respective light emitting elements D0, so that the light emitting elements D0 may accurately emit light.

Based on the same inventive concept, the embodiment of the present invention further provides a display device, where the display device includes the silicon-based display panel provided by any embodiment of the present invention, so that the display device provided by the embodiment of the present invention includes the technical features of the silicon-based display panel provided by any embodiment of the present invention, so that the beneficial effects of the silicon-based display panel provided by any embodiment of the present invention can be achieved, and the same points can be referred to the above description of the silicon-based display panel provided by any embodiment of the present invention, and are not repeated herein.

Alternatively, fig. 17 is a schematic structural diagram of a display device according to an embodiment of the present invention, and as shown in fig. 17, the display device may be a near-eye display device 002. The near-eye display device 002 may be VR or AR-based smart glasses, capable of creating virtual images in single-eye or double-eye fields of view, and rendering light field information to human eyes through a silicon-based display panel placed in a non-apparent viewing distance of human eyes, so as to create virtual scenes in front of the human eyes.

It should be appreciated that various forms of the flows shown above may be used to reorder, add, or delete steps. For example, the steps described in the present invention may be performed in parallel, sequentially, or in a different order, so long as the desired results of the technical solution of the present invention are achieved, and the present invention is not limited herein.

The above embodiments do not limit the scope of the present invention. It will be apparent to those skilled in the art that various modifications, combinations, sub-combinations and alternatives are possible, depending on design requirements and other factors. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present invention should be included in the scope of the present invention.

Claims

1. The shift register is applied to a silicon-based display panel, and is characterized in that the silicon-based display panel comprises a plurality of pixel circuits which are arranged in an array; the pixel circuit includes a switching transistor, and the shift register includes: a plurality of shift register units in cascade;

2. The shift register of claim 1, wherein the clock signal input comprises a first clock signal terminal that receives a first clock signal and a second clock signal terminal that receives a second clock signal;

the clock signals comprise the first clock signal and the second clock signal with the clock period of H; at the same time, the first clock signal and the second clock signal are opposite in polarity.

3. The shift register of claim 2, wherein the latch module comprises a D flip-flop; the input end of the D trigger is electrically connected with the upper level shift signal input end, the control end of the D trigger is electrically connected with the first clock signal end, the reset end of the D trigger is electrically connected with the second clock signal end, and the output end of the D trigger is electrically connected with the lower level shift signal output end;

wherein the width of the effective pulse of the upper level shift signal and the width of the effective pulse of the lower level shift signal are the same as the width of the effective pulse of the gate driving signal.

4. A shift register as claimed in claim 3, in which the D flip-flop comprises a first latch and a second latch;

the input end of the first latch is electrically connected with the upper level shift signal input end, the enabling end of the first latch is electrically connected with the first clock signal end, and the output end of the first latch is electrically connected with the input end of the second latch;

the enabling end of the second latch is electrically connected with the second clock signal end, and the output end of the second latch is electrically connected with the lower-stage shift signal output end.

5. The shift register of claim 1, wherein the clock signal has a clock period of 2*H, the clock period comprising a first phase and a second phase each having a duration of H;

the clock signal comprises a first clock signal and a second clock signal; in one of the clock cycles, the time of the active pulse of the first clock signal is in the first phase, and the time of the active pulse of the second clock signal is in the second phase;

the clock signal ends of the shift register units at odd-numbered stages receive the first clock signal, and the clock signal ends of the shift register units at even-numbered stages receive the second clock signal.

6. The shift register of claim 5, wherein each of said shift register cells further comprises a logic module, an enable control terminal and a lower shift signal input terminal; the lower-stage shift signal input end is electrically connected with the lower-stage shift signal output end of the shift register unit of the next stage;

the logic module is electrically connected between the level conversion module and the lower level shift signal output end, and is also electrically connected with the lower level shift signal input end and the enabling control end; the logic module is used for responding to the lower-stage shift signal output by the lower-stage shift signal output end, the lower-stage shift signal input by the lower-stage shift signal input end and the enabling control signal of the enabling control end, and providing a level conversion control signal for the level conversion module; when N is an odd number, the enabling control signal is an active level; when N is even, the enable control signal is at an invalid level;

The level conversion module is specifically configured to control a voltage of a gate driving signal and a width of an effective pulse provided to the output module in response to the level conversion control signal;

the width of the effective pulse of the upper level shift signal is I.H, and the width of the effective pulse of the lower level shift signal is J.H; n-1 is less than or equal to I is less than or equal to N, N-1 is less than or equal to J is less than or equal to N, and I is more than or equal to J.

7. The shift register according to claim 6, wherein when N is an odd number, in the same shift register unit, a start timing of an effective pulse of the gate driving signal output by the driving signal output terminal and a start timing of an effective pulse of the lower shift signal output by the lower shift signal output terminal are the same timing; and the termination time of the effective pulse of the grid driving signal output by the driving signal output end is the same as the termination time of the effective pulse of the lower-stage shifting signal input by the lower-stage shifting signal input end.

8. The shift register of claim 6, wherein the logic module comprises a first nand gate and a second nand gate;

the first input end of the first NAND gate is electrically connected with the lower level shift signal input end, the second input end of the first NAND gate is electrically connected with the enabling control end, and the output end of the first NAND gate is electrically connected with the first input end of the second NAND gate;

The second input end of the second NAND gate is electrically connected with the lower level shift signal output end, and the output end of the second NAND gate is electrically connected with the level conversion module.

9. The shift register of claim 6, wherein the latch module comprises a latch;

the input end of the latch is electrically connected with the upper level shift signal input end, the enabling end of the latch is electrically connected with the clock signal end, and the output end of the latch is electrically connected with the lower level shift signal output end.

10. The shift register of claim 1, wherein the level shift module comprises a level shifter;

the input end of the level shifter is coupled with the lower level shift signal output end; the output end of the level shifter is electrically connected with the output module.

11. The shift register of claim 1, wherein the output module comprises at least one buffer connected in series between the drive signal output and the level shift module.

12. A silicon-based display panel, comprising: a plurality of pixel circuits, a plurality of gate signal lines, a start signal line, and the shift register according to any one of claims 1 to 11 arranged in an array;

13. A display device, comprising: a silicon-based display panel as defined in claim 12.