CN115798555A - Shift register, grid driving circuit, display panel and driving method - Google Patents

Abstract

The application provides a shift register, a grid driving circuit, a display panel and a driving method. The shift register includes: the device comprises a first input module, a second input module, a bootstrap module and an output module; the first input module is electrically connected with the first clock signal end, the control signal end and the first node respectively; the second input module is respectively and electrically connected with the control signal end, the first power supply signal end, the second clock signal end and the second node; the output module is respectively and electrically connected with the first node, the second node, the bootstrap module, the first power supply signal end, the second power supply signal end and the output end; the bootstrap module comprises a switch unit and a bootstrap unit, wherein a control end, a first end and a second end of the switch unit are respectively and electrically connected with the output module, the second clock signal end and the first end of the bootstrap unit, and the second end of the bootstrap unit is electrically connected with the output module. The technical scheme of this application can improve output signal's stability.

Description

Shift register, grid driving circuit, display panel and driving method

Technical Field

The present disclosure relates to display technologies, and in particular, to a shift register, a gate driving circuit, a display panel and a driving method.

Background

In the related art, the drive requirement of an LTPO (Low Temperature Polycrystalline Oxide) pixel circuit on a shift register (GOA) is high, the output stability of a conventional shift register is poor, and the LTPO pixel circuit is easy to fluctuate along with the fluctuation of a clock signal, and cannot meet the drive requirement of the LTPO pixel circuit on the shift register.

Disclosure of Invention

The embodiment of the application provides a shift register, a grid driving circuit, a display panel and a driving method, which are used for solving the problems in the related art, and the technical scheme is as follows:

in a first aspect, an embodiment of the present application provides a shift register, including: the device comprises a first input module, a second input module, a bootstrap module and an output module;

the first input module is respectively and electrically connected with the first clock signal end, the control signal end and the first node, and the first input module is used for controlling the connection and disconnection between the control signal end and the first node based on a clock signal provided by the first clock signal end;

the second input module is respectively electrically connected with the control signal end, the first power signal end, the second clock signal end and the second node, and is used for controlling the connection and disconnection between the first power signal end and the second node and controlling the connection and disconnection between the second power signal end and the second node based on signals provided by the control signal end and the second clock signal end;

the output module is respectively and electrically connected with the first node, the second node, the bootstrap module, the first power supply signal end, the second power supply signal end and the output end, and is used for controlling the connection and disconnection between the first power supply signal end and the output end and controlling the connection and disconnection between the second power supply signal end and the output end based on the electric potential of the first node, the electric potential of the second node and the regulation of the bootstrap module;

the bootstrap module comprises a switch unit and a bootstrap unit, wherein a control end, a first end and a second end of the switch unit are respectively and electrically connected with an output module, a second clock signal end and a first end of the bootstrap unit, a second end of the bootstrap unit is electrically connected with the output module, the switch unit is used for controlling the on-off between the second clock signal end and the bootstrap unit based on the electric potential of the output module, and the bootstrap unit is used for bootstrapping the electric potential of the output module.

In a second aspect, an embodiment of the present application provides a gate driving circuit, including: each stage of the cascaded multi-stage shift register is the shift register provided by the first aspect of the embodiment of the application;

the control signal end of the first stage shift register is electrically connected with the frame starting signal end;

for the adjacent two stages of shift registers, the output end of the previous stage of shift register is electrically connected with the control signal end of the next stage of shift register.

In a third aspect, an embodiment of the present application provides a display panel, including: a pixel circuit and a gate driving circuit provided by a second aspect of an embodiment of the present application;

the grid driving circuit is electrically connected with the pixel circuit and is used for providing a grid driving signal for the pixel circuit.

In a fourth aspect, an embodiment of the present application provides a driving method, which is applied to the shift register provided in the first aspect of the embodiment of the present application, and the method includes:

in the first stage, a control signal end provides a first potential signal, a first input module controls the connection or disconnection between the control signal end and a first node based on a clock signal provided by a first clock signal end, a switch unit controls the connection between a second clock signal end and a bootstrap unit based on the first potential of an output module, the bootstrap unit performs bootstrap on the first potential of the output module, and the output module controls the connection between a first power supply signal end and an output end based on the potential of the first node, the potential of a second node and the bootstrap action of the bootstrap unit;

in the second stage, the second input module controls the second power supply signal terminal and the second node to be disconnected based on a second potential signal provided by the control signal terminal, the second input module controls the first power supply signal terminal and the second node to be connected or disconnected based on a clock signal provided by the second clock signal terminal, and the output module controls the second power supply signal terminal and the output terminal to be connected based on the potential of the second node.

The advantages or benefits in the above technical solution at least include:

the bootstrap module in shift register includes switch unit and bootstrap unit, the switch unit is connected between second clock signal end and bootstrap unit, can transmit the bootstrap unit with the clock signal that second clock signal end provided, can completely cut off the direct signal transmission between second clock signal end and the bootstrap unit, and then can reduce the influence of the signal fluctuation of second clock signal end to the bootstrap unit, when bootstrapping to the electric potential of output module through the bootstrap unit, can reduce the influence of the signal fluctuation of second clock signal end to output module, thereby make the output signal of the output that output module and output module connect more stable.

The foregoing summary is provided for the purpose of description only and is not intended to be limiting in any way. In addition to the illustrative aspects, embodiments, and features described above, further aspects, embodiments, and features of the present application will be readily apparent by reference to the drawings and the following detailed description.

Drawings

In the drawings, like reference numerals refer to the same or similar parts or elements throughout the several views unless otherwise specified. The figures are not necessarily to scale. It is appreciated that these drawings depict only some embodiments in accordance with the disclosure and are not to be considered limiting of its scope.

FIG. 1 is a schematic diagram of a LTPO pixel circuit according to the related art;

fig. 2 is a schematic structural framework diagram of a shift register according to an embodiment of the present disclosure;

fig. 3 is a schematic circuit diagram of a shift register according to an embodiment of the present disclosure;

fig. 4 is a schematic flowchart of a driving method according to an embodiment of the present disclosure;

FIG. 5 is a schematic diagram showing signal timing sequences of signal terminals and nodes of the shift register shown in FIG. 3;

fig. 6 is a schematic structural frame diagram of a gate driving circuit according to an embodiment of the present disclosure;

FIG. 7 is a schematic diagram of a simulation of the step-by-step output of cascaded shift registers;

FIG. 8 is another simulation diagram of the stage-by-stage outputs of cascaded shift registers;

fig. 9 is a schematic diagram of another simulation of the cascade output of the cascaded shift registers.

Detailed Description

In the following, only certain exemplary embodiments are briefly described. As those skilled in the art would realize, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the present application. Accordingly, the drawings and description are to be regarded as illustrative in nature, and not as restrictive.

First, the related art to which the present application relates is described as follows:

a circuit structure of an LTPO pixel circuit in the related art is shown in fig. 1, and includes transistors M1 to M7, a capacitor Cst, a capacitor C _ Data, and a light emitting device EL, where the input signals include: driving signals (N-Scan, P-Scan), data signals Data, light emitting signals EM, high level signals ELVDD, low level signals ELVSS, and initialization signals (Vinit 1 and Vinit 2), and the transistors M1, M2, M5, and M6 require a shift register for signal stabilization to drive.

The following describes the technical solutions of the present application and how to solve the above technical problems in detail with specific embodiments.

An embodiment of the present application provides a shift register, as shown in fig. 2, including: a first input module 100, a second input module 200, an output module 300 and a bootstrap module 400.

The first input module 100 is electrically connected to the first clock signal terminal CK1, the control signal terminal STV, and the first node N1, respectively. The first input module 100 is configured to control on/off between the control signal terminal STV and the first node N1 based on a clock signal provided by the first clock signal terminal CK1, for example, when the clock signal provided by the first clock signal terminal CK1 is at a first potential, the first input module 100 may enable the control signal terminal STV and the first node N1 to be on, transmit a signal provided by the control signal terminal STV to the first node N1, and when the clock signal provided by the first clock signal terminal CK1 is at a second potential, the first input module 100 may enable the control signal terminal STV and the first node N1 to be off.

The second input module 200 is electrically connected to the control signal terminal STV, the first power signal terminal VGL, the second power signal terminal VGH, the second clock signal terminal CK2, and the second node N2, respectively. The second input module 200 is configured to control on/off between the first power signal terminal VGL and the second node N2 and control on/off between the second power signal terminal VGH and the second node N2 based on signals provided by the control signal terminal STV and the second clock signal terminal CK 2. For example, when the signal provided by the second clock signal terminal CK2 is at the first potential, the second input module 200 may control the first power signal terminal VGL and the second node N2 to be turned on, when the signal provided by the second clock signal terminal CK2 is at the second potential, the second input module 200 may control the first power signal terminal VGL and the second node N2 to be turned off, when the signal provided by the control signal terminal STV is at the first potential, the second input module 200 may control the second power signal terminal VGH and the second node N2 to be turned on, and when the signal provided by the control signal terminal STV is at the second potential, the second input module 200 may control the second power signal terminal VGH and the second node N2 to be turned off.

The output module 300 is electrically connected to the first node N1, the second node N2, the bootstrap module 400, the first power signal terminal VGL, the second power signal terminal VGH, and the output terminal OUT, respectively. The output module 300 is configured to control on/off between the first power signal terminal VGL and the output terminal OUT based on the potential of the first node N1, the potential of the second node N2, and the regulation of the bootstrap module, and control on/off between the second power signal terminal VGH and the output terminal, when the first power signal terminal VGL and the output terminal OUT are turned on, the output terminal OUT may output a signal provided by the first power signal terminal VGL, when the first power signal terminal VGL and the output terminal OUT are turned off, the output terminal OUT may not output a signal provided by the first power signal terminal VGL, when the second power signal terminal VGH and the output terminal OUT are turned on, the output terminal OUT may output a signal provided by the second power signal terminal VGH, and when the second power signal terminal VGH and the output terminal OUT are turned off, the output terminal OUT may not output a signal provided by the second power signal terminal VGH.

The bootstrap module 400 includes a switch unit and a bootstrap unit, a control electrode, a first electrode, and a second electrode of the switch unit are electrically connected to the output module 300, the second clock signal terminal CK2, and a first end of the bootstrap unit, respectively, and a second end of the bootstrap unit is electrically connected to the output module 300. The switch unit is configured to control on/off between the second clock signal terminal CK2 and the bootstrap unit based on the potential of the output module 300, and the bootstrap unit is configured to bootstrap the potential of the output module 300.

In the above-mentioned shift register that this application embodiment provided, the bootstrap module includes switch unit and bootstrap unit, the switch unit is connected between second clock signal end CK2 and the bootstrap unit, can transmit the clock signal that second clock signal end CK2 provided the bootstrap unit, can completely cut off the direct signal transmission between second clock signal end CK2 and the bootstrap unit, and then can reduce the influence of the signal fluctuation of second clock signal end CK2 to the bootstrap unit, when bootstrapping to the electric potential of output module 300 through the bootstrap unit, can reduce the influence of the signal fluctuation of second clock signal end CK2 to output module 300, thereby make the output signal of the output module of output module and output module connection more stable.

In an alternative embodiment, referring to the example of fig. 3, the output module 300 may include a first output unit 301 and a second output unit 302.

The first output unit 301 may be electrically connected to the first node N1, the first power signal terminal VGL, and the output terminal, respectively. The first output unit 301 may be configured to control on/off between the first power signal terminal VGL and the output terminal OUT based on a potential of the first node N1 and a bootstrap of the bootstrap unit, for example, based on the potential of the first node N1 and the bootstrap of the bootstrap unit, when a potential of an output control node in the first output unit 301 is a first potential, the first output unit 301 may control conduction between the first power signal terminal VGL and the output terminal OUT, so that the output terminal OUT may output a signal provided by the first power signal terminal VGL, and when the potential of the output control node in the first output unit 301 is a second potential, the first output unit 301 may control disconnection between the first power signal terminal VGL and the output terminal OUT, so that the output terminal OUT cannot output the signal provided by the first power signal terminal VGL.

The second output unit 302 may be electrically connected to the second node N2, the second power signal terminal VGH, and the output terminal, respectively. The second output unit 302 is configured to control on/off between the second power signal terminal VGH and the output terminal OUT based on the potential of the second node N2, for example, when the potential of the second node N2 is the first potential, the second output unit 302 may control on/off between the second power signal terminal VGH and the output terminal OUT, so that the output terminal OUT may output a signal provided by the second power signal terminal VGL, and when the potential of the second node N2 is the second potential, the second output unit 302 may control off between the second power signal terminal VGH and the output terminal OUT, so that the output terminal OUT may not output the signal provided by the second power signal terminal VGH.

The first input module 100 and the first output unit 301 may form a first output path for outputting a signal provided by the first power signal terminal VGL, the second input module 200 and the second output unit may form a second output path for outputting a signal provided by the second power signal terminal VGH, the signal provided by the first power signal terminal VGL may be a signal at a first potential, the signal provided by the second power signal terminal VGH may be a signal at a second potential, and the first output path and the second output path may cooperate to realize different signal outputs at different stages.

In an alternative embodiment, referring to the example of fig. 3, the first output unit 301 may include a first transistor T1 and a second transistor T2, a control electrode, a first electrode, and a second electrode of the first transistor T1 may be electrically connected to the first power signal terminal VGL, the first node N1, and the third node N3, respectively, and a control electrode, a first electrode, and a second electrode of the second transistor T2 may be electrically connected to the third node N3, the first power signal terminal VGL, and the output terminal OUT, respectively. The output control node may be the third node N3.

In one example, the first transistor T1 may be turned on under the control of a first potential signal provided by the first power signal terminal VGL, and transmit the potential signal of the first node N1 to the third node N3, and the potential of the third node N3 may control the on/off of the second transistor T2, for example, when the potential of the third node N3 is a first potential, the second transistor T2 may be turned on, and thus the first power signal terminal VGL is turned on with the output terminal OUT, and when the potential of the third node N3 is a second potential, the second transistor T2 may be turned off, and thus the first power signal terminal VGL is turned off with the output terminal OUT.

Set up first transistor T1 between first node N1 and third node N3, can completely cut off the direct signal transmission between two nodes, and then can completely cut off the influence of the signal fluctuation of first clock signal end CK1 to third node N3, keep the stability of third node N3 department turn-on voltage, under the control of the turn-on voltage of third node N3, can keep the stability of second transistor T2, the output that finally can be connected with second transistor T2 is more stable.

In another embodiment, the first output unit 301 may include a second transistor T2, and a control electrode, a first electrode, and a second electrode of the second transistor T2 may be electrically connected to the first node N1, the first power signal terminal VGL, and the output terminal OUT, respectively. The second transistor T2 may be turned on or off under the control of the potential of the first node N1.

In an alternative implementation, referring to the example of fig. 3, in the bootstrap module 400, the switch unit may include a third transistor T3, the bootstrap unit may include a first capacitor C1, a control electrode, a first electrode, and a second electrode of the third transistor T3 are electrically connected to the first output unit 301, the second clock signal terminal CK2, and a first end (e.g., a positive electrode plate) of the first capacitor C1, respectively, and a second end (e.g., a negative electrode plate) of the first capacitor C1 is electrically connected to the first output unit 301.

In one example, referring to fig. 3, a control electrode of the third transistor T3 and a second end of the first capacitor C1 may be electrically connected to a third node N3 in the first output unit 301. The third transistor T3 may be turned on or off under the control of the potential of the third node N3, and when the third transistor T3 is turned on, the clock signal provided by the second clock signal terminal CK2 may be transmitted to the first capacitor C1, and the first capacitor C1 may bootstrap the potential of the third node N3 in the first output unit 301.

In another example, the control electrode of the third transistor T3 and the second end of the first capacitor C1 may be electrically connected to the first node N1 (the connection is not shown in fig. 3), so as to be electrically connected to the first output unit 301 through the first node N1. The third transistor T3 may be turned on or off under the control of the potential of the first node N1, and when the third transistor T3 is turned on, the clock signal provided by the second clock signal terminal CK2 may be transmitted to the first capacitor C1, and the first capacitor C1 may bootstrap the potential of the first node N1.

In an alternative embodiment, the second output unit 302 may include a fourth transistor T4 and a fifth transistor T5, a control electrode, a first electrode, and a second electrode of the fourth transistor T4 may be electrically connected to the first power signal terminal VGL, the second node N2, and the fourth node N4, respectively, and a control electrode, a first electrode, and a second electrode of the fifth transistor T5 are electrically connected to the fourth node N4, the second power signal terminal VGH, and the output terminal OUT, respectively.

In one example, the fourth transistor T4 may be turned on under the control of the first potential signal provided by the first power signal terminal VGL, the potential of the fourth node N4 is adjusted based on the potential of the second node N2, and the potential of the fourth node N4 may control the on/off of the fifth transistor T5, for example, when the potential of the second node N2 is the first potential, the tenth transistor T10 may be turned on, and thus the second power signal terminal VGH and the output terminal OUT may be turned on, and when the potential of the second node N2 is the second potential, the tenth transistor T10 may be turned off, and thus the second power signal terminal VGH and the output terminal OUT may be turned off.

The fourth transistor T4 is disposed between the second node N2 and the fourth node N4, so that direct signal transmission between the two nodes can be isolated, further, the influence of signal fluctuation of the second clock signal terminal CK2 on the fourth node N4 can be isolated, the stability of the turn-on voltage at the fourth node N4 can be maintained, the stability of the fifth transistor T5 can be maintained under the control of the turn-on voltage at the fourth node N4, and finally, the output of the output terminal connected to the fifth transistor T5 is more stable.

In another embodiment, the second output unit 302 may include a fifth transistor T5, a control electrode, a first electrode, and a second electrode of the fifth transistor T5 may be electrically connected to the second node N2, the second power signal terminal VGH, and the output terminal OUT, respectively, and the fifth transistor T5 may be turned on or off under the control of the potential of the second node N2.

Referring to the example of fig. 3, the first output unit 301 may further include a second capacitor C2, two ends of which are electrically connected to the control electrode and the first electrode of the second transistor T2, respectively, so as to implement noise reduction and cooperate with the first capacitor C1 to stabilize the turn-on voltage of the second transistor T2. The second output unit 302 may further include a third capacitor C3, and two ends of the third capacitor C3 are electrically connected to the control electrode and the first electrode of the fifth transistor T5, respectively, so as to implement noise reduction.

In an alternative implementation, referring to the example of fig. 3, the output module 400 may further include an output control unit 303, the output control unit 303 may be electrically connected to the first output unit 301, the second power signal terminal VGH, and the second output unit 301, respectively, and the output control unit 303 may be configured to control on/off between the second power signal terminal VGH and the second output unit based on a potential of the first output unit.

Referring to the example of fig. 3, the output control unit 303 may include a sixth transistor T6, a control electrode, a first electrode, and a second electrode of the sixth transistor T6 may be electrically connected to the third node N3, the second power signal terminal VGH, and the fourth node N4, respectively, a potential of the third node N3 may control on/off of the sixth transistor T6, for example, when a potential of the third node N3 is a first potential, the sixth transistor T6 may be controlled to be turned on, and the sixth transistor T6 may adjust a potential of the fourth node N4 based on a second potential signal provided by the second power signal terminal VGH, so that when the first output unit 301 outputs a signal to the output terminal, the second output unit 302 may stop outputting.

In an alternative embodiment, referring to the example of fig. 3, the second input module 200 may include a seventh transistor T7, an eighth transistor T8, a ninth transistor T9, and a fourth capacitor C4. A control electrode, a first electrode, and a second electrode of the seventh transistor T7 may be electrically connected to the control signal terminal STV, the first power signal terminal VGL, and the fifth node N5, respectively; a control electrode, a first electrode, and a second electrode of the eighth transistor T8 may be electrically connected to the fifth node N5, the second power signal terminal VGH, and the first end of the fourth capacitor C4, respectively, a control electrode, a first electrode, and a second electrode of the ninth transistor T9 may be electrically connected to the second clock signal terminal CK2, the first power signal terminal VGL, and the second node N2, respectively, and a second end of the fourth capacitor C4 may be electrically connected to the second node N2.

The seventh transistor T7 may be turned on or off under the control of a signal provided from the control signal terminal STV, the potential of the fifth node N5 may be adjusted based on a signal provided from the first power signal terminal VGL when turned on, the eighth transistor T8 may be turned on or off under the control of the potential of the fifth node N5, the first terminal of the fourth capacitor C4 may be charged based on a signal provided from the second power signal terminal VGH when turned on, the ninth transistor T9 may be turned on or off under the control of a clock signal provided from the second clock signal terminal CK2, the potential of the second node N2 may be adjusted based on a signal provided from the first power signal terminal VGL when turned on, and the second terminal of the fourth capacitor C4 may be charged by the potential of the second node N2. On the basis of the above-described structure of the second input block 200, the turn-on voltage for shifting can be realized by the cooperation of the signal of the control signal terminal STV and the signal of the second clock signal terminal CK 2.

In an optional embodiment, the fifth node N5 may further be electrically connected to the control signal terminal STV to access a signal provided by the control signal terminal STV, further control the eighth transistor T8, and may cooperate with signals of other nodes to implement shifting.

In another alternative embodiment, referring to fig. 3, the second input module 200 may further include a fifth capacitor C5, and two ends of the fifth capacitor C5 are electrically connected to the control signal terminal STV and the fifth node N5, respectively. The control signal terminal STV can be transmitted to the fifth node N5 through the fifth capacitor C5, so that the stability of the fifth node N5 is improved, the fifth node N5 can stably control the eighth transistor T8, the output stability of the output terminal OUT can be improved, and the influence on the next stage of shift register is avoided.

In an alternative embodiment, the first input module 100 may include a tenth transistor T10 having a control electrode, a first electrode and a second electrode electrically connected to the first clock signal terminal CK1, the control signal terminal STV and the first node N1, respectively. The tenth transistor T10 may be turned on to transmit the signal of the control signal terminal STV to the first node N1 when the first clock signal terminal CK1 is at the first potential, and the tenth transistor T10 may be turned off when the first clock signal terminal CK1 is at the second potential.

In the embodiments of the present application, each transistor may be a thin film transistor, a field effect transistor, or another switching device with the same characteristics. The source and drain of each transistor may be symmetrical in structure, so that the source and drain may be indistinguishable in structure. In the embodiments of the present application, in order to distinguish two poles of a transistor except for a gate, one of the two poles is directly described as a first pole, and the other pole is directly described as a second pole, and the gate of the transistor may be referred to as a control pole. In addition, the transistors may be divided into N-type and P-type transistors according to their characteristics, and the P-type transistor shown in fig. 3 is only an example and is not a limitation to the embodiments of the present application. When the transistor is a P-type transistor, the turn-on voltage is a low potential, and the turn-off voltage is a high potential. When the transistor is an N-type transistor, the turn-on voltage is a high voltage, and the turn-off voltage is a low voltage.

The shift register provided by the embodiment of the application can output a high-potential signal as a scanning driving signal to realize forward scanning (or called positive voltage scanning) so as to meet the driving requirements of the LTPO pixel circuit, and can also output low-potential information as a scanning driving signal to realize reverse scanning (or called negative voltage scanning) so as to meet the possible driving requirements of other pixel circuits.

Based on the same technical concept, an embodiment of the present application further provides a driving method, which can be applied to any one of the shift registers provided in the embodiment of the present application, as shown in fig. 4, the method includes the following steps S401 to S402:

s401, in the first stage, a control signal end provides a first potential signal, a first input module controls the connection or disconnection between the control signal end and a first node based on a clock signal provided by a first clock signal end, a switch unit controls the connection between a second clock signal end and a bootstrap unit based on the first potential of an output module, the bootstrap unit conducts bootstrap on the first potential of the output module, and the output module controls the connection between a first power supply signal end and an output end based on the potential of the first node, the potential of a second node and the bootstrap action of the bootstrap unit.

In one example, the clock signal provided by the first clock signal terminal CK1 may be a pulse signal that jumps between a first potential and a second potential, the clock signal provided by the first clock signal terminal CK1 periodically jumps between the first potential and the second potential in the first phase, the first input module may make conduction between the control signal terminal STV and the first node N1 when the signal provided by the first clock signal terminal CK1 is the first potential, so that the potential of the first node N1 may be adjusted based on the signal provided by the control signal terminal STV, and the first input module may make disconnection between the control signal terminal STV and the first node N1 when the signal provided by the first clock signal terminal CK1 is the second potential, so that the first node N1 cannot be adjusted based on the signal provided by the control signal terminal STV.

After the output module controls the first power signal end VGL to be conducted with the output end, the output end can output a signal provided by the first power signal end VGL. The second input module may control the second power signal terminal VGH to be disconnected from the second node N2 based on the first potential signal provided by the control signal terminal STV while the first power signal terminal VGL and the output terminal are turned on. The clock signal provided by the second clock signal terminal CK2 may be a pulse signal that jumps between a first potential and a second potential, the clock signal provided by the second clock signal terminal CK2 periodically jumps between the first potential and the second potential in the first stage, the second input module may be turned on when the signal provided by the second clock signal terminal CK2 is the first potential, the potential of the second node N2 is adjusted based on the signal provided by the first power signal terminal VGL, and the output module may further control the second power signal terminal VGH and the output terminal to be turned off based on the potential of the second node N2, so that the output terminal outputs only the signal of the first power signal terminal VGL in the first stage.

S402, in the second stage, the second input module controls the second power supply signal terminal and the second node to be disconnected based on a second potential signal provided by the control signal terminal, the second input module controls the first power supply signal terminal and the second node to be connected or disconnected based on a clock signal provided by the second clock signal terminal, and the output module controls the second power supply signal terminal and the output terminal to be connected based on the potential of the second node.

After the output module controls the conduction between the second power signal terminal VGH and the output terminal, the output terminal can output the signal provided by the second power signal terminal VGH. The second input module may control the second power signal terminal VGH to be disconnected from the second node N2 based on the first potential signal provided by the control signal terminal STV while the first power signal terminal VGL and the output terminal are turned on. The clock signal provided by the second clock signal terminal CK2 may be a pulse signal that jumps between a first potential and a second potential, the clock signal provided by the second clock signal terminal CK2 periodically jumps between the first potential and the second potential in the first stage, the second input module may adjust the potential of the second node N2 based on the signal provided by the first power signal terminal VGL when the signal provided by the second clock signal terminal CK2 is the first potential, and the output module may control the second power signal terminal VGH and the output terminal to be disconnected based on the potential of the second node N2, so that the output terminal outputs only the signal of the first power signal terminal VGL in the first stage.

In an optional implementation manner, in the case that the output module includes a first output unit and a second output unit, in step S401, the controlling, by the output module, conduction between the first power signal terminal VGL and the output terminal based on the potential of the first node N1, the potential of the second node N2, and a bootstrap of the bootstrap unit may include: the first output unit in the output module controls the first power signal terminal VGL to be connected with the output terminal based on the potential of the first node N1, the potential of the second node N2 and the bootstrap action of the bootstrap unit. For example, based on the potential of the first node N1 and the bootstrap of the bootstrap unit, when the potential of the output control node in the first output unit is the first potential, the first output unit 401 may control conduction between the first power signal terminal VGL and the output terminal OUT, so that the output terminal OUT may output a signal provided by the first power signal terminal VGL, and when the potential of the output control node in the first output unit 401 is the second potential, the first output unit 401 may control disconnection between the first power signal terminal VGL and the output terminal OUT, so that the output terminal OUT cannot output the signal provided by the first power signal terminal VGL.

In the step S402, the controlling, by the output module, the conduction between the second power signal terminal VGH and the output terminal based on the potential of the second node N2 may include: the second output unit in the output module controls the conduction between the second power signal terminal VGL and the output terminal based on the potential of the second node N2. For example, when the potential of the second node N2 is the first potential, the second output unit 402 may control conduction between the second power signal terminal VGH and the output terminal OUT, so that the output terminal OUT may output the signal provided by the second power signal terminal VGL, and when the potential of the second node N2 is the second potential, the second output unit 402 may control disconnection between the second power signal terminal VGH and the output terminal OUT, so that the output terminal OUT may not output the signal provided by the second power signal terminal VGH.

In an optional implementation manner, in a case that the switch unit includes the third transistor T3 and the bootstrap unit includes the first capacitor C1, in step S401, the switch unit controls conduction between the second clock signal terminal CK2 and the bootstrap unit based on the first potential of the output module, and the bootstrap unit performs bootstrap on the first potential of the output module, which may include: the third transistor T3 controls conduction between the second clock signal terminal CK2 and the first capacitor C1 based on the potential of the first output unit, transmits a signal provided by the second clock signal terminal CK2 to the first capacitor C1, and the first capacitor C1 bootstraps the potential of the first output unit.

In an optional implementation manner, the driving method provided in the embodiment of the present application may further include: in the first stage, the output control unit in the output module controls the second power signal terminal VGH and the second output unit to be conducted based on the potential of the first output unit, so that the potential of the second output unit can be adjusted (e.g., raised) based on the signal provided by the second power signal terminal VGH, and the second output unit stops outputting the signal to the output terminal.

Fig. 5 shows a signal timing diagram of each signal terminal and each node in the shift register shown in fig. 3, and the operation principle of the shift register provided in the embodiment of the present application is described below with reference to fig. 3 and fig. 5.

Referring to fig. 3 and 5, in the first phase T1, i.e., the charging phase, the signal provided by the control signal terminal STV is a low-potential signal, the signals provided by the first clock signal terminal CK1 and the second clock signal terminal CK2 are pulse signals, the first output path controls the output terminal OUT to output a low-potential signal provided by the first power signal terminal VGL, and the second output path controls the output terminal OUT to stop outputting a high-potential signal provided by the second power signal terminal VGH.

The working principle of the first output path in the first stage T1 is as follows: when the first clock signal terminal CK1 jumps to a low potential, the tenth transistor T10 is turned on, a low potential signal provided by the control signal terminal STV is transmitted to the first node N1 to pull down the potential of the first node N1, the first transistor T1 is turned on under the control of the low potential signal provided by the first power signal terminal VGL, the low potential signal of the first node N1 is transmitted to the third node N3 to pull down the potential of the third node N3, the third transistor T3 is turned on under the control of the low potential signal of the third node N3, and when the second clock signal terminal CK2 jumps to a low potential, the third transistor T3 is transmitted to the first capacitor C1 through the third transistor T3, the potential of the third node N3 is bootstrapped through the first capacitor C1, so that the potential of the third node N3 is continuously pulled down, and the third node N3 can control the second transistor T2 to be sufficiently turned on, so that the output terminal OUT can output the low potential signal provided by the first power signal terminal VGL.

The working principle of the second output path in the first stage T1 is as follows: the seventh transistor T7 is turned on under the control of the low potential provided by the control signal terminal STV, and transmits the low potential signal of the first power signal terminal VGL to the fifth node N5 to maintain the fifth node N5 at a low potential, the eighth transistor T8 is turned on under the control of the low potential signal of the fifth node N5, and the high potential signal provided by the second power signal terminal VGH charges one electrode of the fourth capacitor C4; when the second clock signal terminal CK2 transitions to a low potential, the ninth transistor T9 is turned on, and transmits a low potential signal of the first power signal terminal VGL to the second node N2 to pull down the potential of the second node N2, and the second node N2 charges the other electrode of the fourth capacitor C4; under the control of the low potential signal provided by the first power signal terminal VGL, the fourth transistor T4 is turned on, the low potential signal of the second node N2 is transmitted to the fourth node N4 to pull down the potential of the fourth node N4, and meanwhile, under the control of the low potential signal of the third node N3, the sixth transistor T6 is turned on, the high potential signal provided by the second power signal terminal VGH can be transmitted to the fourth node N4 to raise the potential of the fourth node N4, so that the potential of the fourth node N4 is not low enough to control the fifth transistor T5 to be turned on, and thus the output terminal OUT cannot output the high potential signal provided by the second power signal terminal VGH.

Referring to fig. 3 and 5, in the second stage T2, i.e. the output stage, the signal provided by the control signal terminal STV changes from a low level to a high level and from a high level to a low level, the signals provided by the first clock signal terminal CK1 and the second clock signal terminal CK2 are still pulse signals, the second output path control output terminal OUT outputs a high level signal provided by the second power signal terminal VGH as a driving signal for driving the pixel, and the first output path control output terminal OUT stops outputting a low level signal provided by the first power signal terminal VGL.

The working principle of the first output path in the second stage T2 is as follows: when the first clock signal terminal CK1 jumps to a low potential, the tenth transistor T10 is turned on, a high potential signal provided by the control signal terminal STV is transmitted to the first node N1 to raise the potential of the first node N1, the first transistor T1 is turned on under the control of a low potential signal provided by the first power signal terminal VGL, a high potential signal of the first node N1 is transmitted to the third node N3 to raise the potential of the third node N3, and the sixth transistor T6, the third transistor T3 and the second transistor T2 are all turned off under the control of a high potential signal of the third node N3, so that the output terminal OUT stops outputting a low potential signal provided by the first power signal terminal VGL, and the sixth transistor T6 does not raise the potential of the fourth node N4, thereby avoiding affecting the normal output of the output terminal OUT.

The working principle of the second output path in the second stage T2 is as follows: after the signal of the control signal terminal STV changes from the low potential to the high potential, the seventh transistor T7 is turned off, the potential of the fifth node N5 is controlled to be turned off by the first power signal terminal VGL, at this time, the high potential signal of the control signal terminal STV is written into the fifth node N5 through the fifth capacitor C5, the potential of the fifth node N5 is raised, and the eighth transistor T8 is turned off under the control of the high potential of the fifth node N5; when the second clock signal terminal CK2 transitions to a low potential, the ninth transistor T9 is turned on, the low potential signal of the first power signal terminal VGL is transmitted to the second node N2 to pull down the potential of the second node N2, the fourth transistor T4 is turned on under the control of the low potential signal provided by the first power signal terminal VGL, the low potential signal of the second node N2 is transmitted to the fourth node N4 to pull down the potential of the fourth node N4, and the fifth transistor T5 is turned on under the control of the low potential of the fourth node N4, so that the output terminal OUT outputs a high potential signal provided by the second power signal terminal VGH.

Within a period of time after the signal of the control signal terminal STV is changed from the high potential to the low potential again, the signal of the first clock signal terminal CK1 is at the high potential, the tenth transistor T10 is in an off state, the first node N1 and the third node N3 still maintain the high potential, and then the sixth transistor T6, the third transistor T3 and the second transistor T2 can be controlled to still maintain the off state, the potential of the fourth node N4 cannot be raised by the sixth transistor T6, the second transistor T2 cannot output the low potential signal of the first power signal terminal VGL, the output terminal can continue to maintain the output of the high potential signal until the signal of the first clock signal terminal CK1 jumps to the low potential, and thus, one-time scanning output of the driving signal can be completed.

Based on the same technical concept, the embodiment of the application also provides a display panel, which comprises a pixel circuit and a gate driving circuit, wherein the gate driving circuit is electrically connected with the pixel circuit and is used for providing a gate driving signal for the pixel circuit.

Referring to the example of fig. 6, the gate driving circuit may include a cascade of shift registers, and each shift register may be any one of the shift registers provided in the embodiments of the present application. The control signal end of the first stage shift register is electrically connected with the frame start signal end, and for the adjacent two stages of shift registers, the output end of the previous stage shift register is electrically connected with the control signal end of the next stage shift register. The output end of each stage of shift register may be further electrically connected to a corresponding row of pixel circuits, each stage of shift register may drive a row of pixel circuits, and fig. 6 shows four shift registers as an example, and the numbers of shift registers, i.e., GOA1, GOA2, GOA3, and GOA4, are respectively, and are only used as an example and not as a limitation on the number of cascaded shift registers.

The pixel circuit connected to the shift register may be an LTPO pixel circuit, such as the pixel circuit shown in fig. 1, when the pixel circuit is the circuit shown in fig. 1, the output terminal of each stage of the shift register may be connected to the gate of at least one transistor of the transistors M1, M2, M5 and M6 in a corresponding row of pixel circuits to provide the gate driving signal to the transistors M1, M2, M5 and M6, and in other examples, each stage of the shift register may be further electrically connected to other transistors in a corresponding row of pixel circuits, such as the transistors M4 and/or M7 to provide the gate driving signal to the transistors M4 and/or M7. It will be appreciated that in actual use, which transistors in the pixel circuit to connect the output of the shift register to can be determined according to the particular driving requirements.

In an alternative embodiment, referring to fig. 6, the first clock signal terminal CK1 of the odd-numbered stage shift register can be used for accessing the first clock signal CKV1, and the second clock signal terminal CK1 of the odd-numbered stage shift register can be used for accessing the second clock signal CKV2; the first clock signal terminal CK1 of the even-numbered stage shift register is used for accessing the second clock signal CKV2, and the second clock signal terminal CK2 of the even-numbered stage shift register is used for accessing the first clock signal CKV1. Each stage of shift register is connected with two clock signals, and vertical shift scanning of the gate driving circuit can be realized based on the matching control of the two clock signals.

In the vertical shift scanning process of the gate driving circuit, the output of the shift register of the next stage is relative to the output of the shift register of the previous stage, the shift duration can be adjusted according to actual requirements, and in order to realize the flexible adjustment of the interval duration, parameters such as pulse width, duty ratio and the like of each input signal of the shift register can be flexibly set.

Fig. 7 to 9 show simulation diagrams of cascade outputs of the shift registers, in fig. 7 to 9, an STV signal is a frame start signal provided by a control signal terminal STV, a CK1 signal is a clock signal provided by a first clock signal terminal CK1, a CK2 signal is a clock signal provided by a second clock signal terminal CK2, an OUT1 signal is a driving signal output by the shift register of the first stage, an OUT2 signal is a driving signal output by the shift register of the second stage, and an OUT3 signal is a driving signal output by the shift register of the third stage.

In the example of fig. 7, the pulse widths of the CK1 signal and the CK2 signal are both 1h, the pulse width of the STV signal is 5h, the shift time period of the out1 signal with respect to the STV signal is 1h, the shift time period of the out2 signal with respect to the OUT1 signal is 1h, and the shift time period of the out3 signal with respect to the OUT2 signal is 1H.

In the example of fig. 8, the pulse widths of the CK1 signal and the CK2 signal are both 1h, the pulse width of the STV signal is 1h, the shift period of the out1 signal with respect to the STV signal is 1h, the shift period of the out2 signal with respect to the OUT1 signal is 1h, and the shift period of the out3 signal with respect to the OUT2 signal is 1H.

In the example of FIG. 9, the CK1 signal and the CK2 signal both have a pulse width of 3H, the STV signal has a pulse width of 14H, the OUT1 signal is shifted with respect to the STV signal for a period of 2H, the OUT2 signal is shifted with respect to the OUT1 signal for a period of 2H, and the OUT3 signal is shifted with respect to the OUT2 signal for a period of 2H.

The step-by-step shifting manner shown in fig. 7 to fig. 9 can satisfy the driving requirement of the LTPO pixel circuit, and can support the PWM (Pulse width modulation) function.

In the description of the present specification, reference to the description of "one embodiment," "some embodiments," "an example," "a specific example," or "some examples" or the like means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the present application. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples. Moreover, various embodiments or examples and features of various embodiments or examples described in this specification can be combined and combined by one skilled in the art without being mutually inconsistent.

Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or to implicitly indicate the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of the feature. In the description of the present application, "a plurality" means two or more unless specifically limited otherwise.

The term "comprises/comprising" when used in this specification is taken to specify the presence of stated features, integers, steps, operations, elements, and/or components, but does not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. As used herein, the term "and/or" includes all or any element and all combinations of one or more of the associated listed items.

It will be understood that when an element is referred to as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element or intervening elements may also be present. Further, "connected" or "coupled" as used herein may include wirelessly connected or wirelessly coupled.

In this specification, "electrically connected" includes a case where constituent elements are connected together by an element having some kind of electrical action. The "element having some kind of electrical function" is not particularly limited as long as it can transmit and receive an electrical signal between connected components. Examples of the "element having some kind of electric function" include not only an electrode and a wiring but also a switching element such as a transistor, a resistor, an inductor, a capacitor, other elements having various functions, and the like.

The above description is only for the specific embodiments of the present application, but the scope of the present application is not limited thereto, and any person skilled in the art can easily conceive various changes or substitutions within the technical scope of the present application, and these should be covered by the scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.

Claims (15)

1. A shift register, comprising: the device comprises a first input module, a second input module, a bootstrap module and an output module;

the first input module is respectively and electrically connected with a first clock signal end, a control signal end and a first node, and the first input module is used for controlling the on-off between the control signal end and the first node based on a clock signal provided by the first clock signal end;

the second input module is respectively electrically connected with a control signal end, a first power signal end, a second clock signal end and a second node, and is used for controlling the connection and disconnection between the first power signal end and the second node and controlling the connection and disconnection between the second power signal end and the second node based on signals provided by the control signal end and the second clock signal end;

the output module is respectively electrically connected with the first node, the second node, the bootstrap module, the first power supply signal end, the second power supply signal end and the output end, and the output module is used for controlling the connection and disconnection between the first power supply signal end and the output end and controlling the connection and disconnection between the second power supply signal end and the output end based on the electric potential of the first node, the electric potential of the second node and the regulation of the bootstrap module;

the bootstrap module comprises a switch unit and a bootstrap unit, wherein a control end, a first end and a second end of the switch unit are respectively and electrically connected with the output module, the second clock signal end and the first end of the bootstrap unit, the second end of the bootstrap unit is electrically connected with the output module, the switch unit is used for controlling the connection and disconnection between the second clock signal end and the bootstrap unit based on the potential of the output module, and the bootstrap unit is used for bootstrapping the potential of the output module.

2. The shift register of claim 1, wherein the output module comprises a first output unit and a second output unit;

the first output unit is respectively and electrically connected with the first node, the first power supply signal end and the output end, and the first output unit is used for controlling the connection and disconnection between the first power supply signal end and the output end based on the electric potential of the first node and the bootstrap effect of the bootstrap unit;

the second output unit is electrically connected with the second node, the second power supply signal end and the output end respectively, and the second output unit is used for controlling the connection and disconnection between the second power supply signal end and the output end based on the potential of the second node.

3. The shift register according to claim 2, wherein the first output unit comprises: a first transistor and a second transistor;

a control electrode, a first electrode and a second electrode of the first transistor are respectively and electrically connected with the first power supply signal end, the first node and the third node;

and a control electrode, a first electrode and a second electrode of the second transistor are respectively and electrically connected with the third node, the first power supply signal end and the output end.

4. The shift register of claim 2, wherein the switching unit comprises a third transistor, and the bootstrap unit comprises a first capacitor;

a control electrode, a first electrode and a second electrode of the third transistor are electrically connected to the first output unit, the second clock signal terminal and the first end of the first capacitor, respectively, and a second end of the first capacitor is electrically connected to the first output unit.

5. The shift register according to any one of claims 2 to 4, wherein the second output unit includes: a fourth transistor and a fifth transistor;

a control electrode, a first electrode and a second electrode of the fourth transistor are respectively and electrically connected with the first power signal end, the second node and a fourth node;

and a control electrode, a first electrode and a second electrode of the fifth transistor are respectively and electrically connected with the fourth node, the second power signal end and the output end.

6. The shift register according to any one of claims 2 to 4, wherein the output module further comprises an output control unit;

the output control unit is electrically connected with the first output unit, the second power signal end and the second output unit respectively, and the output control unit is used for controlling the connection and disconnection between the second power signal end and the second output unit based on the potential of the first output unit.

7. The shift register according to any one of claims 1 to 4, wherein the second input module comprises: a seventh transistor, an eighth transistor, a ninth transistor, and a fourth capacitor;

a control electrode, a first electrode and a second electrode of the seventh transistor are respectively and electrically connected with the control signal end, the first power supply signal end and the fifth node;

a control electrode, a first electrode and a second electrode of the eighth transistor are electrically connected with the fifth node, the second power signal end and the first end of the fourth capacitor respectively;

a control electrode, a first electrode and a second electrode of the ninth transistor are electrically connected with the second clock signal end, the first power signal end and the second node respectively;

a second terminal of the fourth capacitor is electrically connected to the second node.

8. The shift register of claim 7, wherein the second input module further comprises: a fifth capacitor;

and two ends of the fifth capacitor are respectively electrically connected with the control signal end and the fifth node.

9. A gate drive circuit, comprising: a cascade of multiple stages of shift registers, each stage of shift register being a shift register according to any one of claims 1 to 8;

the control signal end of the first-stage shift register is electrically connected with the frame starting signal end;

for the adjacent two stages of shift registers, the output end of the shift register of the previous stage is electrically connected with the control signal end of the shift register of the next stage.

10. The gate driving circuit according to claim 9, wherein the first clock signal terminal of the odd-numbered stage shift register is used for receiving a first clock signal, and the second clock signal terminal of the odd-numbered stage shift register is used for receiving a second clock signal;

and the first clock signal end of the even-level shift register is used for accessing the second clock signal, and the second clock signal end of the even-level shift register is used for accessing the first clock signal.

11. A display panel, comprising: a pixel circuit and the gate driver circuit of claim 9 or 10;

the gate driving circuit is electrically connected with the pixel circuit and is used for providing a gate driving signal for the pixel circuit.

12. A driving method applied to the shift register according to any one of claims 1 to 8, the method comprising:

in a first stage, a control signal end provides a first potential signal, a first input module controls the control signal end and a first node to be connected or disconnected based on a clock signal provided by a first clock signal end, a switch unit controls the second clock signal end and the bootstrap unit to be connected based on a first potential of an output module, the bootstrap unit performs bootstrap on the first potential of the output module, and the output module controls the first power supply signal end and an output end to be connected based on a potential of the first node, a potential of a second node and a bootstrap action of the bootstrap unit;

in a second stage, the second input module controls the second power signal terminal and the second node to be disconnected based on a second potential signal provided by the control signal terminal, the second input module controls the first power signal terminal and the second node to be connected or disconnected based on a clock signal provided by a second clock signal terminal, and the output module controls the second power signal terminal and the output terminal to be connected based on the potential of the second node.

13. The driving method according to claim 12, wherein the controlling the conduction between the first power signal terminal and the output terminal by the output module based on the potential of the first node, the potential of the second node, and the bootstrap of the bootstrap unit comprises:

a first output unit in the output module controls the conduction between the first power supply signal end and an output end based on the electric potential of the first node, the electric potential of the second node and the bootstrap action of the bootstrap unit;

the output module controls the conduction between the first power signal terminal and the output terminal based on the potential of the second node, and includes:

and a second output unit in the output module controls the conduction between the first power supply signal end and the output end based on the potential of the second node.

14. The driving method according to claim 13, wherein the switching unit controls conduction between the second clock signal terminal and the bootstrap unit based on the first potential of the output module, and the bootstrap unit performs bootstrap on the first potential of the output module, including:

a third transistor in the switch unit controls conduction between the second clock signal terminal and a first capacitor in the bootstrap unit based on the potential of the first output unit, and transmits a signal provided by the second clock signal terminal to the first capacitor, and the first capacitor performs bootstrap on the potential of the first output unit.

15. The driving method according to claim 13 or 14, further comprising:

in the first stage, an output control unit in the output module controls the second power supply signal terminal and the second output unit to be conducted based on the potential of the first output unit.

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