CN113793563A - Drive circuit, drive module, drive method and display device - Google Patents

Abstract

The invention provides a driving circuit, a driving module, a driving method and a display device. The driving circuit comprises a first driving signal output end, a second driving signal output end, a first pull-up node control circuit, a second pull-up node control circuit, a first energy storage circuit, a second energy storage circuit, a pull-down node control circuit, a first driving signal output circuit and a second driving signal output circuit; the first driving signal output circuit controls a first driving signal output by the first driving signal output end under the control of the potentials of the first pull-up node and the pull-down node; the second driving signal output circuit is used for controlling a second driving signal output by the second driving signal output end under the control of the potential of the second pull-up node and the potential of the pull-down node. The invention can realize narrow frame, and reduce power consumption and flicker.

Description

Drive circuit, drive module, drive method and display device

Technical Field

The invention relates to the technical field of display, in particular to a driving circuit, a driving module, a driving method and a display device.

Background

The mobile product is updated very fast, the product is developed towards the trend of lightness, thinness, refinement and ultra-long standby, from the perspective of customer experience, the requirement on the frame of the screen is narrower and narrower, and the standby time is longer. Therefore, a driving circuit supporting narrow frames and not increasing Flicker under the condition of reducing power consumption at low frequency is developed, and the driving circuit plays a great role in improving the competitiveness of the display device.

Disclosure of Invention

The invention mainly aims to provide a driving circuit, a driving module, a driving method and a display device, and solves the problems that two-stage driving signal output cannot be realized, narrow frames cannot be realized, and the possibility of flicker cannot be reduced while power consumption is reduced in the prior art.

In order to achieve the above object, an embodiment of the present invention provides a driving circuit, which includes a first driving signal output terminal, a second driving signal output terminal, a first pull-up node control circuit, a second pull-up node control circuit, a first energy storage circuit, a second energy storage circuit, a pull-down node control circuit, a first driving signal output circuit, and a second driving signal output circuit;

the first pull-up node control circuit is used for controlling the potential of the first pull-up node according to a first scanning voltage provided by a first scanning voltage end, a second scanning voltage provided by a second scanning voltage end and a first voltage signal provided by a first voltage end under the control of an input signal provided by a first scanning control end, the potential of the pull-down node and a second driving signal provided by a second driving signal output end;

the second pull-up node control circuit is used for controlling the potential of a second pull-up node according to the first scanning voltage, the second scanning voltage and the first voltage signal under the control of a reset signal provided by a second scanning control end, the potential of the pull-down node and the first driving signal provided by the first driving signal output end;

the first energy storage circuit is electrically connected with the first pull-up node and is used for storing electric energy;

the second energy storage circuit is electrically connected with the second pull-up node and is used for storing electric energy;

the pull-down node control circuit is used for controlling the potential of the pull-down node under the control of an initial control signal provided by an initial control end and the potential of the first pull-up node, and controlling the potential of the pull-down node under the control of a second voltage signal provided by a second voltage end and the potential of the second pull-up node;

the first driving signal output circuit is used for controlling the communication between the first driving signal output end and a first clock signal end under the control of the potential of the first pull-up node and controlling the communication between the first driving signal output end and the first voltage end under the control of the potential of the pull-down node;

the second driving signal output circuit is used for controlling the second driving signal output end to be communicated with the second clock signal end under the control of the potential of the second pull-up node, and controlling the second driving signal output end to be communicated with the first voltage end under the control of the potential of the pull-down node.

Optionally, the first pull-up node control circuit is configured to control a first pull-up node to be communicated with a first scan voltage end under control of an input signal provided by a first scan control end, control the first pull-up node to be communicated with a first voltage end under control of a potential of a pull-down node, and control the first pull-up node to be communicated with a second scan voltage end under control of a second driving signal provided by a second driving signal output end;

the second pull-up node control circuit is used for controlling the communication between a second pull-up node and a second scanning voltage end under the control of a reset signal provided by a second scanning control end, controlling the communication between the second pull-up node and the first voltage end under the control of the potential of the pull-down node, and controlling the communication between the second pull-up node and the first scanning voltage end under the control of a first driving signal provided by a first driving signal output end.

Optionally, the first pull-up node control circuit includes a first transistor, a second transistor and a third transistor, and the second pull-up node control circuit includes a fourth transistor, a fifth transistor and a sixth transistor;

a control electrode of the first transistor is electrically connected with the first scan control terminal, a first electrode of the first transistor is electrically connected with the first scan voltage terminal, and a second electrode of the first transistor is electrically connected with the first pull-up node;

a control electrode of the second transistor is electrically connected with the pull-down node, a first electrode of the second transistor is electrically connected with the first pull-up node, and a second electrode of the second transistor is electrically connected with the first voltage end;

a control electrode of the third transistor is electrically connected to the second driving signal output terminal, a first electrode of the third transistor is electrically connected to the first pull-up node, and a second electrode of the third transistor is electrically connected to the second scan voltage terminal;

a control electrode of the fourth transistor is electrically connected with the first driving signal output end, a first electrode of the fourth transistor is electrically connected with the first scanning voltage end, and a second electrode of the fourth transistor is electrically connected with the second pull-up node;

a control electrode of the fifth transistor is electrically connected with the second scanning control end, a first electrode of the fifth transistor is electrically connected with the second pull-up node, and a second electrode of the fifth transistor is electrically connected with the second scanning voltage end;

a control electrode of the sixth transistor is electrically connected to the pull-down node, a first electrode of the sixth transistor is electrically connected to the second pull-up node, and a second electrode of the sixth transistor is electrically connected to the first voltage terminal.

Optionally, the first tank circuit includes a first capacitor, and the second tank circuit includes a second capacitor;

a first end of the first capacitor is electrically connected with the first pull-up node, and a second end of the first capacitor is electrically connected with the first voltage end;

the first end of the second capacitor is electrically connected with the second pull-up node, and the second end of the second capacitor is electrically connected with the first voltage end.

Optionally, the pull-down node control circuit includes a seventh transistor, an eighth transistor, a ninth transistor, a tenth transistor, and an eleventh transistor;

a control electrode of the seventh transistor and a first electrode of the seventh transistor are electrically connected with the initial control end, and a second electrode of the seventh transistor is electrically connected with the pull-down node;

a control electrode of the eighth transistor and a first electrode of the eighth transistor are both electrically connected to the second voltage terminal, and a second electrode of the eighth transistor is electrically connected to a control electrode of the ninth transistor;

a first electrode of the ninth transistor is electrically connected to the second voltage terminal, and a second electrode of the ninth transistor is electrically connected to the pull-down node;

a gate of the tenth transistor is electrically connected to the second pull-up node, a first electrode of the tenth transistor is electrically connected to the pull-down node, and a second electrode of the tenth transistor is electrically connected to the first voltage terminal;

a control electrode of the eleventh transistor is electrically connected to the first pull-up node, a first electrode of the eleventh transistor is electrically connected to the pull-down node, and a second electrode of the eleventh transistor is electrically connected to the first voltage terminal.

Optionally, the driving circuit according to at least one embodiment of the present invention further includes a first control transistor and a second control transistor;

the first driving signal output circuit is electrically connected with the first pull-up node through the first control transistor, and the second driving signal output circuit is electrically connected with the second pull-up node through the second control transistor;

the control electrode of the first control transistor is electrically connected with a third voltage end, the first electrode of the first control transistor is electrically connected with the first pull-up node, and the second electrode of the first control transistor is electrically connected with a first driving signal output circuit;

and the control electrode of the second control transistor is electrically connected with the third voltage end, the first electrode of the second control transistor is electrically connected with the second pull-up node, and the second electrode of the second control transistor is electrically connected with the second driving signal output circuit.

Optionally, the first driving signal output circuit includes a twelfth transistor and a thirteenth transistor;

a control electrode of the twelfth transistor is electrically connected with a second electrode of the first control transistor, a first electrode of the twelfth transistor is electrically connected with the first clock signal end, and a second electrode of the twelfth transistor is electrically connected with the first driving signal output end;

a control electrode of the thirteenth transistor is electrically connected to the pull-down node, a first electrode of the thirteenth transistor is electrically connected to the first driving signal output terminal, and a second electrode of the thirteenth transistor is electrically connected to the first voltage terminal.

Optionally, the second driving signal output circuit includes a fourteenth transistor and a fifteenth transistor;

a control electrode of the fourteenth transistor is electrically connected with a second electrode of the second control transistor, a first electrode of the fourteenth transistor is electrically connected with the second driving signal output end, and a second electrode of the fourteenth transistor is electrically connected with the first voltage end;

a control electrode of the fifteenth transistor is electrically connected to the pull-down node, a first electrode of the fifteenth transistor is electrically connected to the second driving signal output terminal, and a second electrode of the fifteenth transistor is electrically connected to the first voltage terminal.

The embodiment of the invention also provides a driving module which is applied to the display device and used for providing driving signals for the multi-row pixel circuits in the display panel of the display device; the driving module comprises a first driving unit and a second driving unit, the first driving unit comprises a multi-stage driving circuit, and the second driving unit comprises a multi-stage driving circuit;

the first driving unit is used for driving the pixel circuits in the odd rows;

the second driving unit is used for driving the pixel circuits in the even rows.

Optionally, in the first driving unit, a first scan control end of the first stage driving circuit is electrically connected to the first start voltage end; the second scanning control end of the nth stage driving circuit is electrically connected with the first driving signal output end of the (n + 1) th stage driving circuit; n is a positive integer, and n +1 is less than or equal to the number of stages of the driving circuit included in the first driving unit;

in the second driving unit, a first scanning control end of the first-stage driving circuit is electrically connected with a second initial voltage end; the second scanning control end of the mth level driving circuit is electrically connected with the first driving signal output end of the (m + 1) th level driving circuit; m is a positive integer, and m +1 is less than or equal to the number of stages of the driving circuit included in the second driving unit.

The embodiment of the invention also provides a driving method which is applied to the driving module, and the display period comprises a first display stage and a second display stage which are mutually independent; the driving method includes:

in the first display stage, each stage of driving circuits in the first driving unit provide driving signals for the pixel circuits in the odd rows;

in the second display stage, each stage of driving circuit in the second driving unit provides driving signals for the pixel circuits in the even rows.

The embodiment of the invention also provides a display device which comprises the driving module.

The driving circuit, the driving module, the driving method and the display device can realize two-stage driving signal output, are beneficial to realizing narrow frames, can eliminate the brightness difference between positive and negative frames in an odd-even output mode, and can reduce the possibility of flicker while reducing power consumption.

Drawings

FIG. 1 is a block diagram of a driving circuit according to at least one embodiment of the present disclosure;

FIG. 2 is a circuit diagram of a driving circuit according to at least one embodiment of the present disclosure;

FIG. 3 is a timing diagram illustrating operation of the driving circuit shown in FIG. 2 according to at least one embodiment of the present invention;

FIG. 4A is a schematic diagram illustrating alternate scanning of odd and even rows of pixels during a frame time when a driving module according to at least one embodiment of the present invention is in operation;

FIG. 4B is a graph showing the relationship between luminance and time when the odd and even rows of pixels are scanned alternately according to at least one embodiment of the present invention;

FIG. 4C is a schematic diagram of a sequential scanning multi-line driving circuit during a frame time when a driving module according to at least one embodiment of the invention is in operation;

FIG. 4D is a diagram illustrating the relationship between brightness and time during sequential scanning according to at least one embodiment of the present invention;

fig. 5 is a schematic diagram of a driving module according to at least one embodiment of the invention;

FIG. 6 is a timing diagram illustrating operation of the driving module shown in FIG. 5 according to at least one embodiment of the present invention;

FIG. 7 is a timing diagram illustrating operation of the driving module shown in FIG. 5 according to at least one embodiment of the present invention.

Detailed Description

The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

The transistors used in all embodiments of the present invention may be transistors, thin film transistors, or field effect transistors or other devices with the same characteristics. In the embodiment of the present invention, in order to distinguish two poles of the transistor except the control pole, one pole is called a first pole, and the other pole is called a second pole.

In practical operation, when the transistor is a thin film transistor or a field effect transistor, the first electrode may be a drain electrode, and the second electrode may be a source electrode; alternatively, the first pole may be a source and the second pole may be a drain.

As shown in fig. 1, the driving circuit according to the embodiment of the present invention includes a first driving signal output terminal OUTN, a second driving signal output terminal OUTN +1, a first pull-up node control circuit 11, a second pull-up node control circuit 12, a first tank circuit 13, a second tank circuit 14, a pull-down node control circuit 15, a first driving signal output circuit 16, and a second driving signal output circuit 17;

the first pull-up node control circuit 11 is electrically connected to the first scan control terminal STVF, the pull-down node PD, the second drive signal output terminal OUTN +1, the first scan voltage terminal CN, the second scan voltage terminal CNB, the first voltage terminal V1, and the first pull-up node PU1, respectively, and is configured to control a potential of the first pull-up node PU1 according to a first scan voltage provided by the first scan voltage terminal CN, a second scan voltage provided by the second scan voltage terminal CNB, and a first voltage signal provided by the first voltage terminal V1 under control of an input signal provided by the first scan control terminal STVF, a potential of the pull-down node PD, and a second drive signal provided by the second drive signal output terminal OUTN + 1;

the second pull-up node control circuit 12 is electrically connected to the second scan control terminal STVB, the pull-down node PD, the first driving signal output terminal OUTN, the first scan voltage terminal CN, the second scan voltage terminal CNB, the first voltage terminal V1, and the second pull-up node PU2, respectively, and is configured to control the potential of the second pull-up node PU2 according to the first scan voltage, the second scan voltage, and the first voltage signal under the control of the reset signal provided by the second scan control terminal STVB, the potential of the pull-down node PD, and the first driving signal provided by the first driving signal output terminal OUTN;

the first energy storage circuit 13 is electrically connected to the first pull-up node PU1 and is configured to store electric energy;

the second tank circuit 14 is electrically connected to the second pull-up node PU2 and is configured to store electrical energy;

the pull-down node control circuit 15 is electrically connected to the initial control terminal Reset, the first pull-up node PU1, the pull-down node PD, the second voltage terminal V2 and the second pull-up node PU2, respectively, and is configured to control the potential of the pull-down node PD under the control of an initial control signal provided by the initial control terminal Reset and the potential of the first pull-up node PU1, and control the potential of the pull-down node PD under the control of a second voltage signal provided by the second voltage terminal V2 and the potential of the second pull-up node PU 2;

the first driving signal output circuit 16 is electrically connected to the first pull-up node PU1, the first driving signal output terminal OUTN, the first clock signal terminal CK, the pull-down node PD, and the first voltage terminal V1, respectively, and is configured to control the communication between the first driving signal output terminal OUTN and the first clock signal terminal CK under the control of the potential of the first pull-up node PU1, and control the communication between the first driving signal output terminal OUTN and the first voltage terminal V1 under the control of the potential of the pull-down node PD; the first clock signal terminal CK is used for providing a first clock signal;

the second driving signal output circuit 17 is electrically connected to a second pull-up node PU2, a second driving signal output terminal OUTN +1, a second clock signal terminal CKB, the pull-down node PD, and a first voltage terminal V1, respectively, and is configured to control the communication between the second driving signal output terminal OUTN +1 and the second clock signal terminal CKB under the control of the potential of the second pull-up node PU2, and control the communication between the second driving signal output terminal OUTN +1 and the first voltage terminal V1 under the control of the potential of the pull-down node PD; the second clock signal terminal CKB is used for providing a second clock signal.

In at least one embodiment of the driving circuit shown in fig. 1, the first voltage terminal V1 can be a low voltage terminal, and the second voltage terminal V2 can be a high voltage terminal, but not limited thereto.

The driving circuit provided by the embodiment of the invention can realize two-stage driving signal output, and is beneficial to realizing a narrow frame.

In the related art, the first-stage driving circuit can only drive one row of pixel circuits, and the number of the pixel circuits is the required number.

In the embodiment of the driving circuit shown in fig. 1, the initial control signal provided by Reset may be a high voltage in the initialization phase, charge the PD so that the potential of the PD is a high voltage, and pull down the potential of PU1 and the potential of PU2 to a low voltage;

CN is a first scanning voltage end and is used for controlling forward scanning; CNB is a second scan voltage terminal for controlling the reverse scan.

In the present invention, as shown in fig. 1, when at least one embodiment of the driving circuit works, the forward scanning is taken as an example for explanation, the CN provides a high voltage signal, the CNB provides a low voltage signal, and the driving cycle includes an initialization stage, a charging stage, a first output stage, a second output stage, and a reset stage that are sequentially set;

in the initialization stage, the pull-down node control circuit 15 controls the potential of the pull-down node PD to be a high voltage under the control of the initial control signal; the first pull-up node control circuit 11 controls the potential of the first pull-up node PU1 to be a low voltage under the control of the potential of the pull-down node PD, and the second pull-up node control circuit 12 controls the potential of the second pull-up node PU2 to be a low voltage under the control of the potential of the pull-down node PD, so as to complete initialization;

in the charging phase, the first pull-up node control circuit 11 controls the first node PU1 to communicate with the first scan voltage terminal CN under the control of the input signal provided by the first scan control terminal STVF, so that the potential of the first node PU1 is a high voltage, thereby completing the charging function; the pull-down node control circuit 15 controls the potential of the pull-down node PD to be a low voltage under the control of the potential of the first pull-up node PU 1;

in the first output stage, the first clock signal terminal CK provides a high voltage signal, the first driving signal output circuit 16 controls the connection between the first driving signal output terminal OUTN and the first clock signal terminal CK under the control of the potential of the first pull-up node PU1 to control the OUTN to output the high voltage signal, the potential of PU1 is further pulled up by bootstrap action, the second pull-up node control circuit 12 controls the connection between the second pull-up node PU2 and the first scan voltage terminal CN under the control of the first driving signal provided by the OUTN to make the potential of PU2 be a high voltage, and the pull-down node control circuit 15 controls the potential of the pull-down node PD to be a low voltage under the control of the second voltage signal and the potential of the second pull-up node PU 2;

in the second output stage, the potential of the first clock signal provided by the first clock signal terminal CK changes from high voltage to low voltage, and the first driving signal output circuit 16 controls the connection between the first driving signal output terminal OUTN and the first clock signal terminal CK under the control of the potential of the first pull-up node PU1 to control the OUTN to output a low voltage signal and reduce the potential of the first pull-up node PU1 through a bootstrap effect; the second clock signal terminal CKB provides a high voltage signal, and the second driving signal output circuit 17 controls the connection between the second driving signal output terminal OUTN +1 and the second clock signal terminal CKB under the control of the potential of the second pull-up node PU2, so that OUTN +1 outputs the high voltage signal; the potential of the second pull-up node PU2 is further pulled high by the bootstrap action, and the pull-down node control circuit 15 controls the potential of the pull-down node PD to be a low voltage under the control of a second voltage signal and the potential of the first pull-up node PU 1; the first pull-up node control circuit 11 controls the connection between the first pull-up node PU1 and the second scan voltage terminal CNB under the control of the second driving signal provided by OUTN +1, so that the potential of the first pull-up node PU1 is a low voltage;

in a reset phase, the reset signal provided by the STVB is a high voltage signal, the second pull-up node control circuit 12 controls the potential of the second pull-up node PU2 to be a low voltage under the control of the reset signal, the pull-down node control circuit 15 controls the potential of the pull-down node PD to be a high voltage under the control of the potential of the first pull-up node PU1, the potential of the second pull-up node PU2 and the second voltage signal, and the first driving signal output circuit 16 controls the connection between the first driving signal output terminal OUTN and the first voltage terminal V1 under the control of the potential of the pull-down node PD, so that the OUTN outputs a low voltage signal; the second driving signal output circuit 17 controls the connection between the second driving signal output terminal OUTN +1 and the first voltage terminal V1 under the control of the potential of the pull-down node PD, so as to control OUTN +1 to output a low voltage signal.

In practical implementation, the first pull-up node control circuit 11 is configured to control communication between the first pull-up node PU1 and the first scan voltage terminal CN under the control of an input signal provided by the first scan control terminal STVF, control communication between the first pull-up node PU1 and the first voltage terminal V1 under the control of a potential of the pull-down node PD, and control communication between the first pull-up node PU1 and the second scan voltage terminal CNB under the control of a second driving signal provided by the second driving signal output terminal OUTN + 1;

the second pull-up node control circuit 12 is configured to control the communication between the second pull-up node PU2 and the second scan voltage terminal CNB under the control of the reset signal provided by the second scan control terminal STVB, control the communication between the second pull-up node PU2 and the first voltage terminal V1 under the control of the potential of the pull-down node PD, and control the communication between the second pull-up node PU2 and the first scan voltage terminal CN under the control of the first driving signal provided by the first driving signal output terminal OUTN.

Optionally, the first pull-up node control circuit includes a first transistor, a second transistor and a third transistor, and the second pull-up node control circuit includes a fourth transistor, a fifth transistor and a sixth transistor;

a control electrode of the first transistor is electrically connected with the first scan control terminal, a first electrode of the first transistor is electrically connected with the first scan voltage terminal, and a second electrode of the first transistor is electrically connected with the first pull-up node;

a control electrode of the second transistor is electrically connected with the pull-down node, a first electrode of the second transistor is electrically connected with the first pull-up node, and a second electrode of the second transistor is electrically connected with the first voltage end;

a control electrode of the third transistor is electrically connected to the second driving signal output terminal, a first electrode of the third transistor is electrically connected to the first pull-up node, and a second electrode of the third transistor is electrically connected to the second scan voltage terminal;

a control electrode of the fourth transistor is electrically connected with the first driving signal output end, a first electrode of the fourth transistor is electrically connected with the first scanning voltage end, and a second electrode of the fourth transistor is electrically connected with the second pull-up node;

a control electrode of the fifth transistor is electrically connected with the second scanning control end, a first electrode of the fifth transistor is electrically connected with the second pull-up node, and a second electrode of the fifth transistor is electrically connected with the second scanning voltage end;

a control electrode of the sixth transistor is electrically connected to the pull-down node, a first electrode of the sixth transistor is electrically connected to the second pull-up node, and a second electrode of the sixth transistor is electrically connected to the first voltage terminal.

Optionally, the first tank circuit includes a first capacitor, and the second tank circuit includes a second capacitor;

a first end of the first capacitor is electrically connected with the first pull-up node, and a second end of the first capacitor is electrically connected with the first voltage end;

the first end of the second capacitor is electrically connected with the second pull-up node, and the second end of the second capacitor is electrically connected with the first voltage end.

Optionally, the pull-down node control circuit includes a seventh transistor, an eighth transistor, a ninth transistor, a tenth transistor, and an eleventh transistor;

a control electrode of the seventh transistor and a first electrode of the seventh transistor are electrically connected with the initial control end, and a second electrode of the seventh transistor is electrically connected with the pull-down node;

a control electrode of the eighth transistor and a first electrode of the eighth transistor are both electrically connected to the second voltage terminal, and a second electrode of the eighth transistor is electrically connected to a control electrode of the ninth transistor;

a first electrode of the ninth transistor is electrically connected to the second voltage terminal, and a second electrode of the ninth transistor is electrically connected to the pull-down node;

a gate of the tenth transistor is electrically connected to the second pull-up node, a first electrode of the tenth transistor is electrically connected to the pull-down node, and a second electrode of the tenth transistor is electrically connected to the first voltage terminal;

a control electrode of the eleventh transistor is electrically connected to the first pull-up node, a first electrode of the eleventh transistor is electrically connected to the pull-down node, and a second electrode of the eleventh transistor is electrically connected to the first voltage terminal.

In practical implementation, the driving circuit according to at least one embodiment of the present invention may further include a first control transistor and a second control transistor;

the first driving signal output circuit is electrically connected with the first pull-up node through the first control transistor, and the second driving signal output circuit is electrically connected with the second pull-up node through the second control transistor;

the control electrode of the first control transistor is electrically connected with a third voltage end, the first electrode of the first control transistor is electrically connected with the first pull-up node, and the second electrode of the first control transistor is electrically connected with a first driving signal output circuit;

and the control electrode of the second control transistor is electrically connected with the third voltage end, the first electrode of the second control transistor is electrically connected with the second pull-up node, and the second electrode of the second control transistor is electrically connected with the second driving signal output circuit.

In at least one embodiment of the present invention, when the first control transistor and the second control transistor are n-type transistors, the third voltage terminal may be a high voltage terminal; when the first control transistor and the second control transistor are p-type transistors, the third voltage terminal may be a low voltage terminal; but not limited thereto.

Optionally, the first driving signal output circuit includes a twelfth transistor and a thirteenth transistor;

a control electrode of the twelfth transistor is electrically connected with a second electrode of the first control transistor, a first electrode of the twelfth transistor is electrically connected with the first clock signal end, and a second electrode of the twelfth transistor is electrically connected with the first driving signal output end;

a control electrode of the thirteenth transistor is electrically connected to the pull-down node, a first electrode of the thirteenth transistor is electrically connected to the first driving signal output terminal, and a second electrode of the thirteenth transistor is electrically connected to the first voltage terminal.

Optionally, the second driving signal output circuit includes a fourteenth transistor and a fifteenth transistor;

a control electrode of the fourteenth transistor is electrically connected with a second electrode of the second control transistor, a first electrode of the fourteenth transistor is electrically connected with the second driving signal output end, and a second electrode of the fourteenth transistor is electrically connected with the first voltage end;

a control electrode of the fifteenth transistor is electrically connected to the pull-down node, a first electrode of the fifteenth transistor is electrically connected to the second driving signal output terminal, and a second electrode of the fifteenth transistor is electrically connected to the first voltage terminal.

As shown in fig. 2, on the basis of the embodiment of the driving circuit shown in fig. 1,

the first pull-up node control circuit includes a first transistor M1, a second transistor M2, and a third transistor M3, and the second pull-up node control circuit includes a fourth transistor M4, a fifth transistor M5, and a sixth transistor M6;

a gate of the first transistor M1 is electrically connected to the first scan control terminal STVF, a source of the first transistor M1 is electrically connected to the first scan voltage terminal CN, and a drain of the first transistor M1 is electrically connected to the first pull-up node PU 1;

the gate of the second transistor M2 is electrically connected to the pull-down node PD, the source of the second transistor M2 is electrically connected to the first pull-up node PU1, and the drain of the second transistor M2 is electrically connected to the low voltage terminal; the low voltage end is used for providing a low voltage VGL;

a gate of the third transistor M3 is electrically connected to the second driving signal output terminal OUTN +1, a source of the third transistor M3 is electrically connected to the first pull-up node PU1, and a drain of the third transistor M3 is electrically connected to the second scan voltage terminal CNB;

a gate of the fourth transistor M4 is electrically connected to the first driving signal output terminal OUTN, a source of the fourth transistor M4 is electrically connected to the first scan voltage terminal CN, and a drain of the fourth transistor M4 is electrically connected to the second pull-up node PU 2;

a gate of the fifth transistor M5 is electrically connected to the second scan control terminal STVB, a source of the fifth transistor M5 is electrically connected to the second pull-up node PU2, and a drain of the fifth transistor M5 is electrically connected to the second scan voltage terminal CNB;

the gate of the sixth transistor M6 is electrically connected to the pull-down node PD, the source of the sixth transistor M6 is electrically connected to the second pull-up node PU2, and the drain of the sixth transistor M6 is electrically connected to the low-voltage terminal;

the first tank circuit comprises a first capacitor C1, and the second tank circuit comprises a second capacitor C2;

a first end of the first capacitor C1 is electrically connected to the first pull-up node PU1, and a second end of the first capacitor C1 is electrically connected to the low voltage terminal;

a first end of the second capacitor C2 is electrically connected to the second pull-up node PU2, and a second end of the second capacitor C2 is electrically connected to the low voltage terminal;

the pull-down node control circuit includes a seventh transistor M7, an eighth transistor M8, a ninth transistor M9, a tenth transistor M10, and an eleventh transistor M11;

a gate of the seventh transistor M7 and a source of the seventh transistor M7 are electrically connected to the initial control terminal Reset, and a drain of the seventh transistor M7 is electrically connected to the pull-down node PD;

the gate of the eighth transistor M8 and the source of the eighth transistor M8 are both electrically connected to a high voltage terminal, and the drain of the eighth transistor M8 is electrically connected to the gate of the ninth transistor M9; the high voltage end is used for providing a high voltage VGH;

the source of the ninth transistor M9 is electrically connected to the high voltage terminal, and the drain of the ninth transistor M9 is electrically connected to the pull-down node PD;

a gate of the tenth transistor M10 is electrically connected to the second pull-up node PU2, a source of the tenth transistor M10 is electrically connected to the pull-down node PD, and a drain of the tenth transistor M10 is electrically connected to the low voltage terminal;

a gate of the eleventh transistor M11 is electrically connected to the first pull-up node PU1, a source of the eleventh transistor M11 is electrically connected to the pull-down node PD, and a drain of the eleventh transistor M11 is electrically connected to the low voltage terminal;

the driving circuit according to at least one embodiment of the present invention further includes a first control transistor M01 and a second control transistor M02;

the gate of the first control transistor M01 is electrically connected to the high voltage terminal, and the source of the first control transistor M01 is electrically connected to the first pull-up node PU 1;

the gate of the second control transistor M02 is electrically connected to the high voltage terminal, and the source of the second control transistor M02 is electrically connected to the second pull-up node PU 2;

the first driving signal output circuit includes a twelfth transistor M12 and a thirteenth transistor M13;

a gate of the twelfth transistor M12 is electrically connected to the drain of the first control transistor M01, a source of the twelfth transistor M12 is electrically connected to the first clock signal terminal CK, and a drain of the twelfth transistor M12 is electrically connected to the first driving signal output terminal OUTN;

the gate of the thirteenth transistor M13 is electrically connected to the pull-down node PD, the source of the thirteenth transistor M13 is electrically connected to the first driving signal output terminal OUTN, and the drain of the thirteenth transistor M13 is electrically connected to the low voltage terminal;

the second driving signal output circuit includes a fourteenth transistor M14 and a fifteenth transistor M15;

the gate of the fourteenth transistor M14 is electrically connected to the drain of the second control transistor M02, the source of the fourteenth transistor M14 is electrically connected to the second driving signal output terminal OUTN +1, and the drain of the fourteenth transistor M14 is electrically connected to the low voltage terminal;

the gate of the fifteenth transistor M15 is electrically connected to the pull-down node PD, the source of the fifteenth transistor M15 is electrically connected to the second driving signal output terminal OUTN +1, and the drain of the fifteenth transistor M15 is electrically connected to the low voltage terminal.

In at least one embodiment of the present invention, M01 and M02 can prevent current leakage, thereby enhancing the stability of the driving circuit.

In at least one embodiment of the driving circuit shown in fig. 2, all the transistors are NMOS (N-type metal-oxide-semiconductor) transistors, but not limited thereto.

Taking forward scan as an example of at least one embodiment of the driving circuit shown in fig. 2, CN provides a high voltage signal, and CNB provides a low voltage signal, as shown in fig. 3, the driving cycle includes an initialization stage S1, a charging stage S2, a first output stage S3, a second output stage S4, and a reset stage S5, which are sequentially arranged;

in the initialization stage S1, Reset provides a high voltage signal, M7 is turned on, the potential of PD is high voltage, M2 and M6 are turned on, and the potential of PU1 and the potential of PU2 are low voltage, so as to implement the initialization function;

in a charging stage S2, the STVF provides a high-voltage signal, the M1 is opened, the M01 is in a normally open state, the potential of the PU1 is high voltage, the M11 is opened, and the potential of the PD is low voltage through charging, so that a charging function is realized;

in the first output stage S3, CK provides a high voltage signal, CKB provides a low voltage signal, M12 generates a bootstrap effect, so that the potential of PU1 rises further, M11 is continuously turned on, the potential of PD is kept at a low voltage, the potential of PU1 becomes a high voltage, M12 starts sufficiently, OUTN outputs a high voltage signal, M4 is turned on, PU2 is charged, so that the potential of PU2 becomes a high voltage, M10 is turned on, and the potential of PD is a low voltage; m02 is in a normally open state, M14 is opened, and OUTN +1 outputs a low-voltage signal;

in the second output stage S4, the potential of the first clock signal provided by CK changes from high voltage to low voltage, M12 generates a bootstrap effect, and pulls down the potential of PU1 (the potential of PU1 is reduced from the potential of S3 to the potential of S2), CKB provides a high voltage signal, M14 generates a bootstrap effect, so that the potential of PU2 rises further, M10 is continuously turned on, the potential of PD is continuously low voltage, the potential of PU2 is high voltage, M14 is turned on, OUTN +1 outputs a high voltage signal, M3 is turned on, so as to pull down the potential of PU1 further;

in the reset phase S5, STVB provides a high voltage signal, M5 is turned on to pull the potential of PU2 low, M11 and M10 are both turned off, M8 and M9 are both turned on, so that the potential of PD becomes a high voltage, M15 and M13 are turned on, so that OUTN outputs a low voltage signal, and OUTN +1 outputs a low voltage signal.

The embodiment of the invention supports a forward scanning mode and a reverse scanning mode, and CN provides a low-voltage signal and CNB provides a high-voltage signal during reverse scanning.

The driving module is used for providing driving signals for a plurality of rows of pixel circuits in a display panel of a display device; the driving module comprises a first driving unit and a second driving unit, the first driving unit comprises a multi-stage driving circuit, and the second driving unit comprises a multi-stage driving circuit;

the first driving unit is used for driving the pixel circuits in the odd rows;

the second driving unit is used for driving the pixel circuits in the even rows.

When the driving module works, the first driving unit drives the odd-numbered row pixel circuits, the second driving unit drives the even-numbered row pixel circuits, and the odd-numbered row pixel circuits and the even-numbered row pixel circuits are scanned alternately; the method comprises the steps that pixel circuits of odd rows are scanned sequentially through a first driving unit in the first half of a frame time, after all the pixel circuits of the odd rows are scanned, pixel circuits of even rows are scanned sequentially through a second driving unit in the second half of the frame time, or the pixel circuits of even rows are scanned sequentially through the first driving unit in the first half of the frame time, and after all the pixel circuits of even rows are scanned, the pixel circuits of odd rows are scanned sequentially through the second driving unit in the second half of the frame time; according to the embodiment of the invention, through the driving mode, the brightness difference between the positive and negative frames can be eliminated, and the possibility of flicker generation can be reduced while the power consumption is reduced.

For example, at least one embodiment of the present invention performs alternate scanning of odd and even rows of pixels, ensures that a clock signal is identical to 60Hz, scans odd row pixel circuits/even row pixel circuits in the first half of one frame time, and scans even row pixel circuits/odd row pixel circuits in the second half of one frame time, thereby achieving reduction in flicker while achieving low power consumption.

As shown in fig. 4A, when the driving module according to at least one embodiment of the present invention is operated, the odd line driving circuits are sequentially scanned during the first half F11 of the first frame time, and the even line driving circuits are sequentially scanned during the second half F12 of the first frame time; the odd-numbered line driving circuits are sequentially scanned during the first half F21 of the second frame time, and the even-numbered line driving circuits are sequentially scanned during the second half F22 of the second frame time.

Fig. 4B is a schematic diagram illustrating the relationship between luminance and time when the odd and even rows of pixels are scanned alternately according to at least one embodiment of the present invention.

As shown in fig. 4C, when the driving module according to at least one embodiment of the present invention is in operation, the driving module sequentially scans the plurality of rows of driving circuits at a first frame time F1; at the second frame time F2, the multi-line driving circuits are sequentially scanned.

Fig. 4D is a schematic diagram of a relationship between luminance and time when performing sequential scanning according to at least one embodiment of the present invention.

In a specific implementation, in the first driving unit, a first scan control end of the first-stage driving circuit is electrically connected with a first starting voltage end; the second driving signal output end of the nth stage driving circuit is connected with the input end of the (n + 1) th stage driving circuit, and the second scanning control end of the nth stage driving circuit is electrically connected with the first driving signal output end of the (n + 1) th stage driving circuit; n is a positive integer, and n +1 is less than or equal to the number of stages of the driving circuit included in the first driving unit;

in the second driving unit, a first scanning control end of the first-stage driving circuit is electrically connected with a second initial voltage end; the second scanning control end of the mth level driving circuit is electrically connected with the first driving signal output end of the (m + 1) th level driving circuit; m is a positive integer, and m +1 is less than or equal to the number of stages of the driving circuit included in the second driving unit.

Fig. 5 shows a first three-stage driving circuit included in a first driving unit of a driving module according to at least one embodiment of the invention, and a first three-stage driving circuit included in a second driving unit of the driving module according to at least one embodiment of the invention;

in fig. 5, a first stage driving circuit denoted by S11, a second stage driving circuit denoted by S12, and a third stage driving circuit denoted by S13 are included in the first driving unit;

a first stage driving circuit denoted by reference numeral S21, a second stage driving circuit denoted by reference numeral S22, and a third stage driving circuit denoted by reference numeral S23, the second stage driving circuit being included in the second driving unit;

a first row driving signal terminal denoted by the reference numeral OUT1, a third row driving signal terminal denoted by the reference numeral OUT3, a fifth row driving signal terminal denoted by the reference numeral OUT5, a seventh row driving signal terminal denoted by the reference numeral OUT7, a ninth row driving signal terminal denoted by the reference numeral OUT9, and an eleventh row driving signal terminal denoted by the reference numeral OUT 11; OUT1 is electrically connected with a first row of gate lines included in the display panel, OUT3 is electrically connected with a third row of gate lines included in the display panel, OUT5 is electrically connected with a fifth row of gate lines included in the display panel, OUT7 is electrically connected with a seventh row of gate lines included in the display panel, OUT9 is electrically connected with a ninth row of gate lines included in the display panel, and OUT11 is electrically connected with an eleventh row of gate lines included in the display panel;

a second row driving signal terminal denoted by the reference numeral OUT2, a fourth row driving signal terminal denoted by the reference numeral OUT4, a sixth row driving signal terminal denoted by the reference numeral OUT6, an eighth row driving signal terminal denoted by the reference numeral OUT8, a tenth row driving signal terminal denoted by the reference numeral OUT10, and a twelfth row driving signal terminal denoted by the reference numeral OUT 12; OUT2 is electrically connected with the second row of gate lines included in the display panel, OUT4 is electrically connected with the fourth row of gate lines included in the display panel, OUT6 is electrically connected with the sixth row of gate lines included in the display panel, OUT8 is electrically connected with the eighth row of gate lines included in the display panel, OUT10 is electrically connected with the tenth row of gate lines included in the display panel, and OUT12 is electrically connected with the twelfth row of gate lines included in the display panel.

In at least one embodiment shown in fig. 5, the first start voltage terminal and the second start voltage terminal are the same start voltage terminal.

As shown in fig. 5, the reference sign STV is a start voltage terminal, the reference sign CKL is a first left clock signal line, the reference sign CKBL is a second left clock signal line, the reference sign CKR is a first right clock signal line, the reference sign CKBR is a second right clock signal line, the reference sign CN is a first scan voltage terminal, and the reference sign CNB is a second scan voltage terminal;

the first scan control terminal of S11 and the first scan control terminal of S21 are both electrically connected to the start voltage terminal STV;

the first drive signal output terminal of S11 is electrically connected to OUT1, and the second drive signal output terminal of S11 is electrically connected to OUT 3; the second driving signal output end of the S11 is electrically connected with the first scanning control end of the S12;

the first driving signal output end of the S12 is electrically connected with the OUT5, the second driving signal output end of the S12 is electrically connected with the OUT7, the first driving signal output end of the S12 is electrically connected with the second scanning control end of the S11, and the second driving signal output end of the S12 is electrically connected with the first scanning control end of the S13;

the first drive signal output terminal of S13 is electrically connected to OUT9, and the second drive signal output terminal of S13 is electrically connected to OUT 11; the first driving signal output end of the S13 is electrically connected with the second scanning control end of the S12;

the first drive signal output terminal of S21 is electrically connected to OUT2, and the second drive signal output terminal of S21 is electrically connected to OUT 4; the second driving signal output end of the S21 is electrically connected with the first scanning control end of the S22;

the first driving signal output end of the S22 is electrically connected with the OUT6, the second driving signal output end of the S22 is electrically connected with the OUT8, the first driving signal output end of the S22 is electrically connected with the second scanning control end of the S21, and the second driving signal output end of the S22 is electrically connected with the first scanning control end of the S23;

the first drive signal output terminal of S23 is electrically connected to OUT10, and the second drive signal output terminal of S23 is electrically connected to OUT 12; the first driving signal output end of the S23 is electrically connected with the second scanning control end of the S22;

the first clock signal terminal of S11 is electrically connected to the first left clock signal line CKL, and the second clock signal terminal of S11 is electrically connected to the second left clock signal line CKBL;

the first clock signal terminal of S12 is electrically connected to the second left clock signal line CKBL, and the second clock signal terminal of S11 is electrically connected to the first left clock signal line CKL;

the first clock signal terminal of S13 is electrically connected to the first left clock signal line CKL, and the second clock signal terminal of S13 is electrically connected to the second left clock signal line CKBL;

the first clock signal terminal of S21 is electrically connected to the first right clock signal line CKR, and the second clock signal terminal of S21 is electrically connected to the second right clock signal line CKBR;

the first clock signal terminal of S22 is electrically connected to the second right clock signal line CKBR, and the second clock signal terminal of S21 is electrically connected to the first right clock signal line CKR;

the first clock signal terminal of S23 is electrically connected to the first right clock signal line CKR, and the second clock signal terminal of S23 is electrically connected to the second right clock signal line CKBR.

In operation of at least one embodiment of the driving module shown in fig. 5 of the present invention, the driving module may sequentially provide driving signals to the odd-numbered rows of pixel circuits during a half of a frame time, and sequentially provide driving signals to the even-numbered rows of pixel circuits during another half of the frame time.

In a specific implementation, when the driving module according to at least one embodiment of the present invention is used to drive a plurality of rows of pixel circuits, a first driving unit in the driving module is used to drive an odd-numbered row of driving circuits, and a second driving unit in the driving module is used to drive an even-numbered row of driving circuits, as shown in fig. 6, in a first half of a first frame time F1 and a first half of a second frame time F2, OUT1, OUT3, …, OUT2n-3, and OUT2n-1 output driving signals, and in a second half of the first frame time F1 and a second half of the second frame time F2, OUT2, OUT4, OUT …, OUT2n-2, and OUT2n output driving signals successively. Wherein n is a positive integer.

The embodiment of the invention can eliminate the brightness difference between positive and negative frames by an odd-even output mode (namely, driving the pixel circuits of the odd rows in the first half of a display period and driving the pixel circuits of the even rows in the second half of the display period, or driving the pixel circuits of the even rows in the first half of the display period and driving the pixel circuits of the odd rows in the second half of the display period), thereby reducing the power consumption and reducing the possibility of flicker.

In practical implementation, when the driving module according to at least one embodiment of the present invention is used to drive a plurality of rows of pixel circuits, a first driving unit in the driving module is used to drive an odd-numbered row of driving circuits, and a second driving unit in the driving module is used to drive an even-numbered row of driving circuits, as shown in fig. 7, at a first frame time F1, OUT1, OUT2, OUT3, OUT4, …, OUT2n-3, OUT2n-2, OUT2n-1, and OUT2n sequentially output driving signals, and at a second frame time, OUT1, OUT2, OUT3, OUT4, …, OUT2n-3, OUT2n-2, OUT2n-1, and OUT2n sequentially output driving signals.

In fig. 6 and 7, OUT1 is a first row driving signal terminal, OUT2 is a second row driving signal terminal, OUT3 is a third row driving signal terminal, OUT4 is a fourth row driving signal terminal, OUT2n-3 is a 2n-3 row driving signal terminal, OUT2n-2 is a 2n-2 row driving signal terminal, OUT2n-1 is a 2n-1 row driving signal terminal, and OUTM is a 2n row driving signal terminal.

The driving method provided by the embodiment of the invention is applied to the driving module, and the display period comprises a first display stage and a second display stage which are independent of each other; the driving method includes:

in the first display stage, each stage of driving circuits in the first driving unit provide driving signals for the pixel circuits in the odd rows;

in the second display stage, each stage of driving circuit in the second driving unit provides driving signals for the pixel circuits in the even rows.

In at least one embodiment of the present invention, the display period may be a frame time, the first display phase may be a first half of the frame time, and the second display phase may be a second half of the frame time; alternatively, the first display phase may be a second half of a frame time, and the second display phase may be a first half of a frame time.

Since the resolution of the related display device is higher and higher, the power consumption is also increased along with the increase of the resolution, and the standby time is greatly reduced, in order to reduce the power consumption, reducing the refresh frequency of the display device is an effective method for significantly reducing the power consumption, but reducing the refresh frequency can bring about the problem that Flicker is higher and worse. The embodiment of the invention eliminates the brightness difference between the positive and negative frames by an odd-even output mode, thereby reducing the possibility of flicker while reducing the power consumption.

The display device provided by the embodiment of the invention comprises the driving module.

The display device provided by the embodiment of the invention can be any product or component with a display function, such as a mobile phone, a tablet personal computer, a television, a display, a notebook computer, a digital photo frame, a navigator and the like.

While the foregoing is directed to the preferred embodiment of the present invention, it will be understood by those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the invention as defined in the appended claims.

Claims (12)

1. A drive circuit is characterized by comprising a first drive signal output end, a second drive signal output end, a first pull-up node control circuit, a second pull-up node control circuit, a first energy storage circuit, a second energy storage circuit, a pull-down node control circuit, a first drive signal output circuit and a second drive signal output circuit;

the first pull-up node control circuit is used for controlling the potential of the first pull-up node according to a first scanning voltage provided by a first scanning voltage end, a second scanning voltage provided by a second scanning voltage end and a first voltage signal provided by a first voltage end under the control of an input signal provided by a first scanning control end, the potential of the pull-down node and a second driving signal provided by a second driving signal output end;

the second pull-up node control circuit is used for controlling the potential of a second pull-up node according to the first scanning voltage, the second scanning voltage and the first voltage signal under the control of a reset signal provided by a second scanning control end, the potential of the pull-down node and the first driving signal provided by the first driving signal output end;

the first energy storage circuit is electrically connected with the first pull-up node and is used for storing electric energy;

the second energy storage circuit is electrically connected with the second pull-up node and is used for storing electric energy;

the pull-down node control circuit is used for controlling the potential of the pull-down node under the control of an initial control signal provided by an initial control end and the potential of the first pull-up node, and controlling the potential of the pull-down node under the control of a second voltage signal provided by a second voltage end and the potential of the second pull-up node;

the first driving signal output circuit is used for controlling the communication between the first driving signal output end and a first clock signal end under the control of the potential of the first pull-up node and controlling the communication between the first driving signal output end and the first voltage end under the control of the potential of the pull-down node;

the second driving signal output circuit is used for controlling the second driving signal output end to be communicated with the second clock signal end under the control of the potential of the second pull-up node, and controlling the second driving signal output end to be communicated with the first voltage end under the control of the potential of the pull-down node.

2. The driving circuit as claimed in claim 1, wherein the first pull-up node control circuit is configured to control communication between a first pull-up node and a first scan voltage terminal under control of an input signal provided from a first scan control terminal, control communication between the first pull-up node and the first voltage terminal under control of a potential of a pull-down node, and control communication between the first pull-up node and the second scan voltage terminal under control of a second driving signal provided from the second driving signal output terminal;

the second pull-up node control circuit is used for controlling the communication between a second pull-up node and a second scanning voltage end under the control of a reset signal provided by a second scanning control end, controlling the communication between the second pull-up node and the first voltage end under the control of the potential of the pull-down node, and controlling the communication between the second pull-up node and the first scanning voltage end under the control of a first driving signal provided by a first driving signal output end.

3. The drive circuit according to claim 1 or 2, wherein the first pull-up node control circuit includes a first transistor, a second transistor, and a third transistor, and the second pull-up node control circuit includes a fourth transistor, a fifth transistor, and a sixth transistor;

a control electrode of the first transistor is electrically connected with the first scan control terminal, a first electrode of the first transistor is electrically connected with the first scan voltage terminal, and a second electrode of the first transistor is electrically connected with the first pull-up node;

a control electrode of the second transistor is electrically connected with the pull-down node, a first electrode of the second transistor is electrically connected with the first pull-up node, and a second electrode of the second transistor is electrically connected with the first voltage end;

a control electrode of the third transistor is electrically connected to the second driving signal output terminal, a first electrode of the third transistor is electrically connected to the first pull-up node, and a second electrode of the third transistor is electrically connected to the second scan voltage terminal;

a control electrode of the fourth transistor is electrically connected with the first driving signal output end, a first electrode of the fourth transistor is electrically connected with the first scanning voltage end, and a second electrode of the fourth transistor is electrically connected with the second pull-up node;

a control electrode of the fifth transistor is electrically connected with the second scanning control end, a first electrode of the fifth transistor is electrically connected with the second pull-up node, and a second electrode of the fifth transistor is electrically connected with the second scanning voltage end;

a control electrode of the sixth transistor is electrically connected to the pull-down node, a first electrode of the sixth transistor is electrically connected to the second pull-up node, and a second electrode of the sixth transistor is electrically connected to the first voltage terminal.

4. The drive circuit of claim 1 or 2, wherein the first tank circuit comprises a first capacitor and the second tank circuit comprises a second capacitor;

a first end of the first capacitor is electrically connected with the first pull-up node, and a second end of the first capacitor is electrically connected with the first voltage end;

the first end of the second capacitor is electrically connected with the second pull-up node, and the second end of the second capacitor is electrically connected with the first voltage end.

5. The drive circuit according to claim 1 or 2, wherein the pull-down node control circuit includes a seventh transistor, an eighth transistor, a ninth transistor, a tenth transistor, and an eleventh transistor;

a control electrode of the seventh transistor and a first electrode of the seventh transistor are electrically connected with the initial control end, and a second electrode of the seventh transistor is electrically connected with the pull-down node;

a control electrode of the eighth transistor and a first electrode of the eighth transistor are both electrically connected to the second voltage terminal, and a second electrode of the eighth transistor is electrically connected to a control electrode of the ninth transistor;

a first electrode of the ninth transistor is electrically connected to the second voltage terminal, and a second electrode of the ninth transistor is electrically connected to the pull-down node;

a gate of the tenth transistor is electrically connected to the second pull-up node, a first electrode of the tenth transistor is electrically connected to the pull-down node, and a second electrode of the tenth transistor is electrically connected to the first voltage terminal;

a control electrode of the eleventh transistor is electrically connected to the first pull-up node, a first electrode of the eleventh transistor is electrically connected to the pull-down node, and a second electrode of the eleventh transistor is electrically connected to the first voltage terminal.

6. The drive circuit according to claim 1 or 2, further comprising a first control transistor and a second control transistor;

the first driving signal output circuit is electrically connected with the first pull-up node through the first control transistor, and the second driving signal output circuit is electrically connected with the second pull-up node through the second control transistor;

the control electrode of the first control transistor is electrically connected with a third voltage end, the first electrode of the first control transistor is electrically connected with the first pull-up node, and the second electrode of the first control transistor is electrically connected with a first driving signal output circuit;

and the control electrode of the second control transistor is electrically connected with the third voltage end, the first electrode of the second control transistor is electrically connected with the second pull-up node, and the second electrode of the second control transistor is electrically connected with the second driving signal output circuit.

7. The drive circuit according to claim 6, wherein the first drive signal output circuit includes a twelfth transistor and a thirteenth transistor;

a control electrode of the twelfth transistor is electrically connected with a second electrode of the first control transistor, a first electrode of the twelfth transistor is electrically connected with the first clock signal end, and a second electrode of the twelfth transistor is electrically connected with the first driving signal output end;

a control electrode of the thirteenth transistor is electrically connected to the pull-down node, a first electrode of the thirteenth transistor is electrically connected to the first driving signal output terminal, and a second electrode of the thirteenth transistor is electrically connected to the first voltage terminal.

8. The drive circuit according to claim 6, wherein the second drive signal output circuit includes a fourteenth transistor and a fifteenth transistor;

a control electrode of the fourteenth transistor is electrically connected with a second electrode of the second control transistor, a first electrode of the fourteenth transistor is electrically connected with the second driving signal output end, and a second electrode of the fourteenth transistor is electrically connected with the first voltage end;

a control electrode of the fifteenth transistor is electrically connected to the pull-down node, a first electrode of the fifteenth transistor is electrically connected to the second driving signal output terminal, and a second electrode of the fifteenth transistor is electrically connected to the first voltage terminal.

9. A driving module is applied to a display device and used for providing driving signals for a plurality of rows of pixel circuits in a display panel of the display device; the driving module comprises a first driving unit and a second driving unit, wherein the first driving unit comprises a plurality of stages of driving circuits according to any one of claims 1 to 8, and the second driving unit comprises a plurality of stages of driving circuits according to any one of claims 1 to 8;

the first driving unit is used for driving the pixel circuits in the odd rows;

the second driving unit is used for driving the pixel circuits in the even rows.

10. The drive module of claim 9,

in the first driving unit, a first scanning control end of a first-stage driving circuit is electrically connected with a first starting voltage end; the second scanning control end of the nth stage driving circuit is electrically connected with the first driving signal output end of the (n + 1) th stage driving circuit; n is a positive integer, and n +1 is less than or equal to the number of stages of the driving circuit included in the first driving unit;

in the second driving unit, a first scanning control end of the first-stage driving circuit is electrically connected with a second initial voltage end; the second scanning control end of the mth level driving circuit is electrically connected with the first driving signal output end of the (m + 1) th level driving circuit; m is a positive integer, and m +1 is less than or equal to the number of stages of the driving circuit included in the second driving unit.

11. A driving method applied to the driving module set according to claim 9 or 10, wherein the display period includes a first display stage and a second display stage which are independent of each other; the driving method includes:

in the first display stage, each stage of driving circuits in the first driving unit provide driving signals for the pixel circuits in the odd rows;

in the second display stage, each stage of driving circuit in the second driving unit provides driving signals for the pixel circuits in the even rows.

12. A display device comprising a drive module according to claim 9 or 10.

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