CN117330843A - Method for reducing Kelvin resistance test difference - Google Patents
Method for reducing Kelvin resistance test difference Download PDFInfo
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- CN117330843A CN117330843A CN202310960521.0A CN202310960521A CN117330843A CN 117330843 A CN117330843 A CN 117330843A CN 202310960521 A CN202310960521 A CN 202310960521A CN 117330843 A CN117330843 A CN 117330843A
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- 238000012360 testing method Methods 0.000 title claims abstract description 174
- 238000000034 method Methods 0.000 title claims abstract description 23
- 239000004065 semiconductor Substances 0.000 claims description 18
- 239000000758 substrate Substances 0.000 claims description 18
- 239000000523 sample Substances 0.000 claims description 6
- 239000012212 insulator Substances 0.000 claims description 4
- 238000009792 diffusion process Methods 0.000 claims description 3
- 239000002184 metal Substances 0.000 claims description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 3
- 229920005591 polysilicon Polymers 0.000 claims description 3
- 238000010586 diagram Methods 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- 229910045601 alloy Inorganic materials 0.000 description 2
- 239000000956 alloy Substances 0.000 description 2
- 230000007547 defect Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 1
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 238000002474 experimental method Methods 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- 238000007689 inspection Methods 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
Classifications
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R27/00—Arrangements for measuring resistance, reactance, impedance, or electric characteristics derived therefrom
- G01R27/02—Measuring real or complex resistance, reactance, impedance, or other two-pole characteristics derived therefrom, e.g. time constant
- G01R27/08—Measuring resistance by measuring both voltage and current
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Abstract
The invention provides a method for reducing Kelvin resistance test difference, which is characterized in that a first test machine is respectively connected with first to fourth test ends of a device to be tested, wherein a fixed current I is applied to the first test end, a second test end is used for measuring a first voltage value V1, a third test end is used for measuring a second voltage value V2, and a voltage value is applied to the fourth test end to be 0V, so that a first resistance value of the device to be tested is obtained; the method comprises the steps of respectively connecting a second test machine with first to fourth test ends of a device to be tested, wherein the voltage value applied by the first test end is 0V, the second test end is used for measuring a third voltage value V2', the third test end is used for measuring a fourth voltage value V1', and the fourth test end is used for applying a fixed current I, so that a second resistance value R2 of the device to be tested is obtained; and obtaining a final resistance value R= (R1+R2)/2 according to the first resistance value and the second resistance value. The Kelvin resistance test difference caused by the hardware difference between different machines is eliminated through the test twice.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a method for reducing Kelvin resistance test difference.
Background
WAT (wafer acceptance test) machine produced by different manufacturers has different hardware suppliers due to different machine structures, so that unavoidable deviation of partial parameters occurs due to inherent difference of hardware precision of the machine in the machine inspection process of the latter machine. Kelvin resistance is one type of parameter, and FIG. 1 shows a Kelvin resistance test structure in the prior art. The resistance is equal to the voltage divided by the current, and the difference is the voltage since the current is a fixed applied value and is not measured. The common practice is to collect the fixed difference value of the measured voltages of two types of machines through experiments, and compensate the value in the test program. Although the problems are solved, the defects are also: WAT test files used by the two types of machines are different, and unified management is not facilitated.
To solve the above problems, a new method for reducing the kelvin resistance test difference is needed.
Disclosure of Invention
In view of the above drawbacks of the prior art, the present invention is directed to a method for reducing kelvin resistance test differences, so as to solve the problem that WAT test files used for two types of machines in the prior art are different, which is not beneficial to unified management.
To achieve the above and other related objects, the present invention provides a method for reducing kelvin resistance test variation, comprising:
step one, providing a first test machine table, a second test machine table and a device to be tested, wherein the first test machine table, the second test machine table and the device to be tested are used for Kelvin resistance testing, and the two sides of the device to be tested are respectively provided with a first test end, a second test end, a third test end and a fourth test end;
step two, the first test machine is respectively connected with the first to fourth test ends of the device to be tested, the first test end is used for applying a fixed current I, the second test end is used for measuring a first voltage value V1, the third test end is used for measuring a second voltage value V2, the fourth test end is used for applying a voltage value of 0V, and the hardware test error of the first test machine is E1, so that a first resistance value R1= (V2+V1+E1)/I of the device to be tested is obtained;
the second test machine is respectively connected with the first to fourth test ends of the device to be tested, the voltage value applied by the first test end is 0V, the second test end is used for measuring a third voltage value V2', the third test end is used for measuring a fourth voltage value V1', the fourth test end is used for applying a fixed current I, and the hardware test error of the second test machine is E2, so that a second resistance value R2= (V2 '-V1' -E2)/I of the device to be tested is obtained;
and thirdly, obtaining a final resistance value R= (R1+R2)/2 according to the first resistance value and the second resistance value, wherein hardware test errors of the first test machine and the second test machine are counteracted.
Preferably, the first and second test machines in the first step are wafer acceptance test machines.
Preferably, the test resistor of the test device in the first step includes: polysilicon resistor, diffusion resistor, metal resistor.
Preferably, the test resistor in step one is integrated on a semiconductor substrate.
Preferably, the semiconductor substrate in step one comprises a bulk semiconductor substrate or a silicon-on-insulator (SOI) substrate.
Preferably, each of the first to fourth test terminals in the first step is formed with a pad.
Preferably, each pad in the second step is connected to a probe on the probe card of the first and second test machines respectively.
Preferably, the first voltage value in the second step is less than 0.01V.
Preferably, the second voltage value in the second step is less than 0.01V.
Preferably, in the second step, the deviation between the voltage values measured by the first and second test machines is smaller than a preset value.
As described above, the method for reducing the kelvin resistance test difference of the present invention has the following advantageous effects:
the Kelvin resistance test difference caused by the hardware difference between different machines is eliminated through the test twice.
Drawings
FIG. 1 is a schematic diagram showing the Kelvin resistance test results of the prior art;
FIG. 2 shows a schematic diagram of two tests of the present invention;
FIG. 3 is a schematic diagram showing a method for reducing the Kelvin resistance test variation according to the present invention.
Detailed Description
Other advantages and effects of the present invention will become apparent to those skilled in the art from the following disclosure, which describes the embodiments of the present invention with reference to specific examples. The invention may be practiced or carried out in other embodiments that depart from the specific details, and the details of the present description may be modified or varied from the spirit and scope of the present invention.
Referring to fig. 3, the present invention provides a method for reducing kelvin resistance test difference, which includes:
step one, providing a first test machine table, a second test machine table and a device to be tested, wherein the first test machine table and the second test machine table are used for Kelvin resistance test (four-wire test), and the two sides of the device to be tested are respectively provided with a first test end, a second test end, a third test end and a fourth test end;
in an embodiment of the present invention, the first and second test tools in the first step are Wafer Acceptance Test (WAT) tools.
In an embodiment of the present invention, the test resistor of the test device in the step one includes: polysilicon resistance, diffusion resistance, metal resistance, and the type of resistance of the devices tested herein may also be other types known to those skilled in the art.
In an embodiment of the present invention, the test resistor in step one is integrated on the semiconductor substrate.
In an embodiment of the invention, the semiconductor substrate in step one comprises a bulk semiconductor substrate or a silicon-on-insulator (SOI) substrate. The SOI substrate includes an insulator layer under a thin semiconductor layer that is an active layer of the SOI substrate. The semiconductor and bulk semiconductor of the active layer typically comprise crystalline semiconductor material silicon, but may also comprise one or more other semiconductor materials such as germanium, silicon germanium alloys, compound semiconductors (e.g., gaAs, alAs, inAs, gaN, alN, etc.) or alloys thereof (e.g., gaxAl1-xAs, gaxAl1-xN, inxGa1-xAs, etc.), oxide semiconductors (e.g., znO, snO2, tiO2, ga2O3, etc.), or combinations thereof. The semiconductor material may be doped or undoped. Other substrates that may be used include multilayer substrates, gradient substrates, or hybrid orientation substrates.
In an embodiment of the present invention, pads (pads) are formed on the first to fourth test terminals in the first step.
Step two, a first test machine is respectively connected with first to fourth test ends of a device to be tested, a fixed current I is applied to the first test end, a second test end is used for measuring a first voltage value V1, a third test end is used for measuring a second voltage value V2, a fourth test end is used for applying a voltage value of 0V, and a hardware test error (such as a test error caused by a conductive wire and a machine parasitic capacitance) of the first test machine is E1, so that a first resistance value R1= (V2+V1+E1)/I of the device to be tested is obtained;
the method comprises the steps of respectively connecting a second test machine with first to fourth test ends of a device to be tested, wherein the voltage value applied by the first test end is 0V, the second test end is used for measuring a third voltage value V2', the third test end is used for measuring a fourth voltage value V1', the fixed current I is applied by the fourth test end, and the hardware test error of the second test machine is E2, so that a second resistance value R2= (V2 '-V1' -E2)/I of the device to be tested is obtained;
referring to fig. 1 and fig. 2, in the test of the first test machine, the first test end is the HF end in fig. 1, the fourth test end is the LF end in fig. 1, the second test end and the third test end are voltage test ends corresponding to the device to be tested, so as to obtain a first resistance value r1= (v2+v1+δv2- δv1)/I, where δv2- δv1 is a voltage test error caused by the hardware of the first test machine; in the test of the second test machine, the applied current is opposite in direction, so that the second resistance value R2= (V2 '-V1' -delta V2+ delta V1)/I, delta V1-delta V2 is the voltage test error brought by the hardware of the second test machine, namely the voltage test error brought by the hardware of the first test machine and the hardware of the second test machine is counteracted.
In the embodiment of the invention, each pad in the second step is respectively connected with the probes on the probe cards of the first test machine and the second test machine.
In an embodiment of the present invention, the first voltage value in the second step is less than 0.01V.
In an embodiment of the present invention, the second voltage value in the second step is less than 0.01V.
In the embodiment of the invention, the deviation between the voltage values measured by the first test machine and the second test machine in the second step is smaller than a preset value.
And thirdly, obtaining a final resistance value R= (R1+R2)/2 according to the first resistance value and the second resistance value, wherein hardware test errors of the first test machine and the second test machine are counteracted.
It should be noted that, the illustrations provided in the present embodiment merely illustrate the basic concept of the present invention by way of illustration, and only the components related to the present invention are shown in the drawings and are not drawn according to the number, shape and size of the components in actual implementation, and the form, number and proportion of the components in actual implementation may be arbitrarily changed, and the layout of the components may be more complex.
In summary, the Kelvin resistance test difference caused by the hardware difference between different machines is eliminated by testing twice. Therefore, the invention effectively overcomes various defects in the prior art and has high industrial utilization value.
The above embodiments are merely illustrative of the principles of the present invention and its effectiveness, and are not intended to limit the invention. Modifications and variations may be made to the above-described embodiments by those skilled in the art without departing from the spirit and scope of the invention. Accordingly, it is intended that all equivalent modifications and variations of the invention be covered by the claims, which are within the ordinary skill of the art, be within the spirit and scope of the present disclosure.
Claims (10)
1. A method for reducing kelvin resistance test variation, comprising at least:
step one, providing a first test machine table, a second test machine table and a device to be tested, wherein the first test machine table, the second test machine table and the device to be tested are used for Kelvin resistance testing, and the two sides of the device to be tested are respectively provided with a first test end, a second test end, a third test end and a fourth test end;
step two, the first test machine is respectively connected with the first to fourth test ends of the device to be tested, the first test end is used for applying a fixed current I, the second test end is used for measuring a first voltage value V1, the third test end is used for measuring a second voltage value V2, the fourth test end is used for applying a voltage value of 0V, and the hardware test error of the first test machine is E1, so that a first resistance value R1= (V2+V1+E1)/I of the device to be tested is obtained;
the second test machine is respectively connected with the first to fourth test ends of the device to be tested, the voltage value applied by the first test end is 0V, the second test end is used for measuring a third voltage value V2', the third test end is used for measuring a fourth voltage value V1', the fourth test end is used for applying a fixed current I, and the hardware test error of the second test machine is E2, so that a second resistance value R2= (V2 '-V1' -E2)/I of the device to be tested is obtained;
and thirdly, obtaining a final resistance value R= (R1+R2)/2 according to the first resistance value and the second resistance value, wherein hardware test errors of the first test machine and the second test machine are counteracted.
2. The method of reducing the variation in kelvin resistance test according to claim 1, wherein: the first and second test machines in the first step are wafer acceptance test machines.
3. The method of reducing the variation in kelvin resistance test according to claim 1, wherein: the test resistor of the test device in the first step comprises: polysilicon resistor, diffusion resistor, metal resistor.
4. A method of reducing the variation in kelvin resistance test according to claim 3, wherein: the test resistor in step one is integrated on a semiconductor substrate.
5. The method of reducing the variation in kelvin resistance test according to claim 4, wherein: the semiconductor substrate in step one comprises a bulk semiconductor substrate or a silicon-on-insulator (SOI) substrate.
6. The method of reducing the variation in kelvin resistance test according to claim 1, wherein: the first to fourth test terminals in the first step are each formed with a pad.
7. The method of reducing the variation in kelvin resistance test according to claim 6, wherein: and step two, each pad is respectively connected with the probes on the probe cards of the first test machine and the second test machine.
8. The method of reducing the variation in kelvin resistance test according to claim 1, wherein: the first voltage value in the second step is smaller than 0.01V.
9. The method of reducing the variation in kelvin resistance test according to claim 8, wherein: the second voltage value in the second step is smaller than 0.01V.
10. The method of reducing the variation in kelvin resistance test according to claim 9, wherein: and in the second step, the deviation between the voltage values measured by the first test machine and the second test machine is smaller than a preset value.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202310960521.0A CN117330843A (en) | 2023-08-01 | 2023-08-01 | Method for reducing Kelvin resistance test difference |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202310960521.0A CN117330843A (en) | 2023-08-01 | 2023-08-01 | Method for reducing Kelvin resistance test difference |
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| Publication Number | Publication Date |
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| CN117330843A true CN117330843A (en) | 2024-01-02 |
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| CN202310960521.0A Pending CN117330843A (en) | 2023-08-01 | 2023-08-01 | Method for reducing Kelvin resistance test difference |
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2023
- 2023-08-01 CN CN202310960521.0A patent/CN117330843A/en active Pending
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