CN117330800A - Test probe card and test apparatus - Google Patents

Abstract

The present disclosure provides a test probe card and a test apparatus. The test probe card is used for transmitting electric signals between the chip to be tested and the tester, the test probe card comprises a substrate and a power signal probe, the substrate comprises a power metal surface used for being electrically connected with a power supply end and a power test end of the tester, one end of the power signal probe is electrically connected with the power metal surface, and the other end of the power signal probe is used for being electrically connected with a power receiving end of the chip to be tested. By adopting the technical scheme disclosed by the invention, the occupation of the power receiving end of the chip to be tested can be avoided in the chip testing stage, so that the increase of the current flowing through the power receiving end of the chip to be tested is prevented, and the risk of needle burning or chip burning is further avoided.

Description

Test probe card and test apparatus

Technical Field

The present disclosure relates to the field of chip testing technologies, and in particular, to a test probe card and a test apparatus.

Background

Integrated circuit chip testing is largely divided into wafer testing and finished chip testing, and plays an important role in product quality screening in the whole manufacturing process of integrated circuit chips. The main function of the integrated circuit chip test is to detect the failure and the bad effect of the integrated circuit chip in the manufacturing process.

In the test stage, the power supply of the integrated circuit chip needs to be detected and compensated, but not all the integrated circuit chips are designed with a power supply detection end and a ground signal detection end, so that reasonable ports are generally selected from the power supply end and the ground signal end of the integrated circuit chip as the power supply detection end and the ground signal detection end, and the number of ports of the power supply is reduced. Under the same current condition, the currents of the rest power supply end and the ground signal end are increased, and the risk of chip burning is increased.

Disclosure of Invention

The disclosure provides a test probe card and a test device, which can prevent a power supply end of a chip from being occupied during a chip test stage so as to prevent an increase of current flowing through the power supply end of the chip, and further avoid the risk of pin burning or chip burning.

According to one aspect of the present disclosure, there is provided a test probe card for transmitting electrical signals between a chip to be tested and a tester, the test probe card including a substrate and a power signal probe, the substrate including a power metal face for electrically connecting a power supply end and a power test end of the tester, one end of the power signal probe being electrically connected with the power metal face, the other end of the power signal probe being for electrically connecting a plurality of power receiving ends of the chip to be tested.

In one possible implementation of the disclosure, the test probe card further includes a ground signal probe, the substrate further includes a ground metal surface for electrically connecting with a first ground signal end and a ground test end of the tester, one end of the ground signal probe is electrically connected with the ground metal surface, and the other end of the ground signal probe is further electrically connected with a plurality of second ground signal ends of the chip to be tested.

In a possible implementation manner of the present disclosure, the substrate further includes a first connection element and a signal layer, and the power metal surface is electrically connected to the power test end through the first connection element and the signal layer.

In one possible implementation of the present disclosure, the substrate further includes a second connection element, and the ground metal surface is electrically connected to the ground test terminal through the second connection element and the signal layer.

In one possible implementation of the present disclosure, the power metal face and the ground metal face are stacked on different layers of the substrate.

In one possible implementation of the disclosure, the first connecting piece is connected with a first contact portion of the power supply metal surface, the second connecting piece is connected with a second contact portion of the ground metal surface, and the first contact portion and the second contact portion are oppositely arranged.

In one possible implementation of the present disclosure, the first connector and the second connector are disposed in parallel.

In one possible implementation of the present disclosure, the first contact is disposed in a middle region of the power metal face.

In one possible implementation of the present disclosure, the power metal face and the ground metal face are disposed on the same layer of the substrate, and the power metal face and the ground metal face are electrically isolated.

In one possible implementation manner of the present disclosure, if the chip to be tested includes a plurality of power supplies, each power supply is correspondingly provided with a plurality of power supply receiving terminals, the power supply metal surfaces are correspondingly provided in a plurality, and the plurality of power supply metal surfaces are electrically connected with the power supply receiving terminals of the plurality of power supplies in a one-to-one correspondence manner through the power supply signal probes.

In one possible implementation of the present disclosure, multiple power supply metal planes are stacked on different layers of a substrate.

In one possible implementation of the present disclosure, a plurality of power supply metal planes are disposed on the same layer of the substrate, and are electrically isolated from each other.

In a possible implementation manner of the present disclosure, the test probe card further includes a printed circuit board, and the power metal surface is electrically connected to the power supply end and the power test end through the printed circuit board, respectively.

In one possible implementation of the present disclosure, the test probe card further includes a printed circuit board, and the ground metal plane is electrically connected to the first ground signal terminal and the ground test terminal, respectively, through the printed circuit board.

According to another aspect of the present disclosure, there is also provided a test apparatus including a tester and the test probe card described in any one of the above embodiments.

Drawings

FIG. 1 is a schematic diagram of a test apparatus according to one embodiment of the present disclosure;

FIG. 2 is a schematic diagram of a test probe card according to one embodiment of the present disclosure;

FIG. 3 is a schematic diagram of a test probe card according to another embodiment of the present disclosure;

FIG. 4 is a schematic diagram of a test probe card according to another embodiment of the present disclosure;

FIG. 5 is a schematic diagram of a test probe card according to another embodiment of the present disclosure;

FIG. 6 is a schematic diagram of a test probe card according to another embodiment of the present disclosure;

fig. 7 is a schematic diagram of a test probe card according to another embodiment of the disclosure.

Icon:

10-testing equipment; 100-testing the probe card; 110-a substrate; 111-a power supply metal face; 112-ground metal surface; 113-a first connector; 114-a second connector; 115-a signal layer; 116-a first surface; 117-a second surface; 1113-a third connector; 1114-fourth connector; 120-power signal probe; 130-a printed circuit board; 131-a third surface; 132-a fourth surface; 140-ground signaling probes; 200-a tester; 210-a power supply end; 220-a power supply test terminal; 230-a first ground signal terminal; 240-ground test terminal; 300-chip to be tested; 310-a power receiving end; 320-second ground signal terminal.

Detailed Description

Before describing embodiments of the present disclosure, it should be noted that:

the terms "first," "second," and the like may be used in embodiments of the present disclosure to describe various features, but these features should not be limited by these terms. These terms are only used to distinguish one feature from another.

The term "and/or," "and/or" may be used in embodiments of the present disclosure to include any and all combinations of one or more of the associated features listed.

It will be understood that when two elements are described in a connected or communicating relationship, unless a direct connection or direct communication between the two elements is explicitly stated, connection or communication between the two elements may be understood as direct connection or communication, as well as indirect connection or communication via intermediate elements.

In order to make the technical solutions and advantages of the embodiments of the present disclosure more apparent, the following detailed description of exemplary embodiments of the present disclosure is provided in conjunction with the accompanying drawings, and it is apparent that the described embodiments are only some embodiments of the present disclosure, not all embodiments of which are exhaustive. It should be noted that, without conflict, the embodiments of the present disclosure and features of the embodiments may be combined with each other.

It is an object of the present disclosure to provide a test apparatus. The testing equipment is used for testing the chip to be tested. The chip to be tested may be a die (die) on a Wafer (Wafer) or a packaged chip. Therefore, the test equipment can perform wafer test on the chip to be tested, and can also perform chip test on the chip to be tested.

Referring to fig. 1, a test apparatus 10 provided in the present disclosure includes a tester 200 and a test probe card 100; the test probe card 100 is used for transmitting electrical signals between the chip 300 under test and the tester 200. The tester 200 may send a test signal to the chip 300 to be tested, and may also receive an electrical signal sent by the chip 300 to be tested based on the test signal to test, so as to determine whether the chip 300 to be tested is invalid or bad; the tester 200 may also supply power to the chip 300 under test and detect the voltage drop of the chip 300 under test.

It should be appreciated that the test probe card 100 is an important medium for connection of the tester 200 and the chip 300 under test, and transmission of electrical signals through the test probe card 100. The electrical signal may be an electrical signal to be tested generated by the chip to be tested 300, a power signal provided by the tester 200, or a test signal provided by the tester 200.

When the test device 10 provided by the disclosure performs power supply test on the chip 300 to be tested, the power supply end of the chip 300 to be tested is not occupied for the chip 300 to be tested which is not designed with the power supply end of the chip 300 to be tested, so that the power supply test function of the chip 300 to be tested can be realized, the current increase of the power supply end of the chip 300 to be tested is avoided, and the risk of needle burning or chip burning is avoided.

Referring to fig. 2, a schematic diagram of an exemplary structure of a test probe card 100 according to the present disclosure is shown. The test probe card 100 includes a substrate 110 and a power signal probe 120, the substrate 110 includes a power metal surface 111 for electrically connecting with a power supply end 210 and a power test end 220 of the tester 200, one end of the power signal probe 120 is electrically connected with the power metal surface 111, and the other end of the power signal probe 120 is electrically connected with a plurality of power receiving ends 310 of the chip 300 to be tested.

It should be appreciated that the substrate 110 is a small multi-layered printed circuit board for combining the power network, the ground network and the signal network of the chip 300 to be tested and connecting the power network, the ground network and the signal network to the tester 200 according to a certain design rule.

The power receiving end 310 of the chip 300 to be tested may be disposed on the surface of the chip 300 to be tested in the form of pads (bumps), and when the chip 300 to be tested is tested, the pins at the other end of the power signal probe 120 are in one-to-one direct contact with the power receiving ends 310 on the chip 300 to be tested, so as to realize electrical connection.

In the present disclosure, in a stage of detecting a power supply of a chip 300 to be tested, a plurality of power receiving ends 310 of the chip 300 to be tested are electrically connected to a power supply metal surface 111 on a substrate 110 through a power supply signal probe 120; the power supply end 210 of the tester 200 is electrically connected with the power supply metal surface 111, the power supply end 210 provides a power supply signal for the power supply metal surface 111, and the power supply metal surface 111 transmits the power supply signal to the power supply receiving end 310 of the chip 300 to be tested through the power supply signal probe 120, so that the power supply function of the chip 300 to be tested is realized; the power supply testing end 220 of the tester 200 is also electrically connected to the power supply metal surface 111, and the power supply metal surface 111 transmits a power supply signal to the power supply testing end 220 of the tester 200, and the tester 200 performs power supply detection according to the power supply signal.

It can be seen that, since the tester 200 obtains the power signal to be tested from the power metal face 111, the power signal to be tested is not obtained from the power receiving end 310. In the power test stage of the chip 300 to be tested, the power receiving end 310 is not occupied as a power detecting end, the power receiving end 310 receiving the power signal is not reduced, under the same current condition, the currents obtained by the power receiving end 310 in the power supply stage and the power test stage are kept consistent, the current increase condition does not exist between the power signal probe 120 and the chip 300 to be tested, and the burn-in or chip burn-in condition is avoided.

Referring to fig. 3, another exemplary structure of a test probe card 100 according to the present disclosure is shown. The test probe card 100 shown in fig. 3 is based on the test probe card 100 shown in fig. 2, the test probe card 100 further includes ground signal probes 140, the substrate 110 further includes a ground metal plane 112 for electrically connecting with a first ground signal terminal 230 and a ground test terminal 240 of the tester 200, one end of the ground signal probes 140 is electrically connected with the ground metal plane 112, and the other end of the ground signal probes 140 is further electrically connected with a plurality of second ground signal terminals 320 of the chip 300 to be tested.

The second ground signal terminals 320 of the chip 300 to be tested may be disposed on the surface of the chip 300 to be tested in the form of pads or bumps, and when the chip 300 to be tested is tested, the pins at the other end of the ground signal probe 140 are in one-to-one direct contact with the second ground signal terminals 320 on the chip 300 to be tested, so as to realize electrical connection.

With continued reference to fig. 3, the substrate 110 further includes a first connecting member 113 and a signal layer 115, and the power metal surface 111 is electrically connected to the power testing terminal 220 through the first connecting member 113 and the signal layer 115.

The substrate 110 further includes a second connection 114, and the ground metal surface 112 is electrically connected to the ground test terminal 240 through the second connection 114 and the signal layer 115.

In the present disclosure, the substrate 110 further includes a third connection 1113 and a fourth connection 1114, the power metal plane 111 is electrically connected to the power supply terminal 210 through the third connection 1113, and the ground metal plane 112 is electrically connected to the first ground signal terminal 230 through the fourth connection 1114.

It should be appreciated that the first connector 113 and the second connector 114 may be traces and the third connector 1113 and the fourth connector 1114 may be vias.

In the present disclosure, the first connection member 113 is connected to a first contact portion of the power metal face 111, and the second connection member 114 is connected to a second contact portion of the ground metal face 112.

Referring to fig. 3, a schematic positional relationship between the power metal surface 111 and the ground metal surface 112 provided in the present disclosure is shown, where the power metal surface 111 and the ground metal surface 112 are stacked on different layers of the substrate 110.

It should be appreciated that the substrate 110 is a multi-layer printed circuit board, including a power layer and a ground layer; the power metal face 111 is disposed in the power plane and the ground metal face 112 is disposed in the ground plane. The power layer and the ground layer may be two adjacent layers or two non-adjacent layers, and may be set according to actual situations, which is not limited herein. In order that the measured data of the power signal and the ground signal are closer to the chip 300 to be measured to actually obtain the power signal and the ground signal, the positions of the power layer and the stratum should be close to the chip 300 to be measured; the closer the power plane and the ground plane are located to the chip 300 under test, the less the trace impedance between the power plane and the ground plane and the chip 300 under test. The power metal surface 111 may be understood as a copper sheet on the power layer, and the ground metal surface 112 may be understood as a copper sheet on the ground layer.

In order to reduce crosstalk and noise of signals, the first contact portion and the second contact portion may be disposed opposite to each other in a structure in which the power metal face 111 and the ground metal face 112 are stacked on different layers of the substrate 110.

The first contact portion may be disposed in a middle region of the power metal face 111, and the second contact portion may be disposed in a corresponding middle region of the ground metal face 112. The middle region may be understood as a region near the midpoint of the power metal surface 111 and the ground metal surface 112, or may be a position near the midpoint of the power metal surface 111 and the ground metal surface 112.

And the first connector 113 and the second connector 114 are disposed in parallel in order to reduce crosstalk and noise of signals even further.

It should be appreciated that the first and second connectors 113, 114 may include multi-segment traces and that the first and second connectors 113, 114 may also include a plurality of vias. The number of the wirings and the vias is not limited herein, and may be set according to actual situations.

In the present disclosure, the first connection 113 and the second connection 114 are configured as differential wires, so that power test signal conduction can be performed between the power metal surface 111 and the ground metal surface 112 and the signal layer 115, and between the signal layer 115 and the power test terminal 220 and the ground test terminal 240.

In the present disclosure, the signal layer 115 is one layer of the substrate 110, and the power metal surface 111 cannot be directly electrically connected to the power test terminal 220 through the first connecting member 113 and the ground metal surface 112 cannot be directly electrically connected to the ground test terminal 240 through the second connecting member 114 due to the limitation of the structural space and other wiring of the substrate, so the signal layer 115 needs to be configured to specifically guide the power signal.

Referring to fig. 4, another schematic positional relationship between the power metal surface 111 and the ground metal surface 112 provided in the present disclosure is shown, in which the power metal surface 111 and the ground metal surface 112 are disposed on the same layer of the substrate 110, and the power metal surface 111 and the ground metal surface 112 are electrically isolated.

It should be appreciated that two separate copper sheets are provided on one of the layers of the substrate 110, one copper sheet being provided as the power metal face 111 and the other copper sheet being provided as the ground metal face 112.

In order to reduce crosstalk and noise of signals, under a structure in which the power metal face 111 and the ground metal face 112 are disposed on the same layer of the substrate 110, the first contact portion and the second contact portion should be disposed adjacently such that the first connection member 113 and the second connection member 114 are equally equidistant.

In another embodiment of the present disclosure, the chip 300 under test may include multiple power supplies, i.e., each power supply provides a different operating voltage for the chip 300 under test. As shown in fig. 5, each power source is provided with a power receiving end 310, a plurality of power metal surfaces 111 are provided correspondingly, and the plurality of power metal surfaces 111 are electrically connected with the power receiving ends 310 of the plurality of power sources in a one-to-one correspondence manner through the probes 120.

It should be understood that each power source is correspondingly allocated to one power source metal surface 111, that is, the power receiving end 310 of each power source is electrically connected to the corresponding power source metal surface 111.

For example, if the chip 300 to be tested includes 3 power supplies, which are a first power supply, a second power supply and a third power supply, the first power supply is correspondingly provided with a power receiving terminal a, the second power supply is correspondingly provided with a power receiving terminal b, and the third power supply is correspondingly provided with a power receiving terminal c; meanwhile, the number of the power supply metal surfaces 111 is correspondingly 3, namely a first power supply metal surface, a second power supply metal surface and a third power supply metal surface; in the present disclosure, a first power supply corresponds to a first power supply metal surface, a second power supply corresponds to a second power supply metal surface, and a third power supply corresponds to a third power supply metal surface. The first power supply metal surface is correspondingly and electrically connected with a power supply receiving end a of the first power supply through the probe 120, the second power supply metal surface is correspondingly and electrically connected with a power supply receiving end b of the second power supply through the probe 120, and the third power supply metal surface is correspondingly and electrically connected with a power supply receiving end c of the third power supply through the probe 120.

With continued reference to fig. 5, a plurality of power metal planes 111 may be stacked on different layers of the substrate 110. It should be appreciated that the substrate 110 includes multiple power layers with physical isolation between the power layers, and the multiple power metal planes 111 are disposed in the power layers of different layers.

In another embodiment of the present disclosure, as shown in fig. 6, a plurality of power metal planes 111 are disposed on the same layer of the substrate 110, and the plurality of power metal planes 111 are electrically isolated from each other. It should be appreciated that a plurality of individual copper sheets are provided on one layer of the substrate 110, with electrical isolation between each copper sheet.

With continued reference to fig. 3, the substrate 110 includes a first surface 116 and a second surface 117, where the first surface 116 and the second surface 117 are disposed opposite to each other. The first surface 116 is a surface close to the chip 300 to be tested, the second surface 117 is a surface far away from the chip 300 to be tested, and the layers of the power metal surface 111 and the ground metal surface 112 are close to the first surface 116.

Referring to fig. 7, the test probe card 100 further includes a printed circuit board 130, and the power metal surface 111 is electrically connected to the power supply end 210 and the power test end 220 through the printed circuit board 130.

Wherein, the power metal surface 111 is electrically connected with the power test terminal 220 through the first connecting member 113, the signal layer 115 and the printed circuit board 130; the power metal face 111 is also electrically connected to the power supply terminal 210 through the third connector 1113 and the printed circuit board 130.

It should be appreciated that the printed circuit board 130 is also a multi-layer printed circuit board 130 that functions to connect the substrate 110 with the tester 200 and to perform some circuit function. The printed circuit board 130 includes a third surface 131 and a fourth surface 132, where the third surface 131 and the fourth surface 132 are disposed opposite to each other, the third surface 131 is a surface close to the substrate 110, the fourth surface 132 is a surface close to the tester 200, i.e. the fourth surface 132 is a surface far away from the substrate 110.

With continued reference to fig. 7, the ground metal 112 is electrically connected to the first ground signal terminal 230 and the ground test terminal 240 through the printed circuit board 130, respectively.

Wherein the ground metal plane 112 is electrically connected to the ground test terminal 240 through the second connection member 114, the signal layer 115 and the printed circuit board 130; the ground plane 112 is also electrically connected to the first ground signal terminals 230 through the fourth connector 1114 and the printed circuit board 130.

In the present disclosure, the printed circuit board 130 may be communicatively connected to the substrate 110 by soldering and probing, although other connection methods may be used in other embodiments, and are not limited thereto.

The first ground signal terminal 230 of the tester 200 is connected to the ground plane 112 through the fourth connection member 1114 and the printed circuit board 130, and the power supply terminal 210 of the tester 200 is connected to the power plane 111 through the third connection member 1113 and the printed circuit board 130, so that a power supply loop can be formed. The power metal surface 111 is electrically connected with the power receiving end 310 of the chip 300 to be tested through the power signal probe 120, the ground metal surface 112 is electrically connected with the second ground signal end 320 of the chip 300 to be tested through the ground signal probe 140, and the power metal surface 111 and the ground metal surface 112 can transmit a power signal provided by the tester 200 to the chip 300 to be tested, so that power supply of the chip 300 to be tested is realized.

Similarly, the power test end 220 of the tester 200 is connected with the power metal surface 111 through the first connecting piece 113 and the signal layer 115, and the ground test end 240 of the tester 200 is connected with the ground metal surface 112 through the second connecting piece 114 and the signal layer 115, so as to form a test loop, and realize the test of the power signal.

In another embodiment, the test probe card 100 may further include a stiffener (not shown) for preventing warpage and deformation of the test probe card 100 when it is affected by external environmental temperature or stress.

For chip testing, the power metal face 111 and the ground metal face 112 may be disposed in the printed circuit board 130, and the tester 200 is electrically connected to the chip 300 to be tested through the printed circuit board 130. Electrically connecting a plurality of power receiving ends 310 of the chip 300 to be tested to the power metal surface 111 on the printed circuit board 130 through the power signal probe 120; the power supply end 210 of the tester 200 is electrically connected with the power supply metal surface 111, the power supply end 210 provides a power supply signal for the power supply metal surface 111, and the power supply metal surface 111 transmits the power supply signal to the power supply receiving end 310 of the chip 300 to be tested through the power supply signal probe 120, so that the power supply function of the chip 300 to be tested is realized; the power supply testing end 220 of the tester 200 is also electrically connected to the power supply metal surface 111, and the power supply metal surface 111 transmits a power supply signal to the power supply testing end 220 of the tester 200, and the tester 200 performs power supply detection according to the power supply signal.

Similarly, the first ground signal terminal 230 and the ground test terminal 240 of the tester 200 are electrically connected to the ground plane 112 through the printed circuit board 130, and the ground plane 112 is also electrically connected to the ground signal probes 140.

Due to the non-ideal conductive nature of the test probe card 100, the equivalent impedance presented by the test probe card 100 may cause the voltage of the electrical signal to drop, and the electrical signal obtained by the tester 200 may be less accurate.

To solve the above-mentioned problem, the tester 200 of the present disclosure can adjust the power signal to eliminate the problem that the equivalent impedance of the test probe card 100 causes the voltage drop of the electrical signal in case that the voltage drop of the electrical signal is detected. For example, if the tester 200 detects that the voltage drop exists in the electrical signal, the tester 200 may amplify the power signal provided to the chip 300 under test to perform voltage compensation on the electrical signal.

Based on the above scheme, in the power test stage of the chip to be tested, for the chip to be tested, which is not designed with the power detection pin and the ground detection pin, the tester obtains the power signal to be tested from the power metal surface and the ground metal surface, but not from the power receiving end and the second ground signal end. In the power test stage of the chip to be tested, the power receiving end and the second ground signal end are not occupied as a power detection pin and a ground detection pin, the power receiving end and the second ground signal end which receive the power signals are not reduced, under the same current condition, the currents obtained by the power receiving end and the second ground signal end in the power supply stage and the power test stage are consistent, the probe and the chip to be tested cannot have the condition of current increase, and further the condition of burning pins or chips is avoided.

While the preferred embodiments of the present disclosure have been described, additional variations and modifications in those embodiments may occur to those skilled in the art once they learn of the basic inventive concepts. It is therefore intended that the following claims be interpreted as including the preferred embodiments and all such alterations and modifications as fall within the scope of the disclosure.

It will be apparent to those skilled in the art that various modifications and variations can be made to the present disclosure without departing from the spirit or scope of the disclosure. Thus, the present disclosure is intended to include such modifications and alterations insofar as they come within the scope of the appended claims or the equivalents thereof.

Claims (15)

1. The utility model provides a test probe card for transmission signal of telecommunication between chip and the tester that awaits measuring, test probe card includes base plate and power signal probe, the base plate include be used for with the power metal covering that power supply end and power test end electricity of tester are connected, the one end of power signal probe with power metal covering electricity is connected, the other end of power signal probe be used for with a plurality of power receiving ends electricity of chip awaits measuring are connected.

2. The test probe card of claim 1, further comprising ground signal probes, the substrate further comprising a ground metal face for electrically connecting with a first ground signal terminal and a ground test terminal of the tester, one end of the ground signal probes being electrically connected with the ground metal face, the other end of the ground signal probes being further for electrically connecting with a plurality of second ground signal terminals of the chip under test.

3. The test probe card of claim 2, the substrate further comprising a first connector and a signal layer, the power metal face being electrically connected to the power test terminal through the first connector and the signal layer.

4. The test probe card of claim 3, the substrate further comprising a second connector, the ground metal plane being electrically connected to the ground test terminal through the second connector and the signal layer.

5. The test probe card of claim 4, the power metal face and the ground metal face being stacked on different layers of the substrate.

6. The test probe card of claim 5, the first connector being connected to a first contact of the power metal face, the second connector being connected to a second contact of the ground metal face, the first contact being disposed opposite the second contact.

7. The test probe card of claim 6, the first connector and the second connector being disposed in parallel.

8. The test probe card of claim 6, the first contact being disposed in a middle region of the power metal face.

9. The test probe card of claim 4, the power metal face and the ground metal face being disposed on a same layer of the substrate, and the power metal face and the ground metal face being electrically isolated.

10. The test probe card of claim 1, wherein if the chip to be tested includes a plurality of power supplies, each power supply is provided with a plurality of power receiving ends correspondingly, the plurality of power metal surfaces are provided in a plurality correspondingly, and the plurality of power metal surfaces are electrically connected with the power receiving ends of the plurality of power supplies in a one-to-one correspondence through the power signal probes.

11. The test probe card of claim 10, a plurality of said power metal planes being stacked on different layers of said substrate.

12. The test probe card of claim 10, a plurality of the power metal planes being disposed on a same layer of the substrate and being electrically isolated from each other.

13. The test probe card of claim 1, further comprising a printed circuit board, the power metal face being electrically connected to the power supply terminal and the power test terminal, respectively, through the printed circuit board.

14. The test probe card of claim 2, further comprising a printed circuit board, the ground metal face being electrically connected to the first ground signal terminal and the ground test terminal, respectively, through the printed circuit board.

15. A test apparatus comprising a tester and the test probe card of any one of claims 1-14.