CN117491738A

CN117491738A - Chip socket mounting contact resistance testing device and method

Info

Publication number: CN117491738A
Application number: CN202311441158.8A
Authority: CN
Inventors: 杨晓君; 袁飞; 徐宾; 陈杰
Original assignee: Haiguang Information Technology Chengdu Co ltd
Current assignee: Haiguang Information Technology Chengdu Co ltd
Priority date: 2023-10-31
Filing date: 2023-10-31
Publication date: 2024-02-02

Abstract

The embodiment of the invention discloses a device and a method for testing the mounting contact resistance of a chip socket, which relate to the technical field of semiconductor testing and comprise the following steps: the test main board is provided with at least a first wire, a second wire and a third wire; the test substrate is at least provided with four pins and is interconnected through a fourth wiring, and the third pin and the fourth pin are interconnected through a fifth wiring; the chip socket is positioned between the test main board and the test substrate; and the measurement analysis unit is respectively connected with the second ends of the first wire and the third wire, and is configured to send a test signal to the first wire and transmit a return test signal to test the contact resistance of the first terminal to the fourth terminal through the third wire. The invention is convenient for measuring the mounting contact resistance of the chip socket terminal, can evaluate the contact state of the chip socket terminal to a certain extent, and is suitable for the chip socket terminal test scene.

Description

Chip socket mounting contact resistance testing device and method

Technical Field

The invention relates to the technical field of semiconductor testing. In particular to a device and a method for testing the contact resistance of chip socket installation.

Background

A chip Socket (IC Socket) is a device for mounting a chip on a motherboard, and two ends of a chip Socket terminal are respectively in contact with a chip pin and a motherboard pad, so that a conductive effect is achieved between the chip and the motherboard. Good contact between the chip socket terminals and the motherboard, the chip is critical to ensure proper operation of the chip. Therefore, the measurement is used for effectively evaluating the contact state between the two ends of the chip socket terminal and the main board and the chip pins, and becomes a necessary link in the chip test.

Disclosure of Invention

In view of this, the embodiment of the invention provides a device and a method for testing the mounting contact resistance of a chip socket, which are convenient for measuring the mounting contact resistance of a chip socket terminal, so that the contact state of the chip socket terminal can be evaluated to a certain extent.

In order to achieve the aim of the invention, the following technical scheme is adopted:

an embodiment of the present application provides a testing device, including: the test main board comprises a test partition, wherein the test partition is at least provided with a first wire, a second wire and a third wire; the test substrate is at least provided with a first pin, a second pin, a third pin and a fourth pin, wherein the first pin is interconnected with the second pin through a fourth wiring, and the third pin is interconnected with the fourth pin through a fifth wiring; the chip socket is positioned between the test main board and the test substrate and comprises a first terminal, a second terminal, a third terminal and a fourth terminal; the first end of the first terminal is connected with the first end of the first wiring, and the second end of the first terminal is connected with the first pin; the first end of the second terminal is connected with the first end of the third terminal through the second wiring, the second end of the second terminal is connected with the second pin, the second end of the third terminal is connected with the third pin, the first end of the fourth terminal is connected with the first end of the third wiring, and the second end of the fourth terminal is connected with the fourth pin; and the measurement analysis unit is respectively connected with the second ends of the first wire and the third wire, and is configured to send a test signal to the first wire and transmit a return test signal to test the contact resistance of the first terminal to the fourth terminal through the third wire.

According to a specific implementation manner of the embodiment of the present application, the test partition and the test substrate are correspondingly arranged up and down, the first trace, the second trace and the third trace are printed on the test motherboard, and the first ends corresponding to the first end of the first trace, the two ends of the second trace and the first end of the third trace are respectively provided with a joint, and are correspondingly exposed on the surface of the test motherboard; the first ends of the first terminal, the second terminal, the third terminal and the fourth terminal are respectively connected to the corresponding joint points.

According to a specific implementation manner of the embodiment of the application, the second ends of the first terminal, the second terminal, the third terminal and the fourth terminal are respectively used for being connected with a chip pin, the thickness of the test substrate is consistent with that of the chip, the layout of the first pin, the second pin, the third pin and the fourth pin of the test substrate is consistent with that of the chip pin, and the physical structure and the electrical characteristics of the test partition are consistent with those of a chip main board.

According to a specific implementation manner of the embodiment of the application, a de-embedding partition is further arranged on the test motherboard, the de-embedding partition is separately arranged with the test partition, and the layout structure and the electrical characteristics of the de-embedding partition and the test partition are consistent.

According to a specific implementation manner of the embodiment of the present application, the de-embedding partition includes: the test device comprises a sixth wire and a seventh wire which is arranged on the same layer as the sixth wire, wherein two ends of the sixth wire and two ends of the seventh wire are respectively exposed on the surface of a test main board, the first end of the sixth wire and the first end of the seventh wire are arranged at intervals, the second end of the sixth wire and the second end of the seventh wire are arranged at intervals, the first end of the sixth wire and the first end of the seventh wire are interconnected through an eighth wire to form a de-embedded link, the length and the electrical characteristics of a test link formed by the de-embedded link and the first to fifth wires are approximately consistent, and the second end of the sixth wire and the second end of the seventh wire are respectively connected to the measurement analysis unit.

According to a specific implementation manner of the embodiment of the application, the apparatus further includes: the first data acquisition module, the first data acquisition module includes: the device comprises a first power supply, a first sampling resistor, a first data acquisition card and a second data acquisition card, wherein the output end of the first power supply is connected with the first end of the first sampling resistor, and the second end of the first sampling resistor is connected with the second ends of the first wiring and the third wiring; two terminals of the first data acquisition card are respectively connected with a first end and a second end of the first sampling resistor, and two terminals of the second data acquisition card are respectively connected with second ends of the first wiring and the third wiring; and, further comprising: a second data acquisition module, the second data acquisition module comprising: the output end of the second power supply is connected with the first end of the second sampling resistor, and the second end of the second sampling resistor is connected with the second ends of the sixth wiring and the seventh wiring; the two terminals of the third data acquisition card are respectively connected to the first end and the second end of the second sampling resistor, the two terminals of the fourth data acquisition card are respectively connected to the second ends of the sixth wiring and the seventh wiring, the second ends of the sixth wiring and the seventh wiring are respectively exposed on the surface of the test main board and are connected to the two terminals of the third data acquisition card, the second ends of the sixth wiring and the second ends of the seventh wiring are respectively connected to the two terminals of the fourth data acquisition card, and the configuration information of the two terminals of the third data acquisition card and the configuration information of the two terminals of the fourth data acquisition card are consistent; the first power supply is configured to provide an electrical signal to the test link; the second power supply is configured to provide an electrical signal to the de-embedded link; the first data acquisition card is configured to acquire a first voltage of the first sampling resistor, and the second data acquisition card is configured to acquire a second voltage of the test link; the third data acquisition card is configured to acquire a third voltage of the second sampling resistor, and the fourth data acquisition card is configured to acquire a fourth voltage of the de-embedded link; the first data acquisition card, the second data acquisition card, the third data acquisition card and the fourth data acquisition card are respectively configured to be connected with the measurement analysis unit; the measurement analysis unit is configured to calculate and obtain a first resistance of the test link according to the first voltage and the second voltage; calculating to obtain a second resistance of the de-embedded link according to the third voltage and the fourth voltage; and performing de-embedding calculation according to the first resistor and the second resistor, and measuring to obtain the mounting contact resistance of each terminal.

According to a specific implementation manner of the embodiment of the application, the apparatus further includes: the pressing buckle is configured to be pressed on the test substrate so as to simulate the compressive stress applied to the actual chip during operation.

In a second aspect, further embodiments of the present application provide a test method, the method including:

providing an electrical signal for testing to a first terminal of the chip socket via a first trace of the test motherboard; receiving test electric signals transmitted to a second end loop of the third wire through a first terminal, a first pin, a fourth wire, a second pin, a second terminal, a second wire, a third terminal, a third pin, a fifth wire, a fourth pin and a fourth terminal, wherein the test main board comprises a test partition, and the test partition is at least provided with the first wire, the second wire and the third wire;

the first pin, the second pin, the third pin and the fourth pin are arranged on the test substrate, the first pin and the second pin are interconnected through a fourth wiring, and the third pin and the fourth pin are interconnected through a fifth wiring; the chip socket is positioned between the test main board and the test substrate, and comprises a first terminal, a second terminal, a third terminal and a fourth terminal; the first end of the first terminal is connected with the first end of the first wiring, and the second end of the first terminal is connected with the first pin; the first end of the second terminal is connected with the first end of the third terminal through the second wiring, the second end of the second terminal is connected with the second pin, the second end of the third terminal is connected with the third pin, the first end of the fourth terminal is connected with the first end of the third wiring, and the second end of the fourth terminal is connected with the fourth pin; and calculating the mounting contact resistance of each terminal of the chip socket based on the received looped-back test electric signals.

According to a specific implementation manner of the embodiment of the present application, receiving the test electrical signal transmitted to the second end loop of the third wire via the first terminal, the first pin, the fourth wire, the second pin, the second terminal, the second wire, the third terminal, the third pin, the fifth wire, the fourth pin, the fourth terminal further includes: providing an electrical signal for de-embedding to the de-embedding link via a sixth trace of the test motherboard; the de-embedded link includes: a sixth wire, a seventh wire which is arranged on the test main board in the same layer with the sixth wire, and an eighth wire which interconnects a first end of the sixth wire and a first end of the seventh wire, wherein the length and the electrical characteristics of a test link formed by the de-embedded link and the first to fifth wires are approximately consistent; receiving an electrical signal for de-embedding of the second loop via the seventh trace; the received loopback electrical signal for testing is based on, and the mounting contact resistance of each terminal of the chip socket is calculated, comprising: and performing de-embedding calculation according to the test electric signal and the de-embedding electric signal to obtain the mounting contact resistance of each terminal of the chip socket.

According to a specific implementation manner of the embodiment of the application, when receiving the looped-back test electric signal, the method further includes: collecting a first voltage of a first sampling resistor, wherein the looped-back test electric signal is a second voltage; the first end of the first sampling resistor is connected with a first power supply, and the second end of the first sampling resistor is connected with the second end of the first wiring; and collecting a third voltage of the second sampling resistor when receiving the looped-back electrical signal for de-embedding, wherein the looped-back electrical signal for de-embedding is a fourth voltage; the first end of the second sampling resistor is connected with a second power supply, and the second end of the first sampling resistor is connected with the second end of the sixth wiring; performing the de-embedding calculation according to the electrical signal for testing and the electrical signal for de-embedding to obtain the mounting contact resistance of each terminal of the chip socket, including: calculating to obtain a first resistance of the test link according to the first voltage and the second voltage; calculating to obtain a second resistance of the de-embedded link according to the third voltage and the fourth voltage; and performing de-embedding calculation according to the first resistor and the second resistor, and measuring to obtain the mounting contact resistance of each terminal.

According to a specific implementation manner of the embodiment of the application, before the test electrical signal is provided to the first terminal of the chip socket via the first trace of the test motherboard, the method further includes: and applying compressive stress to the test substrate to simulate the compressive stress applied to the actual chip during operation.

Drawings

In order to more clearly illustrate the embodiments of the invention or the technical solutions in the prior art, the drawings that are required in the embodiments or the description of the prior art will be briefly described, it being obvious that the drawings in the following description are only some embodiments of the invention, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.

Fig. 1 is a schematic diagram of an embodiment of a mounting structure of a chip Socket on a test motherboard.

Fig. 2 is a schematic diagram of a Socket testing device according to an embodiment of the prior art.

Fig. 3 is a schematic structural diagram of a testing device according to an embodiment of the present application.

Fig. 4 is a schematic structural diagram of a test device according to another embodiment of the present application.

Fig. 5 is a schematic diagram of a test principle equivalent structure of a test device according to an embodiment of the present application.

FIG. 6 is a flow chart of a testing method according to an embodiment of the present application.

Detailed Description

Embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

It should be understood that the described embodiments are merely some, but not all, of the embodiments of the present application. All other embodiments, based on the embodiments herein, which would be apparent to one of ordinary skill in the art without making any inventive effort, are intended to be within the scope of the present application.

In order to help understand the innovative gist of the technical solution of the present application, some related prior art are briefly described as follows: the integrated circuit chip must take the main board as a carrier, the main board provides corresponding power supply, and meanwhile, the interface pins of each functional module of the chip are led out to the main board and are connected with peripheral circuits on the main board, so that an external environment for the chip to work is constructed, various functions of the chip are realized, and data operation and various task processing are completed.

Fig. 1 illustrates one of the main connection modes of the chip and the motherboard at present: a chip Socket 103 is mounted on the motherboard 105, and then the chip 102 is mounted into the chip Socket 103, and the chip needs to be pressed into place by the fastener 101. The pins 102 of the chip are connected to the chip package pads 104 on the motherboard via metal terminals 107 on the chip socket.

The chip socket has the advantages of capability of quickly replacing the chip, convenience in use and low system maintenance cost for application scenes such as chip verification, chip screening and the like. Because the two ends of the chip socket terminals are respectively contacted with the pins of the chip and the bonding pads of the main board, a critical conduction effect is achieved between the chip and the main board, and therefore, the condition of the chip operation can be greatly influenced by the contact between the terminals and the main board and between the terminals and the chip in the application process of the chip socket.

As shown in fig. 2, in some test schemes, a single socket terminal test scheme is adopted, and in general, focus is paid on the current capacity and high-frequency characteristics of the socket terminal, the test device comprises a test base 303 and a test board 302 capable of shifting the press-fit terminal, the press-fit force of the test board is used for simulating a real chip scene, and then a precision resistance measuring instrument is used for completing the resistance test of the terminal 301. However, the test device cannot cover the actual application scene of normal mounting and use of the chip, for example, due to the reasons of multiple mounting of the chip, multiple dismounting and use of the chip socket, chip solder ball deformation, chip socket terminal deformation and the like occur, so that poor contact is caused, and each Pin needle (i.e. the terminal in the text) of the chip socket cannot be pulled out one by one for testing. In addition, the actual pressing condition during the actual chip mounting cannot be simulated in practice.

In view of at least one of the above problems, fig. 3 shows a testing apparatus according to an embodiment of the present invention. Referring to fig. 3, a test apparatus 400 of the present application includes: the test motherboard 410, the test substrate 420, the chip socket 500, and the measurement analysis unit 430.

The test motherboard 410 includes a test partition 411, and the test partition 411 is at least provided with a first trace 41, a second trace 42, and a third trace 43. The first trace 41, the second trace 42, and the third trace 43 may be Microstrip lines (Microstrip lines) made of copper, and are disposed on a trace layer of the test motherboard 410, for example, the second trace 42 is formed on a surface of the test motherboard by copper sheets.

The test substrate 420 is at least provided with a first pin 421, a second pin 422, a third pin 423 and a fourth pin 424. The first pin 421 and the second pin 422 are interconnected by a fourth wire 425, and the third pin 423 and the fourth pin 424 are interconnected by a fifth wire 426. These traces are used to simulate the internal circuit traces of a real chip. The fourth trace 425 and the fifth trace 426 may be Strip conductors (Strip conductors) made of copper, which are disposed on the trace layer of the test substrate 420, and have a high current carrying capability and a low parasitic inductance.

The chip socket 500 (which is not part of the test apparatus and is a device under test, generally referred to as a DUT) is located between the test motherboard 410 and the test substrate 420 and includes a first terminal 501, a second terminal 502, a third terminal 503, and a fourth terminal 504. Wherein, a first end of the first terminal 501 is connected to a first end of the first trace 41, and a second end of the first terminal 501 is connected to the first pin 421; the first end of the second terminal 502 is connected with the first end of the third terminal 503 through the second trace 42, the second end of the second terminal 502 is connected with the second pin, the second end of the third terminal 503 is connected with the third pin 423, the first end of the fourth terminal 504 is connected with the first end of the third trace 43, and the second end of the fourth terminal 504 is connected with the fourth pin 424. These terminals may be resilient or rigid metal sheets or pins for making electrical contact in the chip socket 500; for example, a nickel gold plated spring metal sheet (Elastic Metal Sheet) is provided and routed inside the chip socket 500. Alternatively, needle-shaped conductors made of stainless steel are gold-plated to form a smooth circular contact surface for connection with corresponding traces on the test motherboard 410 or pins of the test board 420.

The measurement and analysis unit 430 is connected to the second ends of the first wire 41 and the third wire 43, and is configured to send a test signal to the first wire 41, and transmit a return test signal via the third wire 43 to test the contact resistance of each terminal (including the first terminal 501 to the fourth terminal 504) of the chip socket 500.

The contact resistance refers to the resistance generated on the contact surface between two conductors, and can reflect the contact quality condition and the conductivity between the conductors. The excessive contact resistance can influence the transmission of signals and currents, so that the problems of signal distortion, power loss, temperature rise and the like are caused. Therefore, for high-speed, high-frequency, high-density, low-power consumption, etc., application scenarios, it is required that the contact resistance between the chip socket terminals and the chip pins and circuit board pads is as small as possible.

According to the device for testing the mounting contact resistance of the chip socket, provided by the embodiment of the invention, the test main board 410, the test substrate 420, the chip socket 500 and the wiring and the terminals between the test main board and the chip socket are designed to form a test circuit, the test circuit is matched with the measurement analysis unit 430 to send and receive test signals, and the contact resistance of each terminal is tested based on the looped-back test signals, so that the measurement of the mounting contact resistance of the terminals of the chip socket 500 is conveniently realized; further, by measuring the calculated value of the contact resistance, the contact quality and the conductivity between the terminals of the chip socket 500 and the chip and the motherboard can be judged. So that the contact state of the terminals of the chip socket 500 can be evaluated to some extent.

Specifically, when the contact resistance is smaller, the contact between the terminal and the chip and the main board is good, the conductivity is good, and the chip can work normally; when the contact resistance is large, the poor contact between the terminal and the chip and the main board is indicated, the conductivity is poor, and the chip may be abnormal or not work. Specifically, a resistance threshold may be set, and a value smaller than the threshold is regarded as a smaller contact resistance, and a value larger than the threshold is regarded as a larger contact resistance. Of course, finer divisions may also be made to achieve a quantitative assessment of its state.

Referring to fig. 4, the test motherboard 410 is designed in two parts, namely a chip socket 500 contact resistance test backplane (corresponding to the test partition 411, also described below as a test partition) and a contact resistance test link de-inlay backplane (corresponding to the de-inlay partition 412). The test partition 411 is disposed vertically corresponding to the test substrate 420, and forms a receiving space therebetween for providing a mounting space for the chip socket 500.

The test section 411 is used to test the contact resistance of the chip socket 500. The test partition 411 has first, second and third traces 41, 42 and 43 printed thereon. The first end of the first trace 41 is provided with a first joint 44, the two ends of the second trace 42 are respectively provided with a second joint and a third joint, and the first end of the third trace 43 is provided with a fourth joint 45. These joints are each correspondingly exposed to the surface of the test motherboard 410 for connection with a first end of each terminal of the chip socket 500.

The chip socket 500 includes four terminals, namely a first terminal 501, a second terminal 502, a third terminal 503 and a fourth terminal 504, for electrically connecting the test motherboard 410 to the test substrate 420 thereon. A first terminal 501 has a first end connected to the first junction 44, a second terminal 502 has a first end connected to the second junction, a third terminal 503 has a first end connected to the third junction, and a fourth terminal 504 has a first end connected to the fourth junction 45. The bonding point may be a pad, and the shape of the pad may be circular, square, rectangular, or the like, which is not particularly limited in this embodiment.

In using the test apparatus, the test motherboard 410, the chip sockets 500 and the test substrate 420 are first connected together, so that the pins 301 of each chip socket 500 are connected with corresponding joints. The measurement and analysis unit 430 and the like are then connected to the test motherboard 410 via the second ends of the first trace 41 and the third trace 43. Then, a test signal such as a voltage is applied to the chip socket 500 through the first wire 41, and the test signal looped back through the third wire 43 is received, so that the contact resistance of the chip socket 500 is calculated.

The testing device provided by the embodiment of the invention can be suitable for testing the layout of the chip socket 500, and simultaneously, the contact resistance of a plurality of terminals of the chip socket 500 is tested, so that the testing efficiency is improved.

In addition, the testing device can adapt to chip sockets 500 with different specifications by replacing different testing substrates 420, so that the universality of the testing device is improved.

In some embodiments, the second ends of the first terminal 501, the second terminal 502, the third terminal 503 and the fourth terminal 504 are respectively used for connecting chip pins, the thickness of the test substrate 420 is consistent with the thickness of the chip, and the layout of the first pin 421, the second pin, the third pin 423 and the fourth pin 424 of the test substrate 420 is consistent with the layout of the chip pins, i.e. the test substrate 420 is used for simulating a dummy chip, and the package form of the pins and the size of the PCB (printed circuit board) include thicknesses consistent with those of a real chip substrate; the physical structure and electrical characteristics of the test partition 411 are consistent with those of the chip motherboard, including: the thickness of the motherboard in the test partition is consistent with the thickness of the chip motherboard actually applied by the tested chip socket 500, pad points of the mounting area of the chip socket 500, wiring layout, electrical characteristic requirements and the like, so as to ensure the accuracy of the test.

Specifically, the test substrate 420 may divide all pins into a plurality of test blocks corresponding to the chip, each test block is composed of a plurality of pins, for example, in fig. 2, four pins are used as one test block, each block forms a current path, a direct connection wire on the test substrate 420 needs to be completed, the test motherboard 410 is matched to complete interconnection of the current paths, and contact resistances of the chip sockets 500 corresponding to each block divided by block or parallel test are performed.

Of course, it should be understood that the technical solution provided in this embodiment is equally applicable to a case of using two pins as one test block, and the two pins can be interconnected to complete the direct connection wiring on the test substrate 420.

Referring to fig. 4, the test motherboard 410 is further provided with a de-embedding partition 412, the de-embedding partition 412 is separately arranged from the test partition 411, and the de-embedding partition 412 is consistent with the layout structure and the electrical characteristics of the test partition 411.

Specifically, the de-embedding partition 412 includes: the two ends of the sixth wire 417 and the two ends of the seventh wire 418 are respectively exposed on the surface of the test motherboard 410, the first end of the sixth wire 417 and the first end of the seventh wire 418 are spaced apart, the second end of the sixth wire 417 and the second end of the seventh wire 418 are spaced apart, the first end of the sixth wire 417 and the first end of the seventh wire 418 are interconnected by an eighth wire 419 to form a de-embedded link, the length and the electrical characteristics of the test link formed by the de-embedded link and the first to fifth wires are substantially identical, and the second end of the sixth wire 417 and the second end of the seventh wire 418 are respectively connected to the measurement analysis unit 430.

In this embodiment, the chip socket 500 is not mounted on the portion of the test motherboard 410 where the de-embedding partition 412 is located, pins (i.e., second ends of the sixth trace 417 and the seventh trace 418 described below) of current paths (which are corresponding to the test partition 411) going in and out of the chip socket 500 are connected by copper sheets through the eighth trace 419, and other portions including traces and the like are identical to the layout of the test partition 411 and are used for precisely de-embedding the trace resistance value of the test motherboard, thereby improving the test accuracy.

Second ends of the sixth trace 417 and the seventh trace 418 are provided with a junction 46, respectively. Wherein the joints 46 and 45 have the same size, shape, and the same number and positions of the nodes in the link, thereby ensuring the accuracy of the de-embedding test result.

In some embodiments, the sixth trace 417 is disposed in correspondence with the length and impedance of the first trace 41, the third trace 43 is disposed in correspondence with the length and impedance of the seventh trace 418, the length of the eighth trace 419 is substantially equal to the sum of the lengths of the second trace 42, the fourth trace, and the fifth trace, and the trace of the test link and the trace of the inlay link are made of the same material, and the trace shapes remain in correspondence, illustratively, each trace of the test link is disposed in a straight shape, and the trace of the inlay link is also disposed in a straight shape; the wiring of the test link is arranged in an S shape, and the wiring of the de-embedded link is also arranged in an S shape, so that the structural characteristics and the electrical characteristics of the test link and the de-embedded link are kept consistent, and the complete consistency is best achieved.

In addition, each wire of the test link is laid on the same layer, and correspondingly, each wire of the de-embedded link is laid on the same layer, so that the situation of wire crossing can be avoided.

In some embodiments, when the traces are laid out in different layers, vias (TSVs) are provided at the intersections if necessary to be cross-laid to reduce cross-talk and coupling.

Wherein in some embodiments, the de-embedded partition 412 and the test partition 411 are designed on the same PCB (Printed Circuit Board), and the two-part routing designs need to be identical. Thus, by integrating two boards on one board, PCB board materials and assembly costs can be saved. In addition, as the wiring of the de-embedded bottom plate is completely consistent with that of the test bottom plate, parasitic parameter differences caused by different PCB boards can be reduced to the greatest extent, and the test accuracy is improved.

Referring to fig. 5, the device further includes: a first data acquisition module 440, the first data acquisition module 440 comprising: the output end of the first power source 441 is connected with the first end of the first sampling resistor R2, and the second end of the first sampling resistor R2 is connected with the second ends of the first wire 41 and the third wire 43;

A current limiting resistor R1 is further disposed between the output end of the first power source 441 and the first sampling resistor R2, for current limiting protection. The first sampling resistor R2 can be integrated in the data acquisition module 440, or can be set independently, and the first sampling resistor R2 is a precision resistor, and because the precision resistor has high resistance accuracy, the accuracy is generally within ±1%, and even can reach 0.01%, so that the measurement accuracy and reliability of the sampling circuit can be improved.

Two terminals of the first data acquisition card 443 are respectively connected to the first end and the second end of the first sampling resistor R2, and two terminals of the second data acquisition card 444 are respectively connected to the second ends of the first trace 41 and the third trace 43;

and, further comprising: the second data acquisition module 450, which is identical in composition to the first data acquisition module 440 and the circuit, may also refer to fig. 5, except for the object of connection.

Specifically, the second data acquisition module 450 includes: the output end of the second power supply is connected with the first end of the second sampling resistor, and the second end of the second sampling resistor is connected with the second ends of the sixth wire 417 and the seventh wire 418;

The two terminals of the third data acquisition card are respectively connected to the first end and the second end of the second sampling resistor, the two terminals of the fourth data acquisition card are respectively connected to the second ends of the sixth wire 417 and the seventh wire 418, the second ends of the sixth wire 417 and the seventh wire 418 are respectively exposed on the surface of the test motherboard 410 and are connected to the two terminals of the third data acquisition card, the second ends of the sixth wire 417 and the second ends of the seventh wire 418 are respectively connected to the two terminals of the fourth data acquisition card, and the configuration information of the two terminals of the third data acquisition card and the two terminals of the fourth data acquisition card are consistent;

the first power source 441 is configured to provide an electrical signal to the test link;

the second power supply is configured to provide an electrical signal to the de-embedded link;

the first data acquisition card 443 is configured to acquire a first voltage of the first sampling resistor R2, and the second data acquisition card 444 is configured to acquire a second voltage of the test link;

the third data acquisition card is configured to acquire a third voltage of the second sampling resistor, and the fourth data acquisition card is configured to acquire a fourth voltage of the de-embedded link;

The first data acquisition card 443, the second data acquisition card 444, the third data acquisition card, and the fourth data acquisition card are respectively configured to be connected to the measurement analysis unit 430;

the measurement analysis unit 430 is configured to calculate a first resistance of the test link according to the first voltage and the second voltage; calculating to obtain a second resistance of the de-embedded link according to the third voltage and the fourth voltage; and performing de-embedding calculation according to the first resistor and the second resistor, and measuring to obtain the mounting contact resistance of each terminal.

Each data acquisition card may be a voltage value reading module integrated with a large number of ADCs (analog-to-digital conversion units), and may upload the read data to an upper computer (may be a measurement analysis unit 430) for analysis and calculation, where the data acquisition module also plays a role in providing power input for the circuit. The data acquisition module is mainly divided into three partial functional modules, namely a voltage source, an ADC data reading module and an upper computer data interface. The data acquisition module can be realized by using a data acquisition instrument, and can be designed into a plug-in card form for convenient connection so as to facilitate plug-in installation.

The chip socket 500 contact resistance test scheme provided in this embodiment can effectively measure the contact resistance value of the terminals of the chip socket 500, thereby evaluating the performance and reliability of the chip socket 500. The basic test principle is as follows: the contact resistance of the chip socket 500 is regarded as a resistor R1, the resistor R1 is connected into a circuit formed by the electronic component or the module, and the contact resistance value R1 of the terminal of the chip socket 500 can be obtained through embedding calculation by precisely sampling the voltage V1 and the current I at two ends of the resistor R2 according to ohm law. The precision sampling resistor R2 is a known fixed value.

For example, as shown in fig. 5, during testing, the inlet and outlet of the testing path of the chip socket 500, that is, the second ends of the first trace 41 and the third trace 43 are respectively connected with one data acquisition module, and each data acquisition module includes one power port, two ADC data acquisition cards and an upper computer data interface. The data acquisition module supplies power to the whole link through a power port, and the two ADC acquisition cards respectively acquire voltage V1 at two ends of the precision resistor R2 and voltage V2 of the test link.

The precision resistor R2 (i.e., the first sampling resistor R2) is connected to the test circuit of the chip socket 500, so as to form a terminal resistor test path of the chip socket 500. As shown in fig. 6, the interfaces 511 and 514 are the inlets and outlets of the test paths of the chip socket 500.

A second end of the sixth trace 417 of the data acquisition module and de-embedding partition 412 is connected to a second end of the seventh trace 418 to form a de-embedding path. The contact resistance value R1 of the terminals of the chip socket 500 is calculated by de-embedding the collected data, and the result is outputted to a display or stored in a memory.

Repeating the above testing steps, and sequentially connecting the precision resistor R2 with the testing loops formed by other terminals of the chip socket 500 to form different chip socket 500 terminal resistance testing paths. After each connection, the data acquisition module automatically performs a test and outputs or stores a corresponding result.

And according to all the test results, analyzing the contact resistance distribution condition of the terminals of the chip socket 500, and judging whether the chip socket 500 is abnormal or damaged. In this way, the contact resistance value of the terminals of the chip socket 500 can be measured rapidly and accurately, thereby comprehensively evaluating the performance and reliability of the chip socket 500.

The testing device provided by the embodiment of the invention supports two means of mounting the test substrate 420 (dummy chip) and mounting the real chip to complete the contact resistance test of the chip socket 500, and the testing principle is the same, so that the process suitable for the real chip test is not repeated.

In order to help understand the technical solution for testing the contact resistance of the chip socket 500 provided in the embodiment of the present invention, the test substrate 420 (dummy chip) and the chip socket 500 connection are described as follows: firstly, the test link construction task is completed according to the circuit connection relation between the test partition 411 and the de-embedded partition 412 and the data acquisition module, the voltage source respectively provides current for the resistor test link and the de-embedded partition 412, and then the ADC data acquisition card respectively reads out the voltage values of the precision sampling resistor R2 and the equivalent resistor of the chip socket 500 contact resistor test circuit. For the de-embedded partition 412 link and the tested partition 411 link, the following relations are derived according to ohm's law, respectively.

R _V2 (de-embedding partition 412) =v2×r2++v1; (equation 1)

R _V2 (test partition 411) =v2×r2++v1; (equation 2)

R (contact resistance) = [ RV2 (test floor) -RV2 (de-inlay floor) ]/N; (equation 3)

Wherein equation 1 is the resistance value of the trace link of the calculated de-embedded section 412. Equation 2 is a circuit resistance value obtained after calculating the test floor mounted chip socket 500 and the test substrate 420. The resistance value obtained by equation 2 contains three parts: the wiring resistance, the contact resistance across the terminals of the chip socket 500, and the resistance of the terminals of the chip socket 500 themselves. Therefore, only subtracting the trace resistance is required to obtain the contact resistance values of the terminals of the chip socket 500. N in equation 3 represents the number of terminals of the chip socket in the circuit, and the single contact resistance value of the single terminal of the chip socket 500 can be obtained by performing the de-embedding calculation according to equation 3 and taking the average value. Based on the resistance value, the contact condition of the chip socket 500 can be evaluated.

Further, as shown in fig. 6, a test for testing contact impedance for a real chip mounting is exemplarily described as follows: in the design, pins of the serial links of the input substrate and the output substrate of the link are selected on the substrate and are both selected as the ground pin VSS. Therefore, when the real chip is tested, the part of the circuit path after the interface 511 becomes the chip ground plane, V2 is the voltage of the whole chip ground plane, and the voltage value V2 (VSS) of the chip ground plane in the test environment is measured separately, and according to this voltage value, the contact impedance test of all the chip socket 500 terminals connected to the link of the real chip can be completed.

The method comprises the following steps: the length of the input and output links on the test floor is substantially the same as the routing layer, so the routing resistance of the test floor into the chip socket 500 is also substantially the same as the routing resistance of the chip socket 500 out to the pick-up card. Based on the design, after the real chip is mounted, the contact resistance of the chip socket 500 corresponding to one test link is calculated as follows:

RV2 (de-embedded partition 412) =v2×r2++v1; (equation 4)

R (contact resistance) = { [ V2-V2 (VSS) ]r2 ≡v1} -RV2 (de-inlay bottom) } 2; (equation 5)

Equation 4 is a calculation of the resistance value of the trace link on the de-embedded section 412. V2 in formula 5 is the voltage data read from the test backplane circuit, which includes half of the trace voltage and the voltage of the ground plane of the real chip, and the voltage difference between the two voltages is the contact resistance voltage of one chip socket 500 terminal during the real chip mounting. And performing de-embedding calculation according to the formula 5 to complete the contact resistance test of one chip socket 500 terminal of the real chip.

In some test schemes, for example, in the scheme shown in fig. 2, the lamination condition during the actual chip mounting cannot be completely simulated, so that the tested contact resistance data are more applied to the test requirements such as high-frequency electrical characteristics, and the problem caused by the abnormal contact resistance of the chip socket 500 in the chip verification stage cannot be solved.

To address the above, please continue with reference to fig. 3 or 4, in some embodiments, the apparatus further comprises: the press-fit buckle 450 is configured to be pressed on the test substrate 420 to simulate the compressive stress applied by the actual chip during operation, so as to simulate the press-fit condition of the actual chip during installation and improve the test accuracy.

Specifically, the pressing buckle 450 is provided with a through channel structure in the middle, and is designed to form a power input and a test link on the test substrate 420, and is directly connected to the measurement analysis unit 430 to form a test loop, so that a terminal-by-terminal test can be also realized. But this solution requires the design of special purpose fasteners.

The testing device provided by the embodiment of the invention is convenient for measuring the mounting contact resistance of the chip socket 500 terminal, so that the contact state of the chip socket 500 terminal can be estimated to a certain extent. Further, it is possible to simulate the testing of the contact resistance of the chip socket 500 under the pressing force of the actual chip socket 500 and the structural buckle, and determine whether the contact of the chip socket 500 is good according to the resistance value, thereby improving the testing accuracy.

Example two

As shown in fig. 6, a method for testing a contact resistance of a chip socket 500, the method includes:

s210, providing an electrical signal for testing to the first terminal 501 of the chip socket 500 via the first trace 41 of the test motherboard 410;

s220, receiving a test electrical signal transmitted to a second ring loop of the third wire 43 via the first terminal 501, the first pin 421, the fourth wire, the second pin, the second terminal 502, the second wire 42, the third terminal 503, the third pin 423, the fifth wire, the fourth pin 424, and the fourth terminal 504, wherein the test motherboard 410 includes a test partition 411, and the test partition 411 is at least provided with the first wire 41, the second wire 42, and the third wire 43; the first pin 421, the second pin, the third pin 423 and the fourth pin 424 are arranged on the test substrate 420, the first pin 421 and the second pin are interconnected through a fourth wire, and the third pin 423 and the fourth pin 424 are interconnected through a fifth wire; the chip socket 500 is located between the test motherboard 410 and the test substrate 420, and includes a first terminal 501, a second terminal 502, a third terminal 503, and a fourth terminal 504; wherein, a first end of the first terminal 501 is connected to a first end of the first trace 41, and a second end of the first terminal 501 is connected to the first pin 421; the first end of the second terminal 502 is connected with the first end of the third terminal 503 through the second wire 42, the second end of the second terminal 502 is connected with the second pin, the second end of the third terminal 503 is connected with the third pin 423, the first end of the fourth terminal 504 is connected with the first end of the third wire 43, and the second end of the fourth terminal 504 is connected with the fourth pin 424;

And S230, calculating the mounting contact resistance of each terminal of the chip socket 500 based on the received looped-back test electric signals.

The method provided in this embodiment may be cured in a certain manufactured product in the form of software to form the testing device shown in any one of the first embodiments, and when the user uses the product, the flow of the method described in the embodiment of the present application may be reproduced, and its implementation principle and technical effects are similar to those of the first embodiment, which are not repeated herein.

Specifically, in step S220, receiving the test electrical signal transmitted to the second loop of the third trace 43 via the first terminal 501, the first pin 421, the fourth trace, the second pin, the second terminal 502, the second trace 42, the third terminal 503, the third pin 423, the fifth trace, the fourth pin 424, and the fourth terminal 504 further includes:

providing a de-embedding electrical signal to the de-embedding link via a sixth trace 417 of the test motherboard 410; the de-embedded link includes: a sixth trace 417, a seventh trace 418 that is arranged on the test motherboard 410 in the same layer as the sixth trace 417, and an eighth trace 419 that interconnects a first end of the sixth trace 417 and a first end of the seventh trace 418, wherein the length and electrical characteristics of the de-embedded link and the test link formed by the first to fifth traces are substantially identical; a second end loop of the de-inlay electrical signal via the seventh trace 418 is received.

The calculating, based on the received looped-back electrical signal for testing, the mounting contact resistance of each terminal of the chip socket 500 includes: and performing de-embedding calculation according to the electrical signals for testing and the electrical signals for de-embedding to obtain the mounting contact resistance of each terminal of the chip socket 500.

The electrical signal for de-embedding is typically a voltage signal.

Specifically, when receiving the looped-back electrical signal for testing, the method further comprises: collecting a first voltage of a first sampling resistor R2, wherein the looped-back test electric signal is a second voltage; a first end of the first sampling resistor R2 is connected to the first power source 441, and a second end of the first sampling resistor R2 is connected to the second end of the first trace 41;

and collecting a third voltage of the second sampling resistor when receiving the looped-back electrical signal for de-embedding, wherein the looped-back electrical signal for de-embedding is a fourth voltage; the first end of the second sampling resistor is connected with a second power supply, and the second end of the first sampling resistor R2 is connected with the second end of the sixth wiring 417;

the performing the de-embedding calculation according to the electrical signal for testing and the electrical signal for de-embedding to obtain the mounting contact resistance of each terminal of the chip socket 500 includes:

Calculating to obtain a first resistance of the test link according to the first voltage and the second voltage; calculating to obtain a second resistance of the de-embedded link according to the third voltage and the fourth voltage;

and performing de-embedding calculation according to the first resistor and the second resistor, and measuring to obtain the mounting contact resistance of each terminal.

To be able to simulate the stressed state of the chip when actually applied, the test accuracy is improved, in some embodiments, before providing the test electrical signals to the first terminals 501 of the chip socket 500 via the first traces 41 of the test motherboard 410, the method further comprises: compressive stress is applied to the test substrate 420 to simulate the compressive stress experienced by an actual chip during operation.

In the drawings used in the description of the embodiments, in order to clearly show the components in the drawings, the components may be shown in different scales, and the number, shape, and size of the components described in the drawings, the relative positional relationship of the components, the mutual positions or the connection relationship of the components are not limited to the illustrated form, for example, four terminals illustrated in fig. 2 may be connected to each other, and similarly, four or more terminals may be connected to each other according to the test requirements.

In summary, the device and the method for testing the contact resistance of the chip socket 500 provided by the embodiment of the invention solve the problem that the prior art cannot cover the contact impedance test in the actual chip mounting and use scene; the structure-based adaptation screening can be realized when the new chip socket 500 is initially matched with a chip; further, fault problem positioning caused by abnormal contact in the application process of the chip socket 500 can be completed; the test scheme has strong universality, and is applicable to a metal structure needle, various pogo pin needles, various coaxial and non-coaxial terminals and the like.

It should be noted that, in this document, emphasis on the solutions described between the embodiments is different, but there is a certain interrelation between the embodiments, and when the solution of the present application is understood, the embodiments may be referred to each other; additionally, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or measurement control unit that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or measurement control unit 103. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude that an additional identical element is present in a process, method, article or measurement control unit comprising the element.

The foregoing is merely specific embodiments of the present application, but the scope of the present application is not limited thereto, and any changes or substitutions easily conceivable by those skilled in the art within the technical scope of the present application should be covered in the scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.

Claims

1. A test device, the test device comprising:

the test main board comprises a test partition, wherein the test partition is at least provided with a first wire, a second wire and a third wire;

the test substrate is at least provided with a first pin, a second pin, a third pin and a fourth pin, wherein the first pin is interconnected with the second pin through a fourth wiring, and the third pin is interconnected with the fourth pin through a fifth wiring;

the chip socket is positioned between the test main board and the test substrate and comprises a first terminal, a second terminal, a third terminal and a fourth terminal which are sequentially arranged; the first end of the first terminal is connected with the first end of the first wiring, and the second end of the first terminal is connected with the first pin; the first end of the second terminal is connected with the first end of the third terminal through the second wiring, the second end of the second terminal is connected with the second pin, the second end of the third terminal is connected with the third pin, the first end of the fourth terminal is connected with the first end of the third wiring, and the second end of the fourth terminal is connected with the fourth pin;

And the measurement analysis unit is respectively connected with the second ends of the first wire and the third wire, and is configured to send a test signal to the first wire and transmit a return test signal to test the contact resistance of the first terminal to the fourth terminal through the third wire.

2. The test device according to claim 1, wherein the test partition is disposed up and down with respect to the test substrate, the first trace, the second trace, and the third trace are printed on the test motherboard, and bonding points are disposed corresponding to a first end of the first trace, two ends of the second trace, and a first end of the third trace, respectively, and are correspondingly exposed on a surface of the test motherboard;

the first ends of the first terminal, the second terminal, the third terminal and the fourth terminal are respectively connected to the corresponding joint points.

3. The test device of claim 2, wherein the second ends of the first terminal, the second terminal, the third terminal and the fourth terminal are respectively used for connecting chip pins, the thickness of the test substrate is consistent with the thickness of the chip, the layout of the first pin, the second pin, the third pin and the fourth pin of the test substrate is consistent with the layout of the chip pins, and the physical structure and the electrical characteristics of the test partition are consistent with the physical structure and the electrical characteristics of a chip motherboard.

4. The test device of claim 1, wherein a de-embedding partition is further provided on the test motherboard, the de-embedding partition being provided separately from the test partition, the de-embedding partition being consistent with a layout structure and electrical characteristics of the test partition.

5. The test device of claim 4, wherein the de-embedded partition comprises: the test device comprises a sixth wire and a seventh wire which is arranged on the same layer as the sixth wire, wherein two ends of the sixth wire and two ends of the seventh wire are respectively exposed on the surface of a test main board, the first end of the sixth wire and the first end of the seventh wire are arranged at intervals, the second end of the sixth wire and the second end of the seventh wire are arranged at intervals, the first end of the sixth wire and the first end of the seventh wire are interconnected through an eighth wire to form a de-embedded link, the length and the electrical characteristics of a test link formed by the de-embedded link and the first to fifth wires are approximately consistent, and the second end of the sixth wire and the second end of the seventh wire are respectively connected to the measurement analysis unit.

6. The test device of claim 5, wherein a length of the eighth trace is approximately equal to a sum of lengths of the second trace, the fourth trace, and the fifth trace.

7. The test device of claim 5, wherein the device further comprises: the first data acquisition module, the first data acquisition module includes: the device comprises a first power supply, a first sampling resistor, a first data acquisition card and a second data acquisition card, wherein the output end of the first power supply is connected with the first end of the first sampling resistor, and the second end of the first sampling resistor is connected with the second ends of the first wiring and the third wiring;

two terminals of the first data acquisition card are respectively connected with a first end and a second end of the first sampling resistor, and two terminals of the second data acquisition card are respectively connected with second ends of the first wiring and the third wiring;

and, further comprising: a second data acquisition module, the second data acquisition module comprising: the output end of the second power supply is connected with the first end of the second sampling resistor, and the second end of the second sampling resistor is connected with the second ends of the sixth wiring and the seventh wiring;

the two terminals of the third data acquisition card are respectively connected to the first end and the second end of the second sampling resistor, the two terminals of the fourth data acquisition card are respectively connected to the second ends of the sixth wiring and the seventh wiring, the second ends of the sixth wiring and the seventh wiring are respectively exposed on the surface of the test main board and are connected to the two terminals of the third data acquisition card, the second ends of the sixth wiring and the second ends of the seventh wiring are respectively connected to the two terminals of the fourth data acquisition card, and the configuration information of the two terminals of the third data acquisition card and the configuration information of the two terminals of the fourth data acquisition card are consistent;

The first power supply is configured to provide an electrical signal to the test link;

the first data acquisition card is configured to acquire a first voltage of the first sampling resistor, and the second data acquisition card is configured to acquire a second voltage of the test link;

the first data acquisition card, the second data acquisition card, the third data acquisition card and the fourth data acquisition card are respectively configured to be connected with the measurement analysis unit;

the measurement analysis unit is configured to calculate and obtain a first resistance of the test link according to the first voltage and the second voltage; calculating to obtain a second resistance of the de-embedded link according to the third voltage and the fourth voltage;

8. The test device of claim 1, wherein the device further comprises: the pressing buckle is configured to be pressed on the test substrate so as to simulate the compressive stress applied to the actual chip during operation.

9. A method of testing, the method comprising:

providing an electrical signal for testing to a first terminal of the chip socket via a first trace of the test motherboard;

receiving test electric signals transmitted to a second end loop of the third wire through a first terminal, a first pin, a fourth wire, a second pin, a second terminal, a second wire, a third terminal, a third pin, a fifth wire, a fourth pin and a fourth terminal, wherein the test main board comprises a test partition, and the test partition is at least provided with the first wire, the second wire and the third wire;

the first pin, the second pin, the third pin and the fourth pin are arranged on the test substrate, the first pin and the second pin are interconnected through a fourth wiring, and the third pin and the fourth pin are interconnected through a fifth wiring; the chip socket is positioned between the test main board and the test substrate, and comprises a first terminal, a second terminal, a third terminal and a fourth terminal; the first end of the first terminal is connected with the first end of the first wiring, and the second end of the first terminal is connected with the first pin; the first end of the second terminal is connected with the first end of the third terminal through the second wiring, the second end of the second terminal is connected with the second pin, the second end of the third terminal is connected with the third pin, the first end of the fourth terminal is connected with the first end of the third wiring, and the second end of the fourth terminal is connected with the fourth pin;

And calculating the mounting contact resistance of each terminal of the chip socket based on the received looped-back test electric signals.

10. The method of testing of claim 9, wherein receiving the test electrical signal transmitted back to the second ring of the third trace via the first terminal, the first pin, the fourth trace, the second pin, the second terminal, the second trace, the third terminal, the third pin, the fifth trace, the fourth pin, the fourth terminal further comprises:

providing an electrical signal for de-embedding to the de-embedding link via a sixth trace of the test motherboard; the de-embedded link includes: a sixth wire, a seventh wire which is arranged on the test main board in the same layer with the sixth wire, and an eighth wire which interconnects a first end of the sixth wire and a first end of the seventh wire, wherein the length and the electrical characteristics of a test link formed by the de-embedded link and the first to fifth wires are approximately consistent;

receiving an electrical signal for de-embedding of the second loop via the seventh trace;

the received loopback electrical signal for testing is based on, and the mounting contact resistance of each terminal of the chip socket is calculated, comprising: and performing de-embedding calculation according to the test electric signal and the de-embedding electric signal to obtain the mounting contact resistance of each terminal of the chip socket.

11. The test method according to claim 9 or 10, wherein upon receiving the looped-back test electrical signal, the method further comprises: collecting a first voltage of a first sampling resistor, wherein the looped-back test electric signal is a second voltage; the first end of the first sampling resistor is connected with a first power supply, and the second end of the first sampling resistor is connected with the second end of the first wiring;

and collecting a third voltage of the second sampling resistor when receiving the looped-back electrical signal for de-embedding, wherein the looped-back electrical signal for de-embedding is a fourth voltage; the first end of the second sampling resistor is connected with a second power supply, and the second end of the first sampling resistor is connected with the second end of the sixth wiring;

performing the de-embedding calculation according to the electrical signal for testing and the electrical signal for de-embedding to obtain the mounting contact resistance of each terminal of the chip socket, including:

12. The method of testing of claim 9, wherein prior to providing the test electrical signals to the first terminal of the chip socket via the first trace of the test motherboard, the method further comprises: and applying compressive stress to the test substrate to simulate the compressive stress applied to the actual chip during operation.