CN117320492A

CN117320492A - Display panel and display device

Info

Publication number: CN117320492A
Application number: CN202311251706.0A
Authority: CN
Inventors: 祁一歌; 曾平川; 于天成; 黄高坤; 姚亮; 李兵川; 金广
Original assignee: BOE Technology Group Co Ltd; Chengdu BOE Optoelectronics Technology Co Ltd; Beijing BOE Technology Development Co Ltd
Current assignee: BOE Technology Group Co Ltd; Chengdu BOE Optoelectronics Technology Co Ltd; Beijing BOE Technology Development Co Ltd
Priority date: 2023-09-26
Filing date: 2023-09-26
Publication date: 2023-12-29

Abstract

The disclosure provides a display panel and a display device, and belongs to the technical field of display. The display panel comprises a drive backboard, a flattening layer, a pixel electrode layer, a pixel definition layer, a light-emitting functional layer and a public electrode layer which are sequentially stacked; the pixel electrode layer is provided with a plurality of pixel electrodes; the pixel defining layer has a plurality of pixel openings exposing at least a partial region of the pixel electrode; the pixel definition layer comprises an inorganic material structure and an organic material structure; the inorganic material structure and the organic material structure together form a partition structure between the pixel openings; the partition structure is provided with an internally tangent groove; the luminous functional layers are arranged in staggered layers at the partition structure. The display panel can effectively block the transverse electric leakage among the sub-pixels, and cannot cause the loss of luminous efficiency.

Description

Display panel and display device

Technical Field

The disclosure relates to the field of display technologies, and in particular, to a display panel and a display device.

Background

With the development of display technology, active matrix organic electroluminescent devices (AMOLED, active matrix organic light emitting device) are increasingly used in electronic devices. Due to the process, crosstalk is easily generated between adjacent sub-pixels of the AMOLED display product, for example, a driving current driving one sub-pixel may be laterally leaked to the adjacent sub-pixel, thereby causing the adjacent sub-pixel to emit light. This significantly reduces the display quality of the AMOLED display product.

Disclosure of Invention

The present disclosure is directed to overcoming the shortcomings of the prior art, and providing a display panel and a display device, which reduce lateral leakage between adjacent sub-pixels.

In order to achieve the above purpose, the present disclosure adopts the following technical scheme:

according to a first aspect of the present disclosure, there is provided a display panel including a driving back plate, a planarization layer, a pixel electrode layer, a pixel definition layer, a light emitting function layer, and a common electrode layer, which are sequentially stacked; wherein the pixel electrode layer has a plurality of pixel electrodes; the pixel defining layer has a plurality of pixel openings exposing at least a partial region of the pixel electrode;

the pixel definition layer comprises an inorganic material structure and an organic material structure; the inorganic material structure and the organic material structure together form a partition structure between the pixel openings; the partition structure is provided with an internally tangent groove;

the luminous functional layers are arranged in staggered layers at the partition structure.

In an exemplary embodiment of the present disclosure, the pixel defining layer includes an organic sub-film layer and an inorganic sub-film layer sequentially stacked on a side of the pixel electrode layer remote from the driving back plate; the inorganic sub-film layer is provided with partition openings between the pixel openings;

The organic sub-film layer is provided with a partition groove corresponding to the partition opening; the front projection of the partition opening on the driving backboard is positioned in the front projection of the partition groove on the driving backboard;

the light-emitting functional layer is arranged in a staggered mode between the part positioned in the partition groove and the part positioned on the surface of the inorganic sub-film layer.

In one exemplary embodiment of the present disclosure, the inorganic sub-film layer has a thickness of

The depth of the partition groove isThe width of the inscribed single-sided groove of the partition groove is

In an exemplary embodiment of the present disclosure, the pixel defining layer includes a first inorganic sub-film layer, an organic sub-film layer, and a second inorganic sub-film layer sequentially stacked on a side of the pixel electrode layer remote from the driving back plate; the second inorganic sub-film layer has partition openings between the pixel openings;

the organic sub-film layer is provided with a partition groove corresponding to the partition opening; the front projection of the partition opening on the driving backboard is positioned in the front projection of the partition groove on the driving backboard; the front projection of the partition groove on the driving backboard is positioned in the front projection of the first inorganic sub-film layer on the driving backboard;

The light-emitting functional layer is arranged in a staggered mode between the part positioned in the partition groove and the part positioned on the surface of the second inorganic sub-film layer.

In an exemplary embodiment of the present disclosure, the partition groove penetrates the organic sub-film layer in a normal direction of the driving back plate;

the depth of the partition groove is

In an exemplary embodiment of the present disclosure, the pixel defining layer includes a first organic sub-film layer, a second inorganic sub-film layer, and a second organic sub-film layer sequentially stacked on a side of the pixel electrode layer remote from the driving back plate; the second inorganic sub-film layer has partition openings between the pixel openings;

the first organic sub-film layer is provided with a partition groove corresponding to the partition opening; the front projection of the partition opening on the driving backboard is positioned in the front projection of the partition groove on the driving backboard;

the second organic sub-film layer is provided with a first auxiliary isolation groove corresponding to the isolation opening, and the orthographic projection of the isolation opening on the driving backboard is positioned in the orthographic projection of the corresponding first auxiliary isolation groove on the driving backboard.

In an exemplary embodiment of the disclosure, the pixel definition layer further includes a first inorganic sub-film layer, the first inorganic sub-film layer is located on a side of the pixel electrode layer away from the driving back plate, and the first organic sub-film layer is located on a side of the first inorganic sub-film layer away from the driving back plate;

The first inorganic sub-film layer is provided with a second auxiliary isolating groove corresponding to the isolating groove; the orthographic projection of the second auxiliary partition groove on the driving backboard is at least partially overlapped with the orthographic projection of the corresponding partition groove on the driving backboard.

In one exemplary embodiment of the present disclosure, the display panel further includes an auxiliary blocking structure between the pixel defining layer and the light emitting function layer, the auxiliary blocking structure being between the pixel openings; the top dimension of the auxiliary partition structure is larger than the bottom dimension of the auxiliary partition structure; the light emitting functional layer is discontinuous at the auxiliary partition structure.

In one exemplary embodiment of the present disclosure, the auxiliary partition structure is combined with the partition structure to have a height difference of no less than 2 micrometers.

In one exemplary embodiment of the present disclosure, the display panel further includes an organic buffer layer between the light emitting functional layer and the common electrode layer;

the organic buffer layer is positioned in the inscribed groove of the partition structure.

In an exemplary embodiment of the present disclosure, the light emitting functional layer is located at a portion of the partition groove not to exceed an opening of the partition groove;

The common electrode layer comprises a first part of the common electrode layer, and the orthographic projection of the first part of the common electrode layer on the driving backboard coincides with the orthographic projection of the opening of the partition groove on the driving backboard;

at least a partial area of the first part of the common electrode layer is positioned outside the partition groove.

According to a second aspect of the present disclosure, there is provided a display device including the display panel of any one of the above.

Drawings

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the disclosure and together with the description, serve to explain the principles of the disclosure. It will be apparent to those of ordinary skill in the art that the drawings in the following description are merely examples of the disclosure and that other drawings may be derived from them without undue effort.

Fig. 1 is a schematic structural diagram of a display panel according to an embodiment of the disclosure.

Fig. 2 is a schematic view showing a partial cross-sectional structure of a display panel according to an embodiment of the present disclosure.

Fig. 3 is a schematic diagram of a partial structure of a pixel layer according to an embodiment of the disclosure.

Fig. 4 is a schematic structural view of a light emitting element according to an embodiment of the present disclosure.

Fig. 5 is a schematic structural view of a light emitting element according to an embodiment of the present disclosure.

Fig. 6 is a schematic structural view of a light emitting element according to an embodiment of the present disclosure.

Fig. 7 is a schematic structural view of a light emitting element according to an embodiment of the present disclosure.

Fig. 8 is a schematic diagram of a partial structure of a pixel layer according to an embodiment of the disclosure.

Fig. 9-1 is a schematic diagram of a structure in which a T-layer isolation pillar is disposed on a planarization layer in the first related art.

Fig. 9-2 is a schematic diagram of an inverted trapezoidal optical isolation column structure disposed on a pixel defining layer according to a second related art.

Fig. 9-3 are diagrams of a green light emitting device of a stacked design in a low gray scale according to the related art.

Fig. 9-4 is an enlarged view of a portion of fig. 9-3.

Fig. 9-5 are spectral diagrams of blue light emitting devices of stacked designs at low gray scale in the related art.

Fig. 9-6 is an enlarged view of a portion of fig. 9-5.

Fig. 10-1 is a schematic structural diagram of a pixel defining layer according to a first embodiment of the present disclosure.

Fig. 10-2 is a schematic diagram illustrating a structure of forming a pixel electrode layer on a driving back plate according to a first embodiment of the present disclosure.

Fig. 10-3 are schematic views illustrating a structure of forming an organic sub-film layer on a pixel electrode layer according to a first embodiment of the present disclosure.

Fig. 10-4 are schematic structural views of an inorganic sub-film layer formed on an organic sub-film layer in a first embodiment of the present disclosure.

Fig. 11-1 is a spectrum diagram of a green light emitting device at a low gray scale in the first embodiment.

Fig. 11-2 is an enlarged view of a portion of fig. 11-1.

Fig. 11-3 are spectral diagrams of the blue light emitting device at low gray scale in the first embodiment.

Fig. 11-4 is an enlarged view of a portion of fig. 11-3.

Fig. 12-1 is a schematic view showing a structure of a pixel defining layer according to a second embodiment of the present disclosure.

Fig. 12-2 is a schematic view illustrating a structure of forming a pixel electrode layer on a driving back plate according to a second embodiment of the present disclosure.

Fig. 12-3 are schematic views illustrating a structure of forming a first inorganic sub-film layer on a pixel electrode layer according to a second embodiment of the present disclosure.

Fig. 12-4 are schematic structural views of an organic sub-film layer formed on a first inorganic sub-film layer in a second embodiment of the present disclosure.

Fig. 12-5 are schematic structural diagrams of forming a second inorganic sub-film layer on an organic sub-film layer in a second embodiment of the present disclosure.

Fig. 13-1 is a schematic structural diagram of a stacked device mounted on a mobile phone according to an example of the second embodiment of the present disclosure.

Fig. 13-2 is a schematic structural view of a laminated device mounted on a vehicle in an example of a second embodiment of the present disclosure.

Fig. 13-3 is a schematic view of a partition effect of a partition structure according to a second embodiment of the present disclosure.

Fig. 14-1 is a schematic view showing a structure of a pixel defining layer according to a third embodiment of the present disclosure.

Fig. 14-2 is a schematic view showing a structure of forming a pixel electrode layer on a driving back plate according to a third embodiment of the present disclosure.

Fig. 14-3 is a schematic structural diagram of a first inorganic sub-film layer, a first organic sub-film layer, and a second inorganic sub-film layer sequentially formed on a pixel electrode layer according to a third embodiment of the present disclosure.

Fig. 14-4 are schematic structural diagrams of a second organic sub-film layer formed on a second inorganic sub-film layer in a third embodiment of the present disclosure.

Fig. 15 is a schematic view showing a combination of a partition structure and an inverted trapezoidal auxiliary partition structure according to a fourth embodiment of the present disclosure.

FIG. 16 is a schematic view of a combination of a sandwich partition structure and an inverted trapezoidal auxiliary partition structure according to four embodiments of the present disclosure.

Fig. 17-1 is a spectral diagram of a stacked device green light emitting element with different depth of cut-off grooves at low gray scale in one embodiment of the present disclosure.

Fig. 17-2 is an enlarged view of a portion of fig. 17-1.

Fig. 18 is a schematic view showing a partial structure of an organic buffer layer in a partition structure according to an embodiment of the present disclosure.

Reference numerals illustrate:

AA. A display area; AE. An anode; APS1, first auxiliary barrier groove; APS2, second auxiliary barrier groove; BB. A peripheral region; electron blocking layers of BEBL, blue light emitting elements; BEML, blue light emitting element organic light emitting layer; B. a blue light emitting element; BUF, inorganic buffer layer; CE. A cathode; CFL, color film layer; CGL, charge generation layer; COML, common electrode layer; COML1, common electrode layer first portion; CVD1, first inorganic encapsulation layer; CVD2, a second inorganic encapsulation layer; DBP, drive backboard; DPTS, auxiliary partition structure; DRL, driving layer; an EBL, an electron blocking layer; EFL, light-emitting functional layer; EFU, luminous functional unit; EIL, electron injection layer; EILX, electron injection material layer; ELS, light-emitting stacked structure; an EML, an organic light emitting layer; ETL, electron transport layer; ETLX, electron transporting material layer; electron blocking layers of GEBL, green light emitting elements; an organic light emitting layer of a GEML, green light emitting element; G. a green light emitting element; GI. A gate insulating layer; GT, gate layer; HBL, hole blocking layer; HBLX, hole blocking material layer; HIL, hole injection layer; a layer of HILX and hole injecting material; an HTL, hole transport layer; HTLX, hole transporting material layer; ILD, interlayer dielectric layer; IJP, organic encapsulation layer; an LD, a light emitting element; NCGL, N-type charge generation layer; NCGLX, N-type charge generating material layer; OBL, organic buffer layer; PCGL, P-type charge generation layer; PCGLX, P-type charge generation material layer; a PDL, pixel definition layer; PDLA, organic sub-film layer; PDLA1, a first organic sub-film layer; PDLA2, a second organic sub-film layer; PDLB, inorganic sub-film layer; PDLB1, a first inorganic sub-membrane layer; PDLB2, a second inorganic sub-film layer; PE, pixel electrode; PEL, pixel electrode layer; PG and partition grooves; PIXL, pixel layer; PLN, planarization layer; PNL, display panel; PO, partition opening; PS, optical isolation columns; PTS, partition structure; PXO, pixel openings; QDL, quantum dot layer; REBL, electron blocking layer of the red light-emitting component; an organic light-emitting layer of REML, red light-emitting element; r, red light emitting element; SBT and substrate base plate; an SCL, semiconductor layer; SD, source drain metal layer; t, T layer separator column; TFE, film encapsulation layer; a TFT, a thin film transistor; TSL, touch functional layer.

Detailed Description

Example embodiments will now be described more fully with reference to the accompanying drawings. However, the exemplary embodiments can be embodied in many forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the example embodiments to those skilled in the art. The same reference numerals in the drawings denote the same or similar structures, and thus detailed descriptions thereof will be omitted. Furthermore, the drawings are merely schematic illustrations of the present disclosure and are not necessarily drawn to scale.

Although relative terms such as "upper" and "lower" are used in this specification to describe the relative relationship of one component of an icon to another component, these terms are used in this specification for convenience only, such as in terms of the orientation of the examples described in the figures. It will be appreciated that if the device of the icon is flipped upside down, the recited "up" component will become the "down" component. When a structure is "on" another structure, it may mean that the structure is integrally formed with the other structure, or that the structure is "directly" disposed on the other structure, or that the structure is "indirectly" disposed on the other structure through another structure.

The terms "a," "an," "the," "said" and "at least one" are used to indicate the presence of one or more elements/components/etc.; the terms "comprising" and "having" are intended to be inclusive and mean that there may be additional elements/components/etc. in addition to the listed elements/components/etc.; the terms "first," "second," and "third," etc. are used merely as labels, and do not limit the number of their objects.

The disclosed embodiments provide a display panel PNL, referring to fig. 1, including a display area AA and a peripheral area BB located at least one side of the display area AA, e.g., the peripheral area BB surrounds the display area AA. In the display area AA, the display panel PNL is provided with subpixels for display; in the peripheral area BB, the display panel PNL may not be provided with sub-pixels for display, or the sub-pixels provided are not used for displaying a picture.

In the embodiment of the present disclosure, the sub-pixel in the display panel PNL is a thin film type self-luminous light emitting element LD, for example OLED, PLED, QLED or the like. Further, the light emitting elements LD in the display area AA include a plurality of light emitting elements LD of different colors. For example, in the examples of fig. 3 and 8, the light emitting element LD includes a red light emitting element R for emitting red light, a blue light emitting element B for emitting blue light, and a green light emitting element G for emitting green light. It is understood that in other embodiments of the present disclosure, the light emitting elements LD in the display area AA may also be light emitting elements LD of only one color, or may also have light emitting elements LD of other colors (e.g., a yellow light emitting element for emitting yellow light, a cyan light emitting element for emitting cyan light, a white light emitting element for emitting white light, etc.).

In one embodiment of the present disclosure, referring to fig. 2, the display panel PNL may include a driving back plate DBP and a pixel layer PIXL, which are sequentially stacked, in which the light emitting element LD is disposed and the driving back plate DBP is used to drive the light emitting element LD in the pixel layer PIXL. The driving back plate DBP may drive the light emitting elements LD by active driving, or may drive the light emitting elements LD by passive driving.

In one embodiment of the present disclosure, referring to fig. 2, the driving back plate DBP includes a substrate base plate SBT and a driving layer DRL provided at one side of the substrate base plate SBT; the pixel layer PIXL is disposed on a side of the driving layer DRL away from the substrate SBT. The driving layer DRL is provided with a pixel driving circuit for driving the light emitting element LD; each light emitting element LD can emit light to display a picture under the drive of the pixel driving circuit. Further, the display panel PNL further includes a thin film encapsulation layer TFE located on a side of the pixel layer PIXL away from the driving back plate DBP, where the thin film encapsulation layer TFE can encapsulate and protect the pixel layer PIXL.

Alternatively, the substrate SBT may be a substrate of an inorganic material or a substrate of an organic material; of course, a composite substrate in which a base substrate of an inorganic material and a base substrate of an organic material are laminated may be used. For example, in some embodiments of the present disclosure, the material of the substrate base plate SBT may be a glass material such as soda lime glass, quartz glass, sapphire glass, or the like. In further embodiments of the present disclosure, the material of the substrate base SBT may be polymethyl methacrylate, polyvinyl alcohol, polyvinyl phenol, polyethersulfone, polyimide, polyamide, polyacetal, polycarbonate, polyethylene terephthalate, polyethylene naphthalate, or a combination thereof. In other embodiments of the present disclosure, the substrate SBT may also be a flexible substrate, for example the material of the substrate SBT may comprise polyimide.

Alternatively, in the driving layer DRL, any one of the pixel driving circuits may include a thin film transistor TFT and a storage capacitor. Further, the thin film transistor TFT may be selected from a top gate thin film transistor, a bottom gate thin film transistor, or a double gate thin film transistor; the material of the active layer of the thin film transistor may be an amorphous silicon semiconductor material, a low-temperature polysilicon semiconductor material, a metal oxide semiconductor material, an organic semiconductor material, a carbon nanotube semiconductor material or other types of semiconductor materials; the thin film transistor may be an N-type thin film transistor or a P-type thin film transistor.

It will be appreciated that the type between any two transistors in the individual transistors in the pixel drive circuit may be the same or different. Illustratively, in some embodiments, in one pixel driving circuit, a portion of the transistors may be N-type transistors and a portion of the transistors may be P-type transistors. Still further exemplary, in other embodiments, in one pixel driving circuit, the material of the active layer of the partial transistor may be a low temperature polysilicon semiconductor material, and the material of the active layer of the partial transistor may be a metal oxide semiconductor material. In some embodiments of the present disclosure, the thin film transistor is a low temperature polysilicon transistor. In other embodiments of the present disclosure, a portion of the thin film transistors are low temperature polysilicon transistors and a portion of the thin film transistors are metal oxide transistors.

Alternatively, the driving layer DRL may include a semiconductor layer SCL, a gate insulating layer GI, a gate layer GT, an interlayer dielectric layer ILD, a source drain metal layer SD, a planarization layer PLN, and the like stacked between the substrate SBT and the pixel layer PIXL. Each of the thin film transistors and the storage capacitor may be formed of a film layer such as a semiconductor layer SCL, a gate insulating layer GI, a gate layer GT, an interlayer dielectric layer ILD, a source drain metal layer SD, or the like. The positional relationship of each film layer can be determined according to the film layer structure of the thin film transistor. Further, the semiconductor layer SCL may be used to form a channel region of a transistor, and may also form part of a track or a conductive structure by conducting if necessary. The gate layer may be used to form one or more of scan lines, reset control lines, light emission control lines, etc., may be used to form a gate of a transistor, and may be used to form part or all of the electrode plates of the storage capacitor. The source-drain metal layer can be used for forming source-drain metal layer wires such as data wires, driving power supply voltage wires and the like, and can also be used for forming part of electrode plates of the storage capacitor. Of course, in other embodiments of the present disclosure, the driving layer DRL may further include other film layers as needed, for example, a light shielding layer between the semiconductor layer SCL and the substrate SBT, and the like. Any one of the film layers such as the semiconductor layer SCL, the gate layer GT, the source drain metal layer SD may be a plurality of layers, for example, the driving layer DRL may include two different semiconductor layers SCL, or include two or three source drain metal layers SD, or include two or three gate layers GT; accordingly, the insulating film layer (e.g., gate insulating layer GI, interlayer dielectric layer ILD, planarizing layer PLN, etc.) in the driving layer DRL may be increased or decreased adaptively, or a new insulating film layer may be added as needed.

Optionally, the driving layer DRL may further include a passivation layer, where the passivation layer may be disposed on a surface of the source drain metal layer SD away from the substrate SBT, so as to protect the source drain metal layer SD.

As an example, referring to fig. 2, the driving layer DRL may include an inorganic buffer layer BUF, a semiconductor layer SCL, a gate insulating layer GI, a gate layer GT, an interlayer dielectric layer ILD, a source drain metal layer SD, and a planarization layer PLN, which are sequentially stacked, and thus the thin film transistor formed is a top gate thin film transistor.

It is to be understood that the above example of a drive back plate DBP is only one possible way of driving the back plate DBP of an embodiment of the present disclosure. In other embodiments of the present disclosure, the driving back plate DBP may also be other structures, for example, the driving back plate DBP may also be a passive driving glass substrate, a silicon-based driving back plate, or the like.

Referring to fig. 2 and 3, the light emitting element LD in the pixel layer PIXL is a thin film type light emitting element, which may include two electrodes disposed in a stacked manner and a light emitting functional unit EFU interposed between the two electrodes. For example, referring to fig. 2, the pixel layer PIXL may include a pixel electrode layer PEL, a light emitting function layer EFL, and a common electrode layer COML, which are sequentially stacked. The pixel electrode layer PEL is provided with a plurality of pixel electrodes PE in a display area of the display panel; the portion of the light emitting function layer EFL connected to the pixel electrode PE serves as a light emitting function unit EFU of the light emitting element LD, and the common electrode layer COML serves as a common electrode electrically connected to the light emitting function units EFU of the respective light emitting elements LD.

Further, the pixel layer PIXL may further include a pixel defining layer PDL between the pixel electrode layer PEL and the light emitting function layer EFL. The pixel defining layer PDL has a plurality of through pixel openings provided in one-to-one correspondence with the plurality of pixel electrodes PE, and any one of the pixel openings exposes at least a partial region of the corresponding pixel electrode. For example, the pixel defining layer PDL covers the edge of the pixel electrode PE and exposes at least a part of the inner area of the pixel electrode PE, so that the pixel defining layer PDL can effectively define the actual effective area (the area directly connected to the light emitting functional unit EFU) of the pixel electrode PE, thereby defining the light emitting area and the light emitting area of the light emitting element LD. The light emitting function layer EFL covers at least the pixel electrode PE exposed by the pixel defining layer PDL. The common electrode layer COML may cover the light emitting function layer EFL in the display region. The pixel electrode PE and the common electrode layer COML supply carriers such as electrons, holes, and the like to the light emitting function layer EFL to cause the light emitting function layer EFL to emit light. The portion of the light emitting function layer EFL between the pixel electrode PE and the common electrode layer COML may be regarded as the light emitting function unit EFU. The pixel electrode PE, the common electrode layer COML, and the light emitting functional unit EFU form a light emitting element LD. One of the pixel electrode PE and the common electrode layer COML serves as an anode of the light emitting element LD, and the other serves as a cathode of the light emitting element LD.

In one example, the pixel electrode PE serves as an anode of the light emitting element LD, and the common electrode layer COML serves as a cathode of the light emitting element LD, for example, a magnesium-silver alloy is employed as a cathode of the light emitting element.

In one example, the pixel layer PIXL may further include an organic capping layer on a side of the common electrode layer COML remote from the driving back plate DBP.

It will be appreciated that the types of light emitting elements are different and the materials and film layers of the light emitting functional unit EFU are different.

For example, referring to fig. 4, when the light emitting element is an OLED, the light emitting functional unit EFU may include an organic light emitting layer EML, and may include one or more of a hole injection layer HIL, a hole transport layer HTL, an electron blocking layer EBL, a hole blocking layer HBL, an electron transport layer ETL, and an electron injection layer EIL. Further, the organic light emitting layer EML may include a light emitting layer host material and a light emitting layer guest material, which may be a fluorescent dopant or a phosphorescent dopant, and in particular, may be a thermally activated delayed fluorescent material. Referring to fig. 5, when the OLED adopts a stacked structure, a charge generation layer CGL may be further provided in the light emitting functional layer EFL.

For another example, referring to fig. 6, when the light emitting element is a QLED, the light emitting functional unit EFU may include a quantum dot layer QDL, and may include one or more of a hole injection layer HIL, an electron transport layer ETL, an electron blocking layer EBL, a hole blocking layer HBL, an electron transport layer ETL, and an electron injection layer EIL. Further, the quantum dot layer QDL may have quantum dot particles, and the quantum dot particles may be connected to each other through a surface modification group. Referring to fig. 7, when the QLED adopts a stacked structure, a charge generation layer CGL may also be provided in the light emitting functional unit EFU.

In the embodiments of the present disclosure, referring to fig. 4 to 7, the light emitting functional unit EFU may include one layer of the light emitting stack structure ELS, and may include a stacked multi-layer light emitting stack structure ELS. When the light emitting functional unit EFU includes the multi-layered light emitting stack structure ELS, a charge generation layer CGL may be disposed between adjacent two layers of the light emitting stack structures ELS. Wherein each light emitting stack structure ELS is provided with one or more light emitting layers, which may be any one of an organic light emitting layer EML or a quantum dot layer QDL.

In the examples of fig. 4 and 6, the light emitting functional unit EFU has a one-layer light emitting stack structure ELS. Referring to fig. 4 and 6, the light emitting element LD includes an anode AE, a light emitting stack structure ELS, and a cathode CE, which are sequentially stacked; the light emitting stacked structure ELS includes a hole adjusting layer, a light emitting layer (for example, an organic light emitting layer EML or a quantum dot layer QDL), and an electron adjusting layer which are sequentially stacked; the hole adjusting layer is located on the side of the light emitting layer close to the anode AE, and the electron adjusting layer is located on the side of the light emitting layer close to the cathode CE. The anode AE is used to inject holes into the light emitting layer through the hole adjusting layer, and the cathode CE is used to inject electrons into the light emitting layer through the electron adjusting layer. The hole adjusting layer and the electron adjusting layer are respectively used for adjusting injection efficiency and injection speed of holes and electrons injected into the light emitting layer, adjusting energy levels of the injected electrons and holes, improving balance of hole injection and electron injection, and further improving performance of the light emitting functional unit EFU, such as one or more of improving light emitting efficiency of the light emitting element LD, prolonging service life of the light emitting element LD, reducing power supply voltage of the light emitting element LD, etc.

The hole adjusting layer may include one or more layers of a hole injection layer HIL (a material of which may be doped with a P-type dopant using a hole transport material), a hole transport layer HTL, an electron blocking layer EBL, and the like, which are sequentially stacked in a direction from the anode AE to the light emitting layer. It is understood that in some examples, one or more of the film layers of the hole injection layer HIL, the hole transport layer HTL, the electron blocking layer EBL, etc. may be provided as a multilayer laminated structure, for example, the hole transport layer HTL may include a first type hole transport layer and a second type hole transport layer, etc. that are provided in a laminated manner.

The electron adjusting layer may include one or more of film layers such as an electron injection layer EIL, an electron transport layer ETL (for example, a mixture of an electron transport material and Liq may be used), a hole blocking layer HBL, and the like, which are stacked in this order in a direction from the cathode CE to the light emitting layer. It will be appreciated that in some examples, one or more of the electron injection layer EIL, electron transport layer ETL, hole blocking layer HBL, etc. film layers may be provided as a multilayer stack structure, for example the electron transport layer ETL may comprise a first electron transport layer and a second electron transport layer, etc. in a stack arrangement.

In the example of fig. 5 and 7, the light emitting functional unit EFU has a light emitting stack structure ELS in which a plurality of layers are stacked (a two-layer light emitting stack structure ELS is illustrated in fig. 5 and 7). Referring to fig. 5 and 7, the light emitting element LD includes an anode AE, a light emitting stack structure ELS, and a cathode CE, which are sequentially stacked. Wherein, any one of the light emitting stacked structures ELS includes a hole adjusting layer, a light emitting layer (for example, an organic light emitting layer EML or a quantum dot layer QDL), and an electron adjusting layer which are sequentially stacked, the hole adjusting layer is located at a side of the light emitting layer near the anode AE, and the electron adjusting layer is located at a side of the light emitting layer near the cathode CE.

Alternatively, the light emitting functional unit EFU may further include a charge generation layer CGL located between adjacent two light emitting stack structures ELS to improve efficiency of injecting electrons and holes into the adjacent two light emitting stack structures ELS. For example, the charge generation layer CGL includes an N-type charge generation layer NCGL and a P-type charge generation layer PCGL stacked between adjacent two light-emitting stack structures ELS; wherein the N-type charge generation layer NCGL is disposed adjacent to the electron modulation layer of one of the light emitting stack structures ELS for injecting electrons into the electron modulation layer of the light emitting stack structure ELS; the P-type charge generation layer PCGL is disposed adjacent to the hole adjustment layer of the other light-emitting stack structure ELS for injecting holes into the hole adjustment layer of the light-emitting stack structure ELS. In other words, the P-type charge generation layer PCGL is disposed on a side of the N-type charge generation layer NCGL away from the anode AE. Of course, it is understood that in other examples, the charge generation layer CGL may also include other structures.

It is understood that in some other embodiments of the present disclosure, the electron adjusting layer of the light emitting stack structure ELS may be omitted, or have other structures other than the electron injection layer EIL, the electron transport layer ETL, and the hole blocking layer HBL.

It is understood that in some other embodiments of the present disclosure, the hole adjusting layer of the light emitting stack structure ELS may be omitted, or have other structures other than the hole injection layer HIL, the hole transport layer HTL, and the electron blocking layer EBL.

It is understood that when a plurality of light emitting layers are provided in the light emitting stack structure ELS, colors of the plurality of light emitting layers may be the same or different, and kinds of the plurality of light emitting layers may be the same or different. For example, two light emitting layers are disposed in one light emitting stacked structure ELS, and the two light emitting layers may be a red organic light emitting layer EML and a green organic light emitting layer EML, respectively. For another example, two light emitting layers are disposed in one light emitting stacked structure ELS, and the two light emitting layers may be respectively a red organic light emitting layer EML and a red quantum dot layer QDL that are stacked.

It is understood that for any one of the light emitting stack structures ELS, it may be provided with a light emitting layer (e.g., a quantum dot layer QDL or an organic light emitting layer EML), and one or more of a hole injection layer HIL, an electron transport layer ETL, an electron blocking layer EBL, a hole blocking layer HBL, an electron transport layer ETL, and an electron injection layer EIL, or other film layers may be added as needed. Of course, in the light emitting stack structure ELS, one or more of the hole injection layer HIL, the electron transport layer ETL, the electron blocking layer EBL, the hole blocking layer HBL, the electron transport layer ETL, and the electron injection layer EIL may be omitted. For the two light emitting stack structures ELS of the same light emitting element LD, the film layer structures of the two light emitting stack structures ELS may be the same or different.

For example, in the example of fig. 8, three light emitting elements LD of different colors such as a red light emitting element R, a green light emitting element G, and a blue light emitting element B are provided on the display panel PNL; the light emitting functional unit EFU of each light emitting element LD includes a light emitting stack structure ELS, a charge generating layer CGL, and a light emitting stack structure ELS that are stacked. In this example, the light emitting stack structure ELS near the anode AE includes a hole injection layer HIL, a hole transport layer HTL, an electron blocking layer EBL (e.g., an electron blocking layer REBL of a red light emitting element, an electron blocking layer GEBL of a green light emitting element, or an electron blocking layer BEBL of a blue light emitting element), an organic light emitting layer EML (e.g., an organic light emitting layer REML of a red light emitting element, an organic light emitting layer GEML of a green light emitting element, or an organic light emitting layer BEML of a blue light emitting element), and a hole blocking layer HBL, which are sequentially stacked; in other words, the electron transport layer and the electron injection layer are omitted in the light emitting stack structure ELS. In this example, the light emitting stack structure ELS near the cathode CE includes a hole transport layer HTL, an electron blocking layer EBL (e.g., an electron blocking layer REBL of a red light emitting element, an electron blocking layer GEBL of a green light emitting element, or an electron blocking layer BEBL of a blue light emitting element), an organic light emitting layer EML (e.g., an organic light emitting layer REML of a red light emitting element, an organic light emitting layer GEML of a green light emitting element, or an organic light emitting layer BEML of a blue light emitting element), a hole blocking layer HBL, an electron transport layer ETL, and a hole injection layer HIL, which are stacked in this order; in other words, the hole injection layer is omitted in the light emitting stack structure ELS.

Referring to fig. 2, the thin film encapsulation layer TFE may be provided on a surface of the pixel layer PIXL remote from the substrate base plate SBT, which may include an inorganic encapsulation layer and an organic encapsulation layer alternately stacked. The inorganic packaging layer can effectively block external moisture and oxygen, and avoids aging of materials in the pixel layer PIXL caused by invasion of the moisture and the oxygen into the pixel layer PIXL. Alternatively, the edges of the inorganic encapsulation layer may be located at the peripheral region. The organic encapsulation layer is located between two adjacent inorganic encapsulation layers in order to achieve planarization and to attenuate stresses between the inorganic encapsulation layers. Wherein an edge of the organic encapsulation layer may be located between an edge of the display region and an edge of the inorganic encapsulation layer. Illustratively, the thin film encapsulation layer TFE includes a first inorganic encapsulation layer CVD1 (e.g., a silicon oxynitride layer), an organic encapsulation layer IJP (e.g., an organic layer formed using inkjet printing), and a second inorganic encapsulation layer CVD2 (e.g., a silicon nitride layer) laminated in this order on a side of the pixel layer PIXL remote from the substrate SBT. Of course, in other embodiments of the present disclosure, the display panel may not be provided with a thin film encapsulation layer, and the pixel layer may be encapsulated and protected in other manners.

In some embodiments of the present disclosure, referring to fig. 2, the display panel PNL may further include a touch functional layer TSL, and the touch functional layer TSL may be disposed on a side of the thin film encapsulation layer TFE away from the driving back plate DBP, so that the display panel PNL has a touch function.

In some embodiments of the present disclosure, referring to fig. 2, the display panel PNL may further include a color film layer CFL, which may be disposed on a side of the thin film encapsulation layer TFE away from the driving back plate DBP, so as to reduce reflection of ambient light and improve display quality.

In the embodiment of the present disclosure, for process reasons, for example, when an open mask process is used, a common material layer may exist in the light emitting functional layer EFL, and the common material layer may cover the area where the adjacent light emitting elements LD are located and the gaps between the light emitting elements LD, which allows the adjacent light emitting elements LD to be connected by the common material layer. For example, a common material layer may cover the display area AA while being applied to each of the light emitting functional units EFU, and a portion of the common material layer in each of the light emitting functional units EFU serves as a structural film layer (e.g., one of a hole injection layer HIL, a hole transport layer HTL, an electron blocking layer EBL, an N-type charge generation layer NCGL, a P-type charge generation layer PCGL, a hole blocking layer HBL, an electron transport layer ETL, an electron injection layer EIL, etc.) of the light emitting functional unit EFU.

For example, in the example of fig. 8, the light emitting functional layer EFL is provided with a hole injecting material layer HILX, a hole transporting material layer HTLX, a hole blocking material layer HBLX, an N-type charge generating material layer NCGLX, a P-type charge generating material layer PCGLX, an electron transporting material layer ETLX, an electron injecting material layer EILX, and the like. The hole injection material layer HILX covers the display area AA; the hole injection material layer HILX is located at a portion of each of the light emitting functional units EFU as the hole injection layer HIL of the light emitting functional unit EFU; the hole injection material layer HILX is a common material layer of the light emitting function layer EFL. The hole transport material layer HTLX covers the display area AA; the hole transport material layer HTLX is located at a portion of each light emitting functional unit EFU as the hole transport layer HTL of that light emitting functional unit EFU; the hole transport material layer HTLX is a common material layer of the light emitting functional layer EFL. The hole blocking material layer HBLX covers the display area AA; the hole blocking material layer HBLX is located at a portion of each light emitting functional unit EFU as a hole blocking layer HBL of the light emitting functional unit EFU; the hole blocking material layer HBLX is a common material layer of the light emitting functional layer EFL. The N-type charge generating material layer NCGLX covers the display area AA; the N-type charge generation material layer NCGLX is located at a portion of each of the light emitting function units EFU as the N-type charge generation layer NCGL of the light emitting function unit EFU; the N-type charge generating material layer NCGLX is a common material layer of the light emitting function layer EFL. The P-type charge generating material layer PCGLX covers the display area AA; the P-type charge generation material layer PCGLX is located at a portion of each light emitting function unit EFU as the P-type charge generation layer PCGL of the light emitting function unit EFU; the P-type charge generating material layer PCGLX is a common material layer of the light emitting function layer EFL. The electron transport material layer ETLX covers the display area AA; the electron transport material layer ETLX is located at a portion of each light emitting functional unit EFU as the electron transport layer ETL of that light emitting functional unit EFU; the electron transport material layer ETLX is a common material layer of the light emitting functional layer EFL. The electron injection material layer EILX covers the display area AA; the electron injection material layer EILX is positioned at a part of each light emitting function unit EFU and is used as an electron injection layer EIL of the light emitting function unit EFU; the electron injection material layer EILX is a common material layer of the light emitting function layer EFL.

It is to be understood that the common material layers illustrated in fig. 8 are merely examples of common material layers of embodiments of the present disclosure; in other embodiments of the present disclosure, other common material layers may be provided, or at least part of the common material layers illustrated in fig. 8 may be omitted.

However, when one light emitting element LD emits light by being supplied with a driving current, the driving current may leak laterally to the other light emitting element LD along the common material layer to cause the other light emitting element LD to emit light, which causes crosstalk between the adjacent light emitting elements LD.

Since the on-luminance voltage (corresponding driving voltage at luminance 1 nit) of the red light emitting element R is generally significantly smaller than that of the blue light emitting element B and the green light emitting element G, the low gray-scale crosstalk phenomenon is generally caused by light leakage accompanying red light in blue or green light when the blue or green light emitting element is lit, causing color shift.

In the related art, a design of isolation column can be used to reduce lateral leakage. In one strategy, referring to fig. 9-1, a T-layer spacer T may be formed on the planarization layer PLN. But this structure requires the introduction of an additional inorganic layer under the anode, resulting in a change in the surface topography of the anode and a sacrifice in the luminous efficiency. In another strategy, see fig. 9-2, inverted trapezoid-shaped optical isolation pillars PS are formed on the pixel definition layer PDL, which does not affect the anode morphology and the luminous efficiency, but the leakage blocking effect is generally only able to suppress but not eliminate lateral leakage, i.e. low gray scale crosstalk and color shift can still be observed in the stacked device product incorporating the inverted trapezoid-shaped optical isolation pillars PS.

Optionally, referring to fig. 9-3 and fig. 9-4, before and after introducing the T-layer isolation column T and the inverted trapezoid optical isolation column PS between adjacent pixels, the state of varying the crosstalk degree of green light and red light when the stacked device is lit in low gray scale single color is shown; referring to fig. 9-5 and fig. 9-6, before and after introducing a T-layer isolation column T and an inverted trapezoid optical isolation column PS between adjacent pixels, respectively, a state of varying degrees of blue-light crosstalk and red-light crosstalk when the stacked device is lit in a low gray scale single color; referring to table 1 below, the light emitting efficiency of the red light emitting element R and the blue light emitting element B is changed when the stacked device is lit in a single color with a low gray scale before and after introducing the T-layer spacer T and the inverted trapezoid optical spacer PS between adjacent pixels, respectively.

TABLE 1

In the embodiments of the present disclosure, as shown in fig. 10 to 18, the pixel electrode layer PEL has a plurality of pixel electrodes PE, and the pixel defining layer PDL has a plurality of pixel openings PXO exposing at least a partial area of the pixel electrodes PE; the pixel definition layer PDL includes an inorganic material structure and an organic material structure; the inorganic material structure and the organic material structure together form a partition structure PTS between the pixel openings PXO; the partition structure PTS is provided with an inscribed groove; the light emitting functional layers EFL are arranged in staggered layers at the position of the partition structure PTS.

In the embodiment of the disclosure, the partition structure PTS is disposed in the pixel defining layer PDL and has an inscribed groove; the luminous functional layer EFL is arranged in the partition groove in a staggered mode. When one light-emitting element is electrified to emit light, the current for driving the light-emitting element cannot be transversely transmitted to the adjacent light-emitting element through the light-emitting functional layer EFL, so that the adjacent light-emitting element is prevented from emitting light under the influence of the driving currents of other light-emitting elements, the light-emitting crosstalk is avoided, and the color shift caused by the light-emitting crosstalk is eliminated.

Compared with an inverted trapezoid partition structure, the partition structure PTS can more effectively block a transverse leakage channel; compared with the T-layer isolation column T positioned on the planarization layer PLN, the isolation structure PTS does not involve the design and process change of the film layer below the anode, so that the loss of luminous efficiency is not caused. Therefore, the partition structure PTS of the embodiment of the present disclosure can avoid the influence on the light emitting effect while ensuring the partition effect on the lateral current.

For example, in the display panel PNL with RGB light emitting elements, when the green light emitting element G and the blue light emitting element B are turned on, the red light emitting element R is prevented from emitting light due to the leakage of the adjacent green light emitting element G or blue light emitting element B, so as to prevent the low gray crosstalk phenomenon from occurring in the display panel PNL, thereby preventing color shift.

In one embodiment of the present disclosure, the partition structure PTS is disposed in the pixel defining layer PDL between adjacent pixels, and the partition structure PTS is disposed around the light emitting elements so as to maximally partition the lateral current path between the adjacent light emitting elements, such that the partition effect of the partition structure PTS on the lateral current is maximized.

The pixel definition layer PDL of the display panel PNL provided by the embodiment of the present disclosure is described in detail below with reference to the accompanying drawings:

in the first embodiment of the present disclosure, as shown in fig. 10-1, the pixel definition layer PDL includes an organic sub-film layer PDLA and an inorganic sub-film layer PDLB sequentially stacked on a side of the pixel electrode layer PEL away from the driving back plate DBP; the inorganic sub-film layer PDLB is provided with partition openings PO between the pixel openings PXO; the organic sub-film PDLA is provided with a partition groove PG corresponding to the partition opening PO; the front projection of the partition opening PO on the driving backboard DBP is positioned in the front projection of the partition groove PG on the driving backboard DBP; the light emitting functional layer EFL is arranged in a staggered manner between the part positioned in the partition groove PG and the part positioned on the surface of the inorganic sub-film layer PDLB. Therefore, when the EFL of the luminous functional layer is arranged in the staggered layer inside and outside the partition groove PG, the partition groove PG can effectively destroy the continuity of the EFL of the luminous functional layer deposited on the partition groove PG, and the blocking effect of transverse electric leakage is realized, so that low gray scale crosstalk is avoided.

In one example, as shown in fig. 10-1, the display panel PNL includes a planarization layer PLN, a pixel electrode layer PEL, and a pixel definition layer PDL sequentially stacked on the driving back plate DBP, the pixel definition layer PDL including an organic sub-film layer PDLA and an inorganic sub-film layer PDLB sequentially stacked; wherein the pixel electrode layer PEL has a plurality of pixel electrodes PE, and the pixel defining layer PDL has a plurality of pixel openings PXO exposing at least a partial area of the pixel electrodes PE; the inorganic sub-film layer PDLB is provided with partition openings PO between the pixel openings PXO, the organic sub-film layer PDLA is provided with partition grooves PG corresponding to the partition openings PO, and the space where the partition openings PO are located and the space where the partition grooves PG are located jointly form a partition structure PTS.

In one example, the PNL of the above example may be prepared as follows.

Alternatively, as shown in fig. 10-2, a planarization layer PLN is formed on the surface of the driving back plate DBP, for example, by coating and patterning an organic resin, the planarization layer PLN having pixel electrode connection holes exposing the output terminals of the pixel driving circuits.

Alternatively, as shown in fig. 10-2, a magnetron sputtering technique may be used to form the pixel electrode layer PEL on the surface of the planarization layer PLN, and the pixel electrode layer PEL may be patterned by a photolithography process to form the pixel electrode PE (e.g., a photoresist mask defines the pattern of the pixel electrode PE, and the pixel electrode layer PEL is etched by wet etching).

Alternatively, as shown in fig. 10-3, the organic sub-film PDLA having the pixel opening PXO exposing at least a partial area of the pixel electrode PE may be formed by first applying glue, curing, exposing, developing, or the like.

As shown in fig. 10-4, an inorganic sub-film layer PDLB is formed on the surface of the organic sub-film layer PDLA, and the inorganic sub-film layer PDLB is patterned by a photolithography process such that the inorganic sub-film layer PDLB exposes at least a partial area of the pixel electrode PE and has a partition opening PO. For example, a photoresist mask is used to define the pattern of the inorganic sub-film layer PDLB, and CF4 is used to etch the inorganic sub-film layer PDLB.

Then, as shown in fig. 10-1, the organic sub-film PDLA exposed by the barrier openings PO is etched using oxygen plasma to form barrier grooves PG. For example, the portions other than the partition openings PO are protected by a photoresist mask, and then the organic sub-film PDLA exposed by the partition openings PO is etched by oxygen plasma.

Alternatively, the thickness of the planarization layer PLN is 1.5 to 2 μm and the thickness of the organic sub-film layer PDLA is 1.5 to 2 μm. For example, the thickness of the planarizing layer PLN is 1.5 μm, and the thickness of the organic sub-film layer PDLA is 1.5 μm.

Optionally, the thickness of the inorganic sub-film layer PDLB isThe groove depth of the partition groove PG isThe width of the inscribed single-sided groove of the partition groove PG is +.>For example, the thickness of the inorganic sub-film PDLB is +.>The groove depth of the partition groove PG is +.>The width of the inscribed single-sided groove of the partition groove PG is +.>

Alternatively, the pixel electrode layer PEL includes sequentially stacked layersIndium tin oxide layer->Silver layer of (2)Is a sandwich structure of indium tin oxide layers. When the PEL is etched, the etching solution can be a mixed solution of 5% nitric acid HNO3+60% phosphoric acid H3PO4+ additive.

Optionally, the inorganic sub-film layer PDLB may be made of silicon oxynitride, siNx or SiOx.

The inventors have conducted a test on the display panel employing the first embodiment, and the test results are shown in fig. 11-1 to 11-4. It is further clear from the test results that the first embodiment can suppress or eliminate lateral leakage. In summary, in this embodiment, the partition structure PTS is disposed in the pixel defining layer PDL between adjacent pixels, so as to block the common layer, prevent charge from being transmitted laterally, inhibit lateral leakage, and effectively improve the problems of low gray-scale crosstalk and color shift between adjacent pixels with different light colors.

In the embodiment of the present disclosure, the partition structure PTS does not relate to the design of the film layer under the pixel electrode, does not sacrifice the light emitting efficiency, and the light emitting efficiency of the display panel PNL is shown in table 2 below.

TABLE 2

In a second embodiment of the present disclosure, as shown in fig. 12-1, the pixel definition layer PDL includes a first inorganic sub-film layer PDLB1, an organic sub-film layer PDLA, and a second inorganic sub-film layer PDLB2, which are sequentially stacked on one side of the pixel electrode layer PEL away from the driving back plate DBP; the second inorganic sub-film layer PDLB2 is provided with partition openings PO between the pixel openings PXO; the organic sub-film PDLA is provided with a partition groove PG corresponding to the partition opening PO; the front projection of the partition opening PO on the driving backboard DBP is positioned in the front projection of the partition groove PG on the driving backboard DBP; the front projection of the partition groove PG on the driving backboard DBP is positioned in the front projection of the first inorganic sub-film PDLB1 on the driving backboard DBP; the light emitting functional layer EFL is arranged in a staggered manner between the portion located in the partition groove PG and the portion located on the surface of the second inorganic sub-film layer PDLB 2. Therefore, on one hand, the groove depth of the isolation groove PG in the isolation structure PTS can be accurately controlled, the EFL of the luminous functional layer is isolated, and the continuity of the common electrode layer COML is not affected; on the other hand, the partition structure PTS can be suitable for laminated devices of different product types, and the partition requirement of the EFL of the luminous functional layers with different thicknesses is met by adjusting the film thickness difference value of the first inorganic sub-film layer PDLB1 and the organic sub-film layer PDLA, namely the groove depth of the partition groove PG.

In one example, as shown in fig. 12-1, the display panel PNL includes a planarization layer PLN, a pixel electrode layer PEL, and a pixel definition layer PDL sequentially stacked on the driving back plate DBP, the pixel definition layer PDL including a first inorganic sub-film layer PDLB1, an organic sub-film layer PDLA, and a second inorganic sub-film layer PDLB2 sequentially stacked; wherein the pixel electrode layer PEL has a plurality of pixel electrodes PE, and the pixel defining layer PDL has a plurality of pixel openings PXO exposing at least a partial area of the pixel electrodes PE; the second inorganic sub-film layer PDLB2 has partition openings PO between the pixel openings PXO, and the organic sub-film layer PDLA has partition grooves PG corresponding to the partition openings PO, and the space where the partition openings PO are located and the space where the partition grooves PG are located together form a partition structure PTS.

In one example, the PNL of the above example may be prepared as follows.

Alternatively, as shown in fig. 12-2, a planarization layer PLN is formed on the surface of the driving back plate DBP, for example, by coating and patterning an organic resin, the planarization layer PLN having pixel electrode connection holes exposing the output terminals of the pixel driving circuits.

Alternatively, as shown in fig. 12-2, a pixel electrode layer PEL may be formed on the surface of the display panel PNL using a magnetron sputtering technique, and patterned by a photolithography process to form a pixel electrode PE (e.g., a photoresist mask defines a pattern of the pixel electrode PE, and the pixel electrode layer PEL is etched by wet etching).

Alternatively, as shown in fig. 12-3, the first inorganic sub-film layer PDLB1 may be formed by a chemical vapor deposition technique, and the first inorganic sub-film layer PDLB1 may be patterned by a photolithography process such that the first inorganic sub-film layer PDLB1 has the pixel opening PXO exposing at least a partial area of the pixel electrode PE. For example, a photoresist mask is used to define the pattern of the first inorganic sub-film layer PDLB1, and CF4 is used to etch the first inorganic sub-film layer PDLB 1.

As shown in fig. 12 to 4, an organic sub-film PDLA covering the first inorganic sub-film PDLB1 is formed on the surface of the first inorganic sub-film PDLB1 by spreading, curing, exposing, developing, etc., the organic sub-film PDLA has pixel openings PXO exposing at least a partial area of the pixel electrode PE, and then the thickness of the organic sub-film PDLA between the pixel openings PXO is thinned by secondary exposure, developing, etc., so that the overall height of the pixel defining layer PDL is uniform.

Optionally, as shown in fig. 12-5, a second inorganic sub-film layer PDLB2 is formed on the surface of the organic sub-film layer PDLA, and the second inorganic sub-film layer PDLB2 is patterned through a photolithography process, so that at least a partial area of the pixel electrode PE is exposed by the second inorganic sub-film layer PDLB2 and has a partition opening PO. For example, the pattern of the second inorganic sub-film layer PDLB2 is defined using a photoresist mask, and the second inorganic sub-film layer PDLB2 is etched using CF 4.

As shown in fig. 12-1, the organic sub-film PDLA exposed by the barrier openings PO is then etched with oxygen plasma to form barrier grooves PG. For example, the portions other than the partition openings PO are protected by a photoresist mask, and then the organic sub-film PDLA exposed by the partition openings PO is etched by oxygen plasma. The first inorganic sub-film layer PDLB1 is used as an etching barrier layer to limit the depth of the partition groove PG and protect the planarization layer PLN.

Optionally, the second inorganic sub-film layer PDLB2 has a thickness ofFor example, the second inorganic sub-film layer PDLB2 has a thickness of +.>

Optionally, the materials of the first inorganic sub-film layer PDLB1 and the second inorganic sub-film layer PDLB2 may be silicon oxynitride, siNx or SiOx.

Alternatively, as shown in fig. 12-1, the partition groove PG penetrates the organic sub-film layer PDLA along the normal direction of the driving back plate DBP; the groove depth of the partition groove PG isThe width of the inscribed single-sided groove of the partition groove PG isFor example, the groove depth of the partition groove PG is +.>The width of the inscribed single-sided groove of the partition groove PG is

Alternatively, the groove depth of the partition groove PG is a difference in height between the organic sub-film layer PDLA and the first inorganic sub-film layer PDLB1, and the organic sub-film layer PDLA height is typically 1.5 μm. Therefore, the groove depth of the partition groove PG can be accurately regulated and controlled by adjusting the film thickness of the first inorganic sub-film PDLB1, and further the crosstalk prevention requirement of stacked devices carried by different types of products is met.

Fig. 13-1 shows a display panel PNL applied to a mobile phone product, in which the light emitting device includes a hole injection layer HIL (a material of which is a hole transport material HT doped P-type dopant PD)/a hole transport layer HTL 1/a hole blocking layer HBL 1/an n-type charge generation layer n-CGL (a material of which is an ETL doped metal such as Yb or Li)/a P-type charge generation layer P-CGL (a material of which is HT doped PD)/an HTL2/HBL 2/an electron transport layer ETL: liq, which are sequentially stacked from bottom to top.

Fig. 13-2 shows a display panel PNL applied to a vehicle-mounted display, in which the light emitting device includes a hole injection layer HIL (a material of which is a hole transport material HT doped P-type dopant PD)/a hole transport layer HTL 1/a hole blocking layer HBL 1/an n-type charge generation layer n-CGL (a material of which is an ETL doped metal such as Yb or Li)/a P-type charge generation layer P-CGL (a material of which is HT doped PD)/an HTL2/HBL 2/an electron transport layer ETL: liq, which are sequentially stacked from bottom to top.

The thicknesses of fig. 13-1 and 13-2 are different because: the low power consumption is required preferentially for the mobile phone, and the long service life is required preferentially for the vehicle-mounted display, so that the difference exists in film thickness in the EFL design of the luminous functional layers of the laminated devices carried by the mobile phone and the vehicle-mounted display.

Therefore, the thickness of different types of products is different, and thus the groove depth of the partition groove PG is required to be different.

In one example, the total film thickness of the light emitting functional layer EFL of the laminated device for a mobile phone is aboutThe total film thickness of the light-emitting functional layer EFL of the laminated device for vehicle use is about +.>Thus, the thickness of the first inorganic sub-film PDLB1 of the laminated device for the mobile phone is designed to be 1.4 mu m, so that the depth of the partition groove PG is controlled to be +.>The thickness of the first inorganic sub-film PDLB1 of the laminated device for vehicle is designed to be 1.365 mu m, so that the depth of the partition groove PG is controlled to be +.>

Alternatively, as shown in fig. 13-3, the light emitting functional layer EFL is located at a portion of the partition groove PG not exceeding the opening of the partition groove PG; the common electrode layer COML comprises a first part COML1 of the common electrode layer, and the orthographic projection of the first part COML1 of the common electrode layer on the driving backboard DBP coincides with the orthographic projection of the opening of the partition groove PG on the driving backboard DBP; at least a partial region of the common electrode layer first portion COML1 is located outside the partition groove PG. Thus, when the common electrode layer COML is deposited on the partition structure PTS, the continuity and the driving voltage of the common electrode layer COML are not affected.

In a third embodiment of the present disclosure, as shown in fig. 14-1, the pixel definition layer PDL includes a first organic sub-film layer PDLA1, a second inorganic sub-film layer PDLB2, and a second organic sub-film layer PDLA2 sequentially stacked on a side of the pixel electrode layer PEL away from the driving back plate DBP; the second inorganic sub-film layer PDLB2 has partition openings PO between the pixel openings PXO; the first organic sub-film PDLA1 is provided with a partition groove PG corresponding to the partition opening PO; the front projection of the partition opening PO on the driving backboard DBP is positioned in the front projection of the partition groove PG on the driving backboard DBP; the second organic sub-film layer PDLA2 has a first auxiliary barrier groove APS1 corresponding to the barrier opening PO, and the orthographic projection of the barrier opening PO on the driving back plate DBP is located within the orthographic projection of the corresponding first auxiliary barrier groove APS1 on the driving back plate DBP. On one hand, the thickness of the first organic sub-film PDLA1 can be controlled, so that the groove depth of the transverse incision structure can be accurately controlled; on the other hand, the overall height of the pixel definition layer PDL can be kept uniform; meanwhile, the height difference of the partition structure PTS is improved, and further the partition effect of the EFL is improved.

In one example, as shown in fig. 14-1, the display panel PNL includes a planarization layer PLN, a pixel electrode layer PEL, and a pixel definition layer PDL sequentially stacked on the driving back plate DBP, the pixel definition layer PDL including a first organic sub-film layer PDLA1, a second inorganic sub-film layer PDLB2, and a second organic sub-film layer PDLA2 sequentially stacked; the first organic sub-film PDLA1, the second inorganic sub-film PDLB2 and the second organic sub-film PDLA2 form a sandwich structure; the pixel electrode layer PEL has a plurality of pixel electrodes PE, and the pixel defining layer PDL has a plurality of pixel openings PXO exposing at least a partial area of the pixel electrodes PE; the second inorganic sub-film layer PDLB2 has partition openings PO between the pixel openings PXO, the first organic sub-film layer PDLA1 has partition grooves PG corresponding to the partition openings PO, the second organic sub-film layer PDLA2 has first auxiliary partition grooves APS1 corresponding to the partition openings PO, and the space where the partition openings PO are located, the space where the partition grooves PG are located, and the space where the first auxiliary partition grooves APS1 are located together form a partition structure PTS.

In one example, the PNL of the above example may be prepared as follows.

Alternatively, as shown in fig. 14-2, a planarization layer PLN is formed on the surface of the driving back plate DBP, for example, by coating and patterning an organic resin, the planarization layer PLN having pixel electrode connection holes exposing the output terminals of the pixel driving circuits.

Alternatively, as shown in fig. 14-2, a pixel electrode layer PEL may be formed on the surface of the display panel PNL using a magnetron sputtering technique, and patterned by a photolithography process to form a pixel electrode PE (e.g., a photoresist mask defines a pattern of the pixel electrode PE, and the pixel electrode layer PEL is etched by wet etching).

Alternatively, as shown in fig. 14-3, the first organic sub-film layer PDLA1 may be formed by spreading, curing, exposing, developing, or the like, the first organic sub-film layer PDLA1 having the pixel opening PXO exposing at least a partial area of the pixel electrode PE. And forming a second inorganic sub-film PDLB2 on the surface of the first organic sub-film PDLA1, and patterning the second inorganic sub-film PDLB2 through a photoetching process, so that the second inorganic sub-film PDLB2 exposes at least part of the area of the pixel electrode PE and is provided with a partition opening PO. For example, the pattern of the second inorganic sub-film layer PDLB2 is defined using a photoresist mask, and the second inorganic sub-film layer PDLB2 is etched using CF 4.

Then, as shown in fig. 14 to 4, a second organic sub-film layer PDLA2 covering the first organic sub-film layer PDLA1 and the second inorganic sub-film layer PDLB2 is formed on the surface of the second inorganic sub-film layer PDLB2 by a secondary exposure, development, or the like, the second organic sub-film layer PDLA2 having a pixel opening PXO exposing at least a partial area of the pixel electrode PE.

Then, as shown in fig. 14-1, oxygen plasma is used to etch the first organic sub-film layer PDLA1 and the second organic sub-film layer PDLA2 exposed by the partition opening PO, so as to form a partition groove PG and a first auxiliary partition groove APS1 of a transverse incision structure. For example, a photoresist mask is used to protect the portions except the partition openings PO, and then an oxygen plasma is used to etch the first organic sub-film layer PDLA1 and the second organic sub-film layer PDLA2 exposed by the partition openings PO.

Optionally, as shown in fig. 14-1, the pixel defining layer PDL further includes a first inorganic sub-film layer PDLB1, where the first inorganic sub-film layer PDLB1 is located on a side of the pixel electrode layer PEL away from the driving back plate DBP, and the first organic sub-film layer PDLA1 is located on a side of the first inorganic sub-film layer PDLB1 away from the driving back plate DBP; the first inorganic sub-film layer PDLB1 is provided with a second auxiliary partition groove APS2 corresponding to the partition groove PG; the orthographic projection of the second auxiliary isolating grooves APS2 on the driving backboard DBP at least partially coincides with the orthographic projection of the corresponding isolating grooves PG on the driving backboard DBP; the first inorganic sub-film layer PDLB1, the first organic sub-film layer PDLA1 and the second inorganic sub-film layer PDLB2 form a sandwich structure.

Alternatively, as shown in fig. 14-3, after the patterned pixel electrode PE is formed, a chemical vapor deposition technique may be first used to form the first inorganic sub-film layer PDLB1, and the first inorganic sub-film layer PDLB1 may be patterned by a photolithography process, so that the first inorganic sub-film layer PDLB1 has at least a partial area exposing the pixel electrode PE and has the second auxiliary isolation groove APS2. For example, a photoresist mask is used to define the pattern of the first inorganic sub-film layer PDLB1, and CF4 is used to etch the first inorganic sub-film layer PDLB 1.

As shown in fig. 14-3, the first organic sub-film layer PDLA1 is formed by gluing, curing, exposing, developing, etc., and the first organic sub-film layer PDLA1 has a pixel opening PXO exposing at least a partial area of the pixel electrode PE. And forming a second inorganic sub-film PDLB2 on the surface of the first organic sub-film PDLA1, and patterning the second inorganic sub-film PDLB2 through a photoetching process, so that the second inorganic sub-film PDLB2 exposes at least part of the area of the pixel electrode PE and is provided with a partition opening PO. For example, the pattern of the second inorganic sub-film layer PDLB2 is defined using a photoresist mask, and the second inorganic sub-film layer PDLB2 is etched using CF 4.

As shown in fig. 14-3, a second organic sub-film layer PDLA2 covering the first inorganic sub-film layer PDLB1, the first organic sub-film layer PDLA1, and the second inorganic sub-film layer PDLB2 is formed on the surface of the second inorganic sub-film layer PDLB2 by secondary exposure, development, or the like, the second organic sub-film layer PDLA2 having a pixel opening PXO exposing at least a partial area of the pixel electrode PE.

Then, as shown in fig. 14 to 4, the first organic sub-film layer PDLA1 and the second organic sub-film layer PDLA2 exposed by the partition opening PO are etched by using oxygen plasma to form a partition groove PG and a first auxiliary partition groove APS1 of a transverse incision structure. For example, a photoresist mask is used to protect the portions except the partition openings PO, and then an oxygen plasma is used to etch the first organic sub-film layer PDLA1 and the second organic sub-film layer PDLA2 exposed by the partition openings PO.

Optionally, when patterning the first inorganic sub-film layer PDLB1, the first inorganic sub-film layer PDLB1 may not form the second auxiliary isolation groove APS2, and after forming the first organic sub-film layer PDLA1 on the surface of the first inorganic sub-film layer PDLB1, the above process is continuously used to form the isolation groove PG and the first auxiliary isolation groove APS1 of the transverse incision structure. In this way, the first inorganic sub-film layer PDLB1 is used as an etching barrier layer to limit the depth of the isolation groove PG and protect the planarization layer PLN.

Optionally, the thicknesses of the first and second inorganic sub-film layers PDLB1 and PDLB2 areThe groove depth of the partition groove PG is +.>The width of the inscribed single-sided groove of the partition groove PG is +.>For example, the thickness of the inorganic sub-film PDLB is +. >The groove depth of the partition groove PG is +.>The width of the inscribed single-sided groove of the partition groove PG is +.>

Optionally, the pixel definition layer PDL height remains uniform.

Alternatively, the groove depth of the partition groove PG is the film thickness of the first organic sub-film layer PDLA 1. Therefore, the groove depth of the partition groove PG can be accurately controlled by controlling the film thickness of the first organic sub-film PDLA1, so that the crosstalk prevention requirement of stacked devices carried by different types of products is met.

Alternatively, the height variance of the partition structure PTS is 1.5 μm. Thus, the partition effect of the EFL of the light-emitting functional layer is remarkably improved.

In a fourth embodiment of the present disclosure, as shown in fig. 15 to 16, the display panel PNL further includes an auxiliary barrier structure DPTS between the pixel defining layer PDL and the light emitting function layer EFL, the auxiliary barrier structure DPTS being located between the pixel openings PXO; the top dimension of the auxiliary partition structure DPTS is larger than the bottom dimension of the auxiliary partition structure DPTS; the light emitting functional layer EFL is discontinuous at the auxiliary partition structure DPTS. Therefore, the combination of the partition structure PTS and the auxiliary partition structure DPTS can increase the difference between deposited film layers, and further improve the partition effect of the EFL.

In one example, as shown in fig. 15, after the partition structure PTS is formed, an inverted trapezoidal auxiliary partition structure DPTS is formed on the surface of the inorganic sub-film layer PDLB by gluing, curing, exposing, developing, or the like.

Optionally, the partition structure PTS and the auxiliary partition structure DPTS are both located in a pixel definition layer PDL region between adjacent pixels, and the partition structure PTS and the auxiliary partition structure DPTS are both located between adjacent pixel openings PXO.

In another example, as shown in fig. 16, after the partition structure PTS of the sandwich structure is formed, an inverted trapezoidal auxiliary partition structure DPTS is formed on the surface of the second organic sub-film layer PDLA2 by glue application, curing, exposure, development, or the like.

Optionally, the partition structure PTS and the auxiliary partition structure DPTS are both located between adjacent pixel openings PXO, and the partition structure PTS and the auxiliary partition structure DPTS both include an undercut structure.

Optionally, the height difference between the partition structure PTS and the auxiliary partition structure DPTS is more than or equal to 2 μm. Therefore, the partition effect of the EFL of the light-emitting functional layer is further improved.

In one embodiment of the present disclosure, as shown in fig. 18, the display panel PNL further includes an organic buffer layer OBL located between the light emitting function layer EFL and the common electrode layer COML, the organic buffer layer OBL being located within the partition groove PG. Thus, on one hand, the common electrode layer COML can be kept continuous while the light-emitting functional layer EFL is cut off; on the other hand, the organic buffer layer OBL is deposited in the region between adjacent pixels without affecting the light emission characteristics of the device.

In one example, as shown in fig. 18, the display panel PNL includes a planarization layer PLN, a pixel electrode layer PEL, a pixel definition layer PDL, a light emitting function layer EFL, and a common electrode layer COML, which are sequentially stacked on the driving back plate DBP, the pixel definition layer PDL including a first inorganic sub-film layer PDLB1, an organic sub-film layer PDLA, and a second inorganic sub-film layer PDLB2, which are sequentially stacked; wherein the pixel electrode layer PEL has a plurality of pixel electrodes PE, and the pixel defining layer PDL has a plurality of pixel openings PXO exposing at least a partial area of the pixel electrodes PE; the second inorganic sub-film layer PDLB2 has partition openings PO between the pixel openings PXO, the organic sub-film layer PDLA has partition grooves PG corresponding to the partition openings PO, the light emitting functional layers EFL and the organic buffer layers OBL are sequentially stacked in the partition grooves PG, and the common electrode layer COML is disposed in the partition openings PO.

In one example, the PNL of the above example may be prepared as follows.

Alternatively, as shown in fig. 18, after the partition grooves PG are formed, a light emitting function layer EFL may be formed on the surface of the pixel defining layer PDL by a vacuum evaporation technique, and at least a part of the area of the pixel defining layer PDL falls into the partition grooves PG. Then, an organic buffer layer OBL is formed on the surface of the EFL of the luminous functional layer which is exposed by the isolation opening PO by adopting a fine mask evaporation technology. Then, a common electrode layer COML is formed on the surfaces of the luminous functional layer EFL and the organic buffer layer OBL by adopting a vacuum evaporation technology.

Alternatively, the light emitting function layer EFL cannot be completely blocked when the blocking groove PG depth is equal to the light emitting function layer EFL thickness, and therefore, the blocking groove PG depth needs to be greater than the light emitting function layer EFL thickness.

Specifically, as shown in FIGS. 17-1 and 17-2, the light emitting function layer EFL of the laminated device for a mobile phone has a thickness of about 0.1 μm, and the low gray-scale crosstalk can be completely eliminated when the groove depth of the partition groove PG is 0.15. Mu.m. Therefore, the depth of the isolation groove PG is 0.05 μm larger than the thickness of the light emitting function layer EFL, the thickness of the common electrode layer COML is 0.015 μm, and the isolation groove is filled with an organic buffer layer OBL having a thickness of 0.05 μm by vapor deposition through a fine mask between the light emitting function layer EFL and the common electrode layer COML. In this way, the common electrode layer COML can be kept continuous while the light emitting function layer EFL is interrupted.

The disclosed embodiments also provide a display device including any one of the display panels described in the above display panel embodiments. The display device may be a smart phone screen, a tablet computer screen, a smart watch screen, or other types of display devices. Since the display device has any one of the display panels described in the above embodiments of the display panel, the display device has the same beneficial effects, and the disclosure is not repeated here.

Other embodiments of the disclosure will be apparent to those skilled in the art from consideration of the specification and practice of the disclosure disclosed herein. This application is intended to cover any adaptations, uses, or adaptations of the disclosure following, in general, the principles of the disclosure and including such departures from the present disclosure as come within known or customary practice within the art to which the disclosure pertains. It is intended that the specification and examples be considered as exemplary only, with a true scope and spirit of the disclosure being indicated by the following claims.

Claims

1. The display panel is characterized by comprising a driving backboard, a flattening layer, a pixel electrode layer, a pixel definition layer, a light-emitting function layer and a public electrode layer which are sequentially stacked; wherein the pixel electrode layer has a plurality of pixel electrodes; the pixel defining layer has a plurality of pixel openings exposing at least a partial region of the pixel electrode;

2. The display panel according to claim 1, wherein the pixel defining layer includes an organic sub-film layer and an inorganic sub-film layer sequentially stacked on a side of the pixel electrode layer away from the driving back plate; the inorganic sub-film layer is provided with partition openings between the pixel openings;

3. The display panel of claim 2, wherein the inorganic sub-film layer has a thickness of

4. The display panel according to claim 1, wherein the pixel defining layer includes a first inorganic sub-film layer, an organic sub-film layer, and a second inorganic sub-film layer which are sequentially stacked on a side of the pixel electrode layer away from the driving back plate; the second inorganic sub-film layer has partition openings between the pixel openings;

5. The display panel of claim 4, wherein the partition groove penetrates the organic sub-film layer in a normal direction of the driving back plate;

the depth of the partition groove is

6. The display panel according to claim 1, wherein the pixel defining layer includes a first organic sub-film layer, a second inorganic sub-film layer, and a second organic sub-film layer sequentially stacked on a side of the pixel electrode layer away from the driving back plate; the second inorganic sub-film layer has partition openings between the pixel openings;

7. The display panel of claim 6, wherein the pixel definition layer further comprises a first inorganic sub-film layer, the first inorganic sub-film layer being located on a side of the pixel electrode layer away from the drive back plate, and the first organic sub-film layer being located on a side of the first inorganic sub-film layer away from the drive back plate;

8. The display panel according to any one of claims 1 to 7, further comprising an auxiliary partition structure between the pixel defining layer and the light emitting function layer, the auxiliary partition structure being between the pixel openings; the top dimension of the auxiliary partition structure is larger than the bottom dimension of the auxiliary partition structure; the light emitting functional layer is discontinuous at the auxiliary partition structure.

9. The display panel of claim 8, wherein the auxiliary partition structure is combined with the partition structure at a height difference of not less than 2 microns.

10. The display panel according to claim 1, further comprising an organic buffer layer between the light emitting functional layer and the common electrode layer;

11. The display panel according to any one of claims 2 to 7, wherein the light-emitting function layer is located at a portion of the partition groove not to exceed an opening of the partition groove;

12. A display device comprising the display panel according to any one of claims 1 to 11.