CN117294808A - Image signal generator and generating method of DPHY and CPHY signal sharing interface - Google Patents
Image signal generator and generating method of DPHY and CPHY signal sharing interface Download PDFInfo
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- CN117294808A CN117294808A CN202311136130.3A CN202311136130A CN117294808A CN 117294808 A CN117294808 A CN 117294808A CN 202311136130 A CN202311136130 A CN 202311136130A CN 117294808 A CN117294808 A CN 117294808A
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- 230000007274 generation of a signal involved in cell-cell signaling Effects 0.000 claims 1
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N7/00—Television systems
- H04N7/01—Conversion of standards, e.g. involving analogue television standards or digital television standards processed at pixel level
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Abstract
The invention provides an image signal generator and a generating method of a shared interface of DPHY and CPHY signals, comprising the following steps: control chip, bridge piece and output interface; the control chip is used for providing image data and control signals for the bridge piece; the bridge chip is used for converting the image data into corresponding DPHY signals or CPHY signals according to the indication of the control signals; the bridge piece is connected with the output interface through a plurality of signal wires, and the characteristic impedance of each signal wire is a first preset value, so that the differential characteristic impedance between any two signal wires is a second preset value; the second preset value is determined according to the data transmission requirements of the CPHY signal and the DPHY signal so as to generate the DPHY signal or the CPHY signal through multiplexing of a bridge chip and an output interface; and the output interface is used for outputting the DPHY signal or the CPHY signal generated by the bridge chip. The invention enables the DPHY and CPHY data lines to be multiplexed, and reduces the overall cost of PG and the size of PG.
Description
Technical Field
The invention belongs to the field of signal transmission, and in particular relates to an image signal generator (Pattern Generator, PG) with a shared interface for DPHY and CPHY signals and a generating method.
Background
The mobile industry processor interface (Mobile Industry Processor Interface, MIPI) alliance is an organization that determines the standards for communication interfaces, and MIPI specifications determined by MIPI are widely used for communication between hosts and peripheral devices. The Physical (PHY) working group of the MIPI alliance developed CPHY, DPHY, MPHY three specifications for high-speed Physical layer design to support various application requirements; the DPHY standard is largely applied to the connection part of the application processor, the display screen and the camera, but with the increase of the pixels and the frame frequency of the camera and the display screen, the data transmission speed of the DPHY cannot meet the requirement. MPHY is a subsequent standard of DPHY, and has higher speed; the current latest standard is CPHY.
At present, the medium and small-sized screens have two main stream communication protocols, namely DPHY and CPHY. The DPHY and CPHY signals are generated by two mutually independent links in the PG which simultaneously supports the DPHY and the CPHY in the industry, and the DPHY signal output port and the CPHY signal output port are mutually independent and separated.
As shown in fig. 1, the control chip transmits the image data to the DPHY and CPHY bridge chips through two independent data channels, and then the DPHY and CPHY bridge chips transmit the received image data to the screen according to the protocol requirements of the DPHY and the CPHY. The PG structure is large in size, two sets of image output transmission channels are arranged inside the PG structure, the cost is high, and the PG structure is not convenient for customers to use.
Disclosure of Invention
Aiming at the defects of the prior art, the invention aims to provide an image signal generator and a generating method of a shared interface of DPHY and CPHY signals, and aims to solve the problems that two sets of bridge pieces and output interfaces are needed in the traditional PG, the structural size is large and the cost is high.
To achieve the above object, in a first aspect, the present invention provides an image signal generator of a common interface for DPHY and CPHY signals, including: control chip, bridge piece and output interface;
the control chip is used for providing image data and control signals for the bridge piece;
the bridge chip is used for converting the image data into corresponding DPHY signals or CPHY signals according to the indication of the control signals;
the bridge piece is connected with the output interface through a plurality of signal wires, and the characteristic impedance of each signal wire is a first preset value, so that the differential characteristic impedance between any two signal wires is a second preset value; the second preset value is determined according to the data transmission requirements of the CPHY signal and the DPHY signal, so that a plurality of signal wires can be multiplexed to generate and transmit the DPHY signal or the CPHY signal through multiplexing of a bridge chip and an output interface;
the output interface is used for outputting the DPHY signal or the CPHY signal generated by the bridge chip.
In an alternative example, a ground wrap may be used around each signal line to shield external interference.
In an alternative example, the first preset value is 50× (1±10%) ohm;
the second preset value is 100× (1±10%) ohm.
In an optional example, when the bridge chip generates the DPHY signal, every two signal lines in the plurality of signal lines form a LANE data line;
when the bridge piece generates CPHY signals, every three signal lines in the plurality of signal lines form a LANE data line.
In an alternative example, PIN PINs for transmitting the DPHY signal and the CPHY signal in the output interface are multiplexed.
In an alternative example, the image data and control signals are in the form of TTL signals.
In an alternative example, the plurality of signal lines are equal in length, and the characteristic impedance of the signal lines is regulated by the distance between the signal line and the ground line and the line width of the signal line.
Wherein, the equal length refers to that the length error is within a preset range or the absolute value of the error is smaller than the preset error value.
In a second aspect, the present invention provides an image signal generating method of a common interface for DPHY and CPHY signals, including the steps of:
connecting the bridge piece and the output interface through a plurality of signal wires, wherein the characteristic impedance of each signal wire is a first preset value, so that the differential characteristic impedance between any two signal wires is a second preset value; the second preset value is determined according to the data transmission requirements of the CPHY signal and the DPHY signal, so that a plurality of signal wires can be multiplexed to generate and transmit the DPHY signal or the CPHY signal through multiplexing of a bridge chip and an output interface;
the image data and the control signals are provided for the bridge slices, so that the bridge slices convert the image data into corresponding DPHY signals or CPHY signals according to the indication of the control signals, and the DPHY signals or the CPHY signals generated by the bridge slices are output through the output interface.
In an alternative example, the first preset value is 50× (1±10%) ohm;
the second preset value is 100× (1±10%) ohm.
In an optional example, when the bridge chip generates the DPHY signal, every two signal lines in the plurality of signal lines form a LANE data line;
when the bridge piece generates CPHY signals, every three signal lines in the plurality of signal lines form a LANE data line.
In an alternative example, the method further comprises the steps of:
PIN multiplexing for transmitting DPHY signal and CPHY signal in the control output interface.
In general, the above technical solutions conceived by the present invention have the following beneficial effects compared with the prior art:
the invention provides an image signal generator and a generating method of a shared interface of DPHY and CPHY signals, wherein differential pairs are not used when signal wires are routed, each signal wire is routed according to a single-ended characteristic impedance as a first preset value, so that the characteristic impedance difference between every two signal wires is a second preset value; the second preset value is determined according to the data transmission requirements of the industry on the CPHY signal and the DPHY signal, so that a plurality of signal wires can be multiplexed to generate and transmit the DPHY signal or the CPHY signal through multiplexing of a bridge chip and an output interface. In addition, the invention wraps and shields the signal wire around the signal wire by using the GND wire to solve the problem of external common-mode interference, thereby multiplexing the DPHY and the CPHY data wire and combining the CPHY signal and an external output interface of the DPHY signal into a whole. The invention reduces the specification requirement on the control chip, reduces the overall cost of PG and the size of PG, and only needs one set of wire rod turning plate from PG to the client screen body. The use experience is better.
Drawings
FIG. 1 is a diagram of the internal structure of a conventional PG;
fig. 2 is a diagram illustrating an internal structure of a PG according to an embodiment of the present invention;
fig. 3 is a flowchart of an image signal generating method of a DPHY and CPHY signal sharing interface according to an embodiment of the present invention.
Detailed Description
For convenience of understanding, the following explains and describes english abbreviations and related technical terms related to the embodiments of the invention.
Embodiments of the present invention will be described below with reference to the accompanying drawings in the embodiments of the present invention.
As shown in FIG. 2, the control chip is connected with the DPHY/CPHY bridge chip. The image data is transmitted to the CPHY/DPHY bridge chip only through a set of independent data channels, and the received image data is controlled to be transmitted to the same output interface according to the DPHY or CPHY protocol as required.
The bridge chip is preferably used for converting the transistor-transistor logic level (Transistor Transistor Logic, TTL) signals into DPHY or CPHY signals according to requirements. The TTL signal has lower requirement on the control chip, so that the control chip with lower cost can be selected.
Wherein the PIN PIN of the output interface is also common to DPHY and CPHY.
Specifically, each LANE data line of the DPHY signal is composed of P N two differential lines, and when the DPHY signal is transmitted in the industry, the differential characteristic impedance between the two signal lines is required to be about 100 ohms, and the differential wiring between P N is required to solve external common mode interference. Each Lane data line of the CPHY signal is composed of three lines A and B, and when the CPHY signal is transmitted in the industry, the differential characteristic impedance between any two lines of the three lines is required to be about 100 ohms. The high-speed signal line has high impedance requirements, and if the requirements are not met, the screen is not lightened or is different due to the fact that the signal quality is poor. The difference of the CPHY signal and the DPHY signal on the wiring requirement is that the former DPHY signal line and the former CPHY signal line can only be mutually independent, the two external interfaces are mutually independent, and the interior can only use one of two independent image signal transmission channels. In order to solve the problem, the invention adopts the multiplexing of the signal wires as shown in fig. 2, the differential pair is not used when the wires are routed, each signal wire is routed according to the single-ended characteristic impedance of about 50 ohms, so that the characteristic impedance difference between every two signal wires is about 100 ohms, and the problem of external common mode interference is solved by wrapping and shielding around the wires by GND. Therefore, the data lines of the CPHY signal and the DPHY signal can be multiplexed, and the CPHY and the DPHY of the external output interface can be combined into one.
As shown in fig. 2, taking 20 signal lines as an example, 20 signal lines are equal in length, 20 signal lines correspond to 20 output pins, and 2 signal lines form a LANE data line when DPHY signals are transmitted, which is 10LANE in total. When the 20 output pins corresponding to the same 20 signal lines transmit the CPHY signal, 3 signal lines form a LANE data line, which is 6 LANEs in total. Of which 2 are unused and in an idle state.
It should be noted that, in fig. 2, the CPHY/DPHY bridge piece and the CPHY/DPHY output interface are existing products; in the prior art, the CPHY/DPHY bridge chips in a set of image signal transmission channels can only be used as the CPHY bridge chips or the DPHY bridge chips, and multiplexing of the CPHY bridge chips and the DPHY bridge chips cannot be realized. Similarly, the CPHY/DPHY output interface in one set of image signal transmission channel can only be used as the CPHY output interface or the DPHY output interface, and multiplexing of the CPHY output interface and the DPHY output interface cannot be realized.
The invention reduces the specification requirement on the control chip, and reduces the overall cost of PG and the size of PG. Only one set of wire transfer plates from PG to the client screen is needed. The use experience is better.
Fig. 3 is a flowchart of an image signal generating method of a DPHY and CPHY signal sharing interface provided by an embodiment of the present invention; as shown in fig. 3, the method comprises the following steps:
s101, connecting a bridge piece and an output interface through a plurality of signal wires, wherein the characteristic impedance of each signal wire is a first preset value, so that the differential characteristic impedance between any two signal wires is a second preset value; the periphery of each signal wire is wrapped by a ground wire so as to shield external interference; the second preset value is determined according to the data transmission requirements of the CPHY signal and the DPHY signal, so that a plurality of signal wires can be multiplexed to generate and transmit the DPHY signal or the CPHY signal through multiplexing of a bridge chip and an output interface;
s102, providing image data and control signals for the bridge slices so that the bridge slices can convert the image data into corresponding DPHY signals or CPHY signals according to the indication of the control signals, and outputting the DPHY signals or the CPHY signals generated by the bridge slices through an output interface.
It is to be understood that the terms such as "comprises" and "comprising," which may be used in this invention, indicate the presence of the disclosed functions, operations or elements, and are not limited to one or more additional functions, operations or elements. In the present invention, terms such as "comprising" and/or "having" may be construed to mean a particular feature, number, operation, constituent element, component, or combination thereof, but may not be construed to exclude the presence or addition of one or more other features, numbers, operations, constituent elements, components, or combination thereof.
The foregoing is merely illustrative of the present invention, and the present invention is not limited thereto, and any person skilled in the art will readily recognize that variations or substitutions are within the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.
Claims (10)
1. An image signal generator for a common interface for DPHY and CPHY signals, comprising: control chip, bridge piece and output interface;
the control chip is used for providing image data and control signals for the bridge piece;
the bridge chip is used for converting the image data into corresponding DPHY signals or CPHY signals according to the indication of the control signals;
the bridge piece is connected with the output interface through a plurality of signal wires, and the characteristic impedance of each signal wire is a first preset value, so that the differential characteristic impedance between any two signal wires is a second preset value; the second preset value is determined according to the data transmission requirements of the CPHY signal and the DPHY signal, so that a plurality of signal wires can be multiplexed to generate and transmit the DPHY signal or the CPHY signal through multiplexing of a bridge chip and an output interface;
the output interface is used for outputting the DPHY signal or the CPHY signal generated by the bridge chip.
2. The image signal generator of claim 1, wherein the first preset value is 50× (1±10%) ohm;
the second preset value is 100× (1±10%) ohm.
3. The image signal generator of claim 1, wherein when the bridge pad generates a DPHY signal, every two signal lines in the plurality of signal lines form one LANE data line;
when the bridge piece generates CPHY signals, every three signal lines in the plurality of signal lines form a LANE data line.
4. The image signal generator of claim 1, wherein PIN PINs in the output interface that transmit the DPHY signal and the CPHY signal are multiplexed.
5. The image signal generator of claim 1, wherein the image data and control signals are in the form of TTL signals.
6. The image signal generator according to claim 1, wherein the characteristic impedance of the signal line is regulated by a distance of the signal line from a ground line and a line width of the signal line.
7. An image signal generating method of a shared interface of DPHY and CPHY signals is characterized by comprising the following steps:
connecting the bridge piece and the output interface through a plurality of signal wires, wherein the characteristic impedance of each signal wire is a first preset value, so that the differential characteristic impedance between any two signal wires is a second preset value; the second preset value is determined according to the data transmission requirements of the CPHY signal and the DPHY signal, so that a plurality of signal wires can be multiplexed to generate and transmit the DPHY signal or the CPHY signal through multiplexing of a bridge chip and an output interface;
the image data and the control signals are provided for the bridge slices, so that the bridge slices convert the image data into corresponding DPHY signals or CPHY signals according to the indication of the control signals, and the DPHY signals or the CPHY signals generated by the bridge slices are output through the output interface.
8. The image signal generation method according to claim 7, wherein the first preset value is 50× (1±10%) ohm;
the second preset value is 100× (1±10%) ohm.
9. The image signal generating method according to claim 7, wherein when the bridge pad generates a DPHY signal, each two signal lines in the plurality of signal lines form one LANE data line;
when the bridge piece generates CPHY signals, every three signal lines in the plurality of signal lines form a LANE data line.
10. The image signal generating method according to claim 7, further comprising the step of:
PIN multiplexing for transmitting DPHY signal and CPHY signal in the control output interface.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202311136130.3A CN117294808A (en) | 2023-09-01 | 2023-09-01 | Image signal generator and generating method of DPHY and CPHY signal sharing interface |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202311136130.3A CN117294808A (en) | 2023-09-01 | 2023-09-01 | Image signal generator and generating method of DPHY and CPHY signal sharing interface |
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| CN117294808A true CN117294808A (en) | 2023-12-26 |
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| CN109545116A (en) * | 2018-12-10 | 2019-03-29 | 武汉精立电子技术有限公司 | A kind of driving device and detection system of display module |
| CN109714041A (en) * | 2019-01-28 | 2019-05-03 | 龙迅半导体（合肥）股份有限公司 | A kind of high speed signal driving circuit |
| US20220286095A1 (en) * | 2021-03-04 | 2022-09-08 | Samsung Electronics Co., Ltd. | Interface circuit including variable impedance circuit and operating method thereof |
| CN115734062A (en) * | 2021-08-25 | 2023-03-03 | 宁波舜宇光电信息有限公司 | Camera module and connector PIN setting method thereof |
| CN218974847U (en) * | 2022-10-31 | 2023-05-05 | 龙芯中科技术股份有限公司 | Display screen expansion circuit, mainboard and computer equipment |
| CN116471737A (en) * | 2023-04-18 | 2023-07-21 | 湖北长江新型显示产业创新中心有限公司 | Point screen circuit board and point screen system |
-
2023
- 2023-09-01 CN CN202311136130.3A patent/CN117294808A/en not_active Withdrawn
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109545116A (en) * | 2018-12-10 | 2019-03-29 | 武汉精立电子技术有限公司 | A kind of driving device and detection system of display module |
| CN109714041A (en) * | 2019-01-28 | 2019-05-03 | 龙迅半导体（合肥）股份有限公司 | A kind of high speed signal driving circuit |
| US20220286095A1 (en) * | 2021-03-04 | 2022-09-08 | Samsung Electronics Co., Ltd. | Interface circuit including variable impedance circuit and operating method thereof |
| CN115734062A (en) * | 2021-08-25 | 2023-03-03 | 宁波舜宇光电信息有限公司 | Camera module and connector PIN setting method thereof |
| CN218974847U (en) * | 2022-10-31 | 2023-05-05 | 龙芯中科技术股份有限公司 | Display screen expansion circuit, mainboard and computer equipment |
| CN116471737A (en) * | 2023-04-18 | 2023-07-21 | 湖北长江新型显示产业创新中心有限公司 | Point screen circuit board and point screen system |
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Application publication date: 20231226 |
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