CN117293089A - Method for forming semiconductor structure - Google Patents

Method for forming semiconductor structure Download PDF

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Publication number
CN117293089A
CN117293089A CN202210699664.6A CN202210699664A CN117293089A CN 117293089 A CN117293089 A CN 117293089A CN 202210699664 A CN202210699664 A CN 202210699664A CN 117293089 A CN117293089 A CN 117293089A
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China
Prior art keywords
forming
region
etching
semiconductor structure
layer
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CN202210699664.6A
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Chinese (zh)
Inventor
张恩宁
肖杏宇
谭程
王文泰
张海洋
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Semiconductor Manufacturing International Shanghai Corp
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Semiconductor Manufacturing International Shanghai Corp
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Priority to CN202210699664.6A priority Critical patent/CN117293089A/en
Publication of CN117293089A publication Critical patent/CN117293089A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823821—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
    • H01L21/3083—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/3086—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Drying Of Semiconductors (AREA)

Abstract

A method of forming a semiconductor structure, comprising: providing a substrate, wherein the substrate comprises a first region and a second region, and the materials of the first region and the second region are different; forming a plurality of mask layers which are mutually separated on the surface of the first region and the surface of the second region; after forming a mask layer, etching the exposed substrate for a plurality of times to form a first fin portion in the first region and a second fin portion in the second region, wherein the method for etching each time comprises the following steps: etching the exposed substrate to enable the first region to form a transitional first fin portion and enable the second region to form a transitional second fin portion; and forming a first protection layer on the side wall surfaces of the transitional first fin part and the transitional second fin part, reducing the difference of etching rates caused by different materials of the first area and the second area in the etching process, and providing the uniformity of the sizes of the formed first fin part and second fin part.

Description

Method for forming semiconductor structure
Technical Field
The present disclosure relates to semiconductor manufacturing technology, and more particularly, to a method for forming a semiconductor structure.
Background
In the existing semiconductor field, a fin field effect transistor (FinFET) is an emerging multi-gate device, and compared with a planar metal-oxide semiconductor field effect transistor (MOSFET), the fin field effect transistor has stronger short channel suppression capability and stronger working current, and is widely applied to various semiconductor devices.
With further development of semiconductor technology, transistor dimensions shrink below a few nanometers, and fin field effect transistors also face serious problems of leakage, short channel effect, reduced gate control capability, and the like. In order to improve fin field effect transistor performance, control of the fin topography is critical.
However, the fin formation technology in the finfet structure in the prior art needs to be improved.
Disclosure of Invention
The invention solves the technical problem of providing a method for forming a semiconductor structure to improve the performance of the formed semiconductor structure.
In order to solve the above technical problems, a method for forming a semiconductor structure is provided, including: providing a substrate, wherein the substrate comprises a first region and a second region, and the materials of the first region and the second region are different; forming a plurality of mask layers which are mutually separated on the surface of the first area and the surface of the second area; after forming the mask layer, etching the exposed substrate for a plurality of times to form a first fin portion in the first region and a second fin portion in the second region, wherein the method for etching each time comprises the following steps: etching the exposed substrate to enable the first region to form a transitional first fin portion and enable the second region to form a transitional second fin portion; and forming a first protection layer on the side wall surfaces of the transitional first fin part and the transitional second fin part.
Optionally, the forming method of the first protection layer includes: forming a first protective material layer on the surface of the substrate, the surface of the transitional first fin part and the surface of the transitional second fin part; the first protective material layer is etched back until the substrate surface is exposed.
Optionally, the etch-back process comprises a dry etch process.
Optionally, the process parameters of the dry etching process include: the etching gas comprises fluorocarbon gas, the bias voltage range is 600V to 1300V, and the etching power range is 100W to 500W.
Optionally, the ratio of carbon atoms to fluorine atoms in the fluorocarbon gas is in the range of 1.5:1 to 4:1.
Optionally, the material of the first protective material layer includes a dielectric material including one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, and silicon oxycarbonitride.
Optionally, the material of the first protective material layer includes silicon oxide; the forming process of the first protective material layer includes an atomic layer deposition process.
Optionally, the process parameters of the atomic layer deposition process include: the reaction gas includes aminosilane and oxygen.
Optionally, the forming process of the first protective layer and the etching processes are in the same reaction chamber.
Optionally, after forming the mask layer and before etching several times, the method further includes: and forming a second protective layer on the surface of the side wall of the mask layer.
Optionally, the forming method of the second protection layer includes: forming a second protective material layer on the surface of the substrate and the surface of the mask layer; and etching back the second protective material layer until the surface of the substrate is exposed.
Optionally, the material of the second protective material layer includes silicon oxide; the forming process of the second protective material layer includes an atomic layer deposition process.
Optionally, the back etching process includes a dry etching process; the dry etching process comprises the following process parameters: the etching gas comprises fluorocarbon gas, the bias voltage range is 600V to 1300V, and the etching power range is 100W to 500W.
Optionally, the substrate comprises a base, and the first region and the second region are located on the base.
Optionally, the material of the first region comprises silicon; the material of the second region comprises silicon germanium.
Optionally, the etching treatment process comprises dry etching; technological parameters of dry etching: the etching gas comprises hydrogen fluorocarbon gas, SF 6 One or more of HBr, the gas flow rate ranges from 100sccm to 400sccm, and the power ranges from 100W to 500W.
Optionally, the number of etching processes may range from 2 to 20 times.
Optionally, the etching treatment process has an etching selection ratio of 1:1 to 1.2:1 for the first region and the second region; the etching treatment process has an etching selection ratio of 2:1 to 10:1 for the first region and the first protective layer.
Optionally, the thickness of the first protective layer ranges from 0.2nm to 0.6nm.
Compared with the prior art, the technical scheme of the embodiment of the invention has the following beneficial effects:
in the method for forming a semiconductor structure provided by the technical scheme of the invention, the exposed substrate is subjected to etching treatment for a plurality of times, so that a first region forms a first fin part, a second region forms a second fin part, and the method for etching treatment for each time comprises the following steps: etching the exposed substrate to enable the first region to form a transitional first fin portion and enable the second region to form a transitional second fin portion; and forming a first protection layer on the side wall surfaces of the transitional first fin part and the transitional second fin part. In the method, the first fin part and the second fin part are formed by multi-stage etching, the etched part is protected before each etching, and over etching of an etching area is avoided, so that the difference of etching rates caused by different materials of the first area and the second area in the etching process is reduced, and the uniformity of the sizes of the formed first fin part and second fin part is provided.
Further, before forming the mask layer and before etching several times, the method further includes: and forming a second protective layer on the surface of the side wall of the mask layer. The second protection layer is used for protecting the side wall of the mask layer, so that the mask layer is prevented from being consumed in the etching process, the size of the formed first fin portion (second fin portion) is reduced, and the stability of the sizes of the formed first fin portion and the second fin portion is improved.
Drawings
FIGS. 1-2 are schematic cross-sectional views of a semiconductor structure forming process;
fig. 3 to 15 are schematic structural views of steps of a method for forming a semiconductor structure according to an embodiment of the present invention;
fig. 16 is a flowchart illustrating steps of each etching process in a method for forming a semiconductor structure according to an embodiment of the present invention.
Detailed Description
Note that "surface", "upper", as used herein, describes a relative positional relationship in space, and is not limited to whether or not it is in direct contact.
As described in the background, the performance of semiconductor structures formed using existing finfet technology is in need of improvement. Analysis will now be described in connection with a semiconductor structure.
Fig. 1-2 are schematic cross-sectional views of a semiconductor structure forming process.
Referring to fig. 1, a substrate 100 is provided, the substrate 100 including a first region I and a second region II; forming a first channel material layer 101 in the first region I; forming a second channel material layer 102 on the second region II; a hard mask layer 103 is formed on the first channel material layer 101 and the second channel material layer 102, and the hard mask layer 103 exposes a portion of the surfaces of the first channel material layer 101 and a portion of the second channel material layer 102.
Referring to fig. 2, the first channel material layer 101, the second channel material layer 102 and the substrate 100 are etched with the hard mask layer 103 as a mask, so as to form a first fin 104 and a second fin 105, the first fin 104 includes a first bottom structure 104a and a first channel layer 104b, the second fin 105 includes a second bottom structure 105a and a second channel layer 105b, the first channel layer 104b is formed with the first channel material layer 101, and the second channel 105b is formed with the second channel material layer 102.
In the above method, the material of the first channel material layer 101 is silicon, the material of the second channel material layer 102 is germanium-silicon, the first channel 104b is used to form a channel of an N-type device, and the second channel 105b is used to form a channel of a P-type device. The material of the second channel 105b is germanium-silicon, and the material of the second bottom structure 105a is silicon, and compressive stress on the second channel 105 can be generated due to lattice mismatch between germanium-silicon and silicon, and the compressive stress can reduce the effective conduction quality of holes in the channel direction, so that the speed of the PMOS device is improved.
The process of etching the first channel material layer 101 and the second channel material layer 102 generally employs a halogen-based plasma etching gas. However, during the etching process, the etching rate of the germanium-silicon material is greater than that of the silicon material, and the second fin 105 is over-etched with respect to the first fin 104, so that the second fin 105 has a smaller size, and the second fin 105 may have a tapered shape, which is not beneficial to control of uniformity of the fin size.
In order to solve the above technical problems, the present invention provides a method for forming a semiconductor structure, in which a exposed substrate is etched for several times, so that a first region forms a first fin portion, a second region forms a second fin portion, and the method for etching each time includes: etching the exposed substrate to enable the first region to form a transitional first fin portion and enable the second region to form a transitional second fin portion; and forming a first protection layer on the side wall surfaces of the transitional first fin part and the transitional second fin part. In the method, the first fin part and the second fin part are formed by multi-stage etching, the etched part is protected before each etching, and over etching of an etching area is avoided, so that the difference of etching rates caused by different materials of the first area and the second area in the etching process is reduced, and the uniformity of the sizes of the formed first fin part and second fin part is provided.
In order to make the above objects, features and advantages of the present invention more comprehensible, embodiments accompanied with figures are described in detail below.
Fig. 3 to 15 are schematic structural views of steps of a method for forming a semiconductor structure according to an embodiment of the present invention.
Referring to fig. 3, a substrate is provided, the substrate including a first region 201 and a second region 202, the first region 201 and the second region 202 being different in material; a plurality of mask layers 203 are formed on the surface of the first region 201 and the surface of the second region 202, which are separated from each other.
The first region 201 is used to form a first fin; the second region 201 is used to form a second fin.
In this embodiment, the substrate includes a base 200, and a first region 201 and a second region 202 are located on the base 200.
The material of the substrate 200 may be monocrystalline silicon, polycrystalline silicon or amorphous silicon, or semiconductor materials such as silicon, germanium, silicon germanium, gallium arsenide, or semiconductor-on-insulator structures. In this embodiment, the substrate 200 is made of monocrystalline silicon.
In this embodiment, the material of the first region 201 comprises silicon; the material of the second region 202 comprises silicon germanium. Specifically, the first region 201 is used to form an N-type device, and the second region 202 is used to form a P-type device.
In this embodiment, the hard mask layer 203 includes a first hard mask layer 203a and a second hard mask layer 203b on the first hard mask layer 203 a.
The material dielectric material of the hard mask layer 203 includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, and silicon oxycarbonitride.
Specifically, in this embodiment, the material of the first hard mask layer 203a includes silicon nitride; the material of the second hard mask layer 203b includes silicon oxide.
The forming method of the hard mask layer 203 comprises the following steps: forming a first hard mask material layer (not shown) on a surface of a substrate; forming a second hard mask material layer (not shown) on the first hard mask material layer; forming a patterned layer (not shown) on the second hard mask material layer, the patterned layer exposing a portion of the second hard mask layer; and etching the second hard mask material layer and the first hard mask material layer by taking the patterned layer as a mask until the surface of the substrate is exposed.
In this embodiment, an etch stop layer 204 is also formed on the substrate surface prior to forming the first hard mask material layer. Specifically, the second hard mask material layer and the first hard mask material layer are etched using the patterned layer as a mask until the etch stop layer 204 of the substrate surface is exposed.
Subsequently, after the mask layer 203 is formed, etching is performed on the exposed substrate for several times, so that the first region 201 forms a first fin portion, and the second region 202 forms a second fin portion.
After forming the mask layer 203 and before several etching processes, the method further includes: a second protective layer is formed on the sidewall surface of the mask layer 203. Please refer to fig. 4 to fig. 5 for a method of forming the second passivation layer.
Referring to fig. 4, a second protective material layer 205 is formed on the surface of the substrate and the surface of the mask layer 203.
The material of the second protective material layer 205 includes silicon oxide.
The formation process of the second protective material layer 205 includes an atomic layer deposition process. The atomic layer deposition process is advantageous for improving the flatness of the surface of the formed second protective material layer 205.
Referring to fig. 5, the second protective material layer 205 is etched back until the substrate surface is exposed.
The second protection layer 206 is used for protecting the sidewall of the mask layer 203, avoiding consuming the mask layer 203 during etching, resulting in the reduction of the size of the formed first fin (second fin), and improving the stability of the sizes of the formed first fin and second fin.
The back etching process comprises a dry etching process; the dry etching process comprises the following process parameters: the etching gas comprises fluorocarbon gas, the bias voltage range is 600V to 1300V, and the etching power range is 100W to 500W. The process conditions of the dry etching process are favorable for realizing directional etching, improving the uniformity of the film thickness of the formed second protection layer 206, and improving the accuracy of subsequent pattern transfer.
The etching treatment process comprises dry etching; technological parameters of dry etching: the etching gas comprises hydrogen fluorocarbon gas, SF 6 One or more of HBr, the gas flow rate ranges from 100sccm to 400sccm, and the power ranges from 100W to 500W.
Fig. 16 is a flowchart illustrating steps of each etching process in a method for forming a semiconductor structure according to an embodiment of the present invention.
Referring to fig. 16, after forming the mask layer 203, etching is performed on the exposed substrate for several times, so that the first region 201 forms a first fin portion and the second region 202 forms a second fin portion, and the method of each etching includes the following steps:
step 301, etching the exposed substrate to form a transitional first fin portion in the first region and a transitional second fin portion in the second region;
and 302, forming a first protection layer on the side wall surfaces of the transitional first fin part and the transitional second fin part.
Next, each step will be described by analysis.
The number of times of the etching treatment is in the range of 2 times to 20 times. In this embodiment, the number of etching processes is 3.
In this embodiment, after the mask layer 203 is formed, the exposed substrate is etched for 3 times, so that the first region 201 forms a first fin portion and the second region 202 forms a second fin portion, please refer to fig. 6 to 14. Specifically, the first etching process is shown in fig. 6 to 8, the second etching process is shown in fig. 9 to 11, and the third etching process is shown in fig. 12 to 14.
Referring to fig. 6, and with continued reference to fig. 16, the first etch process: the exposed substrate is etched to form a transitional first fin 207 in the first region 201 and a transitional second fin 208 in the second region 202.
The etching process has an etching selectivity to the first region 201 and the second region 202 in the range of 1:1 to 1.2:1.
In this embodiment, the second protection layer 206 is consumed during the etching process.
In the next first etching process, a first protection layer is formed on the sidewall surfaces of the transitional first fin 207 and the transitional second fin 208. Please refer to fig. 7 to 8 for a method of forming the first passivation layer.
Referring to fig. 7 with continued reference to fig. 16, the first etch process: a first protective material layer 209 is formed on the substrate surface, the transitional first fin 207, and the transitional second fin 208 surface.
The material of the first protective material layer 209 includes a dielectric material including one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, and silicon oxycarbonitride.
In this embodiment, the material of the first protective material layer 209 includes silicon oxide.
In this embodiment, the forming process of the first protective material layer 209 includes an atomic layer deposition process. The atomic layer deposition process is beneficial to improving the flatness of the surface of the first protective material layer 209.
In this embodiment, the process parameters of the atomic layer deposition process include: the reaction gas includes aminosilane and oxygen. The atomic layer deposition process is obtained by adopting an aminosilane and oxygen reaction, and material consumption of the transitional first fin 207 and the transitional second fin 208 can not be generated, so that damage to the transitional first fin 207 and the transitional second fin 208 can not be generated, and the stability of the sizes of the first fin and the second fin can be improved.
Referring to fig. 8 with continued reference to fig. 16, the first etch process: the first protective material layer 209 is etched back until the substrate surface is exposed.
The thickness of the first protective layer 210 ranges from 0.2nm to 0.6nm.
The etch-back process includes a dry etching process.
The dry etching process comprises the following process parameters: the etching gas comprises fluorocarbon gas, the bias voltage range is 600V to 1300V, and the etching power range is 100W to 500W. The process conditions of the dry etching process are favorable for realizing directional etching, improving the uniformity of the film thickness of the formed first protective layer 209, and improving the accuracy of subsequent pattern transfer.
In the fluorocarbon gas, the atomic number ratio of carbon atoms to fluorine atoms is in the range of 1.5:1 to 4:1. Different fin etching morphologies can be obtained by adjusting the atomic number ratio of carbon atoms to fluorine atoms in the fluorocarbon gas.
In this embodiment, the forming process and the etching processes of the first protection layer 210 are in the same reaction chamber. The formation process and the several etching processes of the first protection layer 210 do not need to transfer between different reaction chambers, so that unnecessary impurities are prevented from being introduced, and the quality and the uniformity of the film thickness of the first protection layer 210 are improved.
Next, a second etching process is performed on the exposed substrate, please refer to fig. 9 to 11.
Referring to fig. 9, and with continued reference to fig. 16, the second etch process: the exposed substrate is etched to form a transitional first fin 207 in the first region 201 and a transitional second fin 208 in the second region 202.
The etching process has an etching selectivity to the first region 201 and the second region 202 in the range of 1:1 to 1:1.2.
The etching process has an etching selectivity to the first region 201 and the first protective layer 210 ranging from 2:1 to 10:1. The purpose of selecting the etching selection ratio range is to: an appropriate etching process may be selected to consume the first protection layer 210 after the first fin 207 and the second fin 208 are formed, so as to facilitate uniformity of film thickness of the first protection layer 210 formed on the sidewall surfaces of the first fin 207 and the second fin 208, thereby facilitating improvement of accuracy of subsequent pattern transfer and appearance of the first fin and the second fin.
In the next second etching process, the first protection layer 210 is continuously formed on the sidewall surfaces of the transitional first fin 207 and the transitional second fin 208. Please refer to fig. 10 to 11, and continue to refer to fig. 16 for a method of forming the first protection layer 210. The first protection layer 210 is formed in the second etching process in the same manner as in the first etching process.
Next, please refer to fig. 12 to 14 with continued reference to fig. 16, the third etching process is the same as the first two etching processes, and will not be described again.
In this embodiment, the number of etching processes is 3. In other embodiments, the number of etching processes may range from 2 to 20 times. The number of times of the etching treatment for several times can be adjusted according to the actual production cost, etching effect and the like.
So far, the exposed substrate is subjected to etching treatment for a plurality of times, so that the first region 201 forms the first fin portion 211, the second region 202 forms the second fin portion 212, the first fin portion 211 and the second fin portion 212 are formed by etching in a plurality of sections, the etched part is protected before each etching, over etching of an etching area is avoided, and therefore differences of etching rates caused by different materials of the first region 201 and the second region 202 in the etching process are reduced, and uniformity of sizes of the formed first fin portion 211 and second fin portion 212 is provided.
In this embodiment, please refer to fig. 14 to 15.
Referring to fig. 14, a third protection layer 213 is formed on the sidewall surfaces of the first fin 211 and the second fin 212.
The material of the third protective layer 213 includes a dielectric material including one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, and silicon oxycarbonitride. In this embodiment, the material of the third protection layer 213 is silicon oxide.
Referring to fig. 15, after forming third protection layer 213, substrate 200 is further etched, and a first bottom structure 214 at the bottom of first fin 211 and a second bottom structure 215 at the bottom of second fin 212 are formed in substrate 200.
In this embodiment, the process of etching the substrate 200 includes a dry etching process. The dry etching process is advantageous in improving the topography of the first bottom structure 214 and the second bottom structure 215 that are formed.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be made by one skilled in the art without departing from the spirit and scope of the invention, and the scope of the invention should be assessed accordingly to that of the appended claims.

Claims (19)

1. A method of forming a semiconductor structure, comprising:
providing a substrate, wherein the substrate comprises a first region and a second region, and the materials of the first region and the second region are different;
forming a plurality of mask layers which are mutually separated on the surface of the first region and the surface of the second region;
after forming a mask layer, etching the exposed substrate for a plurality of times to form a first fin portion in the first region and a second fin portion in the second region, wherein the method for etching each time comprises the following steps:
etching the exposed substrate to enable the first region to form a transitional first fin portion and enable the second region to form a transitional second fin portion;
and forming a first protection layer on the side wall surfaces of the transitional first fin part and the transitional second fin part.
2. The method of forming a semiconductor structure of claim 1, wherein the method of forming a first protective layer comprises: forming a first protective material layer on the surface of the substrate, the transitional first fin portion and the transitional second fin portion; and etching back the first protective material layer until the surface of the substrate is exposed.
3. The method of forming a semiconductor structure of claim 2, wherein the etch-back process comprises a dry etching process.
4. The method of forming a semiconductor structure of claim 3, wherein the process parameters of the dry etching process comprise: the etching gas comprises fluorocarbon gas, the bias voltage range is 600V to 1300V, and the etching power range is 100W to 500W.
5. The method of claim 4, wherein the ratio of carbon atoms to fluorine atoms in the fluorocarbon gas is in the range of 1.5:1 to 4:1.
6. The method of forming a semiconductor structure of claim 2, wherein the material of the first protective material layer comprises a dielectric material comprising one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, and silicon oxycarbonitride.
7. The method of forming a semiconductor structure of claim 2, wherein the material of the first protective material layer comprises silicon oxide; the forming process of the first protective material layer comprises an atomic layer deposition process.
8. The method of forming a semiconductor structure of claim 7, wherein the process parameters of the atomic layer deposition process comprise: the reaction gas includes aminosilane and oxygen.
9. The method of claim 1, wherein the forming of the first protective layer and the etching processes are performed in a same reaction chamber.
10. The method of forming a semiconductor structure of claim 1, further comprising, after forming the mask layer and before the number of etching processes: and forming a second protective layer on the surface of the side wall of the mask layer.
11. The method of forming a semiconductor structure of claim 10, wherein the method of forming a second protective layer comprises: forming a second protective material layer on the surface of the substrate and the surface of the mask layer; and etching the second protective material layer back until the surface of the substrate is exposed.
12. The method of forming a semiconductor structure of claim 11, wherein a material of the second protective material layer comprises silicon oxide; the forming process of the second protective material layer comprises an atomic layer deposition process.
13. The method of forming a semiconductor structure of claim 11, wherein the etch-back process comprises a dry etching process; the dry etching process comprises the following technological parameters: the etching gas comprises fluorocarbon gas, the bias voltage range is 600V to 1300V, and the etching power range is 100W to 500W.
14. The method of forming a semiconductor structure of claim 1, wherein the substrate comprises a base, the first region and the second region being located on the base.
15. The method of forming a semiconductor structure of claim 1, wherein the material of the first region comprises silicon; the material of the second region comprises silicon germanium.
16. The method of forming a semiconductor structure of claim 1, wherein the etching treatment process comprises dry etching; the dry etching process parameters are as follows: the etching gas comprises hydrogen fluorocarbon gas, SF 6 One or more of HBr, the gas flow rate ranges from 100sccm to 400sccm, and the power ranges from 100W to 500W.
17. The method of forming a semiconductor structure of claim 1, wherein the number of etching processes is in the range of 2 to 20 times.
18. The method of claim 1, wherein the etching process has an etch selectivity to the first region and the second region in a range of 1:1 to 1.2:1; the etching treatment process has an etching selection ratio of 2:1 to 10:1 for the first region and the first protection layer.
19. The method of forming a semiconductor structure of claim 1, wherein a thickness of the first protective layer ranges from 0.2nm to 0.6nm.
CN202210699664.6A 2022-06-20 2022-06-20 Method for forming semiconductor structure Pending CN117293089A (en)

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