CN117279372A

CN117279372A - Semiconductor device and method for manufacturing the same

Info

Publication number: CN117279372A
Application number: CN202311232647.2A
Authority: CN
Inventors: 吴建山; 蔡建成; 许培育; 周芷伊; 林志程; 蔡攀崖; 黄世平
Original assignee: Fujian Jinhua Integrated Circuit Co Ltd
Current assignee: Fujian Jinhua Integrated Circuit Co Ltd
Priority date: 2023-09-22
Filing date: 2023-09-22
Publication date: 2023-12-22

Abstract

The invention discloses a semiconductor device and a method for manufacturing the same. The semiconductor device comprises a semiconductor substrate and a first stacking structure; and a contact structure. The semiconductor substrate has a cell region and a surrounding region, and the semiconductor substrate includes a fin structure. The first stack structure is disposed in the semiconductor substrate, and extends across the fin structure in a horizontal direction and is disposed in the cell region and the surrounding region. The first stack structure includes a conductive layer, a cap layer, and a dielectric cap layer. The conductive layer is partially located in the cell region and partially located in the surrounding region. The cap layer is disposed on the conductive layer and includes a first portion and a second portion. The second portion is at least partially located in the peripheral region, and the thickness of the second portion is less than the thickness of the first portion. A dielectric cap layer is disposed over the cap layer. The contact structure directly contacts the second portion of the cap layer and is electrically connected with the first stack structure. Thus, the electrical connection between the contact structure and the first stacked structure can be improved.

Description

Semiconductor device and method for manufacturing the same

Technical Field

The present invention relates to the field of semiconductor technology, and more particularly, to a semiconductor device and a method of manufacturing the same.

Background

A dynamic random access memory (dynamic random access memory, hereinafter referred to as DRAM) is a volatile memory, which is an essential component in many electronic products. The DRAM is formed by accumulating a large number of memory cells (memory cells) to form an array region for storing data, and each memory cell may be formed by serially connecting a metal oxide semiconductor (metal oxide semiconductor, hereinafter abbreviated as MOS) transistor and a capacitor (capacitor).

The MOS transistor structure of a memory cell may be different from the MOS transistor structure of other regions on the same chip due to a number of different structural designs in consideration of product requirements and/or memory cell density, and thus the complexity of the manufacturing process may be increased. Therefore, how to effectively integrate the manufacturing process of each device in the memory cell and other areas is a very important issue for the related industry.

Disclosure of Invention

The invention provides a semiconductor device and a manufacturing method thereof, by which the electrical connection condition between a contact structure and a stacked structure is improved, thereby improving the manufacturing qualification rate of the semiconductor device.

An embodiment of the invention provides a semiconductor device, which comprises a semiconductor substrate, a first stacking structure and a contact structure. The semiconductor substrate has a cell region and a surrounding region, and the semiconductor substrate includes at least one fin structure separated by an insulating structure. The first stack structure is disposed in the semiconductor substrate, and extends across the fin structure in a horizontal direction and is disposed in the cell region and the surrounding region. The first stack structure includes a conductive layer, a cap layer, and a dielectric cap layer. The conductive layer is partially located in the cell region and partially located in the surrounding region. The cap layer is disposed on the conductive layer and includes a first portion and a second portion. The first portion is at least partially located in the cell region, the second portion is at least partially located in the surrounding region, and the thickness of the second portion is less than the thickness of the first portion. A dielectric cap layer is disposed over the cap layer. The contact structure directly contacts the second portion of the cap layer and is electrically connected with the first stack structure.

An embodiment of the present invention provides a method for manufacturing a semiconductor device, which includes the following steps. A semiconductor substrate is provided, the semiconductor substrate having a cell region and a surrounding region, and the semiconductor substrate including at least one fin structure separated by an insulating structure. A first stack structure is formed in the semiconductor substrate, the first stack structure extending in a horizontal direction across the fin structure and being formed in the cell region and the surrounding region. The first stack structure includes a conductive layer, a cap layer, and a dielectric cap layer. The conductive layer is partially located in the cell region and partially located in the surrounding region. The cap layer is disposed on the conductive layer and includes a first portion and a second portion. The first portion is at least partially located in the cell region, the second portion is at least partially located in the surrounding region, and the thickness of the second portion is less than the thickness of the first portion. A dielectric cap layer is disposed over the cap layer. Then, a contact structure is formed, the contact structure directly contacting the second portion of the cap layer and electrically connected to the first stacked structure.

Another embodiment of the present invention provides a semiconductor device including a semiconductor substrate, a first stack structure, and a contact structure. The semiconductor substrate includes at least one fin structure separated by an insulating structure. The first stack structure is disposed in the semiconductor substrate, and extends in a horizontal direction across the fin structure. The first stack structure includes a conductive layer, a cap layer, and a dielectric cap layer. The cover layer is arranged on the conductive layer, and the surface of the cover layer comprises a step structure. A dielectric cap layer is disposed over the cap layer. The contact structure directly contacts the cap layer and is electrically connected to the first stack structure. The distance between the upper surface of the cap layer in direct contact with the contact structure and the conductive layer is smaller than the distance between the upper surface of another portion of the cap layer and the conductive layer.

Drawings

The accompanying drawings are included to provide a further understanding of embodiments of the invention and are incorporated in and constitute a part of this specification. These drawings and description serve to illustrate principles of some embodiments. It should be noted that all illustrations are schematic, and relative dimensions and proportions are adjusted for ease of illustration and drawing. The same reference signs represent corresponding or similar features in different embodiments.

Fig. 1 is a schematic top view of a semiconductor device according to an embodiment of the invention.

Fig. 2 is a cross-sectional view of a semiconductor device according to a first embodiment of the present invention.

Fig. 3 is another cross-sectional view of the semiconductor device of the first embodiment of the present invention.

Fig. 4 to 13 are schematic views illustrating a method of fabricating a semiconductor device according to an embodiment of the present invention, in which fig. 5 is a schematic view of the situation after fig. 4, fig. 6 is a schematic view of the situation after fig. 5, fig. 7 is a schematic view of the situation after fig. 6, fig. 8 is a schematic view of the situation after fig. 7, fig. 9 is a schematic view of the situation after fig. 8, fig. 10 is a schematic view of the situation after fig. 9, fig. 11 is a schematic view of the situation after fig. 10, fig. 12 is another cross-sectional view in the situation of fig. 11, and fig. 13 is a cross-sectional view of another region in the situation of fig. 11.

Fig. 14 is a cross-sectional view of a semiconductor device according to a second embodiment of the present invention.

Fig. 15 is a cross-sectional view of a semiconductor device according to a third embodiment of the present invention.

Fig. 16 is a cross-sectional view of a semiconductor device according to a fourth embodiment of the present invention.

Fig. 17 is a cross-sectional view of a semiconductor device according to a fifth embodiment of the present invention.

Fig. 18 is a cross-sectional view of a semiconductor device according to a sixth embodiment of the present invention.

Fig. 19 is a cross-sectional view of a semiconductor device according to a seventh embodiment of the present invention.

Fig. 20 is a cross-sectional view of a semiconductor device according to an eighth embodiment of the present invention.

Wherein reference numerals are as follows:

10. semiconductor substrate

10F fin structure

12. Insulation structure

13. Stress material layer

21. Oxide layer

22. Dielectric layer

24. Conductive layer

24A first part

24B second part

24E sidewall

24T upper surface

26. Cover layer

26A first part

26B second part

26E side wall

26M cap layer material

28. Dielectric cap layer

30. Patterning mask layer

32. Mask layer

33. Gate dielectric layer

34. Conductive layer

35. Grid electrode

36. Conductive layer

37. Gate cap layer

38. Cover layer

39. Sidewall structure

40. Source/drain regions

42. Insulation pattern

44. Dielectric layer

46. Dielectric layer

52. Barrier layer

54. Conductive layer

90. Removal process

91. First removing step

92. A second removal step

101. Semiconductor device with a semiconductor device having a plurality of semiconductor chips

102. Semiconductor device with a semiconductor device having a plurality of semiconductor chips

103. Semiconductor device with a semiconductor device having a plurality of semiconductor chips

104. Semiconductor device with a semiconductor device having a plurality of semiconductor chips

105. Semiconductor device with a semiconductor device having a plurality of semiconductor chips

106. Semiconductor device with a semiconductor device having a plurality of semiconductor chips

107. Semiconductor device with a semiconductor device having a plurality of semiconductor chips

108. Semiconductor device with a semiconductor device having a plurality of semiconductor chips

AR active region

BL second stack structure

BS bottom surface

BS1 bottom surface

BS11 first bottom surface

Second bottom surface of BS12

CT1 contact structure

CT2 contact structure

DS1 distance

DS2 distance

DS3 distance

D1 In the horizontal direction

D2 In the horizontal direction

D3 In the vertical direction

INT1 interface

INT2 interface

OP1 open pore

OP2 open pore

OP3 open pore

R1 unit region

R2 peripheral region

SP side wall structure

SS ladder structure

S1 spacer

S2 spacer

S3 spacer

T-transistor structure

TK1 thickness

TK2 thickness

TR groove

TS1 upper surface

TS2 upper surface

WL first stack structure

Detailed Description

In order to enable those skilled in the art to which the invention pertains, a few preferred embodiments of the invention are described below, together with the accompanying drawings, in detail, to explain the principles of the invention and its advantages. Those skilled in the art to which the invention pertains will be able to replace, reorganize, and mix features in several different embodiments with reference to the following examples to complete other embodiments without departing from the spirit of the invention.

The term "forming" or "disposing" is used hereinafter to describe the act of applying a layer of material to a target. These terms are intended to describe any viable layer formation technique including, but not limited to, thermal growth, sputtering, evaporation, chemical vapor deposition, epitaxial growth, electroplating, and the like.

Please refer to fig. 1, fig. 2 and fig. 3. Fig. 1 is a schematic top view of a semiconductor device according to an embodiment of the present invention, fig. 2 is a cross-sectional view of the semiconductor device according to the first embodiment of the present invention, and fig. 3 is another cross-sectional view of the semiconductor device according to the first embodiment of the present invention. In some embodiments, at least a portion of FIG. 2 may be considered a cross-sectional view taken along line A-A 'in FIG. 1, while at least a portion of FIG. 3 may be considered a cross-sectional view taken along line B-B' in FIG. 1, but is not limited thereto. As shown in fig. 1, 2 and 3, the semiconductor device 101 includes a semiconductor substrate 10, a first stack structure WL, and a contact structure CT1. The semiconductor substrate 10 includes at least one fin structure 10F separated by an insulating structure 12. A first stack structure WL is provided in the semiconductor substrate 10, the first stack structure WL extends in a horizontal direction D1 across the fin structure 10F, and the first stack structure WL includes a conductive layer 24, a cap layer 26, and a dielectric cap layer 28. A cap layer 26 is disposed on the conductive layer 24 and a dielectric cap layer 28 is disposed on the cap layer 26. The contact structure CT1 directly contacts the conductive layer 24 and is electrically connected with the first stack structure WL. In some embodiments, the semiconductor substrate 10 may have a cell region R1 and a surrounding region R2, and the first stacked structure WL may extend in the horizontal direction D1 across the fin structure 10F and be disposed in the cell region R1 and the surrounding region R2, but is not limited thereto. In addition, the conductive layer 24 may be partially located in the cell region R1 and partially located in the surrounding region R2, the cap layer 26 is disposed on the conductive layer 24, and the cap layer 26 may include a first portion 26A and a second portion 26B. The first portion 26A is at least partially located in the cell region R1, the second portion 26B is at least partially located in the surrounding region R2, the thickness TK2 of the second portion 26B is smaller than the thickness TK1 of the first portion 26A, and the contact structure CT1 may directly contact the second portion 26B of the cap layer 26 and be electrically connected with the first stack structure WL. In some embodiments, the surface of cap layer 26 may include a stepped structure SS, and the distance between the upper surface of cap layer 26 (e.g., upper surface TS2 of second portion 26B) in direct contact with contact structure CT1 and conductive layer 24 in vertical direction D3 may be less than the distance between the upper surface of another portion of cap layer 26 (e.g., upper surface TS1 of first portion 26A) and conductive layer 24 in vertical direction D3. By the arrangement of the cap layer 26 in the first stacked structure WL, the adverse effect of the cap layer 26 on the manufacturing process for forming the contact structure CT1 can be reduced, so that the electrical connection between the contact structure CT1 and the first stacked structure WL can be improved, thereby improving the manufacturing yield of the semiconductor device.

In some embodiments, semiconductor substrate 10 may comprise a silicon substrate, a silicon-germanium semiconductor substrate, a silicon-on-insulator (SOI) substrate, or a substrate formed of other suitable materials. The semiconductor substrate 10 may have opposite upper and bottom surfaces BS in a vertical direction D3 substantially orthogonal to the horizontal direction D1, and the vertical direction D3 may be regarded as a thickness direction of the semiconductor substrate 10, but is not limited thereto. Herein, a relatively higher position in the vertical direction D3 and/or a distance in the vertical direction D3 between a component and the bottom surface BS of the semiconductor substrate 10 may be larger than a relatively lower position in the vertical direction D3 and/or a distance in the vertical direction D3 between a component and the bottom surface BS of the semiconductor substrate 10, a lower portion or bottom of each component may be closer to the bottom surface BS of the semiconductor substrate 10 in the vertical direction D3 than an upper portion or top of this component, another component above a certain component may be regarded as being relatively farther from the bottom surface BS of the semiconductor substrate 10 in the vertical direction D3, and another component below a certain component may be regarded as being relatively closer to the bottom surface BS of the semiconductor substrate 10 in the vertical direction D3. Furthermore, the upper surface of a certain component described herein may include the uppermost (toppost) surface of the component in the vertical direction D3, while the bottom surface of a certain component may include the bottommost (bottom) surface of the component in the vertical direction D3, but is not limited thereto.

In some embodiments, the semiconductor device 101 may include an insulating structure 12 disposed in the semiconductor substrate 10, the semiconductor substrate 10 may include a plurality of fin structures 10F isolated by the insulating structure 12, and at least a portion of each fin structure 10F may be regarded as an active region AR, but is not limited thereto. In some embodiments, fin structures 10F may be formed by a patterning process on semiconductor substrate 10, so fin structures 10F may comprise semiconductor material (such as, but not limited to, silicon) in semiconductor substrate 10, and a plurality of fin structures 10F may be separated by insulating structures 12. The insulating structure 12 may comprise a single layer or multiple layers of insulating material such as oxide insulating material, nitride insulating material, or other suitable insulating material. In some embodiments, the semiconductor device 101 may further include a stress material layer 13 and an oxide layer 21, the stress material layer 13 may be disposed between the insulating structure 12 and the semiconductor substrate 10, and the oxide layer 21 may be disposed partially between the first stack structure WL and the fin structure 10F and partially between the first stack structure WL and the stress material layer 13. The stress material layer 13 includes a germanium-containing layer, such as a material layer including germanium and/or silicon germanium, which may generate appropriate stress and preferably has a lattice structure, but is not limited thereto. For example, the stress material layer 13 may comprise silicon germanium or germanium, and the semiconductor substrate 10 and the fin structure 10F may comprise silicon, thereby improving the lattice structure of the semiconductor substrate 10 and the fin structure 10F. In some embodiments, the stress material layer 13 may include a carbide such as silicon carbide or other material for generating appropriate stress and improving the lattice structure. The oxide layer 21 disposed between the first stack structure WL and the fin structure 10F may include the same element as the material of the fin structure 10F, for example, may include silicon oxide, and the oxide layer 21 disposed between the first stack structure WL and the stress material layer 13 may include the same element as the material of the stress material layer 13, for example, may include silicon germanium oxide or germanium oxide, but is not limited thereto.

In some embodiments, the semiconductor device 101 may include a plurality of first stacked structures WL, each of which may extend in the horizontal direction D1, a plurality of first stacked structuresWL may be repeatedly arranged along the horizontal direction D2, and the horizontal direction D2 may be substantially orthogonal to the horizontal direction D1, but is not limited thereto. Each first stack structure WL may be disposed within a trench TR in the semiconductor substrate 10, and each first stack structure WL may extend across the plurality of fin structures 10F in the horizontal direction D1. Furthermore, in some embodiments, the first stacked structure WL may further include a dielectric layer 22 located within the trench TR, and the dielectric layer 22 may be partially disposed between the conductive layer 24 and the fin structure 10F and partially disposed between the conductive layer 24 and the insulating structure 12, for example, but not limited to, partially disposed between the sidewall 24E of the conductive layer 24 and the insulating structure 12 in the horizontal direction D1. The dielectric layer 22 may comprise a high-k dielectric material or other suitable dielectric material. The high-k dielectric material may include hafnium oxide (HfO) _X ) Hafnium silicate oxide (hafnium silicon oxide, hfSiO) ₄ ) Hafnium silicate oxynitride (hafnium silicon oxynitride, hfSiON), aluminum oxide (Al) ₂ O ₃ ) Tantalum oxide (Ta) ₂ O ₅ ) Zirconium oxide, zrO ₂ ) Or other suitable high dielectric constant material. Conductive layer 24 may comprise a single layer or multiple layers of conductive material such as titanium nitride, titanium carbide, tantalum nitride, tantalum carbide, tungsten nitride, tungsten carbide, titanium aluminide, aluminum nitride, titanium, tungsten, aluminum, copper, tantalum, or other suitable metallic or non-metallic conductive material, while cap layer 26 may comprise doped polysilicon, undoped polysilicon, or other materials different than conductive layer 24 and dielectric cap layer 28. Dielectric cap layer 28 may comprise silicon nitride, silicon oxide, silicon oxynitride, combinations thereof, or other suitable dielectric materials.

In some embodiments, the conductive layer 24 may include a first portion 24A and a second portion 24B in the cell region R1 and the surrounding region R2, respectively, and the conductive layer 24 (e.g., the second portion 24B) in the surrounding region R2 may be covered by a second portion 26B of the cap layer 26, so that the upper surface 24T of the conductive layer 24 in the surrounding region R2 does not directly contact the dielectric cap layer 28. In some embodiments, the first portion 26A and the second portion 26B of the cap layer 26 may be directly connected, the bottom surface of the first portion 26A and the bottom surface of the second portion 26B may be substantially coplanar, and the upper surface TS1 of the first portion 26A may be higher than the upper surface TS2 of the second portion 26B in the vertical direction D3. In some embodiments, the surface of the cap layer 26 includes a stepped structure SS, such as the upper surface TS1 of the first portion 26A, the sidewall 26E of the first portion 26A, and the upper surface TS2 of the second portion 26B may be connected to one another to form the stepped structure SS, while the sidewall 26E of the first portion 26A may be located at an interface between the first portion 26A and the second portion 26B (e.g., interface INT 2) and face the contact structure CT1 in the horizontal direction D1. In some embodiments, the upper surface of cap layer 26 (e.g., upper surface TS2 of second portion 26B) and another portion of cap layer 26 (e.g., first portion 26A) that are in direct contact with contact structure CT1 may be located on two opposite sides of stepped structure SS, respectively, e.g., two opposite sides of stepped structure SS in horizontal direction D1.

In some embodiments, the sidewalls 26E of the first portion 26A of the cap layer 26 may face the contact structure CT1 in the horizontal direction D1, and the sidewalls 26E of the first portion 26A may be separated from the contact structure CT1, while a portion of the dielectric cap layer 28 may be located between the sidewalls 26E of the first portion 26A and the contact structure CT1 in the horizontal direction D1. In some embodiments, the first portion 26A of the cap layer 26 may be disposed partially in the cell region R1 and partially in the surrounding region R2, and the sidewall 26E of the first portion 26A may be located in the surrounding region R2. The distance in the horizontal direction D1 between the sidewall 26E of the first portion 26A of the cap layer 26 and the contact structure CT1 may be defined as a distance DS1, and the distance in the horizontal direction D1 between the contact structure CT1 and the fin structure 10F adjacent to the contact structure CT1 may be defined as a distance DS3. In some embodiments, the distance DS1 may be smaller than the distance DS3, but is not limited thereto. Furthermore, in some embodiments, the contact structure CT1 may extend downward in the vertical direction D3 and be partially located in the conductive layer 24, so the bottom surface BS1 of the contact structure CT1 may be lower than the upper surface 24T of the conductive layer 24 in the vertical direction D3.

In some embodiments, the semiconductor device 101 may further include a plurality of second stacked structures BL and a plurality of insulating patterns 42 disposed on the semiconductor substrate 10, each of the second stacked structures BL may extend in a horizontal direction D2 and be disposed over the cell region R1 and the surrounding region R2, and each of the fin structures 10F may extend in another horizontal direction different from the horizontal direction D1 and the horizontal direction D2. In addition, the plurality of second stacked structures BL may be repeatedly arranged in the horizontal direction D1, and each insulating pattern 42 may be located between adjacent second stacked structures BL. In some embodiments, one of the second stacked structures BL may be disposed adjacent to an interface (e.g., the interface INT 1) of the cell region R1 and the surrounding region R2 in the horizontal direction D1, and the width of the second stacked structure BL may be larger than that of the other second stacked structures BL, but is not limited thereto. Each of the second stack structures BL may partially overlap the plurality of first stack structures WL in the vertical direction D3, and each of the second stack structures BL may include a conductive layer 34, a conductive layer 36, and a cap layer 38 stacked in the vertical direction D3. In some embodiments, conductive layer 34 may comprise a non-metallic conductive material (e.g., doped polysilicon or other suitable non-metallic conductive material), conductive layer 36 may comprise a metallic conductive material (e.g., tungsten, titanium or other suitable metallic conductive material), and cap layer 38 may comprise a nitride insulating material, an oxynitride insulating material, or other suitable insulating material. In addition, the insulating pattern 42 may include a nitride insulating material or other suitable insulating material. In some embodiments, the first stacked structure WL may be a word line structure (e.g., a buried word line structure), the second stacked structure BL may be a bit line structure, and the semiconductor device 101 may be a memory device, but is not limited thereto. In addition, a distance between the second stacked structure BL and the contact structure CT1 disposed adjacent to the interface INT1 in the horizontal direction D1 may be defined as a distance DS2, and in some embodiments, the above-defined distance DS1 may be smaller than the distance DS2 because the sidewall 26E of the first portion 26A of the cap layer 26 is located in the surrounding region R2, but is not limited thereto.

In some embodiments, the semiconductor device 101 may further include a mask layer 32, the mask layer 32 is disposed on the first stack structures WL, a portion of each second stack structure BL may be disposed on the mask layer 32, and the mask layer 32 may include silicon nitride, silicon oxide, silicon oxynitride, a combination of the above materials, or other suitable mask material. In addition, the semiconductor device 101 may further include a plurality of sidewall structures SP disposed on the sidewalls of the corresponding second stack structures BL, and each sidewall structure SP may include a multi-layer structure formed of different insulating materials, but is not limited thereto. For example, the sidewall structure SP may include a spacer S1, a spacer S2 and a spacer S3 sequentially stacked along the horizontal direction D1 from the sidewall of the second stacked structure BL, and the spacers S1, the spacers S2 and the spacers S3 may be a nitride insulating material, an oxide insulating material and a nitride insulating material, or other combinations thereof, but are not limited thereto.

In some embodiments, semiconductor device 101 may further include dielectric layer 44, dielectric layer 46, and contact structure CT2. The dielectric layer 44 may be disposed on the cell region R1 and the surrounding region R2 of the semiconductor substrate 10 and cover the first stack structure WL, and the dielectric layer 46 may be disposed on the dielectric layer 44, the second stack structure BL and the insulating pattern 42. In some embodiments, the contact structure CT1 may make electrical connection with the conductive layer 24 in the surrounding region R2 of the corresponding first stacked structure WL through the dielectric layer 46, the dielectric layer 44, the dielectric cap layer 28, and the second portion 26B of the cap layer 26 in the vertical direction D3, the contact structure CT2 may be disposed on the surrounding region R2, and the contact structure CT2 may make electrical connection with the conductive layer 36 in the corresponding second stacked structure BL through the dielectric layer 46 and the cap layer 38 in the vertical direction D3. In addition, the contact structure CT1 and the contact structure CT2 may include the same material composition, for example, but not limited to, the barrier layer 52 and the conductive layer 54 disposed on the barrier layer 52. Barrier layer 52 may comprise titanium nitride, tantalum nitride, or other suitable conductive barrier material, and conductive layer 54 may comprise copper, aluminum, tungsten, molybdenum, alloys of the above, composite structures, or other suitable conductive materials. In some embodiments, the contact structure CT1 may be formed together with other contact structures (such as but not limited to the contact structure CT2 described above) in the same manufacturing process, and by disposing the cap layer 26 in the first stacked structure WL of the present embodiment, the negative effect of the cap layer 26 on the manufacturing process for forming the contact structure CT1 may be reduced. For example, when the cover layer 26 does not have the relatively thin second portion 26B, the second portion 26B with relatively thin thickness can still be used to cover the conductive layer 24 to protect the conductive layer 24, so as to improve the manufacturing yield of the semiconductor device.

Please refer to fig. 1 to 13. Fig. 4 to 13 are schematic views illustrating a method of fabricating a semiconductor device according to an embodiment of the present invention, in which fig. 5 is a schematic view of the situation after fig. 4, fig. 6 is a schematic view of the situation after fig. 5, fig. 7 is a schematic view of the situation after fig. 6, fig. 8 is a schematic view of the situation after fig. 7, fig. 9 is a schematic view of the situation after fig. 8, fig. 10 is a schematic view of the situation after fig. 9, fig. 11 is a schematic view of the situation after fig. 10, fig. 12 is another cross-sectional view in the situation of fig. 11, and fig. 13 is a cross-sectional view of another region in the situation of fig. 11. In some embodiments, fig. 2 may be regarded as a schematic diagram of the situation after fig. 11, and fig. 3 may be regarded as a schematic diagram of the situation after fig. 12, but is not limited thereto. As shown in fig. 1, 2 and 3, an embodiment of the present invention provides a method for manufacturing a semiconductor device, which includes the following steps. A semiconductor substrate 10 is provided, the semiconductor substrate 10 has a cell region R1 and a surrounding region R2, and the semiconductor substrate 10 includes at least one fin structure 10F isolated by an insulating structure 12. A first stack structure WL is formed in the semiconductor substrate 10, extends across the fin structure 10F in the horizontal direction D1 and is formed in the cell region R1 and the surrounding region R2, and includes a conductive layer 24, a cap layer 26, and a dielectric cap layer 28. Conductive layer 24 is partially located in cell region R1 and partially located in surrounding region R2, cap layer 26 is disposed on conductive layer 24, and dielectric cap layer 28 is disposed on cap layer 26. The cap layer 26 includes a first portion 26A and a second portion 26B, the first portion 26A is at least partially located in the cell region R1, the second portion 26B is at least partially located in the surrounding region R2, and a thickness TK2 of the second portion 26B is less than a thickness TK1 of the first portion 26A. Then, a contact structure CT1 is formed, the contact structure CT1 directly contacting the second portion 26B of the cap layer 26 and being electrically connected to the first stacked structure WL.

Further, the method for manufacturing the semiconductor device of the present embodiment may include, but is not limited to, the following steps. As shown in fig. 4, a plurality of fin structures 10F may be formed by performing a patterning process on the semiconductor substrate 10, and the stress material layer 13 and the insulating structure 12 may be formed after the fin structures 10F are formed. Then, as shown in fig. 4 and 5, a portion of the fin structure 10F (e.g., an upper portion of the fin structure 10F), a portion of the stress material layer 13, and a portion of the insulating structure 12 may be removed to form a trench TR in the semiconductor substrate 10, and the trench TR may be partially located in the cell region R1 and partially located in the surrounding region R2. In some embodiments, in order to increase the surface area of the fin structure 10F covered by the subsequently formed first stacked structure across the fin structure 10F, the fin structure 10F may protrude upward from the bottom of the trench TR by adjusting the etching process for forming the trench TR. After trench TR is formed, exposed stress material layer 13 and fin structure 10F may be oxidized to form oxide layer 21. Then, as shown in fig. 6, a dielectric layer 22 and a conductive layer 24 may be formed in the trench TR, the dielectric layer 22 may be conformally formed in the trench TR and conformally formed on the surface of the insulating structure 12 and the surface of the oxide layer 21, the conductive layer 24 is formed on the dielectric layer 22, and the conductive layer 24 includes a first portion 24A located in the cell region R1 and a second portion 24B located in the surrounding region R2. In some embodiments, a conductive material may be formed on the semiconductor substrate 10, and the conductive material may partially fill the trench TR and partially be located outside the trench TR, and then a planarization process and/or an etching process may be used to remove the conductive material located outside the trench TR and a portion of the conductive material located inside the trench TR to form the conductive layer 24, but is not limited thereto.

Thereafter, as shown in fig. 10, the cap layer 26 having the first portion 26A and the second portion 26B described above may be formed on the conductive layer 24. As shown in fig. 7, in some embodiments, a capping layer material 26M may be formed on the conductive layer 24, and the capping layer material 26M may be partially located in the cell region R1, partially located in the surrounding region R2, and partially located on the insulating structure 12, but is not limited thereto. A removal process 90 may then be performed on the cap layer material 26M to remove a portion of the cap layer material 26M to form a first portion 26A and a second portion 26B of the cap layer 26 as shown in fig. 10. In some embodiments, the removal process 90 may include, but is not limited to, the following steps. As shown in fig. 7 and 8, a patterned masking layer 30 may be formed on the capping layer material 26M, and a first removing step 91 may be performed on the capping layer material 26M using the patterned masking layer 30 as a mask, where a portion of the capping layer material 26M not covered by the patterned masking layer 30 (e.g., a portion of the capping layer material 26M located in the surrounding region R2) may be partially removed by the first removing step 91. In some embodiments, a portion of the capping layer material 26M located in the surrounding region R2 may be removed by the first removing step 91, so that the thickness of the portion of the capping layer material 26M is reduced, and the capping layer material 26M located on the insulating structure 12 may be completely removed by the first removing step 91, but is not limited thereto. As shown in fig. 7-9, after the first removal step 91, a second removal step 92 may be performed on the cap layer material 26M, and the patterned masking layer 30 may be removed after the first removal step 91 and before the second removal step 92, so that the surface of the cap layer material 26M may be completely exposed in the second removal step 92. As shown in fig. 9 and 10, in some embodiments, another portion of the cap layer material 26M located in the surrounding region R2 and a portion of the cap layer material 26M located in the cell region R1 may be removed by a second removal step 92 to form the cap layer 26 having a first portion 26A and a second portion 26B. It should be noted that the method for forming the cap layer 26 having the first portion 26A and the second portion 26B may include, but is not limited to, the manufacturing steps shown in fig. 7 to 10. In some embodiments, other methods may be used to form the cap layer 26 having different thicknesses of the first portion 26A and the second portion 26B, as desired by the design. In some embodiments, the first removing step 91 in fig. 7 and the second removing step 92 in fig. 9 may each include an etching step (such as, but not limited to, an anisotropic dry etching step) or other suitable removing method, and the capping layer material 26M may include doped polysilicon, undoped polysilicon, or other capping layer material different from the conductive layer 24.

As shown in fig. 11, after the cap layer 26 is formed, a dielectric cap layer 28 may be formed in the trench TR, thereby forming a first stack structure WL. In other words, the dielectric cap layer 28 may be formed in the trench TR after the removal process 90 described above. It should be noted that the method for forming the first stacked structure WL may include, but is not limited to, the manufacturing steps shown in fig. 6 to 11. In some embodiments, the first stack structure WL may be formed in the semiconductor substrate 10 using other methods as desired by design. As shown in fig. 11 and 12, after the first stack structure WL is formed, the mask layer 32, the second stack structure BL, the sidewall structure SP, the insulating pattern 42, the dielectric layer 44, and the dielectric layer 46 may be formed. Then, an opening OP1 extending partially into the conductive layer 24 through the dielectric layer 46, the dielectric layer 44 and the dielectric cap layer 28 and an opening OP2 extending through the dielectric layer 46 and the cap layer 38 may be formed, and a contact structure CT1 corresponding to the first stacked structure WL may be formed in the opening OP1 and a contact structure CT2 corresponding to the second stacked structure BL may be formed in the opening OP2 in a subsequent manufacturing process. In some embodiments, the openings OP1 and OP2 may be formed by the same manufacturing process, but not limited thereto. As shown in fig. 11, 12, and 13, in some embodiments, a transistor structure T may also be formed on the semiconductor substrate 10, the transistor structure T may include a gate dielectric layer 33, a gate 35, a gate cap layer 37, a sidewall structure 39, and source/drain regions 40. In some embodiments, the dielectric layer 44 also covers the transistor structure T, the opening OP3 may penetrate the dielectric layer 46 and the dielectric layer 44 in the vertical direction D3 to expose the source/drain region 40, and a contact structure corresponding to the source/drain region 40 may be formed in the opening OP3 in a subsequent manufacturing process. In some embodiments, the openings OP1, OP2 and OP3 can be formed together by the same manufacturing process, thereby achieving the effect of simplifying the manufacturing process, but not limited thereto. In some embodiments, the gate 35 of the transistor structure T may be disposed on the fin structure 10F, and the fin structure 10F of the corresponding transistor structure T and the fin structure 10F of the corresponding first stacked structure WL may extend in the same or different horizontal directions. As shown in fig. 11, 12, 2 and 3, after the openings OP1 and OP2 are formed, the contact structures CT1 and CT2 may be formed, thereby forming the semiconductor device 101.

The following description will be made with respect to different embodiments of the present invention, and for simplicity of description, the following description mainly describes different parts of each embodiment, and the same parts will not be repeated. In addition, like parts in the various embodiments of the present invention are designated by like reference numerals to facilitate cross-reference between the various embodiments.

Please refer to fig. 14. Fig. 14 is a cross-sectional view of a semiconductor device 102 according to a second embodiment of the present invention. In the semiconductor device 102, the second portion 26B of the cap layer 26 is also partially located in the cell region R1, and the sidewall 26E of the first portion 26A of the cap layer 26 and the stair-step structure SS may be located in the cell region R1. In this case, the defined distance DS1 may be less than or equal to the defined distance DS3, and the distance DS1 may be less than the defined distance DS2, but is not limited thereto.

Please refer to fig. 15. Fig. 15 is a cross-sectional view of a semiconductor device 103 according to a third embodiment of the present invention. In the semiconductor device 103, the sidewall 26E of the first portion 26A of the cap layer 26 is located at the interface between the cell region R1 and the surrounding region R2, so that the interface INT1 and the interface INT2 may at least partially overlap. In this case, the defined distance DS1 may be smaller than the defined distance DS3, and the distance DS1 may be smaller than the defined distance DS2, but is not limited thereto.

Please refer to fig. 16. Fig. 16 is a cross-sectional view of a semiconductor device 104 according to a fourth embodiment of the present invention. In the semiconductor device 104, the contact structure CT1 may directly contact the sidewall 26E of the first portion 26A of the cap layer 26, and the first portion 26A of the cap layer 26 may be partially disposed in the surrounding region R2.

Please refer to fig. 17. Fig. 17 is a cross-sectional view of a semiconductor device 105 according to a fifth embodiment of the present invention. In the semiconductor device 105, the contact structure CT1 also directly contacts the first portion 26A of the cap layer 26, the first bottom surface BS11 of the contact structure CT1 is located between the first portion 26A of the cap layer 26 and the second bottom surface BS12 of the contact structure CT1 in the horizontal direction D1, the first bottom surface BS11 may be regarded as being relatively close to the cell region R1 in the horizontal direction D1, the second bottom surface BS12 may be regarded as being relatively far from the cell region R1 in the horizontal direction D1, and the second bottom surface BS12 is lower than the first bottom surface BS11 in the vertical direction D3. In some embodiments, it is contemplated that the location where the opening OP1 is formed may overlap the stepped structure SS of the cap layer 26 in the vertical direction D3 prior to forming the opening OP1, and thus be affected by the stepped structure SS when forming the opening OP1 such that the bottom of the opening OP1 may also have a stepped structure.

Please refer to fig. 18. Fig. 18 is a cross-sectional view of a semiconductor device 106 according to a sixth embodiment of the present invention. In the semiconductor device 106, the mask layer 32 may be partially located on the surrounding region R2, and the contact structure CT1 may be in contact with the conductive layer 24 in the first stacked structure WL through the dielectric layer 46, the dielectric layer 44, the mask layer 32, the dielectric cap layer 28, and the second portion 26B of the cap layer 26 in the vertical direction D3 to form an electrical connection. In addition, the sidewall 26E of the first portion 26A of the cap layer 26 and the step structure SS may be located in the cell region R1, the defined distance DS1 may be greater than the defined distance DS3, and the distance DS1 may be greater than the defined distance DS2, but is not limited thereto.

Please refer to fig. 19. Fig. 19 is a cross-sectional view of a semiconductor device 107 according to a seventh embodiment of the present invention. In the semiconductor device 107, the sidewall 26E of the first portion 26A of the cap layer 26 and the step structure SS may be located in the cell region R1 and separated from the contact structure CT1, the defined distance DS1 may be smaller than the defined distance DS3, and the distance DS1 may be smaller than the defined distance DS2, but not limited thereto.

Please refer to fig. 20. Fig. 20 is a cross-sectional view of a semiconductor device 108 according to an eighth embodiment of the present invention. In the semiconductor device 108, the sidewall 26E and the step structure SS of the first portion 26A of the cap layer 26 may be located in the cell region R1 and separated from the contact structure CT1, and the sidewall 26E and the step structure SS may be located on one fin structure 10F closest to the contact structure CT1 among the fin structures 10F, and the defined distance DS1 may be greater than the defined distance DS3, and the distance DS1 may be greater than the defined distance DS2, but is not limited thereto.

In summary, in the semiconductor device and the method for manufacturing the same of the present invention, the cap layer having the portions with different thicknesses can be used to reduce the adverse effect of the cap layer on the manufacturing process for forming the contact structure, and the thinner portion of the cap layer can be used to cover the conductive layer to provide the protection effect, so that the electrical connection condition between the contact structure and the first stacked structure can be improved and the manufacturing yield of the semiconductor device can be improved.

The above description is only of the preferred embodiments of the present invention and is not intended to limit the present invention, but various modifications and variations can be made to the present invention by those skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. A semiconductor device, comprising:

a semiconductor substrate having a cell region and a surrounding region, wherein the semiconductor substrate comprises at least one fin structure separated by an insulating structure;

a first stacked structure disposed in the semiconductor substrate, wherein the first stacked structure extends in a horizontal direction across the fin structure and is disposed in the cell region and the surrounding region, and the first stacked structure includes:

a conductive layer partially located in the cell region and partially located in the peripheral region;

a cap layer disposed on the conductive layer, and the cap layer includes:

a first portion at least partially located in the cell region; and

a second portion at least partially located in the peripheral region, wherein a thickness of the second portion is less than a thickness of the first portion; and

a dielectric cap layer disposed on the cap layer; and

and a contact structure directly contacting the second portion of the cap layer and electrically connected to the first stack structure.

2. The semiconductor device of claim 1, wherein said conductive layer in said peripheral region is covered by said second portion of said cap layer.

3. The semiconductor device of claim 1, wherein an upper surface of said first portion of said cap layer is vertically higher than an upper surface of said second portion of said cap layer.

4. The semiconductor device of claim 1, wherein the first portion of the cap layer is connected to the second portion of the cap layer, and a sidewall of the first portion of the cap layer is located at an interface between the first portion of the cap layer and the second portion of the cap layer and faces the contact structure in the horizontal direction.

5. The semiconductor device of claim 4, wherein said sidewalls of said first portion of said cap layer and said contact structure are separated from each other.

6. The semiconductor device of claim 4, wherein said sidewall of said first portion of said cap layer is located at an interface between said cell region and said surrounding region.

7. The semiconductor device of claim 4, wherein said second portion of said cap layer is also partially located in said cell region and said sidewall of said first portion of said cap layer is located in said cell region.

8. The semiconductor device of claim 4, wherein said contact structure directly contacts said sidewall of said first portion of said cap layer.

9. The semiconductor device of claim 4, wherein a distance in the horizontal direction between the sidewall of the first portion of the cap layer and the contact structure is less than a distance in the horizontal direction between the fin structure and the contact structure.

10. The semiconductor device of claim 4, wherein said semiconductor substrate comprises a plurality of fin structures separated by said insulating structure, and said sidewall of said first portion of said cap layer is located over a fin structure of said plurality of fin structures closest to said contact structure.

11. The semiconductor device according to claim 4, further comprising:

and a second stacked structure disposed over the semiconductor substrate, wherein the second stacked structure is disposed on the cell region, the second stacked structure is disposed adjacent to an interface between the cell region and the surrounding region, and a distance between the sidewall of the first portion of the cap layer and the contact structure in the horizontal direction is smaller than a distance between the second stacked structure and the contact structure in the horizontal direction.

12. The semiconductor device of claim 1, wherein said contact structure further directly contacts said first portion of said cap layer, a first bottom surface of said contact structure being located between said first portion of said cap layer and a second bottom surface of said contact structure in said horizontal direction, and said second bottom surface being lower than said first bottom surface in a vertical direction.

13. The semiconductor device of claim 1, wherein said contact structure extends through said second portion of said cap layer to contact said conductive layer in said peripheral region.

14. The semiconductor device of claim 1, wherein the conductive layer comprises a metallic conductive material and the cap layer comprises doped polysilicon or undoped polysilicon.

15. A method of manufacturing a semiconductor device, comprising:

providing a semiconductor substrate, wherein the semiconductor substrate is provided with a cell area and a surrounding area, and comprises at least one fin-shaped structure isolated by an insulating structure;

forming a first stack structure in the semiconductor substrate, wherein the first stack structure extends in a horizontal direction across the fin structure and is formed in the cell region and the surrounding region, and the first stack structure includes:

a cap layer disposed on the conductive layer, and the cap layer includes:

a first portion at least partially located in the cell region; and

a dielectric cap layer disposed on the cap layer; and

a contact structure is formed, wherein the contact structure directly contacts the second portion of the cap layer and is electrically connected to the first stack structure.

16. The method of manufacturing a semiconductor device according to claim 15, wherein the method of forming the first stacked structure comprises:

forming a trench in the semiconductor substrate, wherein the trench is partially located in the cell region and partially located in the peripheral region;

forming the conductive layer in the trench;

forming a cap material on the conductive layer, wherein the cap material is partially located in the cell region and partially located in the peripheral region; and

a removal process is performed on the cap material to remove a portion of the cap material to form the first portion and the second portion of the cap layer.

17. The method of manufacturing a semiconductor device according to claim 16, wherein the removing process comprises:

forming a patterned mask layer on the cover layer material, and performing a first removing step on the cover layer material by using the patterned mask layer as a mask, wherein a part of the cover layer material located in the surrounding area is removed by the first removing step; and

after the first removing step, a second removing step is performed on the cap layer material, wherein another portion of the cap layer material located in the peripheral region and a portion of the cap layer material located in the cell region are removed by the second removing step, and the patterned masking layer is removed after the first removing step and before the second removing step.

18. The method of manufacturing a semiconductor device according to claim 16, wherein the method of forming the first stacked structure further comprises:

after the removal process, the dielectric cap layer is formed in the trench.

19. A semiconductor device, comprising:

a semiconductor substrate, wherein the semiconductor substrate comprises at least one fin structure separated by an insulating structure;

a first stack structure disposed in the semiconductor substrate, wherein the first stack structure extends in a horizontal direction across the fin structure, and the first stack structure includes:

a conductive layer;

a cover layer disposed on the conductive layer, wherein the surface of the cover layer comprises a step structure; and

a dielectric cap layer disposed on the cap layer; and

and a contact structure directly contacting the cap layer and electrically connected with the first stacked structure, wherein a distance between an upper surface of the cap layer in direct contact with the contact structure and the conductive layer is smaller than a distance between an upper surface of another portion of the cap layer and the conductive layer.

20. The semiconductor device of claim 19, wherein the upper surface of the cap layer and the other portion of the cap layer in direct contact with the contact structure are located on two opposite sides of the stair-step structure, respectively.