CN218998732U - Memory device - Google Patents

Abstract

The utility model discloses a memory device. The memory device includes a substrate, a plurality of trenches, an oxide semiconductor layer, a gate dielectric layer, and a plurality of word line structures. The substrate comprises a plurality of active regions and an isolation structure positioned between the active regions, and the active regions contain silicon. A plurality of trenches are disposed in the active region and the isolation structure. An oxide semiconductor layer is conformally disposed in each trench, and a gate dielectric layer is disposed on the oxide semiconductor layer and in each trench. The plurality of word line structures are disposed on the gate dielectric layer and respectively in the plurality of trenches, and at least a portion of the gate dielectric layer is disposed between the oxide semiconductor layer and each of the word line structures. The method of manufacturing the memory device includes forming a plurality of trenches, conformally forming an oxide semiconductor layer in each trench, forming a gate dielectric layer on the oxide semiconductor layer, and forming a plurality of word line structures on the gate dielectric layer. Thus, the effect of improving the operation performance of the memory device can be achieved.

Description

Memory device

Technical Field

The present utility model relates to a memory device, and more particularly, to a memory device including an oxide semiconductor layer.

Background

The dynamic random access memory (dynamic random access memory, DRAM) is a volatile memory, and includes an array area (array area) formed of a plurality of memory cells (memory cells) and a peripheral area (peripheral area) formed of a control circuit. Each memory cell is composed of a transistor (transducer) and a capacitor (capacitor) electrically connected with the transistor, and the transistor controls the storage or release of charges in the capacitor to achieve the purpose of storing data. Control circuitry controls access of data to each memory cell by addressing each memory cell through Word Lines (WL) and Bit Lines (BL) that span the array region and are electrically connected to each memory cell.

To reduce the size of memory cells to produce chips with higher density, the structure of memory cells has been advanced toward three-dimensional (three-dimensional) technology, such as using buried word line (word line) and stacked capacitors (stacked capacitor). However, in this situation, how to improve the device operation performance by new designs in terms of structure and/or manufacturing process has been the goal of continuous efforts in the related industry.

Disclosure of Invention

The utility model provides a memory device and a method of manufacturing the same, which can improve the operation performance of the memory device by disposing an oxide semiconductor layer in a trench.

An embodiment of the utility model provides a memory device, which comprises a substrate, a plurality of trenches, an oxide semiconductor layer, a gate dielectric layer and a plurality of word line structures. The substrate comprises a plurality of active regions and an isolation structure, wherein the isolation structure is positioned among the plurality of active regions, and the plurality of active regions contain silicon. The trenches are disposed in the active regions and the isolation structures. The oxide semiconductor layer is conformally disposed in each of the trenches, and the gate dielectric layer is disposed on the oxide semiconductor layer and in each of the trenches. The plurality of word line structures are disposed on the gate dielectric layer and in the plurality of trenches, respectively, and at least a portion of the gate dielectric layer is disposed between the oxide semiconductor layer and each of the word line structures.

An embodiment of the present utility model provides a method for manufacturing a memory device, including the following steps. A substrate is provided, the substrate including a plurality of active regions and an isolation structure. The isolation structure is positioned between a plurality of the active regions, and the plurality of the active regions contain silicon. A plurality of trenches are formed in the plurality of active regions and the isolation structure, an oxide semiconductor layer is conformally formed in each of the trenches, and a gate dielectric layer is formed on the oxide semiconductor layer. The gate dielectric layer is located in each of the trenches. A plurality of word line structures are formed on the gate dielectric layer, wherein the plurality of word line structures are respectively located in the plurality of trenches, and at least a portion of the gate dielectric layer is disposed between the oxide semiconductor layer and each of the word line structures.

Drawings

The accompanying drawings are included to provide a further understanding of embodiments of the utility model and are incorporated in and constitute a part of this specification. These drawings and description serve to illustrate principles of some embodiments. It should be noted that all illustrations are schematic, and relative dimensions and proportions are adjusted for ease of illustration and drawing. The same reference signs represent corresponding or similar features in different embodiments.

Fig. 1, fig. 2, fig. 3 and fig. 4 are schematic views illustrating a manufacturing method of a memory device according to an embodiment of the utility model, wherein fig. 1 is a top view, fig. 2 is a schematic view of the memory device after fig. 1, fig. 3 is a schematic view of the memory device after fig. 2, and fig. 4 is a schematic view of the memory device after fig. 3.

Fig. 5 is a schematic cross-sectional view of a memory device according to an embodiment of the present utility model.

Fig. 6 is a schematic top view of a memory device according to an embodiment of the utility model.

Wherein reference numerals are as follows:

10. substrate

10B bottom surface

10T upper surface

12. Isolation structure

20. Oxide semiconductor layer

22. Gate dielectric layer

24. Work function layer

26. Conductive layer

28. Cover layer

32. Mask layer

34. Mask layer

36. Mask layer

38. Conductive layer

42. Dielectric layer

44. Dielectric layer

50. Storage node contact structure

52. Bit line contact structure

54. Silicide layer

56. Barrier layer

58. Conductive layer

62. Barrier layer

64. Conductive layer

66. Cover layer

91. First film forming process

92. Second film forming process

101. Memory device

AA active region

BL bit line structure

D1 Direction of

D2 Direction of

D3 Direction of

D4 Direction of

DP1 depth

Depth of DP1

DP2 depth

DP2' depth

L1 length

L2 length

SP1 spacer

SP2 spacer

SS1 section

SS2 section

SS3 section

TK1 thickness

TK2 thickness

TR groove

TR1 first part

TR2 second part

WL word line structure

Detailed Description

In order to enable those skilled in the art to which the utility model pertains, a few preferred embodiments of the utility model are described below in detail, together with the accompanying drawings, in order to further explain the principles of the utility model and its advantages. Those skilled in the art to which the utility model pertains will be able to replace, reorganize, and mix features in several different embodiments with reference to the following examples to complete other embodiments without departing from the spirit of the utility model.

Please refer to fig. 1, 2, 3 and 4. Fig. 1, fig. 2, fig. 3 and fig. 4 are schematic views illustrating a manufacturing method of a memory device according to an embodiment of the utility model, wherein fig. 1 is a top view, fig. 2 is a schematic view of the memory device after fig. 1, fig. 3 is a schematic view of the memory device after fig. 2, and fig. 4 is a schematic view of the memory device after fig. 3. In some embodiments, fig. 2 may be regarded as a schematic view of the situation after the cross-sectional view along the line A-A' in fig. 1, but is not limited thereto. The manufacturing method of the present embodiment may include the following steps. As shown in fig. 4, a substrate 10 is provided, the substrate 10 includes a plurality of active areas AA and an isolation structure 12, and the isolation structure 12 is located between the plurality of active areas AA. A plurality of trenches TR are formed in the plurality of active regions AA and the isolation structure 12, and the oxide semiconductor layer 20 is formed conformally in each trench TR. A gate dielectric layer 22 is formed on the oxide semiconductor layer 20, and the gate dielectric layer 22 is located in each trench TR. A plurality of word line structures WL are formed on the gate dielectric layer 22, wherein the plurality of word line structures WL are respectively located in the plurality of trenches TR, and at least a portion of the gate dielectric layer 22 is disposed between the oxide semiconductor layer 20 and each of the word line structures WL.

Further, the manufacturing method of the present embodiment may include, but is not limited to, the following steps. As shown in fig. 1 and 2, in some embodiments, the substrate 10 may comprise a semiconductor substrate, such as a silicon substrate, an epitaxial silicon substrate, a silicon germanium substrate, a silicon carbide substrate, a silicon-on-insulator (SOI) substrate, or a substrate formed of other suitable materials. Before forming the trench TR, the isolation structure 12 may be formed in the substrate 10, and the isolation structure 12 may be used to define a plurality of active regions AA separated from each other in the substrate 10. For example, when the substrate 10 is a silicon-containing substrate, each active region AA may contain silicon. When silicon is the main component in the substrate 10, silicon may also be the main component in each active area AA. Isolation structure 12 may comprise a single layer or multiple layers of insulating material such as silicon nitride, silicon oxynitride, silicon carbide nitride, or other suitable insulating material. In some embodiments, the isolation structure 12 may be considered as shallow trench isolation (shallow trench isolation, STI), but is not limited thereto. In addition, the trenches TR may be formed in the substrate 10 after the isolation structures 12 are formed, and each trench TR may be staggered with one or more active regions AA. For example, each active region AA may extend in one horizontal direction (e.g., direction D2 shown in fig. 1), each trench TR may extend in another horizontal direction (e.g., direction D3 shown in fig. 1), and the directions D2 and D3 may be substantially orthogonal to the vertical direction (e.g., direction D1 shown in fig. 1), respectively, but not limited thereto. In some embodiments, each active area AA may be interleaved with two trenches TR, and the two trenches TR divide each active area AA into three segments (e.g., segment SS1, segment SS2, and segment SS3 shown in fig. 2), but not limited thereto. In other words, a portion of the substrate 10 (e.g., the sections SS1, SS2, and/or SS3 of the active region AA) may be disposed between adjacent two of the plurality of trenches TR and may be sandwiched (sandwiched) between the adjacent two of the trenches TR in a horizontal direction (e.g., the direction D2).

In some embodiments, the direction D1 may be considered as a thickness direction of the substrate 10, the substrate 10 may have an upper surface 10T and a bottom surface 10B opposite to each other in the direction D1, and each trench TR may extend from the upper surface 10T of the substrate 10 toward the bottom surface 10B along the direction D1 without penetrating through the substrate 10. The horizontal direction (e.g., direction D2, direction D3, and other directions orthogonal to direction D1) that is substantially orthogonal to direction D1 may be substantially parallel to the upper surface 10T and/or the bottom surface 10B of the substrate 10, but is not limited thereto. In this context, a relatively higher position in the direction D1 and/or a distance between a component and the bottom surface 10B of the substrate 10 in the direction D1 may be greater than a relatively lower position in the direction D1 and/or a distance between a component and the bottom surface 10B of the substrate 10 in the direction D1, a lower portion or bottom of each component may also be closer to the bottom surface 10B of the substrate 10 in the direction D1 than an upper portion or top of this component, another component above a certain component may be considered to be relatively farther from the bottom surface 10B of the substrate 10 in the direction D1, and another component below a certain component may be considered to be relatively closer to the bottom surface 10B of the substrate 10 in the direction D1.

In some embodiments, the trenches TR extending along the direction D3 may partially overlap the plurality of active regions AA, so each trench TR may include a first portion TR1 disposed in the active region AA and a second portion TR2 disposed in the isolation structure 12. In addition, the trench TR may be formed by performing an etching process on the substrate 10 and the isolation structure 12, and the depth of the trench TR in the active region AA may be different from the depth of the trench TR in the isolation structure 12, depending on the difference in etching rates of the material of the substrate 10 and the material of the isolation structure 12 in the etching process. For example, the depth DP1 of the first portion TR1 may be smaller than the depth DP2 of the second portion TR2, but is not limited thereto. Further, the depth of the above-described trench TR may be regarded as a distance in the direction D1 between the bottommost portion of the trench TR and the upper surface 10T of the substrate 10.

As shown in fig. 2, after the trench TR is formed, the oxide semiconductor layer 20 may be formed through a first film formation process 91. The oxide semiconductor layer 20 may include an oxide semiconductor material, such as indium gallium zinc oxide (indium gallium zinc oxide, IGZO), indium Tin Oxide (ITO), indium tin gallium oxide (indium tin gallium oxide, ITGO), indium zinc oxide (indium zinc oxide, IZO), zinc oxide (zinc oxide, znO), indium tin gallium zinc oxide (indium tin gallium zinc oxide, ITGZO), or other oxides with semiconductor characteristics, but not limited thereto.

The oxide semiconductor layer 20 may be conformally formed on the surface of each trench TR, the upper surface 10T of the substrate 10, and the upper surface of the isolation structure 12. In other words, the oxide semiconductor layer 20 does not fill each trench TR, and the thickness of the oxide semiconductor layer 20 may be smaller than the depth of each trench TR. For example, the thickness of the oxide semiconductor layer 20 in the direction D1 (e.g., the thickness TK1 of the oxide semiconductor layer 20 in the direction D1 in the first portion TR1 and the thickness TK2 of the oxide semiconductor layer 20 in the direction D1 in the second portion TR2 shown in fig. 2) may be smaller than the depth of each trench TR in the direction D1 (e.g., the above-described depths DP1 and DP 2). In some embodiments, the first film forming process 91 may include an atomic layer deposition (atomic layer deposition, ALD) process or other suitable film forming method to ensure that the oxide semiconductor layer 20 may be conformally formed on the surface of each trench TR to reduce the formation of voids (void) between the oxide semiconductor layer 20 and the substrate 10. In addition, since each trench TR may include a first portion TR1 disposed in the active region AA and a second portion TR2 disposed in the isolation structure 12, and the oxide semiconductor layer 20 may be formed in the first portion TR1 and the second portion TR2 of the trench TR, a portion of the oxide semiconductor layer 20 may also be considered to be disposed in the isolation structure 12.

As shown in fig. 2 and 3, after the oxide semiconductor layer 20 is formed, the gate dielectric layer 22 may be formed through a second film formation process 92. The gate dielectric layer 22 may comprise a high-k dielectric material or other suitable dielectric material. The high-k dielectric material may include hafnium oxide (HfO) _X ) Hafnium silicate oxide (hafnium silicon oxide, hfSiO) ₄ ) Hafnium silicate oxynitride (hafnium silicon oxynitride, hfSiON), aluminum oxide (Al) ₂ O ₃ ) Tantalum oxide (Ta) ₂ O ₅ ) Zirconium oxide, zrO ₂ ) Or other suitable high dielectric constant material. The gate dielectric layer 22 may be conformally formed on the oxide semiconductor layer 20. In other words, the gate dielectric layer 22 does not fill each trench TR, so the thickness of the gate dielectric layer 22 may be smaller than the depth of each trench TR. In some embodiments, the second film formation process 92 may include an atomic layer deposition process or other suitable film formation method to ensure that the gate dielectric layer 22 may be conformally formed on the oxide semiconductor layer 20 in each trench TR. Furthermore, in some embodiments, the first film forming process 91 and the second film forming process 92 may be performed sequentially in the same process chamber (process chamber), thereby reducing adverse effects of external environment and/or achieving process simplification. In some embodiments, the gate dielectric layer 22 having a higher dielectric constant and/or a smaller equivalent gate oxide thickness (equivalent oxide thickness, EOT) may also be used to improve the leakage condition of the corresponding semiconductor structure (e.g., transistor structure), but is not limited thereto.

Then, as shown in fig. 4, a plurality of word line structures WL may be formed in the substrate 10, and a storage node contact (storage node contact) structure 50, a bit line contact structure 52, and a bit line structure BL may be formed on the substrate 10. Each word line structure WL is formed in a corresponding trench TR, and the word line structure WL is formed on the gate dielectric layer 22 in the trench TR. In some embodiments, each word line structure WL may include, but is not limited to, a work function layer 24, a conductive layer 26, and a cap layer 28. Work function layer 24 may comprise titanium nitride, titanium carbide, tantalum nitride, tantalum carbide, tungsten carbide, titanium trialuminate, titanium aluminum nitride, or other suitable conductive work function material, conductive layer 26 may comprise tungsten, aluminum, copper, titanium aluminide, titanium, or other suitable relatively low resistivity conductive material, and cap layer 28 may comprise silicon nitride, silicon oxynitride, silicon carbide nitride, or other suitable insulating material. In some embodiments, after the formation of the word line structures WL, the oxide semiconductor layer 20, the gate dielectric layer 22 and/or other materials located outside the trenches TR may be removed by a suitable process (e.g., a chemical mechanical polishing process, but not limited thereto), and after this process, the depth of each trench TR (e.g., the depths DP1 'and DP2' shown in fig. 4) may be regarded as the distance between the bottommost portion of each trench TR and the upper surface of the word line structures WL (e.g., the upper surface of the cap layer 28) in the direction D1, but not limited thereto.

The word line structures WL located in the respective trenches TR may extend in the direction D1 and be surrounded by the gate dielectric layer 22 and the oxide semiconductor layer 20. In some embodiments, the length of each word line structure WL in the direction D1 is affected by the depth of the trench TR, for example, the length L1 of the word line structure WL in the direction D1 of the first portion TR1 of the trench TR may be smaller than the length L2 of the word line structure WL in the direction D1 of the second portion TR2 of the trench TR, but not limited thereto. In addition, the thickness of the oxide semiconductor layer 20 in the direction D1 (e.g., the thickness TK1 and the thickness TK 2) may be smaller than the depth of each trench TR in the direction D1 (e.g., the depth DP1 'and the depth DP 2'), and the thickness of the oxide semiconductor layer 20 in the direction D1 (e.g., the thickness TK1 and the thickness TK 2) may be smaller than the thickness of each word line structure WL in the direction D1 (e.g., the length L1 and the length L2), so as to increase the overlapping area of the word line structure WL and the oxide semiconductor layer 20, thereby improving the operation performance of the corresponding transistor structure. In addition, the depth of each trench TR in the direction D1 may also be greater than the width of each trench TR in the horizontal direction (e.g., the width in the direction D2 and/or the width in the direction D4 as shown in fig. 1), thereby achieving the effect of increasing the overlapping area between the word line structure WL and the oxide semiconductor layer 20 in cooperation with the oxide semiconductor layer 20 conformally formed in the trench TR.

In some embodiments, the above-mentioned sections SS1, SS2 and SS3 can also be regarded as three sections of the active areas AA divided into three sections by the word line structures WL crossing the active areas AA, the bit line structure BL can be formed on the section SS1, and two storage node contact structures 50 can be formed on the sections SS2 and SS3, respectively, but not limited thereto. Storage node contact structure 50 may comprise silicon, such as amorphous silicon, polysilicon, other silicon-containing conductive materials, or other types of conductive materials. In some embodiments, the bit line structure BL may include the barrier layer 62, the conductive layer 64, and the cap layer 66, and the bit line structure BL may be electrically connected to the active region AA through the bit line contact structure 52. Bit line contact structure 52 may comprise a metallic conductive material or a non-metallic conductive material such as polysilicon, amorphous silicon, or other silicon-containing non-metallic conductive material, barrier layer 62 may comprise titanium, titanium nitride, tungsten nitride, or other suitable conductive barrier material, conductive layer 64 may comprise aluminum, tungsten, copper, titanium aluminum alloy, or other suitable low resistance metallic conductive material, and cap layer 66 may comprise silicon nitride, silicon oxide, or other suitable insulating material. In some embodiments, the mask layer 32, the mask layer 34, and the dielectric layer 42 may be disposed between the adjacent storage node contact structures 50 and/or between the storage node contact structures 50 and the bit line structure BL, the spacers SP1 and SP2 may be disposed on the sidewalls of the bit line structure BL, and the dielectric layer 44, the silicide layer 54, the barrier layer 56, and the conductive layer 58 may be disposed on each storage node contact structure 50, but not limited thereto. Mask layer 32 and mask layer 34 may comprise silicon nitride, silicon oxynitride, silicon carbide nitride, or other suitable insulating material, dielectric layer 42 and dielectric layer 44 may comprise a nitride dielectric material or other suitable dielectric material, silicide layer 54 may comprise a conductive metal silicide material, barrier layer 56 may comprise titanium, titanium nitride, tungsten nitride, or other suitable conductive barrier material, conductive layer 58 may comprise aluminum, tungsten, copper, titanium aluminum alloy, or other suitable low resistance metal conductive material, and spacers SP1 and SP2 may comprise a single layer or a multi-layer stack of insulating materials, respectively. In some embodiments, a capacitor structure (not shown) may be disposed on the conductive layer 58, and the capacitor structure may be electrically connected to the storage node contact structure 50 through the conductive layer 58 and the silicide layer 54, but is not limited thereto.

In some embodiments, the storage node contact structure 50 may be directly connected to the substrate 10. In some embodiments, the storage node contact structure 50 may be directly connected to one of the active regions AA in the substrate 10 and the oxide semiconductor layer 20, and a portion of the oxide semiconductor layer 20 may be sandwiched between the gate dielectric layer 22 and the storage node contact structure 50 in a horizontal direction, but is not limited thereto. In some embodiments, a portion of the word line structure WL may be considered a gate of a transistor structure, the storage node contact structure 50 and the bit line contact structure 52 may be considered a source and a drain of the transistor structure, and a portion of the oxide semiconductor layer 20 and/or the active region AA may be used to form a semiconductor channel region of the transistor structure, but is not limited thereto. By conformally forming the oxide semiconductor layer 20 in the trench TR and utilizing the material characteristics of the oxide semiconductor layer 20, effects such as increasing on-current (Ion) of the transistor structure, decreasing off-current (Ioff), shortening write recovery time (tWR) of the memory device, increasing refresh frequency (refresh frequency) of the memory device, and/or improving operation power consumption condition of the memory device can be achieved.

By the above-described manufacturing method, the memory device 101 shown in fig. 4 can be formed. As shown in fig. 4, the memory device 101 includes a substrate 10, a plurality of trenches TR, an oxide semiconductor layer 20, a gate dielectric layer 22, and a plurality of word line structures WL. The substrate 10 includes a plurality of active areas AA and an isolation structure 12, and the isolation structure 12 is located between the plurality of active areas AA. A plurality of trenches TR are provided in the plurality of active regions AA and the isolation structure 12, an oxide semiconductor layer 20 is conformally provided in each trench TR, and a gate dielectric layer 22 is provided on the oxide semiconductor layer 20 and in each trench TR. A plurality of word line structures WL are disposed on the gate dielectric layer 22 and respectively in the plurality of trenches TR, and at least a portion of the gate dielectric layer 22 is disposed between the oxide semiconductor layer 20 and each word line structure WL.

Please refer to fig. 4, fig. 5 and fig. 6. Fig. 5 is a schematic cross-sectional view of a memory device according to an embodiment of the present utility model, and fig. 6 is a schematic top view of a memory device according to an embodiment of the present utility model. Fig. 6 mainly illustrates the layout of the active area AA, the trench TR, the word line structure WL and the bit line structure BL, fig. 4 may be regarded as a cross-sectional view along a line B-B' in fig. 6, and fig. 5 may be regarded as a cross-sectional view along another horizontal direction, but is not limited thereto. As shown in fig. 4, 5 and 6, the memory device 101 may further include a plurality of storage node contact structures 50, a plurality of bit line contact structures 52 and a plurality of bit line structures BL. The word line structure WL is disposed on the substrate 10 and is electrically connected to the active area AA through the bit line contact structure 52. The word line structures WL may extend along the direction D3 to cross the active areas AA, and divide each active area AA into three segments (e.g., the segment SS1, the segment SS2, and the segment SS 3). Each bit line structure BL may extend in a horizontal direction (e.g., direction D4) across the plurality of active areas AA and the plurality of trenches TR, respectively. The storage node contact structure 50 is disposed on the substrate 10, and the storage node contact structure 50 is directly connected to the substrate 10. In some embodiments, the storage node contact structure 50 may be directly connected to the active region AA in the substrate 10 and the oxide semiconductor layer 20.

In some embodiments, the gate dielectric layer 22 may be conformally disposed on the oxide semiconductor layer 20, and the word line structures WL located in the trenches TR may be surrounded by the gate dielectric layer 22 and the oxide semiconductor layer 20, the gate dielectric layer 22 and the work function layer may have a U-shaped structure or a V-shaped structure in the cross-sectional view of the memory device 101, respectively, but not limited thereto. In some embodiments, memory device 101 may further include a mask layer 36 disposed between bit line structure BL and mask layer 34, and bit line structure BL may further include a conductive layer 38 disposed between mask layer 36 and barrier layer 62. Conductive layer 38 may comprise a metallic conductive material or a non-metallic conductive material such as polysilicon, amorphous silicon, or other silicon-containing non-metallic conductive material, while masking layer 36 may comprise silicon nitride, silicon oxynitride, silicon carbide nitride, or other suitable insulating material. In some embodiments, the bit line contact structure 52 may be directly connected to the active region AA, the oxide semiconductor layer 20, and the gate dielectric layer 22 through the conductive layer 38, the mask layer 36, the mask layer 34, and the mask layer 32, but is not limited thereto.

In view of the above, in the memory device of the present utility model and the method of manufacturing the same, an oxide semiconductor layer may be provided in the trench to improve the operation performance of the memory device. In addition, the oxide semiconductor layer can be conformally formed on the surface of the groove and surrounds the word line structure, so that the overlapping area between the word line structure and the oxide semiconductor layer is increased, and the operation performance of the corresponding semiconductor structure can be improved.

The above description is only of the preferred embodiments of the present utility model and is not intended to limit the present utility model, but various modifications and variations can be made to the present utility model by those skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present utility model should be included in the protection scope of the present utility model.

Claims (10)

1. A memory device, comprising:

a substrate, comprising:

a plurality of active regions; and

an isolation structure between a plurality of the active regions, wherein the plurality of the active regions comprise silicon;

a plurality of trenches disposed in the plurality of active regions and the isolation structure;

an oxide semiconductor layer conformally disposed in each of the trenches;

a gate dielectric layer disposed on the oxide semiconductor layer and located in each of the trenches; and

and a plurality of word line structures disposed on the gate dielectric layer and respectively located in the plurality of trenches, and at least a portion of the gate dielectric layer is disposed between the oxide semiconductor layer and each of the word line structures.

2. The memory device according to claim 1, wherein a thickness of the oxide semiconductor layer in a vertical direction is smaller than a depth of each of the trenches in the vertical direction.

3. The memory device according to claim 1, wherein a thickness of the oxide semiconductor layer in a vertical direction is smaller than a length of each of the word line structures in the vertical direction.

4. The memory device of claim 1, wherein a portion of the substrate is disposed between adjacent ones of the plurality of trenches.

5. The memory device of claim 1, further comprising:

and a storage node contact structure disposed on the substrate, wherein the storage node contact structure is directly connected to one of the plurality of active regions of the substrate.

6. The memory device of claim 5, wherein the storage node contact structure is further directly connected to the oxide semiconductor layer.

7. The memory device according to claim 1, wherein the oxide semiconductor layer has a U-shaped structure in a cross-sectional view of the memory device.

8. The memory device of claim 1, wherein the gate dielectric layer is conformally disposed on the oxide semiconductor layer.

9. The memory device of claim 1, wherein a plurality of said word line structures span a plurality of said active regions and divide each of said active regions into three segments.

10. The memory device according to claim 1, wherein a portion of the oxide semiconductor layer is provided in the isolation structure.

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