CN117277974A - High-bandwidth transimpedance amplifier based on current buffer - Google Patents

Abstract

The invention discloses a high-bandwidth transimpedance amplifier based on a current buffer, which comprises the following components: the current buffer unit adopts an adjustable type cascode structure and comprises a voltage signal input end, a current signal input end and a current signal output end, wherein the voltage signal input end is used for being electrically connected with a power supply voltage signal end of a power supply voltage and a reference voltage signal end of a reference voltage source, the current signal input end is used for being electrically connected with a current signal end of an external device, and the current signal output end is electrically connected with a signal input end of the core amplifier unit; the core amplifier unit comprises N amplifying stages, a signal input end and a signal output end, wherein the input end of the 1 st amplifying stage is the signal input end, and the output end of the N amplifying stage is the signal output end; n is an odd number; the first end of the feedback unit is electrically connected with the signal input end, and the second end of the feedback unit is electrically connected with the signal output end. The invention can be used for isolating the large capacitance of the output end of the silicon photomultiplier and improving the bandwidth of the transimpedance amplifier.

Description

A high-bandwidth transimpedance amplifier based on current buffer

Technical field

The invention belongs to the technical field of integrated circuits, and specifically relates to a high-bandwidth transimpedance amplifier based on a current buffer.

Background technique

With the development of laser technology and integrated circuit technology, lidar is gradually used in fields such as autonomous driving and consumer electronics. Currently, the most widely used lidar is based on the direct time-of-flight method. Please refer to Figure 1. Figure 1 is a schematic framework diagram of a typical lidar system based on the direct time-of-flight method. The lidar system is usually emitted by a laser, It consists of three parts: front-end reception and back-end signal processing. The front-end reception part is usually the main factor limiting the performance of the lidar system.

Since linear mode avalanche photodiodes are usually manufactured using special processes, they are difficult to be integrated monolithically with the front-end receiving circuit. Analog silicon photomultiplier tubes have greater gain than linear mode avalanche photodiodes and can achieve integration with subsequent circuits. Fully integrated design, for longer distance detection, the analog silicon photomultiplier tube also has greater dynamic range and sensitivity. Therefore, analog silicon photomultiplier tubes are often used as photodetector devices and are cascaded with the subsequent transimpedance amplifier circuit by direct coupling. However, the large parasitic capacitance at the output end of the silicon photomultiplier tube reduces the bandwidth of the transimpedance amplifier, which makes the laser Radar systems are severely limited in their measurement speed and accuracy.

Contents of the invention

In order to solve the above problems existing in the related art, the present invention provides a high-bandwidth transimpedance amplifier based on a current buffer. The technical problems to be solved by the present invention are achieved through the following technical solutions:

The invention provides a high-bandwidth transimpedance amplifier based on a current buffer, including:

The current buffer unit adopts an adjustable cascode structure and includes a voltage signal input terminal, a current signal input terminal and a current signal output terminal, wherein the voltage signal input terminal is used to communicate with the power supply voltage signal terminal and reference of the power supply voltage. The reference voltage signal terminal of the voltage source is electrically connected, the current signal input terminal is used to be electrically connected to the current signal terminal of the external device, and the current signal output terminal is electrically connected to the signal input terminal of the core amplifier unit;

The core amplifier unit includes N amplification stages, signal input terminals and signal output terminals, wherein the input terminal of the first amplification stage is the signal input terminal, and the output terminal of the Nth amplification stage is the signal output terminal. end; N is an odd number;

A feedback unit includes a first end and a second end, wherein the first end is electrically connected to the signal input end, and the second end is electrically connected to the signal output end.

The present invention has the following beneficial technical effects:

The current buffer unit of the present invention adopts an adjustable cascode structure, which can isolate the large capacitance at the output end of the silicon photomultiplier tube, and can improve the output of the silicon photomultiplier tube across the large capacitance without affecting the dynamic range and linearity of the circuit. The influence of the bandwidth of the transimpedance amplifier is improved, thereby improving the bandwidth of the transimpedance amplifier; the feedback unit introduces a left half-plane zero point, which can improve the loop stability and realize the conversion and amplification function of input current to output voltage; the core amplifier unit includes an odd number of amplification stages , while increasing the gain of the core amplifier, it can also reduce the input resistance of the core amplifier and increase the bandwidth of the transimpedance amplifier. Therefore, the present invention can increase the bandwidth of the transimpedance amplifier and significantly improve the measurement distance and ranging accuracy of the lidar system.

The present invention will be further described in detail below with reference to the accompanying drawings and examples.

Description of the drawings

Figure 1 is a schematic framework diagram of a typical lidar system based on the direct time-of-flight method provided by an embodiment of the present invention;

Figure 2 is a schematic structural diagram of a high-bandwidth transimpedance amplifier based on a current buffer provided by an embodiment of the present invention;

Figure 3 is a schematic diagram of the circuit topology of an exemplary current buffer unit provided by an embodiment of the present invention;

Figure 4 is a schematic structural diagram of a feedback unit provided by an embodiment of the present invention;

FIG. 5 is a schematic diagram of the circuit topology of a high-bandwidth transimpedance amplifier based on a current buffer according to an embodiment of the present invention.

Detailed ways

The present invention will be described in further detail below with reference to specific examples, but the implementation of the present invention is not limited thereto.

In the description of the present invention, the terms "first" and "second" are used for descriptive purposes only and cannot be understood as indicating or implying relative importance or implicitly indicating the number of indicated technical features. Therefore, features defined as "first" and "second" may explicitly or implicitly include one or more of these features. In the description of the present invention, "plurality" means two or more than two, unless otherwise explicitly and specifically limited.

In the description of this specification, reference to the terms "one embodiment," "some embodiments," "an example," "specific examples," or "some examples" or the like means that specific features are described in connection with the embodiment or example. , structures, materials or features are included in at least one embodiment or example of the invention. In this specification, the schematic expressions of the above terms are not necessarily directed to the same embodiment or example. Furthermore, the specific features, structures, materials or characteristics described may be combined in any suitable manner in any one or more embodiments or examples. Furthermore, those skilled in the art may join and combine the different embodiments or examples described in this specification.

Although the present invention has been described herein in conjunction with various embodiments, those skilled in the art, in practicing the claimed invention, will understand and understand by reviewing the drawings, the disclosure, and the appended claims. Other variations of the disclosed embodiments are implemented. In the claims, the word "comprising" does not exclude other components or steps, and "a" or "an" does not exclude a plurality. A single processor or other unit may perform several of the functions recited in the claims. The mere fact that certain measures are recited in mutually different dependent claims does not mean that a combination of these measures cannot be combined to advantageous effects.

Figure 2 is a circuit structure diagram of a high-bandwidth transimpedance amplifier based on a current buffer provided by an embodiment of the present invention. As shown in Figure 2, the transimpedance amplifier includes: a current buffer unit 100, a feedback unit 200 and a core amplifier unit 300 . The current buffer unit 100 adopts a regulated cascode structure and includes a voltage signal input terminal, a current signal input terminal and a current signal output terminal. The voltage signal input terminal is used to communicate with the power supply voltage signal terminal and the reference voltage of the power supply voltage VDD. The reference voltage signal terminal of the source V1 is electrically connected, the current signal input terminal I _IN is used to be electrically connected to the current signal terminal of the external device, and the current signal output terminal is electrically connected to the signal input terminal of the core amplifier unit 300 . The core amplifier unit 300 includes N amplification stages, signal input terminals and signal output terminals V _OUT , where the input terminal of the first amplification stage is the signal input terminal, and the output terminal of the Nth amplification stage is the signal output terminal, N is an odd number. The feedback unit 200 includes a first end and a second end, wherein the first end is electrically connected to the signal input end, and the second end is electrically connected to the signal output end.

Specifically, the expression of the transfer function of the current buffer unit 100 is as follows: formulas (1-1), (1-2) and (1-3):

a＝{[1+(1+g _mB R _B )g _m2 r _o2 ]+r _o2 /r _o1 }(1-2);

b＝[r _o2 C _in +(r _o2 /r _o1 +1+g _m2 r _o2 )R _B C _B +(r _o2 /r _o1 +r _o2 /R _B +1+g _mB r _o2 )R _B C _Z ]

(1-3);

Among them, g _mB = g _m4 + g _m5 ; R _B = r _o4 //r _o5 //(1/g _m6 ); C _z =C _gs2 +C _gd4 +C _gd5 ; C _B =C _db4 +C _db5 + C _gs6 +C _db6 +C _gb6 ; C _in =C _PD +C _sb2 +C _gs4 +C _gs5 ; C _gs2 , C _gs4 , C _gs5 and C _gs6 are the gate-source parasitic capacitances of transistors M2, M4, M5 and M6 respectively. , C _gd4 and C _gd5 are the gate-drain parasitic capacitances of transistors M4 and M5 respectively, C _db4 , C _db5 and C _db6 are the drain-pad parasitic capacitances of transistors M4, M5 and M6 respectively, C _gb6 is the gate-pad parasitic capacitance of transistor M6 , C _sb2 is the source lining parasitic capacitance of transistor M2, r _o1 , r _o2 , r _o4 and r _o5 are the output resistances of transistors M1, M2, M4 and M5 respectively, g _m2 , g _m4 , g _m5 and g _m6 are respectively Transconductance of transistors M2, M4, M5 and M6, C _PD is the large capacitance at the output of the silicon photomultiplier tube, I' _IN is the input current of the current buffer unit, I' _OUT is the output current of the current buffer unit, s represents Laplace change, s=jw, w is the angular frequency, j is the imaginary unit, // represents parallel connection.

In some embodiments, the reference voltage signal terminal includes: a first reference voltage signal terminal VB1 and a second reference voltage signal terminal VB2. The voltage signal input terminal of the current buffer unit 100 includes: a first signal input terminal for electrical connection with the power supply voltage VDD, a second signal input terminal for electrical connection with the first reference voltage signal terminal VB1, and a second signal input terminal for electrical connection with the first reference voltage signal terminal VB1. The second reference voltage signal terminal VB2 is electrically connected to the third signal input terminal. The current buffer unit includes: transistor M1, transistor M2, transistor M3, transistor M4, transistor M5 and transistor M6. The second pole of the transistor M1, the transistor M4 and the transistor M6 are all electrically connected to the power supply voltage signal terminal; the third pole of the transistor M1 is electrically connected to the first pole of the transistor M4, and the first pole is electrically connected to the second reference voltage signal terminal VB2 ; The third pole of the transistor M4 is electrically connected to the first pole and the third pole of the transistor M6; the first pole of the transistor M5 is electrically connected to the first pole of the transistor M4, and the third pole is electrically connected to the third pole of the transistor M4, The second electrode is electrically connected to the ground terminal CND; the second electrode of the transistor M2 is short-circuited to the substrate and is electrically connected to the first electrode of the transistor M4. The first electrode is electrically connected to the third electrode of the transistor M4, and the third electrode is electrically connected to the transistor M4. The third pole of M3 is electrically connected; the second pole of transistor M3 is electrically connected to the ground terminal CND, and the first pole is electrically connected to the first reference voltage signal terminal VB1; wherein, the third pole of transistor M1 serves as the power signal input terminal, and the transistor M3 The third pole of M3 serves as the power signal output terminal I _OUT ; the second pole of the transistor M1, the second pole of the transistor M4 and the second pole of the transistor M6 serve as the above-mentioned first signal input terminal; the first pole of the transistor M3 serves as the above-mentioned third The second signal input terminal, the first pole of the transistor M1 serves as the above-mentioned third signal input terminal.

Specifically, the first pole is the gate, the second pole is the source, and the third pole is the drain; the transistor M1, the transistor M2, the transistor M4, and the transistor M6 are all PMOS transistors; the transistor M3 and the transistor M5 are NMOS transistors, for example , a schematic diagram of the circuit topology of the current buffer unit 100 is shown in Figure 3 . This structure is based on a common-gate amplifier, and introduces an active feedback common-source tube M4 at the source and gate of its input tube M2; this structure using gain bootstrapping improves the loop gain of the circuit, and is the circuit It provides stable self-bias. At the same time, the added active feedback path greatly reduces the equivalent input impedance of the circuit, thereby increasing the main pole frequency of the circuit and improving the bandwidth of the circuit. The following formula (1-4) is the equivalent input impedance expression, and formula (1-5) is the main pole expression of the circuit:

Since the output node voltage of the current buffer unit 100 is determined by the feedback of the next-stage core amplifier unit 300, the present invention uses the current source tube M3 to replace the resistor of the traditional regulating cascode structure at this position, and the drain of M3 The pole is connected to the output node to provide a larger dynamic range of the output voltage, and VB1 provides a bias for M3 to control the current of this branch. For the branch composed of M4, M5 and M6, the relationship between the current of M4 and M5 controlled by the source voltage of M2 and the current of M6 controlled by the gate voltage of M2 can be established. Since the current of the input tube M2 is determined , so the difference between the gate-source voltage of M2 is determined, so the unique static operating point of the circuit can be solved, and the voltage values of each node of the circuit are determined. The present invention uses the current source tube M5 to replace the resistor of the traditional regulating cascode structure at this position, and the gate of M5 is connected to the source of the input tube M2 to control the maximum current of the branch. Here, the input tube M2 adopts a source-lining short-circuit structure, which can reduce the threshold voltage of the input tube and increase the voltage margin of the circuit to ensure that all transistors operate in the saturation region. Compared with the traditional regulating cascode structure, the present invention connects a diode-connected PMOS tube M6 in parallel to the drain of the active feedback tube M4 to reduce the equivalent impedance of the drain node of M4, thereby increasing the The pole frequency at the node improves the stability of the circuit. For details, please refer to formulas (1-6), (1-7), (1-8) and (1-9), formulas (1-6), (1-7), (1-8) and (1-9 ) is the expression of the transfer function of the circuit feedback loop.

a＝C _B R _B r _o1 (C _in +C _Z )(r _o2 +r _o3 )(1-7);

b＝r _o1 (r _o2 +r _o3 )(C _in +C _Z )+(r _o1 +r _o2 +r _o3 )C _B R _B (1-8);

c＝r _o1 +r _o2 +r _o3 +g _m2 r _o2 r _o1 g _mB R _B (1-9);

Among them, r _o3 is the output resistance of M3.

In some embodiments, among the N amplification stages, the output terminal of the n-th amplification stage is electrically connected to the input terminal of the (n+1)-th amplification stage; n is any integer from 1 to N.

Specifically, the n+1th amplification stage includes: a first transistor, a second transistor and a third transistor; the first pole of the first transistor is electrically connected to the output terminal of the nth amplification stage, and the second pole is connected to the power supply voltage signal. terminals are electrically connected; the first pole of the second transistor is electrically connected to the first pole of the first transistor, the third pole is electrically connected to the third pole of the first transistor, and the second pole is electrically connected to the ground terminal GND; the third pole of the third transistor is electrically connected to the ground terminal GND. The first pole and the third pole are both electrically connected to the third pole of the second transistor and the input terminal of the (n+2)th amplifier stage respectively, and the second pole is electrically connected to the ground terminal GND. The first transistor is a PMOS transistor, and the second transistor and the third transistor are NMOS transistors.

In some embodiments, as shown in FIG. 4 , the feedback unit 200 includes a feedback resistor unit 220 and a feedback capacitor unit 210 , and the feedback resistor unit 220 and the feedback capacitor unit 210 are connected in parallel.

For example, when the core amplifier unit includes three amplification stages, the circuit topology of the high-bandwidth transimpedance amplifier is shown in Figure 5, in which the transistors M1 to M6 constitute the current buffer unit 100, and the transistors M7 to M9 constitute the core amplifier. The first amplification stage in the unit 300, the transistors M10~M12 constitute the second amplification stage in the core amplifier unit 300, the transistors M13~M15 constitute the third amplification stage in the core amplifier unit 300, and the capacitors _CF and _RF constitute the feedback unit 200, and the capacitor C _F is the feedback capacitor unit, and the resistor R _F is the feedback resistor unit.

The parallel connection of the feedback capacitor and the feedback resistor introduces the left half-plane zero point, which improves the loop stability. For details, see formula (2-1). The formula (2-1) is the expression of the left half-plane zero point introduced by the parallel connection of the feedback capacitor and the feedback resistor. :

The core amplifier unit in Figure 5 adopts a classic three-stage push-pull amplifier structure, which can increase the gain of the amplifier while realizing the function of the push-pull output stage, thereby enabling the transimpedance amplifier to drive silicon photovoltaics at low static power consumption. The maximum output current of the multiplier tube. At the same time, since the load of each stage of the circuit uses diode-connected NMOS tubes, namely M9, M12, and M15, the corresponding output nodes of each stage are low-impedance nodes (equivalent impedance is about 1/gm). That is, the pole frequency at the output node of each stage is increased. For the main pole of the circuit at the input end, the overall bandwidth of the circuit is effectively increased and the stability of the circuit is ensured.

This embodiment provides a high-bandwidth transimpedance amplifier based on a circuit buffer, which uses a current buffer unit to isolate the large capacitor at the output end of the silicon photomultiplier tube, improves the bandwidth of the transimpedance amplifier, and uses a feedback capacitor and a The feedback unit of the feedback resistor, the feedback capacitor and the feedback resistor are connected in parallel to introduce the left half-plane zero point, which improves the loop stability. At the same time, the feedback resistor is used to realize the conversion and amplification function of the input current to the output voltage. A core amplifier unit is used, which The structure of the odd-numbered multi-stage amplifier not only increases the gain of the core amplifier, but also reduces the input resistance of the core amplifier and increases the circuit bandwidth.

The above content is a further detailed description of the present invention in combination with specific preferred embodiments, and it cannot be concluded that the specific implementation of the present invention is limited to these descriptions. For those of ordinary skill in the technical field to which the present invention belongs, several simple deductions or substitutions can be made without departing from the concept of the present invention, and all of them should be regarded as belonging to the protection scope of the present invention.

Claims (8)

1. A high bandwidth transimpedance amplifier based on a current buffer, comprising:

the current buffer unit adopts an adjustable type cascode structure and comprises a voltage signal input end, a current signal input end and a current signal output end, wherein the voltage signal input end is used for being electrically connected with a power supply voltage signal end of a power supply voltage and a reference voltage signal end of a reference voltage source, the current signal input end is used for being electrically connected with a current signal end of an external device, and the current signal output end is electrically connected with a signal input end of the core amplifier unit;

the core amplifier unit comprises N amplifying stages, a signal input end and a signal output end, wherein the input end of the 1 st amplifying stage is the signal input end, and the output end of the N th amplifying stage is the signal output end; n is an odd number;

the feedback unit comprises a first end and a second end, wherein the first end is electrically connected with the signal input end, and the second end is electrically connected with the signal output end.

2. The current buffer-based high bandwidth transimpedance amplifier according to claim 1, wherein the reference voltage signal terminal comprises: a first reference voltage signal terminal and a second reference voltage signal terminal; the current buffer unit includes: transistor M1, transistor M2, transistor M3, transistor M4, transistor M5, and transistor M6;

the second pole of the transistor M1, the second pole of the transistor M4 and the second pole of the transistor M6 are electrically connected with the power supply voltage signal terminal; a third electrode of the transistor M1 is electrically connected to a first electrode of the transistor M4, and the first electrode is electrically connected to the second reference voltage signal terminal; the third electrode of the transistor M4 is electrically connected with the first electrode and the third electrode of the transistor M6; a first pole of the transistor M5 is electrically connected to the first pole of the transistor M4, a third pole is electrically connected to a third pole of the transistor M4, and a second pole is electrically connected to the ground terminal CND; the second pole of the transistor M2 is electrically connected with the first pole of the transistor M4 after being in short circuit with the substrate, the first pole is electrically connected with the third pole of the transistor M4, and the third pole is electrically connected with the third pole of the transistor M3; a second pole of the transistor M3 is electrically connected to the ground terminal CND, and a first pole is electrically connected to the first reference voltage signal terminal;

the third electrode of the transistor M1 is used as the power signal input end, and the third electrode of the transistor M3 is used as the power signal output end.

3. The high bandwidth transimpedance amplifier according to claim 2, wherein the first electrode is a gate electrode, the second electrode is a source electrode, and the third electrode is a drain electrode; the transistor M1, the transistor M2, the transistor M4 and the transistor M6 are PMOS transistors; the transistor M3 and the transistor M5 are NMOS transistors.

4. The high bandwidth transimpedance amplifier based on a current buffer according to claim 1, wherein the output of the nth amplification stage is electrically connected to the input of the n+1th amplification stage; n is any integer from 1 to N.

5. The current buffer-based high bandwidth transimpedance amplifier according to claim 4, wherein the n+1th amplification stage comprises: a first transistor, a second transistor, and a third transistor; a first pole of the first transistor is electrically connected with the output end of the nth amplifying stage, and a second pole of the first transistor is electrically connected with the power supply voltage signal end; a first electrode of the second transistor is electrically connected with a first electrode of the first transistor, a third electrode of the second transistor is electrically connected with a third electrode of the first transistor, and a second electrode of the second transistor is electrically connected with a ground end GND; the first pole and the third pole of the third transistor are respectively and electrically connected with the third pole of the second transistor and the input end of the n+2th amplifying stage, and the second pole is electrically connected with the grounding end GND.

6. The high bandwidth transimpedance amplifier based on a current buffer according to claim 5, wherein the first transistor is a PMOS transistor, and the second and third transistors are NMOS transistors.

7. The high bandwidth transimpedance amplifier based on a current buffer according to claim 1, wherein the feedback unit comprises: a capacitor and a resistor connected in parallel; one end of the resistor and one end of the capacitor are electrically connected with the signal input end, and the other end of the resistor and the other end of the capacitor are electrically connected with the signal output end.

8. The high bandwidth transimpedance amplifier based on a current buffer according to claim 2, wherein the transfer function of the current buffer unit has the expression:

a＝{[1+(1+g _mB R _B )g _m2 r _o2 ]+r _o2 /r _o1 }；

b＝[r _o2 C _in +(r _o2 /r _o1 +1+g _m2 r _o2 )R _B C _B +(r _o2 /r _o1 +r _o2 /R _B +1+g _mB r _o2 )R _B C _Z ]；

g _mB ＝g _m4 +g _m5 ；

R _B ＝r _o4 //r _o5 //(1/g _m6 )；

C _z ＝C _gs2 +C _gd4 +C _gd5 ；

C _B ＝C _db4 +C _db5 +C _gs6 +C _db6 +C _gb6 ；

C _in ＝C _PD +C _sb2 +C _gs4 +C _gs5 ；

wherein C is _gs2 、C _gs4 、C _gs5 And C _gs6 Parasitic capacitances of gate sources of transistors M2, M4, M5 and M6, C _gd4 And C _gd5 Parasitic capacitance of gate and drain of transistors M4 and M5, respectively, C _db4 、C _db5 And C _db6 Drain-to-liner parasitic capacitances, C, of transistors M4, M5 and M6, respectively _gb6 Parasitic capacitance of gate line of transistor M6, C _sb2 Parasitic capacitance r is the source line of transistor M2 _o1 、r _o2 、r _o4 And r _o5 Output resistors g of transistors M1, M2, M4 and M5, respectively _m2 、g _m4 、g _m5 And g _m6 Transconductance, C, of transistors M2, M4, M5 and M6, respectively _PD Is the large capacitance of the output end of the silicon photomultiplier, I' _IN For the input current of the current buffer unit, I' _OUT For the output current of the current buffer unit, s represents the laplace variation, s=jw, w is the angular frequency, j is the imaginary unit, and// represents the parallel connection.