CN117272889B

CN117272889B - Circuit delay estimation method and device, electronic equipment and storage medium

Info

Publication number: CN117272889B
Application number: CN202311097251.1A
Authority: CN
Inventors: 尹说; 南海卿
Original assignee: Haiguang Yunxin Integrated Circuit Design Shanghai Co ltd
Current assignee: Haiguang Yunxin Integrated Circuit Design Shanghai Co ltd
Priority date: 2023-08-28
Filing date: 2023-08-28
Publication date: 2024-04-30
Anticipated expiration: 2043-08-28
Also published as: CN117272889A

Abstract

The embodiment of the invention discloses a method and a device for estimating circuit delay, electronic equipment and a storage medium, relates to the technical field of integrated circuits, and can rapidly and accurately estimate the circuit delay under the condition of IR drop. The method comprises the following steps: determining a circuit element needing delay adjustment in a target path to be subjected to delay estimation to obtain a target element; according to attribute parameters of each target element in each target path, respectively searching delay adjustment reference proportion corresponding to each target element in a pre-established lookup table, wherein the lookup table is established based on a first proportion, and the first proportion is the ratio of voltage drop of a first driving voltage corresponding to any circuit element in the lookup table to the first driving voltage; respectively determining delay adjustment proportions corresponding to all target elements in a target path according to the first proportion and the delay adjustment reference proportion; and determining the delay of the target path according to the delay adjustment proportion corresponding to each target element in the target path.

Description

Circuit delay estimation method and device, electronic equipment and storage medium

Technical Field

The present invention relates to the field of integrated circuits, and in particular, to a method and apparatus for estimating circuit delay, an electronic device, and a storage medium.

Background

The static time sequence analysis (STATIC TIMING ANALYSIS, STA), or static time sequence verification, is a work flow for calculating and predicting the time sequence of a digital circuit in chip design, and the flow does not need to simulate in an input excitation mode, but uses a simplified model and takes logic interaction between signals into limited consideration, so that the time sequence estimation task can be completed more quickly, and the work flow plays an important role in quick and accurate measurement of the time sequence of the circuit.

IR drop refers to a phenomenon of voltage drop or rise (collectively referred to as voltage drop) across power and/or ground networks in integrated circuits, and includes mainly static IR drop and dynamic IR drop. The main reason for static IR drop is the voltage division of the metal wiring of the power supply network. The main reason for dynamic IR drop is the voltage drop caused by current fluctuations when the circuit switch is switched, typically occurring at the triggering edge of the clock. IR drop may cause a decrease in chip speed, performance degradation. To maintain performance, the effect of IR drop can typically be offset by moderately increasing the voltage, but this tends to introduce new power consumption.

In the related art, the timing analysis and the IR drop signature are independent of each other, but in practice, the IR drop and the delay of the critical path affect each other. On one hand, the voltage drop of the standard unit in each critical path can cause the delay of the standard unit to be increased so as to influence the time sequence, and on the other hand, the frequency of the turnover can also be changed due to the delay of the standard unit to be increased so as to influence the dynamic current in the power supply and the ground and the corresponding IR drop. Independent analysis of both may result in inaccurate delay estimates for the circuit, which may lead to over-or under-optimization of the circuit. If the whole standard cell timing sequence library is scaled for the purpose of IR drop analysis or a standard cell timing sequence library with lower voltage is adopted, not only a great amount of calculation and running time are needed, the research and development efficiency is greatly affected, but also the delay analysis of the whole design is possibly too pessimistic, so that when the actual working voltage of the chip is higher than the analysis value, new violations are caused instead.

How to quickly and accurately evaluate circuit delay in the presence of IR drop is a problem in the art.

Disclosure of Invention

In view of the above, the embodiments of the present invention provide a method and apparatus for estimating circuit delay, an electronic device, and a storage medium, which can quickly and accurately estimate circuit delay in the presence of IR drop.

In a first aspect, an embodiment of the present invention provides a method for estimating a circuit delay, including: determining a circuit element needing delay adjustment in a target path to be subjected to delay estimation to obtain a target element; according to attribute parameters of each target element in each target path, respectively searching delay adjustment reference proportion corresponding to each target element in a pre-established lookup table, wherein the lookup table is established based on a first proportion, the first proportion is the ratio of voltage drop of a first driving voltage corresponding to any circuit element in the lookup table to the first driving voltage, and the first driving voltage comprises a power supply voltage and/or a ground voltage; respectively determining delay adjustment proportions corresponding to all target elements in the target path according to the first proportion and the delay adjustment reference proportion; and determining the delay of the target path according to the delay adjustment proportion corresponding to each target element in the target path.

In one embodiment, the determining the delay adjustment ratio corresponding to each target element in the target path according to the first ratio and the delay adjustment reference ratio includes: respectively obtaining voltage drops of second driving voltages corresponding to all target elements in the target path to obtain target voltage drops, wherein the second driving voltages comprise power supply voltages and/or ground voltages; and respectively determining delay adjustment proportions corresponding to all target elements in the target path according to the second driving voltage, the target voltage drop, the first proportion and the delay adjustment reference proportion.

In one embodiment, in the target path to be delay estimated, determining a circuit element needing delay adjustment, and before obtaining the target element, the method further includes: and acquiring a signal transmission path of which the delay relaxation amount meets a preset condition in the circuit according to a static time sequence analysis result of the circuit, and obtaining the target path.

In one embodiment, the signal transmission path in which the delay relaxation amount meets a preset condition includes at least one of the following: a signal transmission path having a delay slack less than a preset threshold, wherein the preset threshold is greater than 0; and when the delay relaxation quantity is ordered from small to large, the delay relaxation quantity is positioned in a signal transmission path of N bits before ordering, wherein N is a positive integer.

In one embodiment, determining the circuit element that needs to be subjected to delay adjustment in the target path to be subjected to delay estimation, and obtaining the target element includes: determining the duty ratio of the delay caused by the metal interconnection line in the target path in the total delay of the target path according to the static time sequence analysis result; and determining a circuit element needing delay adjustment in the target path according to the duty ratio to obtain a target element.

In one embodiment, the determining, according to the duty ratio, a circuit element that needs to be delay-adjusted in the target path, to obtain a target element includes: determining a standard unit in the target path as the target element under the condition that the duty ratio is smaller than or equal to a preset duty ratio threshold value; and determining a standard cell and a metal interconnection line connecting different standard cells in the target path as the target element under the condition that the duty ratio is larger than the duty ratio threshold value.

In one embodiment, the target element comprises a standard cell, the attribute parameter comprises a first attribute parameter comprising a threshold voltage and a shortest channel length of a transistor comprising the standard cell, an input transfer time of the standard cell, and an output load capacitance of the standard cell.

In one embodiment, the target element includes metal interconnect lines for connecting different standard cells; the attribute parameters include second attribute parameters including: the shape of the metal interconnection line, the distance between the metal interconnection line and the peripheral metal interconnection line, the number of layers of the metal interconnection line included in the circuit and the distribution of capacitance and inductance in the circuit.

In one embodiment, the determining the delay of the target path according to the delay adjustment ratio corresponding to each target element in the target path includes: according to the delay adjustment proportion corresponding to each target element in the target path, element delay of each target element is respectively determined; and determining the delay of the target path according to the element delay of each target element.

In one embodiment, the determining the element delay of each target element according to the delay adjustment proportion corresponding to each target element in the target path includes: according to the delay adjustment proportion corresponding to each target element in the target path, respectively determining the delay adjustment factor of each target element; and respectively determining the element delay of each target element according to the delay of each target element in static time sequence analysis and the delay adjustment factor of the target element.

In one embodiment, the determining the delay of the target path according to the element delay of each target element includes: determining a circuit element which does not need delay adjustment in the target path to obtain a holding element; and accumulating element delays of all target elements in the target path and element delays of all holding elements in the target path, which are obtained based on static time sequence analysis, to obtain the delay of the target path.

In one embodiment, before searching the delay adjustment reference proportion corresponding to each target element in the pre-established lookup table according to the attribute parameters of each target element in each target path, the method further includes: acquiring attribute parameters of preset circuit elements; and establishing the lookup table according to the attribute parameters of the preset circuit elements.

In one embodiment, the preset circuit elements are divided into a plurality of element types, attribute parameters corresponding to the preset circuit elements of the same element type are the same, and the establishing the lookup table according to the attribute parameters of the preset circuit elements includes: performing time sequence simulation on the preset circuit element under the condition that the first driving voltage corresponding to the preset circuit element generates the voltage drop of the first proportion to obtain a first time delay of the preset circuit element, and performing time sequence simulation on the preset circuit element under the condition that the first driving voltage corresponding to the preset circuit element does not generate the voltage drop to obtain a second time delay of the preset circuit element; determining an element reference delay proportion corresponding to the preset circuit element when the first driving voltage corresponding to the preset circuit element generates the voltage drop of the first proportion according to the first delay and the second delay; determining a delay adjustment reference proportion of an element type to which the preset circuit element belongs according to the element reference delay proportion; and establishing the lookup table according to the attribute parameters of the preset circuit elements and the delay adjustment reference proportion.

In one embodiment, the preset circuit elements include preset standard units, and each element type includes the same preset standard unit with the same attribute parameter and the same logic function, or includes at least two different preset standard units with the same attribute parameter and different logic functions; wherein, the attribute parameters of each preset standard unit comprise: the threshold voltage and the shortest channel length of the transistor forming the preset standard cell, the input transfer time of the preset standard cell and the output load capacitance of the preset standard cell.

In one embodiment, the element types to which the preset standard units belong include at least two preset standard units with the same attribute parameters but different logic functions; the determining the delay adjustment reference proportion of the element type to which the preset circuit element belongs according to the element reference delay proportion comprises: and determining that the delay adjustment reference proportion is equal to an average value of the element reference delay proportions corresponding to various preset standard units under the element type.

In a second aspect, an embodiment of the present invention further provides a circuit delay estimation apparatus, including: the first determining unit is used for determining a circuit element needing delay adjustment in a target path to be subjected to delay estimation to obtain a target element; the searching unit is used for searching delay adjustment reference proportions corresponding to all target elements in a pre-established searching table according to attribute parameters of all the target elements in each target path, wherein the searching table is established based on a first proportion, the first proportion is the ratio of voltage drop of a first driving voltage corresponding to any circuit element in the searching table to the first driving voltage, and the first driving voltage comprises a power supply voltage and/or a ground voltage; the second determining unit is used for determining delay adjustment proportions corresponding to all target elements in the target path according to the first proportion and the delay adjustment reference proportion; and the third determining unit is used for determining the delay of the target path according to the delay adjustment proportion corresponding to each target element in the target path.

In one embodiment, the second determining unit includes: the acquisition module is used for respectively acquiring voltage drops of second driving voltages corresponding to all target elements in the target path to obtain target voltage drops, wherein the second driving voltages comprise power supply voltages and/or ground voltages; and the first determining module is used for respectively determining delay adjustment proportions corresponding to all target elements in the target path according to the second driving voltage, the target voltage drop, the first proportion and the delay adjustment reference proportion.

In one embodiment, the apparatus further comprises: the first acquisition unit is used for determining a circuit element needing delay adjustment in the target path to be subjected to delay estimation, and acquiring a signal transmission path of which the delay relaxation amount in the circuit meets a preset condition according to a static time sequence analysis result of the circuit before the target element is obtained, so as to obtain the target path.

In one embodiment, the first determining unit includes: the second determining module is used for determining the duty ratio of the delay caused by the metal interconnection line in the target path in the total delay of the target path according to the static time sequence analysis result; and the third determining module is used for determining a circuit element needing delay adjustment in the target path according to the duty ratio to obtain a target element.

In one embodiment, the third determining module is specifically configured to: determining a standard unit in the target path as the target element under the condition that the duty ratio is smaller than or equal to a preset duty ratio threshold value; and determining a standard cell and a metal interconnection line connecting different standard cells in the target path as the target element under the condition that the duty ratio is larger than the duty ratio threshold value.

In one embodiment, the third determining unit includes: a fourth determining module, configured to determine element delays of the target elements according to the delay adjustment ratios corresponding to the target elements in the target path; and a fifth determining module, configured to determine a delay of the target path according to an element delay of each target element.

In one embodiment, the fourth determining module is specifically configured to: according to the delay adjustment proportion corresponding to each target element in the target path, respectively determining the delay adjustment factor of each target element; and respectively determining the element delay of each target element according to the delay of each target element in static time sequence analysis and the delay adjustment factor of the target element.

In one embodiment, the fifth determining module is specifically configured to: determining a circuit element which does not need delay adjustment in the target path to obtain a holding element; and accumulating element delays of all target elements in the target path and element delays of all holding elements in the target path, which are obtained based on static time sequence analysis, to obtain the delay of the target path.

In one embodiment, the apparatus further comprises: the second obtaining unit is used for obtaining attribute parameters of preset circuit elements before respectively searching delay adjustment reference proportions corresponding to the target elements in a pre-established lookup table according to the attribute parameters of the target elements in each target path; and the establishing unit is used for establishing the lookup table according to the attribute parameters of the preset circuit elements.

In one embodiment, the preset circuit elements are divided into a plurality of element types, and attribute parameters corresponding to the preset circuit elements with the same element type are the same; the establishing unit includes: the simulation module is used for carrying out time sequence simulation on the preset circuit element under the condition that the first driving voltage corresponding to the preset circuit element generates the voltage drop of the first proportion to obtain a first delay of the preset circuit element, and carrying out time sequence simulation on the preset circuit element under the condition that the first driving voltage corresponding to the preset circuit element does not generate the voltage drop to obtain a second delay of the preset circuit element; a sixth determining module, configured to determine, according to the first delay and the second delay, an element reference delay proportion corresponding to the preset circuit element when the first driving voltage corresponding to the preset circuit element has the voltage drop of the first proportion; a seventh determining module, configured to determine a delay adjustment reference proportion of an element type to which the preset circuit element belongs according to the element reference delay proportion; the establishing module is used for establishing the lookup table according to the attribute parameters of the preset circuit elements and the delay adjustment reference proportion.

In one embodiment, the element types to which the preset standard units belong include at least two preset standard units with the same attribute parameters but different logic functions; the seventh determining module is specifically configured to determine that the delay adjustment reference proportion is equal to an average value of the element reference delay proportions corresponding to various preset standard units under the element type.

In a third aspect, embodiments of the present invention further provide an electronic device, including: the device comprises a shell, a processor, a memory, a circuit board and a power circuit, wherein the circuit board is arranged in a space surrounded by the shell, and the processor and the memory are arranged on the circuit board; a power supply circuit for supplying power to each circuit or device of the electronic apparatus; the memory is used for storing executable program codes; the processor executes a program corresponding to the executable program code by reading the executable program code stored in the memory, for performing the method for estimating the circuit delay provided by any of the embodiments of the present invention.

In a fourth aspect, embodiments of the present invention also provide a computer-readable storage medium storing one or more programs executable by one or more processors to implement the method of estimating circuit delay provided by any of the embodiments of the present invention.

According to the circuit delay estimation method, the circuit delay estimation device, the electronic equipment and the storage medium, the first proportion is the ratio of the voltage drop of the first driving voltage corresponding to any circuit element in the lookup table to the first driving voltage, and the first driving voltage comprises the power supply voltage and/or the ground voltage, so that the lookup table established according to the first proportion can reflect the delay change of each circuit element under the condition that the voltage drop of the first proportion occurs to the power supply voltage and/or the ground voltage, and further, the reference proportion is adjusted according to the delay obtained by the first lookup table, the influence of the voltage drop of the power supply voltage and/or the ground voltage on the delay of the target path can be reflected, and the delay of the target path can be rapidly and accurately estimated under the condition that the voltage drop exists to the power supply network and/or the ground network.

Drawings

In order to more clearly illustrate the embodiments of the invention or the technical solutions in the prior art, the drawings that are required in the embodiments or the description of the prior art will be briefly described, it being obvious that the drawings in the following description are only some embodiments of the invention, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.

FIG. 1 is a flow chart of a method for estimating circuit delay according to an embodiment of the present invention;

FIG. 2 is a detailed flowchart of a circuit delay estimation method according to an embodiment of the present invention;

fig. 3 is a schematic structural diagram of a circuit delay estimation device according to an embodiment of the present invention;

fig. 4 is a schematic structural diagram of an electronic device according to an embodiment of the present invention.

Detailed Description

Embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

It should be understood that the described embodiments are merely some, but not all, embodiments of the invention. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.

The power in the chip is typically delivered to the standard cells via a power delivery network (PDN, power Delivery Network, hereinafter referred to as a power network or supply network). Each metal layer used in the power network has a certain resistivity. When current flows through the supply network, a portion of the applied voltage will drop in the PDN according to ohm's law. The amount of voltage drop will be v=i×r, referred to as IR drop. The voltage drop in the current delivery network before reaching the standard cell is called IR drop. Similarly, similar IR drop exists in the ground network in the chip.

As described in the background art, IR drop signature and static timing analysis are performed independently.

For static timing analysis, all timing constraints (including, but not limited to, clock information, signal transfer time, load, timing information of standard cells, physical parasitic parameter information, etc.) are typically read in a timing analysis tool (e.g., primeTime, etc.), then timing calculations are performed, primarily by reasonably calculating the total delay of each path, and then reporting the critical paths for which there is a timing violation, as well as the corresponding arrival time, demand time, etc. In this process, the chip engineer will locate the problematic locations and repair them so that the design meets the timing requirements. For IR drop signing, an IR drop analysis tool (such as Redhawk) is generally adopted to analyze static IR drop and dynamic IR drop respectively, a certain proportion threshold (such as 10%) is set, and whether the standard unit needs to repair the IR drop problem is judged according to the IR drop value of each standard unit given in the analysis result.

However, the IR drop and critical path delays are mutually influential: on the one hand, the voltage drop of the standard cell in each critical path can lead to the increase of the delay of the standard cell, thereby affecting the time sequence; on the other hand, as the delay of the standard cell increases, the frequency of the flip will also change, which in turn will affect the dynamic current in the power and ground and the corresponding IR drop. In addition, the critical paths where standard cells with IR drop ratios higher than a set threshold (e.g., IR drop of a certain standard cell reaches 15%, exceeds 10% of the set) may have a large amount of timing slack (e.g., more than 200 ps), and even if the IR drop delay is large enough, no risk of a violation occurs; however, some critical paths may be very sensitive to IR drop due to physical layout and other factors, and even if the amount of slack in the static timing analysis is very safe, there is a risk of timing violations due to the presence of IR drop. Thus, both independent analyses may suffer from over-or under-optimization.

If the whole standard cell timing sequence library is scaled for the purpose of IR drop analysis or a standard cell timing sequence library with lower voltage is adopted, not only a great amount of calculation and running time are needed, the research and development efficiency is greatly affected, but also the delay analysis of the whole design is possibly too pessimistic, so that when the actual working voltage of the chip is higher than the analysis value, new violations are caused instead.

In order to solve the above problems, the inventors found in further research and practice that IR drop analysis and static timing analysis can be combined, and the delay of a critical path under the influence of IR drop can be efficiently and simply calculated by a low-order mathematical model before chip streaming.

In order that those skilled in the art will better understand the technical concepts, embodiments and advantageous technical effects of the examples of the present invention, a detailed description will be given below by way of specific examples.

In a first aspect, an embodiment of the present invention provides a method for estimating a circuit delay, which can quickly and accurately estimate a delay of a target path in a case where a voltage drop exists in a power supply network and/or a ground network.

As shown in fig. 1, an embodiment of the present invention provides a method for estimating a circuit delay, including:

S11, determining a circuit element needing delay adjustment in a target path to be subjected to delay estimation to obtain a target element;

The target path may be a path or paths in the circuit that require delay estimation. The target path may include a path that a signal passes from an output of one register to an input of a next register, on which various combinational logic circuits and/or metal interconnect lines may exist. The target path may include either a critical path (CRITICAL PATH) in the circuit or a non-critical path in the circuit, which is not limited by embodiments of the present invention. Where a critical path may refer to the maximum delay path from the output of one register to the data input of the next register (or other sequential logic).

The physical media taken by the signal when transmitted in the target path are circuit elements, and if the physical media are different, the circuit elements are different. In the embodiment of the invention, the delay degree of different circuit elements on signals can be different, and the delay change generated by the influence of the voltage drop (i.e. IR drop) of the power supply network and/or the ground network of different circuit elements can also be different. For example, in one embodiment of the present invention, some circuit elements are insensitive to voltage drops of the power network and/or the ground network, signal transmission delays do not vary greatly due to the voltage drops, while other circuit elements may be more sensitive to voltage drops of the power network and/or the ground network, and signal transmission delays may vary greatly due to the voltage drops. Here, the voltage drop of the power network and/or the ground network voltage drop may be either a static IR drop or a dynamic IR drop, and the embodiment of the present invention only limits the result of generating IR drop, but the generation reason is not limited.

In order to perform more accurate and efficient estimation on the delay of the target path, in one embodiment of the invention, a circuit element needing delay adjustment can be found from various circuit elements of the target path according to whether the delay of the circuit element is sensitive to voltage drop, so as to obtain the target element. For example, a circuit element that is more sensitive to voltage drop may be found from among various circuit elements of the target path as a target element, while other circuit elements that are less sensitive to voltage drop are not. Because only the target element is subjected to delay adjustment, the accurate delay adjustment result can be obtained, and meanwhile, the calculation amount of delay adjustment is greatly reduced.

S12, respectively searching delay adjustment reference proportions corresponding to all target elements in a pre-established lookup table according to attribute parameters of all target elements in each target path, wherein the lookup table is established based on a first proportion, and the first proportion is the ratio of voltage drop of a first driving voltage corresponding to any circuit element in the lookup table to the first driving voltage, and the first driving voltage comprises a power supply voltage and/or a ground voltage;

Each target element in the target path can have its own attribute parameter, and the pre-established lookup table also contains a series of circuit elements determined by different attribute parameters, and the delay adjustment reference proportion corresponding to the circuit elements, and the attribute parameters of the target elements can be used as indexes, so that the corresponding delay adjustment reference proportion can be uniquely determined in the lookup table.

In the embodiment of the invention, the lookup table is established based on the first proportion, that is, the delay adjustment reference proportion corresponding to each circuit element in the lookup table is obtained based on delay change caused by voltage drop of the first proportion of the first driving voltage corresponding to the circuit element. The first ratio may be any ratio, for example, 5%,10%,15%, etc. Illustratively, in one embodiment of the present invention, the first driving voltage is 1.5V, the first ratio is 10%, and the voltage drop of the first ratio is 1.5v×10% =0.15V. Here, the first driving voltage corresponding to the circuit element may refer to a power supply voltage and/or a ground voltage to which the circuit element is connected. The voltage drop, i.e., IP drop, may refer to a voltage change on the power network and/or ground network caused by ohm's law of current-resistance products. For convenience of explanation, the case where the power supply voltage is a positive voltage and the voltage is changed to a voltage decrease will be explained below as an example.

It should be noted that, in the embodiment of the present invention, the voltage drop may be an average voltage drop over a period of time (for example, 10 clock cycles, 100 clock cycles, etc.), or may be an instantaneous voltage drop at a certain moment. The instantaneous voltage drop can be obtained by shortening the statistical time corresponding to the average voltage drop.

S13, respectively determining delay adjustment proportions corresponding to all target elements in the target path according to the first proportion and the delay adjustment reference proportion;

Specifically, in step S12, the delay adjustment reference ratio found in the lookup table is a reference value of the delay ratio of the target element, and the actual delay adjustment ratio of each target element in the target path is further determined according to the first ratio and the delay adjustment reference ratio in this step.

S14, determining the delay of the target path according to the delay adjustment proportion corresponding to each target element in the target path.

In step S13, the delay adjustment ratio corresponding to each target element is determined, that is, the influence of the voltage drop of the power supply voltage and/or the ground voltage on the delay of the target element is obtained, so that the delay change condition of the target path can be determined under the condition that the voltage drop exists in the power supply network and/or the ground network according to the delay adjustment ratio, and the delay of the target path can be further determined.

According to the circuit delay estimation method provided by the embodiment of the invention, circuit elements needing delay adjustment can be determined in the target paths to be subjected to delay estimation, target elements are obtained, delay adjustment reference proportions corresponding to the target elements are respectively searched in a pre-established lookup table according to attribute parameters of the target elements in each target path, the lookup table is established based on a first proportion, delay adjustment proportions corresponding to the target elements in the target paths are respectively determined according to the first proportion and the delay adjustment reference proportions, and delay of the target paths is determined according to the delay adjustment proportions corresponding to the target elements in the target paths. In this way, the first proportion is the ratio of the voltage drop of the first driving voltage corresponding to any circuit element in the lookup table to the first driving voltage, and the first driving voltage comprises the power supply voltage and/or the ground voltage, so that the lookup table established according to the first proportion can reflect the time delay change of each circuit element under the condition that the power supply voltage and/or the ground voltage have the voltage drop of the first proportion, and further, the reference proportion is adjusted according to the time delay obtained by the first lookup table, the influence of the voltage drop of the power supply voltage and/or the ground voltage on the time delay of the target path can be reflected, so that the time delay of the target path can be rapidly and accurately estimated under the condition that the power supply network and/or the ground network has the voltage drop.

Further, the method for estimating the circuit delay provided by the embodiment of the invention is also beneficial to locating at least one part of potential time sequence risks existing due to the IR drop or the critical paths sensitive to the IR drop and repairing the critical paths in a targeted manner, so that the sensitivity of a chip to the IR drop is reduced, the post-silicon test boosting amplitude is reduced, and the power consumption of an additional chip is also reduced.

In particular, in a circuit design having a relatively independent function, there may be a plurality of signal transmission paths, and in one embodiment of the present invention, a path in which a timing violation easily occurs, particularly, a path in which a timing violation easily occurs in the presence of a voltage drop in a power supply network and/or a ground network, may be taken as a target path. For example, in one example, step S11 determines, in a target path to be delay estimated, a circuit element that needs to be delay-adjusted, and before obtaining the target element, the method for estimating the circuit delay according to the embodiment of the present invention may further include: and acquiring a signal transmission path of which the delay relaxation amount meets a preset condition in the circuit according to a static time sequence analysis result of the circuit, and obtaining the target path. That is, in this embodiment, static timing analysis may be performed on the circuit in advance to obtain the delay relaxation amounts of the respective signal transmission paths.

Where the slack (or margin) may refer to the difference between the demand time and the arrival time. At the circuit node, a positive slack represents a time at which the arrival time can be increased by the slack, yet without affecting the overall delay profile of the circuit. Conversely, a negative slack indicates that the transmission on the path is too slow, and the transmission rate of this path must be increased, otherwise the overall circuit consisting of it cannot operate at the desired rate. Arrival time (ARRIVAL TIME) may refer to the time that a signal takes to pass from a specified location of a circuit to another specified location. The arrival time of the clock signal may generally be taken as a reference time, or zero time. The required time (required time) may refer to the limit delay requirement that the signal be able to reach without violating the design requirements of the overall circuit for timing.

Alternatively, in one embodiment of the present invention, the signal transmission path in which the delay relaxation amount meets the preset condition may include one or more of the following: a signal transmission path having a delay slack less than a preset threshold, wherein the preset threshold is greater than 0; and when the delay relaxation quantity is ordered from small to large, the delay relaxation quantity is positioned in a signal transmission path of N bits before ordering, wherein N is a positive integer.

And the signal transmission path with the delay relaxation amount smaller than the preset threshold value is the corresponding signal transmission path as long as the delay relaxation amount is smaller than the preset threshold value. Since the preset threshold is greater than 0, the corresponding target path may include a signal transmission path with a negative delay slack or a signal transmission path with a positive delay slack. Since the amount of delay relaxation is negative, meaning that a timing violation must occur in the signal transmission path in static timing analysis, determining such a signal transmission path as a target path helps to understand the degree of timing degradation in the presence of a voltage drop across the power network and/or the ground network so that the timing violation is eliminated by circuit optimization. When the delay slack amount is positive, although the signal transmission path does not transmit a timing violation in the static timing analysis, this does not mean that the delay of the signal transmission path is not deteriorated and the timing violation does not occur in the case where there is a voltage drop in the power supply network and/or the ground network. Therefore, by determining a signal transmission path, a part of which is positive in delay slack, as a target path, it is possible to effectively prevent the occurrence of the above-described situation, and to further improve the recognition and optimization of circuit timing violations.

After determining the target path, in step S11, in the target path to be delay estimated, a circuit element that needs to be delay adjusted is determined, so as to obtain the target element. Specifically, in one embodiment of the present invention, in a target path to be delay estimated, determining a circuit element that needs to be delay adjusted, and obtaining the target element may include: determining the duty ratio of the delay caused by the metal interconnection line in the target path in the total delay of the target path according to the static time sequence analysis result; and determining a circuit element needing delay adjustment in the target path according to the duty ratio to obtain a target element. For example, in one example, by static timing analysis, in the target path K ₁, the signal propagation delay on the metal interconnect is t ₁, and the total delay in the target path is t ₂, then the duty cycle is t ₁/t₂. Of course, in other examples, the propagation delay t ₁ of the signal on the metal interconnect line and the total delay t ₂ in the target path may be determined in other ways, for example, by timing simulation of the circuit. The embodiments of the present invention are not limited in this regard.

In a specific implementation, according to the duty ratio, determining, in the target path, a circuit element that needs to be delay-adjusted, where obtaining the target element may include: determining a standard unit in the target path as the target element under the condition that the duty ratio is smaller than or equal to a preset duty ratio threshold value; and determining a standard cell and a metal interconnection line connecting different standard cells in the target path as the target element under the condition that the duty ratio is larger than the duty ratio threshold value. The size of the preset duty ratio threshold may be adjusted as required, for example, in one example, the preset duty ratio threshold may be 70%, in another example, the preset duty ratio threshold may be 40%, or 80%, or the like. Thus, if the duty ratio is smaller than or equal to the preset duty ratio threshold value, it means that the delay of the signal on the metal interconnection line is smaller in the total delay of the target path, and the delay change caused by the voltage drop is weaker on the metal interconnection line, so that it can be considered that in this case, the transmission delay of the signal on the metal interconnection line is not affected by the voltage drop, and no adjustment is required to the transmission delay of the metal interconnection line, so that the standard cell in the target path is determined as the target element. Otherwise, if the duty ratio is greater than the preset duty ratio threshold, it means that the delay of the signal on the metal interconnection line is greater in the total delay of the target path, the delay change caused by the voltage drop is more remarkable on the metal interconnection line, and the transmission delay of the metal interconnection line needs to be adjusted, so that both the metal interconnection line and the standard unit can be determined as target elements.

After determining the target elements, in step S12, according to the attribute parameters of each target element in each target path, the delay adjustment reference proportion corresponding to each target element may be respectively searched in a pre-established lookup table.

Optionally, according to the difference of the target elements, the attribute parameters of the target elements are correspondingly different. For example, in one embodiment, the target element may comprise a standard cell, and the attribute parameter of the target element may comprise a first attribute parameter that may comprise a threshold voltage and a shortest channel length of a transistor comprising the standard cell, an input transfer time of the standard cell, and an output load capacitance of the standard cell. Wherein the threshold voltage and the shortest channel length of the transistors constituting a standard cell can be obtained by the process parameters of the standard cell. In general, the threshold voltages and the shortest channel lengths of the transistors constituting the standard cell are equal for the same standard cell. The input transition time (transition time) of the standard cell may refer to the time taken for a signal input to the standard cell to transition from a high level to a low level or a low level to a high level. The output load capacitance of the standard cell may refer to the equivalent capacitance to ground of the output of the standard cell.

Alternatively, in another embodiment, the target element may include a metal interconnection line for connecting different standard cells, and the attribute parameter of the target element may include a second attribute parameter, where the second attribute parameter may include, for example: the shape of the metal interconnection line, the distance between the metal interconnection line and the peripheral metal interconnection line, the number of layers of the metal interconnection line included in the circuit, the distribution condition of capacitance and inductance in the circuit and the like.

Whether the target element is a standard unit or a metal interconnection line, the delay adjustment reference proportion corresponding to the attribute parameter can be searched in the lookup table according to the attribute parameter of the target element. By way of example, a specific structure of a lookup table may be as shown in table 1. For the attribute parameters which do not exist in the lookup table, a linear difference mode can be adopted, and the delay adjustment reference proportion corresponding to the attribute parameters can be determined based on the lookup table.

TABLE 1

In the embodiment of the present invention, the reference proportion of delay adjustment, that is, the reference proportion when delay adjustment is performed on the target element, may specifically refer to the proportion of delay increase of the target element on the signal under the condition that there is a voltage drop of the first proportion in the power supply voltage and/or the ground voltage. For example, in one example, when there is no voltage drop in the power supply voltage and/or the ground voltage, the delay time of the target element to the signal is 0.1 seconds, and when there is a voltage drop in the first ratio in the power supply voltage and/or the ground voltage, the delay time of the target element to the signal is 0.12 seconds, the delay adjustment reference ratio is (0.12-0.1)/0.1=0.2. Thus, the voltage drop of the supply voltage and/or the ground voltage is linked to the delay variation of the circuit element by means of a look-up table.

As can be seen from the foregoing, the lookup table is established based on the first ratio, and the first ratio, regardless of the specific value, can only represent the delay change caused by the voltage drop of the power supply voltage and/or the ground voltage by one ratio. In fact, the target elements on the target path may have different levels of voltage drop during operation, and the resulting delay changes may be correspondingly different. In order to obtain the delay change caused by the voltage drops with different degrees, in one embodiment of the present invention, after the delay adjustment reference proportion is found, the delay adjustment proportion corresponding to each target element in the target path may be determined in step S13 according to the delay adjustment reference proportion and the first proportion. The delay adjustment proportion can represent the delay change condition corresponding to the target element when the voltage of the power supply voltage and/or the ground voltage is reduced by any proportion.

Specifically, in one embodiment of the present invention, determining the delay adjustment ratio corresponding to each target element in the target path according to the first ratio and the delay adjustment reference ratio may include: respectively obtaining voltage drops of second driving voltages corresponding to all target elements in the target path to obtain target voltage drops, wherein the second driving voltages comprise power supply voltages and/or ground voltages; and respectively determining delay adjustment proportions corresponding to all target elements in the target path according to the second driving voltage, the target voltage drop, the first proportion and the delay adjustment reference proportion.

The second driving voltage is different from the first driving voltage, and the second driving voltage is not related to the lookup table and refers to the driving voltage corresponding to the target element in the target path. The voltage drop of the second driving voltage, i.e. the target voltage drop, may refer to the supply voltage and/or the ground voltage of the target element, the voltage change in the supply network and/or the ground network caused by ohm's law of the product of the current and the resistance. Alternatively, the target voltage drop may be obtained in a variety of ways, for example, by checking and verifying the target path with an IR drop checking tool currently available, or by simulating and measuring the circuit in other ways.

According to the second driving voltage, the target voltage drop, the first proportion and the delay adjustment reference proportion, determining the delay adjustment proportion corresponding to each target element in the target path respectively may specifically include: and determining the delay adjustment proportion corresponding to each target element according to the following formula.

D_real＝D_ref*(ΔV₂/V₂)/P₁ (1)

Wherein D _real is the delay adjustment ratio, D _ref is the delay adjustment reference ratio, Δv ₂ is the voltage drop of the second driving voltage, V ₂ is the second driving voltage, Δv ₂/V₂ is the voltage drop ratio of the second driving voltage, and P ₁ is the first ratio.

For example, in one example, the second driving voltage corresponding to one target element in the target path is 1.2V, the voltage drop of the second driving voltage is 0.3V, the first ratio is 10%, and the delay adjustment reference ratio is 0.2, so that the delay adjustment ratio of the target element can be determined to be 0.2 x (0.3/1.2)/10% =0.5. I.e. the ratio of the fraction of delay increase to the delay before no increase is 0.5, i.e. the delay is increased by 50%.

After the delay adjustment proportion is obtained, in step S14, the delay of the target path may be determined according to the delay adjustment proportion corresponding to each target element in the target path. Specifically, determining the delay of the target path according to the delay adjustment proportion corresponding to each target element in the target path may include: according to the delay adjustment proportion corresponding to each target element in the target path, element delay of each target element is respectively determined; and determining the delay of the target path according to the element delay of each target element.

In a specific implementation, according to the delay adjustment proportion corresponding to each target element in the target path, determining the element delay of each target element respectively may include: according to the delay adjustment proportion corresponding to each target element in the target path, respectively determining the delay adjustment factor of each target element; and respectively determining the element delay of each target element according to the delay of each target element in static time sequence analysis and the delay adjustment factor of the target element. The delay adjustment ratio is the ratio of the part with increased delay to the original delay, the delay adjustment factor is the ratio of the increased delay to the original delay, that is, the delay adjustment factor is equal to the delay adjustment ratio plus 1, and then the element delay of the target element can be determined according to the formula (2).

T_dst＝T_ori*(1+D_real) (2)

Wherein T _dst is the element delay of the target element, T _ori is the delay of the target element in static time sequence analysis, D _real is the delay adjustment ratio, and 1+D _real is the delay adjustment factor.

After the element delay of the target element is determined according to the method, the delay of the target path can be determined according to the element delay of each target element in the target path. Specifically, it can check whether a circuit element which is not the target element exists in the target path except the target element, if not, the element delays of the target elements can be accumulated to obtain the delay of the target path; if the circuit element exists, determining the circuit element which does not need to be subjected to delay adjustment in the target path to obtain a holding element; and accumulating element delays of all target elements in the target path and element delays of all holding elements in the target path, which are obtained based on static time sequence analysis, to obtain the delay of the target path.

Optionally, the delay of each element is accumulated, which can be realized by a general calculation tool or a special tool. For example, in one embodiment of the invention, accumulating element delays may be implemented by a static timing analysis tool. Specifically, the delay parameters of the target element can be adjusted, after the corresponding element delay is obtained, static time sequence analysis is performed again, so that the delay of the target path is obtained under the condition that the voltage drop exists in the power supply network and/or the ground network. Therefore, the new time delay is utilized to carry out time sequence analysis of the critical path, the path with the worst time sequence violations or time sequence allowance changes can be positioned, and the limit is set according to the design requirement, so that targeted repair or optimization can be carried out.

In the embodiment of the invention, the delay adjustment reference proportion corresponding to each target element can be obtained through the lookup table, and the delay of the target path under the condition that the voltage drop exists in the power supply network and/or the ground network is obtained accordingly. Because the lookup table does not need to contain all standard cells and/or metal interconnection lines, but only needs to contain target elements in a targeted way or circuit elements which are relatively close to the target elements, compared with the prior art, the operation amount is greatly reduced by carrying out time-delay scaling on the whole standard cell library.

By way of example, by applying the method for estimating circuit delay provided by the embodiment of the present invention, the comparison between the estimated result of the delay of the critical path under the influence of voltage drop in a certain practical project and the actual delay can be shown in table 2. As can be seen from table 2, the error can be within 2% when estimating the delay of the critical path under the influence of IR drop.

TABLE 2

The method for estimating the circuit delay provided by the embodiment of the invention provides a simplified low-order mathematical model for calculating the delay of the critical path under the influence of IR drop. By the model, the method can be used for specifically and rapidly judging: whether a critical path is delayed to increase due to existence of voltage drop or not, and thus, the risk of violation exists; a critical path has negligible impact on the critical path timing in cases where the voltage drop is large and the standard cell delay increases (e.g., 10% above the supply voltage). Therefore, the time for regenerating or expanding the time sequence library of the standard unit under different voltages can be greatly reduced, and the research and development efficiency is improved. By the technical scheme provided by the embodiment of the invention, before the film is formed, the critical paths with more sensitive delay influenced by voltage drop can be optimized in advance; after the silicon of the chip is verified, insufficient power supply and time sequence tension are established due to IR drop, and when the voltage needs to be boosted, the boosting amplitude can be reduced, so that the power consumption of the chip is reduced.

Further, in order to obtain the above lookup table, in one embodiment of the present invention, in step S12, before searching, in a pre-established lookup table, a delay adjustment reference ratio corresponding to each target element according to an attribute parameter of each target element in each target path, an estimation method of circuit delay provided in an embodiment of the present invention may further include: acquiring attribute parameters of preset circuit elements; and establishing the lookup table according to the attribute parameters of the preset circuit elements.

Optionally, the preset circuit elements may be selected according to circuit elements included in the circuit that needs to perform timing analysis, for example, all circuit elements may be selected according to a preset rule in the circuit that needs to perform timing analysis, or a part of the circuit elements may be used as preset circuit elements. The preset rule may be chosen, for example, randomly or according to the magnitude of the delay slack. The embodiments of the present invention are not limited in this regard. Furthermore, the established lookup table can be used for delay estimation of other circuits with the same or similar circuit elements, so that the application range of the lookup table is greatly expanded, and a plurality of repeated works are reduced.

In one embodiment, the preset circuit elements may be divided into a plurality of element types according to whether the attribute parameters are the same, the preset circuit elements of the same element type have the same corresponding attribute parameters, and a lookup table may be established according to the attribute parameters of the preset circuit elements.

Specifically, according to the attribute parameters of the preset circuit elements, establishing the lookup table may include:

performing time sequence simulation on the preset circuit element under the condition that the first driving voltage corresponding to the preset circuit element generates the voltage drop of the first proportion to obtain a first time delay of the preset circuit element, and performing time sequence simulation on the preset circuit element under the condition that the first driving voltage corresponding to the preset circuit element does not generate the voltage drop to obtain a second time delay of the preset circuit element;

Determining an element reference delay proportion corresponding to the preset circuit element when the first driving voltage corresponding to the preset circuit element generates the voltage drop of the first proportion according to the first delay and the second delay;

determining a delay adjustment reference proportion of an element type to which the preset circuit element belongs according to the element reference delay proportion;

And establishing the lookup table according to the attribute parameters of the preset circuit elements and the delay adjustment reference proportion.

In this embodiment, for two cases that each preset circuit element has a voltage drop of a first proportion and no voltage drop at a power supply voltage and/or a ground voltage, time sequence simulation may be performed respectively to obtain a transmission delay of the preset circuit element in each case, that is, a first delay and a second delay, and then a difference between the first delay and the second delay is divided by the second delay, that is, an element reference delay proportion of the preset circuit element.

Optionally, the preset circuit element may include a preset standard cell and/or a connection metal interconnection, which is not limited by the embodiment of the present invention. In an embodiment of the present invention, the preset circuit elements include preset standard units, where the preset standard units may be divided into a plurality of element types according to whether attribute parameters are the same, and the preset standard units of the same element type have the same corresponding attribute parameters. Optionally, each element type may include the same preset standard unit with the same attribute parameter and the same logic function, or may include at least two different preset standard units with the same attribute parameter and different logic functions; wherein, the attribute parameters of each preset standard unit comprise: the threshold voltage and the shortest channel length of the transistor forming the preset standard cell, the input transfer time of the preset standard cell and the output load capacitance of the preset standard cell. The specific meaning of these attribute parameters has been described in the foregoing, and will not be described in detail herein.

That is, in the embodiment of the present invention, the preset circuit element may include a plurality of preset standard cells different from each other, where the preset standard cells different from each other refer to different attribute parameters and/or different functions of the preset standard cells. That is, the corresponding preset standard cell is different as long as there is one difference in the attribute parameter and the function. Specifically, if the attribute parameters are the same but the functions are different, the corresponding preset standard units are different preset standard units belonging to the same element type. And if the attribute parameters and the functions are the same, the corresponding preset standard units are the same.

In one embodiment, if the element types of the preset standard units only include the same preset standard units with the same attribute parameters and the same logic functions, the element reference delay ratio of the preset standard units can be directly used as the corresponding delay adjustment reference ratio to be filled into the lookup table. If the element type to which the preset standard unit belongs includes at least two different preset standard units having the same attribute parameters but different logic functions, determining the delay adjustment reference proportion of the element type to which the preset circuit element belongs according to the element reference delay proportion specifically may include: and determining that the delay adjustment reference proportion is equal to an average value of element reference delay proportions corresponding to various preset standard units under the element type.

For example, an element type may include two different preset standard cells, cell ₁ and cell ₂, where the attribute parameters of cell ₁ and cell ₂ are the same but the functions are different. Specifically, the threshold voltages of the transistors constituting the preset standard cells cell ₁ and cell ₂ are V _th1, the shortest channel length is L ₁,cell₁, the input transfer time of cell ₂ is T ₁, the output load capacitance is C ₁, but cell ₁ is a nand gate, so as to implement a nand logic function, and cell ₂ is an or gate, so as to implement an or logic function. If the element reference delay ratio of cell ₁ is D ₁,cell₂ and the element reference delay ratio is D ₂, the delay adjustment reference ratio for that element type is (D ₁+D₂)/2.

The method for estimating the circuit delay provided by the embodiment of the invention is described in detail below by using a specific embodiment.

As shown in fig. 2, the method for estimating circuit delay provided by the embodiment of the invention may include:

S201, acquiring attribute parameters of preset standard units, wherein the preset standard units are divided into a plurality of element types, and the attribute parameters corresponding to standard units of the same element type are the same;

S202, performing time sequence simulation on a preset standard unit under the condition that a first driving voltage corresponding to the preset standard unit has a first proportion of voltage drop to obtain a first time delay of the preset standard unit, and performing time sequence simulation on the preset standard unit under the condition that the first driving voltage corresponding to the preset standard unit has no voltage drop to obtain a second time delay of the preset standard unit;

S203, determining the element reference delay proportion corresponding to the preset standard unit when the voltage drop of the first proportion occurs to the first driving voltage corresponding to the preset standard unit according to the first delay and the second delay;

S204, determining delay adjustment reference proportion of element types to which a preset standard unit belongs according to element reference delay proportion;

S205, adjusting a reference proportion according to attribute parameters and delay of a preset standard unit, and establishing a lookup table;

S206, acquiring a signal transmission path of which the delay relaxation amount meets preset conditions in the circuit according to a static time sequence analysis result of the circuit, and acquiring a target path;

Optionally, the signal transmission path with the delay relaxation amount meeting the preset condition includes at least one of the following: a signal transmission path having a delay slack less than a preset threshold, wherein the preset threshold is greater than 0; and when the delay relaxation quantity is ordered from small to large, the delay relaxation quantity is positioned in a signal transmission path of N bits before ordering, wherein N is a positive integer.

S207, determining the duty ratio of the delay caused by the metal interconnection line in the target path in the total delay of the target path according to the static time sequence analysis result;

S208, determining standard units in the target path as target elements under the condition that the duty ratio is smaller than or equal to a preset duty ratio threshold value;

S209, respectively searching delay adjustment reference proportions corresponding to all target elements in a lookup table according to attribute parameters of all target elements in each target path;

S210, obtaining voltage drops of second driving voltages corresponding to all target elements in the target path to obtain target voltage drops, wherein the second driving voltages comprise power supply voltages and/or ground voltages;

S211, respectively determining delay adjustment proportions corresponding to all target elements in a target path according to a second driving voltage, a target voltage drop, a first proportion and a delay adjustment reference proportion;

S212, respectively determining delay adjustment factors of all target elements according to the delay adjustment proportion corresponding to all the target elements in the target path;

S213, according to the delay of each target element in the static time sequence analysis and the delay adjustment factor of the target element, determining the element delay of each target element;

S214, determining circuit elements which do not need to be subjected to delay adjustment in the target path to obtain a holding element;

s215, accumulating element delays of all target elements in the target path and element delays of all holding elements in the target path based on static time sequence analysis to obtain the delay of the target path.

In a second aspect, embodiments of the present invention further provide an apparatus for estimating a circuit delay, which can quickly and accurately estimate the circuit delay in the presence of IR drop.

As shown in fig. 3, an embodiment of the present invention provides a circuit delay estimation apparatus, which may include:

A first determining unit 31, configured to determine, in a target path to be subjected to delay estimation, a circuit element that needs to be subjected to delay adjustment, so as to obtain a target element;

A lookup unit 32, configured to separately find, in a pre-established lookup table, a delay adjustment reference ratio corresponding to each target element according to an attribute parameter of each target element in each target path, where the lookup table is established based on a first ratio, where the first ratio is a ratio of a voltage drop of a first driving voltage corresponding to any circuit element in the lookup table to the first driving voltage, and the first driving voltage includes a power supply voltage and/or a ground voltage;

A second determining unit 33, configured to determine delay adjustment ratios corresponding to each target element in the target path according to the first ratio and the delay adjustment reference ratio;

And a third determining unit 34, configured to determine a delay of the target path according to the delay adjustment proportion corresponding to each target element in the target path.

The circuit delay estimation device provided by the embodiment of the invention can determine the circuit elements needing delay adjustment in the target paths to be subjected to delay estimation to obtain the target elements, and respectively find the delay adjustment reference proportion corresponding to each target element in the pre-established lookup table according to the attribute parameters of each target element in each target path, wherein the lookup table is established based on a first proportion, respectively determines the delay adjustment proportion corresponding to each target element in the target paths according to the first proportion and the delay adjustment reference proportion, and determines the delay of the target paths according to the delay adjustment proportion corresponding to each target element in the target paths. In this way, the first proportion is the ratio of the voltage drop of the first driving voltage corresponding to any circuit element in the lookup table to the first driving voltage, and the first driving voltage comprises the power supply voltage and/or the ground voltage, so that the lookup table established according to the first proportion can reflect the time delay change of each circuit element under the condition that the power supply voltage and/or the ground voltage have the voltage drop of the first proportion, and further, the reference proportion is adjusted according to the time delay obtained by the first lookup table, the influence of the voltage drop of the power supply voltage and/or the ground voltage on the time delay of the target path can be reflected, so that the time delay of the target path can be rapidly and accurately estimated under the condition that the power supply network and/or the ground network has the voltage drop.

In a third aspect, embodiments of the present invention further provide an electronic device capable of quickly and accurately evaluating a circuit delay in the presence of IR drop.

As shown in fig. 4, an electronic device provided by an embodiment of the present invention may include: the processor 52 and the memory 53 are arranged on the circuit board 54, wherein the circuit board 54 is arranged in a space surrounded by the shell 51; a power supply circuit 55 for supplying power to the respective circuits or devices of the above-described electronic apparatus; the memory 53 is for storing executable program code; the processor 52 executes a program corresponding to the executable program code by reading the executable program code stored in the memory 53 for performing the circuit delay estimation method provided in any of the foregoing embodiments.

The specific implementation of the above steps by the processor 52 and the further implementation of the steps by the processor 52 through the execution of the executable program code may be referred to the description of the foregoing embodiments, and will not be repeated here.

In a fourth aspect, embodiments of the present invention further provide a computer readable storage medium, where one or more programs are stored, where the one or more programs may be executed by one or more processors, so as to implement any of the circuit delay estimation methods provided in the foregoing embodiments, and thus, corresponding technical effects may also be achieved, which have been described in detail above and will not be repeated herein.

It is noted that relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element.

In this specification, each embodiment is described in a related manner, and identical and similar parts of each embodiment are all referred to each other, and each embodiment mainly describes differences from other embodiments.

In particular, for the device embodiments, since they are substantially similar to the method embodiments, the description is relatively simple, and reference is made to the description of the method embodiments in part.

For convenience of description, the above apparatus is described as being functionally divided into various units/modules, respectively. Of course, the functions of the various elements/modules may be implemented in the same piece or pieces of software and/or hardware when implementing the present invention.

Those skilled in the art will appreciate that implementing all or part of the above-described methods in accordance with the embodiments may be accomplished by way of a computer program stored on a computer readable storage medium, which when executed may comprise the steps of the embodiments of the methods described above. The storage medium may be a magnetic disk, an optical disk, a Read-Only Memory (ROM), a random-access Memory (Random Access Memory, RAM), or the like.

The foregoing is merely illustrative of the present invention, and the present invention is not limited thereto, and any changes or substitutions easily contemplated by those skilled in the art within the scope of the present invention should be included in the present invention. Therefore, the protection scope of the invention is subject to the protection scope of the claims.

Claims

1. A method for estimating circuit delay, comprising:

Determining a circuit element needing delay adjustment in a target path to be subjected to delay estimation to obtain a target element;

According to attribute parameters of each target element in each target path, respectively searching delay adjustment reference proportion corresponding to each target element in a pre-established lookup table, wherein the lookup table is established based on a first proportion, the first proportion is the ratio of voltage drop of a first driving voltage corresponding to any circuit element in the lookup table to the first driving voltage, and the first driving voltage comprises a power supply voltage and/or a ground voltage; the delay adjustment reference proportion is the proportion of the target element to the increase of the delay of the signal under the condition that the first driving voltage has the voltage drop of the first proportion;

Respectively determining delay adjustment proportions corresponding to all target elements in the target path according to the first proportion and the delay adjustment reference proportion;

Determining the delay of the target path according to the delay adjustment proportion corresponding to each target element in the target path;

wherein, the determining the delay adjustment proportion corresponding to each target element in the target path according to the first proportion and the delay adjustment reference proportion includes:

Respectively obtaining voltage drops of second driving voltages corresponding to all target elements in the target path to obtain target voltage drops, wherein the second driving voltages comprise power supply voltages and/or ground voltages;

And respectively determining delay adjustment proportions corresponding to all target elements in the target path according to the second driving voltage, the target voltage drop, the first proportion and the delay adjustment reference proportion.

2. The method according to claim 1, wherein in the target path to be delay estimated, determining a circuit element that needs to be delay adjusted, and before obtaining the target element, the method further comprises:

and acquiring a signal transmission path of which the delay relaxation amount meets a preset condition in the circuit according to a static time sequence analysis result of the circuit, and obtaining the target path.

3. The method of claim 2, wherein the signal transmission path for which the delay relaxation amount meets a preset condition comprises at least one of: a signal transmission path having a delay slack less than a preset threshold, wherein the preset threshold is greater than 0; and when the delay relaxation quantity is ordered from small to large, the delay relaxation quantity is positioned in a signal transmission path of N bits before ordering, wherein N is a positive integer.

4. The method according to claim 2, wherein determining, in the target path to be delay estimated, a circuit element that needs to be delay adjusted, and obtaining the target element includes:

Determining the duty ratio of the delay caused by the metal interconnection line in the target path in the total delay of the target path according to the static time sequence analysis result;

And determining a circuit element needing delay adjustment in the target path according to the duty ratio to obtain a target element.

5. The method of claim 4, wherein determining, in the target path, a circuit element that needs to be delay-adjusted according to the duty cycle, the target element comprises:

Determining a standard unit in the target path as the target element under the condition that the duty ratio is smaller than or equal to a preset duty ratio threshold value;

and determining a standard cell and a metal interconnection line connecting different standard cells in the target path as the target element under the condition that the duty ratio is larger than the duty ratio threshold value.

6. The method of claim 1, wherein the target element comprises a standard cell, the attribute parameter comprises a first attribute parameter comprising a threshold voltage and a shortest channel length of a transistor comprising the standard cell, an input transfer time of the standard cell, and an output load capacitance of the standard cell.

7. The method of claim 1, wherein the target element comprises metal interconnect lines for connecting different standard cells; the attribute parameters include second attribute parameters including: the shape of the metal interconnection line, the distance between the metal interconnection line and the peripheral metal interconnection line, the number of layers of the metal interconnection line included in the circuit and the distribution of capacitance and inductance in the circuit.

8. The method of claim 1, wherein determining the delay of the target path according to the delay adjustment ratio corresponding to each target element in the target path comprises:

According to the delay adjustment proportion corresponding to each target element in the target path, element delay of each target element is respectively determined;

And determining the delay of the target path according to the element delay of each target element.

9. The method of claim 8, wherein the determining the element delay of each target element according to the delay adjustment ratio corresponding to each target element in the target path includes:

according to the delay adjustment proportion corresponding to each target element in the target path, respectively determining the delay adjustment factor of each target element;

And respectively determining the element delay of each target element according to the delay of each target element in static time sequence analysis and the delay adjustment factor of the target element.

10. The method of claim 8, wherein determining the delay of the target path based on the element delays of each of the target elements comprises:

determining a circuit element which does not need delay adjustment in the target path to obtain a holding element;

And accumulating element delays of all target elements in the target path and element delays of all holding elements in the target path, which are obtained based on static time sequence analysis, to obtain the delay of the target path.

11. The method according to any one of claims 1 to 10, wherein before searching a pre-established lookup table for a delay adjustment reference proportion corresponding to each target element according to an attribute parameter of each target element in each target path, the method further comprises:

Acquiring attribute parameters of preset circuit elements;

and establishing the lookup table according to the attribute parameters of the preset circuit elements.

12. The method of claim 11, wherein the predetermined circuit elements are divided into a plurality of element types, attribute parameters corresponding to the predetermined circuit elements of the same element type are the same, and the creating the lookup table according to the attribute parameters of the predetermined circuit elements comprises:

13. The method of claim 12, wherein the preset circuit elements comprise preset standard cells, each of the element types comprising the same preset standard cell having the same attribute parameter and the same logic function, or comprising at least two different preset standard cells having the same attribute parameter and the different logic functions; wherein, the attribute parameters of each preset standard unit comprise: the threshold voltage and the shortest channel length of the transistor forming the preset standard cell, the input transfer time of the preset standard cell and the output load capacitance of the preset standard cell.

14. The method according to claim 13, wherein the element types to which the preset standard cells belong include at least two preset standard cells having the same attribute parameter but different logic functions;

the determining the delay adjustment reference proportion of the element type to which the preset circuit element belongs according to the element reference delay proportion comprises:

And determining that the delay adjustment reference proportion is equal to an average value of the element reference delay proportions corresponding to various preset standard units under the element type.

15. An apparatus for estimating circuit delay, comprising:

The first determining unit is used for determining a circuit element needing delay adjustment in a target path to be subjected to delay estimation to obtain a target element;

The searching unit is used for searching delay adjustment reference proportions corresponding to all target elements in a pre-established searching table according to attribute parameters of all the target elements in each target path, wherein the searching table is established based on a first proportion, the first proportion is the ratio of voltage drop of a first driving voltage corresponding to any circuit element in the searching table to the first driving voltage, and the first driving voltage comprises a power supply voltage and/or a ground voltage; the delay adjustment reference proportion is the proportion of the target element to the increase of the delay of the signal under the condition that the first driving voltage has the voltage drop of the first proportion;

The second determining unit is used for determining delay adjustment proportions corresponding to all target elements in the target path according to the first proportion and the delay adjustment reference proportion;

A third determining unit, configured to determine a delay of the target path according to the delay adjustment proportion corresponding to each target element in the target path;

Wherein the second determining unit includes:

The acquisition module is used for respectively acquiring voltage drops of second driving voltages corresponding to all target elements in the target path to obtain target voltage drops, wherein the second driving voltages comprise power supply voltages and/or ground voltages;

and the first determining module is used for respectively determining delay adjustment proportions corresponding to all target elements in the target path according to the second driving voltage, the target voltage drop, the first proportion and the delay adjustment reference proportion.

16. The apparatus as recited in claim 15, further comprising:

The first acquisition unit is used for determining a circuit element needing delay adjustment in the target path to be subjected to delay estimation, and acquiring a signal transmission path of which the delay relaxation amount in the circuit meets a preset condition according to a static time sequence analysis result of the circuit before the target element is obtained, so as to obtain the target path.

17. The apparatus of claim 16, wherein the signal transmission path for which the delay slack meets a preset condition comprises at least one of: a signal transmission path having a delay slack less than a preset threshold, wherein the preset threshold is greater than 0; and when the delay relaxation quantity is ordered from small to large, the delay relaxation quantity is positioned in a signal transmission path of N bits before ordering, wherein N is a positive integer.

18. The apparatus of claim 16, wherein the first determining unit comprises:

The second determining module is used for determining the duty ratio of the delay caused by the metal interconnection line in the target path in the total delay of the target path according to the static time sequence analysis result;

and the third determining module is used for determining a circuit element needing delay adjustment in the target path according to the duty ratio to obtain a target element.

19. The apparatus according to claim 18, wherein the third determining module is specifically configured to:

20. The apparatus of claim 15, wherein the target element comprises a standard cell, the attribute parameter comprises a first attribute parameter comprising a threshold voltage and a shortest channel length of a transistor comprising the standard cell, an input transition time of the standard cell, and an output load capacitance of the standard cell.

21. The apparatus of claim 15, wherein the target element comprises metal interconnect lines for connecting different standard cells; the attribute parameters include second attribute parameters including: the shape of the metal interconnection line, the distance between the metal interconnection line and the peripheral metal interconnection line, the number of layers of the metal interconnection line included in the circuit and the distribution of capacitance and inductance in the circuit.

22. The apparatus of claim 15, wherein the third determining unit comprises:

A fourth determining module, configured to determine element delays of the target elements according to the delay adjustment ratios corresponding to the target elements in the target path;

And a fifth determining module, configured to determine a delay of the target path according to an element delay of each target element.

23. The apparatus of claim 22, wherein the fourth determining module is specifically configured to:

24. The apparatus of claim 22, wherein the fifth determining module is specifically configured to:

25. The apparatus according to any one of claims 15 to 24, further comprising:

The second obtaining unit is used for obtaining attribute parameters of preset circuit elements before respectively searching delay adjustment reference proportions corresponding to the target elements in a pre-established lookup table according to the attribute parameters of the target elements in each target path;

And the establishing unit is used for establishing the lookup table according to the attribute parameters of the preset circuit elements.

26. The apparatus of claim 25, wherein the predetermined circuit elements are divided into a plurality of element types, and attribute parameters corresponding to the predetermined circuit elements of the same element type are the same;

the establishing unit includes:

The simulation module is used for carrying out time sequence simulation on the preset circuit element under the condition that the first driving voltage corresponding to the preset circuit element generates the voltage drop of the first proportion to obtain a first delay of the preset circuit element, and carrying out time sequence simulation on the preset circuit element under the condition that the first driving voltage corresponding to the preset circuit element does not generate the voltage drop to obtain a second delay of the preset circuit element;

A sixth determining module, configured to determine, according to the first delay and the second delay, an element reference delay proportion corresponding to the preset circuit element when the first driving voltage corresponding to the preset circuit element has the voltage drop of the first proportion;

a seventh determining module, configured to determine a delay adjustment reference proportion of an element type to which the preset circuit element belongs according to the element reference delay proportion;

the establishing module is used for establishing the lookup table according to the attribute parameters of the preset circuit elements and the delay adjustment reference proportion.

27. The apparatus of claim 26, wherein the preset circuit elements comprise preset standard cells, each of the element types comprising a same preset standard cell having a same attribute parameter and a same logic function, or comprising at least two different preset standard cells having a same attribute parameter and a different logic function; wherein, the attribute parameters of each preset standard unit comprise: the threshold voltage and the shortest channel length of the transistor forming the preset standard cell, the input transfer time of the preset standard cell and the output load capacitance of the preset standard cell.

28. The apparatus of claim 27, wherein the element types to which the preset standard cells belong include at least two preset standard cells having the same attribute parameter but different logic functions;

The seventh determining module is specifically configured to determine that the delay adjustment reference proportion is equal to an average value of the element reference delay proportions corresponding to various preset standard units under the element type.

29. An electronic device, the electronic device comprising: the device comprises a shell, a processor, a memory, a circuit board and a power circuit, wherein the circuit board is arranged in a space surrounded by the shell, and the processor and the memory are arranged on the circuit board; a power supply circuit for supplying power to each circuit or device of the electronic apparatus; the memory is used for storing executable program codes; a processor runs a program corresponding to the executable program code by reading the executable program code stored in the memory for performing the method of estimating a circuit delay according to any of the preceding claims 1 to 14.

30. A computer readable storage medium storing one or more programs executable by one or more processors to implement the method of estimating circuit delay of any of the preceding claims 1 to 14.