CN110619137A - Time sequence analysis method aiming at voltage drop and application - Google Patents
Time sequence analysis method aiming at voltage drop and application Download PDFInfo
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Abstract
The invention discloses a time sequence analysis method aiming at voltage drop and application thereof, and relates to the technical field of integrated circuit design. The method comprises the following steps: setting a first voltage drop threshold and a second voltage drop threshold; the power consumption analysis tool acquires a voltage drop violation point according to the post-simulation waveform and judges whether the voltage drop of the voltage drop violation point is between a first voltage drop threshold and a second voltage drop threshold; if yes, the OCV values of the unit library under different state angles are obtained through query based on a preset voltage drop lookup table, and then a delay change value of each unit caused by voltage drop is calculated; and reversely marking each value into a time sequence analysis tool, carrying out STA analysis, judging whether a new time sequence violation occurs, carrying out physical repair when the new time sequence violation occurs, and otherwise, ending. The invention can greatly reduce points needing physical repair, can obviously reduce iteration times and quickly reach the acceptance standard.
Description
Technical Field
The invention relates to the technical field of integrated circuit design.
Background
With the mainstream development of very large scale integrated circuits entering 16/12nm or even lower processes, power consumption becomes a key factor restricting the development of integrated circuits, and reducing the working voltage of a chip is always the most effective low power consumption technology, so that the working voltage is closer to the threshold voltage, and the influence of the voltage on timing analysis is more and more important.
For chip Voltage drop (IR drop), the prior art generally reserves a margin for chip timing by reserving Voltage on-chip variations (OCV) and clock uncertainty (clock uncertainty). However, the above-mentioned reserved margin is usually designed for a convergence standard for voltage fluctuation of about 10%, and in actual power consumption analysis, it is found that the operating voltage of an individual cell (std cell) often exceeds 10% fluctuation; on the other hand, cells with excessive external voltage drop tend to be area-specific, and overly pessimistic if they are tailored to the pessimistic unified voltage drop timing closure criteria for the full chip.
For the above problems, the following methods are generally adopted at present: firstly, finding out points where voltage drops exceed a convergence standard, and repairing the points with overlarge voltage drops through physical implementation; secondly, a abandon (drive) mechanism is established, timing analysis is carried out on some units which are not on the critical path, and abandon is carried out under the condition that enough timing margins are confirmed. The above method has the following defects: firstly, if physical repair is directly carried out, a new timing sequence problem can be introduced while voltage drop is repaired, and iteration times are increased; secondly, the adoption of a waive mechanism is not accurate enough, and the voltage drop on the clock path can only be estimated approximately considering the possibility that a plurality of cells (stdcell) on the same time sequence path have voltage drop. Therefore, a timing analysis method for voltage drop is needed to provide more accurate and reliable timing analysis.
Disclosure of Invention
The invention aims to: the defects of the prior art are overcome, and a time sequence analysis method and application for voltage drop are provided. The invention can inversely mark the delay change caused by the voltage drop into a real static time sequence analysis environment, all state angles can analyze the time sequence change caused by the voltage drop, and the time sequence analysis is more accurate and reliable. The point with larger voltage drop is considered to be repaired when the point accords with the preset rule, so that the points needing physical repair are greatly reduced, the iteration times can be obviously reduced, and the acceptance standard can be quickly reached.
In order to achieve the above object, the present invention provides the following technical solutions:
a method of timing analysis for voltage drops, comprising the steps of:
setting a first voltage drop threshold and a second voltage drop threshold; the first voltage drop threshold is set based on a preset sign-in standard, and the second voltage drop threshold is larger than the first voltage drop threshold;
acquiring the information of the acquired simulated waveform, acquiring a voltage drop violation point by a power consumption analysis tool according to the acquired simulated waveform, and judging whether the voltage drop of the voltage drop violation point is between a first voltage drop threshold and a second voltage drop threshold;
if yes, based on a preset voltage drop lookup table, searching and obtaining OCV values of the unit library under different state angles, obtaining an OCV difference value delta _ OCV between the OCV value of the second voltage drop threshold and the OCV value of the first voltage drop threshold, and then calculating a delay change value of each unit caused by voltage drop; value _ delay (delta _ OCV + guardband)%, wherein the cell _ delay is the original delay value of the corresponding unit, the delta _ OCV is the OCV difference value, and the guardband is the reserved OCV value for the over protection;
and reversely marking each value into a time sequence analysis tool, carrying out STA analysis, judging whether a new time sequence violation occurs, carrying out physical repair when the new time sequence violation occurs, and otherwise, ending.
And further, when the voltage drop of the voltage drop violation point is judged to exceed the second voltage drop threshold, the voltage drop violation point is physically repaired.
Further, according to a preset sign-in standard, reserving a margin for a chip time sequence according to the voltage drop on-chip variation degree corresponding to the first voltage drop threshold, and when the voltage drop of the voltage drop violation point is judged to be smaller than the first voltage drop threshold, no physical repair is needed.
Further, the first voltage drop threshold is set to 10% and the second voltage drop threshold is set to 20%.
Further, the voltage drop lookup table is a TSMC voltage drop lookup table.
Further, the cell _ delay value is obtained through a time sequence analysis tool; the guardland values were obtained by analyzing the OCV values for the different state angles.
Further, a larger guardband value is reserved for units on the clock path compared to units on the data path to increase protection.
Further, the value is back-scaled into the timing analysis tool in such a way that it is added to the line delay of the output port of each voltage drop unit.
The invention also provides a time sequence acceptance system aiming at the voltage drop, which comprises the following structures:
the information setting module is used for setting a first voltage drop threshold value and a second voltage drop threshold value; the first voltage drop threshold is set based on a preset sign-in standard, and the second voltage drop threshold is larger than the first voltage drop threshold;
the information analysis module is used for acquiring the information of the post-simulation waveform, acquiring a voltage drop violation point according to the post-simulation waveform, and judging whether the voltage drop of the voltage drop violation point is between a first voltage drop threshold and a second voltage drop threshold; if yes, based on a preset voltage drop lookup table, searching and obtaining OCV values of the unit library under different state angles, obtaining an OCV difference value delta _ OCV between the OCV value of the second voltage drop threshold and the OCV value of the first voltage drop threshold, and then calculating a delay change value of each unit caused by voltage drop; value _ delay (delta _ OCV + guardband)%, wherein the cell _ delay is the original delay value of the corresponding unit, the delta _ OCV is the OCV difference value, and the guardband is the reserved OCV value for the over protection;
and the information processing module is used for reversely marking each value into the time sequence analysis tool, performing STA analysis, judging whether a new time sequence violation occurs, performing physical repair when the new time sequence violation occurs, and otherwise, ending.
Due to the adoption of the technical scheme, compared with the prior art, the invention has the following advantages and positive effects as examples: 1) the delay change caused by the voltage drop can be inversely marked in a real STA (static timing analysis) environment, all state angles (Corner) can analyze the timing change caused by the voltage drop, and the timing analysis is more accurate and reliable. 2) On the other hand, for points with large voltage drop, the whole voltage drop convergence analysis is carried out, and the repairing is considered only under the condition that the setup time/hold time (setup/hold time) has new time sequence violation, so that the points needing physical repairing can be greatly reduced, the iteration times can be obviously reduced, and the acceptance standard can be quickly reached.
Drawings
Fig. 1 is a flowchart of a timing analysis method for voltage drop according to an embodiment of the present invention.
Fig. 2 is a block diagram of a system according to an embodiment of the present invention.
Detailed Description
The timing analysis method and application for voltage drop disclosed in the present invention are further described in detail with reference to the accompanying drawings and specific embodiments. It should be noted that technical features or combinations of technical features described in the following embodiments should not be considered as being isolated, and they may be combined with each other to achieve better technical effects. In the drawings of the embodiments described below, the same reference numerals appearing in the respective drawings denote the same features or components, and may be applied to different embodiments. Thus, once an item is defined in one drawing, it need not be further discussed in subsequent drawings.
It should be noted that the structures, proportions, sizes, and other dimensions shown in the drawings and described in the specification are only for the purpose of understanding and reading the present disclosure, and are not intended to limit the scope of the invention, which is defined by the claims, and any modifications of the structures, changes in the proportions and adjustments of the sizes and other dimensions, should be construed as falling within the scope of the invention unless the function and objectives of the invention are affected. The scope of the preferred embodiments of the present invention includes additional implementations in which functions may be executed out of order from that described or discussed, including substantially concurrently or in reverse order, depending on the functionality involved, as would be understood by those reasonably skilled in the art of the embodiments of the present invention.
Techniques, methods, and apparatus known to those of ordinary skill in the relevant art may not be discussed in detail but are intended to be part of the specification where appropriate. In all examples shown and discussed herein, any particular value should be construed as merely illustrative, and not limiting. Thus, other examples of the exemplary embodiments may have different values.
Examples
Referring to fig. 1, there is provided a timing analysis method for voltage drop, including the steps of:
s100, setting a first voltage drop threshold value and a second voltage drop threshold value.
The first voltage drop threshold is set based on a preset sign-in criterion. In this embodiment, according to a signature criterion (timing convergence criterion) commonly used in the prior art, the first voltage drop threshold is set to 10%, that is, the allowable voltage fluctuation is within 10%.
In specific implementation, according to the sign-in standard, a voltage on-chip variation (voltage OCV), timing iteration and convergence are reserved for a voltage drop of 10%, and corresponding netlist, DEF, SPEF and other files are output, and the files are used by a power consumption analysis tool (such as rednawk) and a timing analysis tool (Primetime, abbreviated as PT).
The second voltage drop threshold is greater than the first voltage drop threshold. The designer may perform adaptive setting according to actual needs, for example, may obtain the fluctuation value of the operating voltage of all the cells (std cells), and the second voltage drop threshold is set to be more than 90% of the fluctuation value of the operating voltage of the cells. In this embodiment, the second voltage drop threshold is set to 20%.
S200, acquiring the information of the post-simulation waveform, acquiring a voltage drop violation point by the power consumption analysis tool according to the post-simulation waveform, and judging whether the voltage drop of the voltage drop violation point is between a first voltage drop threshold and a second voltage drop threshold.
And the post-simulation refers to that after the layout design is finished, parasitic parameters and interconnection delay are inversely labeled into the extracted circuit netlist for simulation, and the circuit is analyzed to ensure that the circuit meets the design requirement. Acquiring a rear simulation waveform output by a rear simulation verification worker, and intercepting a waveform time period with the maximum consumption POWER (MAX _ POWER); the waveform and information such as netlist, DEF, SPEF, etc. are read into a power consumption analysis tool, and an analysis result is output, wherein points where the voltage drop exceeds 10% are listed in the analysis result. Because for the point that the voltage drop is less than 10%, the allowance can be reserved for the chip time sequence according to the preset sign-in standard and the variation degree on the voltage drop reserved voltage sheet of 10%, the point does not need to be physically repaired and is ensured by the established sign-in standard.
For points where the voltage drop exceeds 20%, physical repair is performed directly.
S300, for the point where the voltage drop is between 10% and 20%, the following steps are performed.
Obtaining OCV values of the cell library under different state angles based on a preset voltage drop lookup table, obtaining an OCV difference value delta _ OCV between the OCV value of the second voltage drop threshold and the OCV value of the first voltage drop threshold, and then calculating a delay change value of each cell caused by voltage drop; value 11_ delay (delta _ OCV + guardband)%, wherein the cell _ delay is the original delay value of the corresponding unit, the delta _ OCV is the aforementioned OCV difference value, and the guardband is the reserved OCV value for the over protection.
The voltage drop lookup table may be provided by a chip manufacturing company. In this embodiment, a TSMC voltage drop look-up table (from taijie corporation) is preferred. For example, and without limitation, according to the TSMC voltage drop lookup table, the IR drop (voltage drop) lookup table of the T30BWP40P140ULVT unit at the state angle of ssg0P81vm40c is shown as the following table:
the OCV difference delta _ OCV of the OCV value of the second voltage drop threshold value 20% from the OCV value of the first voltage drop threshold value 10% may be calculated to be 4.2-2.2-2.
A program is written in the timing analysis tool to calculate a cell delay value (cell _ delay value) for the voltage drop cell. By way of example and not limitation, the code to calculate the cell delay value of the voltage drop cell may be as follows:
then, a delay variation value of each cell caused by the voltage drop is calculated by a calculation formula. The calculation formula is set such that the change in retardation due to voltage drop is% of the retardation value of the original unit (voltage drop OCV difference + over-protection reserved OCV value).
That is, value _ cell _ delay (delta _ ocv + guardband)%;
in the formula, the cell _ delay is an original delay value of each unit and can be obtained by a timing analysis tool;
delta _ OCV is the aforementioned OCV difference;
the guardband reserves OCV values for over-protection, which can be obtained by analyzing the OCV values of different state angles. The specific facility, can be based on analyzing the voltage drop look-up table. By way of example, and not limitation, the following tables are analyzed:
it is noted that the difference between tt1v25c and ffg1p05vm40c at 20% is 5.1-4.5 equal to 0.6, which is less than 1 for different processes by analyzing different cell libraries. For over-protection, the guardband value may be set to 1%.
Meanwhile, based on design experience, a larger guardband value may be reserved for units on the clock path than for units on the data path to increase protection. By way of example and not limitation, such as for a clock signal, the guardband value is set to 2% to leave some more margin.
And S400, reversely marking each value into a time sequence analysis tool, carrying out STA analysis, judging whether a new time sequence violation occurs, carrying out physical repair when the new time sequence violation occurs, and otherwise, ending.
In this embodiment, the value is back-scaled to the timing analysis tool in such a way that the value is added to the line delay of the output port of each voltage drop unit. In particular, the value of each value can be automatically back-marked into the time sequence analysis tool through a writing program.
Then, STA analysis (static timing analysis) is performed. After the time sequence analysis is finished, if a new time sequence violation occurs, performing physical repair; and if no new timing violation occurs, considering that the timing after the voltage drop meets the requirement, and ending.
In another embodiment of the invention, a timing acceptance system for voltage drop is also provided.
Referring to fig. 2, the system includes the following structure: the device comprises an information setting module, an information analysis module and an information processing module.
The information setting module is used for setting a first voltage drop threshold value and a second voltage drop threshold value; the first voltage drop threshold is set based on a preset sign-in criterion, and the second voltage drop threshold is greater than the first voltage drop threshold.
The information analysis module is used for acquiring the information of the post-simulation waveform, acquiring a voltage drop violation point according to the post-simulation waveform, and judging whether the voltage drop of the voltage drop violation point is between a first voltage drop threshold and a second voltage drop threshold; if yes, based on a preset voltage drop lookup table, searching and obtaining OCV values of the unit library under different state angles, obtaining an OCV difference value delta _ OCV between the OCV value of the second voltage drop threshold and the OCV value of the first voltage drop threshold, and then calculating a delay change value of each unit caused by voltage drop; and value ═ cell-delay (delta _ OCV + guardband)%, wherein the cell-delay is the original delay value of the corresponding unit, the delta _ OCV is the OCV difference value, and the guardband is the reserved OCV value for the over protection.
And the information processing module is used for reversely marking each value into the time sequence analysis tool, performing STA analysis, judging whether a new time sequence violation occurs, performing physical repair when the new time sequence violation occurs, and otherwise, ending.
Other technical features are described in the previous embodiment and are not described in detail herein.
In the foregoing description, the disclosure of the present invention is not intended to limit itself to these aspects. Rather, the various components may be selectively and operatively combined in any number within the intended scope of the present disclosure. In addition, terms like "comprising," "including," and "having" should be interpreted as inclusive or open-ended, rather than exclusive or closed-ended, by default, unless explicitly defined to the contrary. All technical, scientific, or other terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs unless defined otherwise. Common terms found in dictionaries should not be interpreted too ideally or too realistically in the context of related art documents unless the present disclosure expressly limits them to that. Any changes and modifications of the present invention based on the above disclosure will be within the scope of the appended claims.
Claims (9)
1. A method for timing analysis of voltage drops, comprising the steps of:
setting a first voltage drop threshold and a second voltage drop threshold; the first voltage drop threshold is set based on a preset sign-in standard, and the second voltage drop threshold is larger than the first voltage drop threshold;
acquiring the information of the acquired simulated waveform, acquiring a voltage drop violation point by a power consumption analysis tool according to the acquired simulated waveform, and judging whether the voltage drop of the voltage drop violation point is between a first voltage drop threshold and a second voltage drop threshold;
if the current state angle is determined to be yes, obtaining OCV values of the unit library under different state angles based on a preset voltage drop lookup table, obtaining an OCV difference value delta _ OCV between the OCV value of the second voltage drop threshold and the OCV value of the first voltage drop threshold, and then calculating a delay change value of each unit caused by voltage drop, wherein the value is cell _ delay (delta _ OCV + guardband)%, in the formula, the cell _ delay is the original delay value of the corresponding unit, the delta _ OCV is the OCV difference value, and the guardband is a reserved OCV value for over-protection;
and reversely marking each value into a time sequence analysis tool, carrying out STA analysis, judging whether a new time sequence violation occurs, carrying out physical repair when the new time sequence violation occurs, and otherwise, ending.
2. The method of claim 1, wherein: and when the voltage drop of the voltage drop violation point is judged to exceed the second voltage drop threshold value, carrying out physical repair on the voltage drop violation point.
3. The method of claim 2, wherein: and reserving allowance for the chip time sequence according to the preset sign-in standard and the voltage drop reserved voltage on-chip variation degree corresponding to the first voltage drop threshold, wherein physical repair is not needed when the voltage drop of the voltage drop violation point is judged to be smaller than the first voltage drop threshold.
4. A method according to claim 1 or 2 or 3, characterized in that: the first voltage drop threshold is set to 10% and the second voltage drop threshold is set to 20%.
5. The method of claim 1, wherein: the voltage drop lookup table is a TSMC voltage drop lookup table.
6. The method of claim 1, wherein: the cell _ delay value is obtained through a time sequence analysis tool; the guardland values were obtained by analyzing the OCV values for the different state angles.
7. The method of claim 6, wherein: larger guardband values are reserved for units on the clock path compared to units on the data path to increase protection.
8. The method of claim 1, wherein: the value is back-scaled into the timing analysis tool by adding it to the line delay of the output port of each voltage drop cell.
9. A time series acceptance system for voltage drop, comprising the structure:
the information setting module is used for setting a first voltage drop threshold value and a second voltage drop threshold value; the first voltage drop threshold is set based on a preset sign-in standard, and the second voltage drop threshold is larger than the first voltage drop threshold;
the information analysis module is used for acquiring the information of the post-simulation waveform, acquiring a voltage drop violation point according to the post-simulation waveform, and judging whether the voltage drop of the voltage drop violation point is between a first voltage drop threshold and a second voltage drop threshold; if yes, based on a preset voltage drop lookup table, searching and obtaining OCV values of the unit library under different state angles, obtaining an OCV difference value delta _ OCV between the OCV value of the second voltage drop threshold and the OCV value of the first voltage drop threshold, and then calculating a delay change value of each unit caused by voltage drop; value _ delay (delta _ OCV + guardband)%, wherein the cell _ delay is the original delay value of the corresponding unit, the delta _ OCV is the OCV difference value, and the guardband is the reserved OCV value for the over protection;
and the information processing module is used for reversely marking each value into the time sequence analysis tool, performing STA analysis, judging whether a new time sequence violation occurs, performing physical repair when the new time sequence violation occurs, and otherwise, ending.
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| CN117272889A (en) * | 2023-08-28 | 2023-12-22 | 海光云芯集成电路设计(上海)有限公司 | Circuit delay estimation method and device, electronic equipment and storage medium |
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| CN110619137B (en) | 2022-12-02 |
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