CN117254888A - Method and device for realizing communication by single signal wire - Google Patents
Method and device for realizing communication by single signal wire Download PDFInfo
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- CN117254888A CN117254888A CN202311210158.7A CN202311210158A CN117254888A CN 117254888 A CN117254888 A CN 117254888A CN 202311210158 A CN202311210158 A CN 202311210158A CN 117254888 A CN117254888 A CN 117254888A
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- 238000004891 communication Methods 0.000 title claims abstract description 46
- 238000000034 method Methods 0.000 title claims abstract description 20
- 239000004020 conductor Substances 0.000 claims description 12
- 230000001360 synchronised effect Effects 0.000 claims description 11
- 238000012795 verification Methods 0.000 claims description 10
- 238000012360 testing method Methods 0.000 claims description 6
- 230000005540 biological transmission Effects 0.000 abstract description 5
- 238000013461 design Methods 0.000 abstract description 3
- 230000009286 beneficial effect Effects 0.000 abstract description 2
- 238000010586 diagram Methods 0.000 description 5
- 230000008569 process Effects 0.000 description 4
- 229910002056 binary alloy Inorganic materials 0.000 description 2
- 238000012937 correction Methods 0.000 description 2
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- 230000008859 change Effects 0.000 description 1
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L1/00—Arrangements for detecting or preventing errors in the information received
- H04L1/24—Testing correct operation
- H04L1/245—Testing correct operation by using the properties of transmission codes
- H04L1/246—Testing correct operation by using the properties of transmission codes two-level transmission codes, e.g. binary
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L12/00—Data switching networks
- H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
- H04L12/40—Bus networks
- H04L12/40169—Flexible bus arrangements
- H04L12/40176—Flexible bus arrangements involving redundancy
- H04L12/40195—Flexible bus arrangements involving redundancy by using a plurality of nodes
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Abstract
The invention provides a method and a device for realizing communication by a single signal wire, comprising the following steps: two nodes are respectively configured before communication, wherein one node is used as a transmitting end, and the other node is used as a receiving end; the transmitting end generates a checksum according to the effective data to be transmitted; the transmitting end serially transmits a data frame containing effective data and checksum to the receiving end through a single signal wire; the receiving end adds the received effective data and the checksum, and judges whether the result is 0 or not; and the receiving end sends the effective data or the error report to the data bus according to the judging result to finish the communication between the two nodes. The invention has the beneficial effects that: the data transmission quality is ensured, meanwhile, the data lines are reduced, the data alignment of multi-signal line communication is not needed to be considered, the resource consumption of SoC design is reduced, the complexity of a hardware system is reduced, the operation efficiency is improved, and the actual use cost is reduced.
Description
Technical Field
The invention belongs to the field of data communication, and particularly relates to a method and a device for realizing communication by a single signal wire.
Background
Common data communication is divided into two types, namely parallel interface communication and serial interface communication, wherein the two types have the advantages that the parallel interface communication speed is relatively high, but the consumption of resources is more, and different interface data need to be considered; serial communication is relatively slow, but consumes little resources, and does not require consideration of data alignment.
At present, serial communication interfaces are more and more popular, particularly the field of high-speed communication interfaces is basically occupied by serial communication interfaces, but in the existing technology for carrying out serial communication by a single signal wire, the error correction function is not available, so that the data transmission quality is low, the situation that data identification fails often occurs, and meanwhile, in the communication process, data needs to be aligned after the data signals are received, so that the analysis efficiency is low.
Disclosure of Invention
In view of the foregoing, the present invention is directed to a method and apparatus for implementing communication with a single signal wire, so as to solve at least one of the above-mentioned problems.
In order to achieve the above purpose, the technical scheme of the invention is realized as follows:
the first aspect of the present invention provides a method for implementing communication by using a single signal conductor, including:
two nodes are respectively configured before communication, wherein one node is used as a transmitting end, and the other node is used as a receiving end;
the transmitting end generates a checksum according to the effective data to be transmitted;
the transmitting end serially transmits a data frame containing effective data and checksum to the receiving end through a single signal wire;
the receiving end adds the received effective data and the checksum, and judges whether the calculated result is 0 or not;
and the receiving end sends the effective data or the error report to the data bus according to the judging result to finish the communication between the two nodes.
Further, the transmitting end encodes the data frame by adjusting the duty ratio of the high level and the low level, and the receiving end analyzes the received data frame according to the tolerance range of the duty ratio;
the duty cycle represents: the high state time of the digital signal in the fixed period is a proportion of the total time of the fixed period.
Further, the data frame sent by the sending end is composed of four parts including a synchronizing signal, valid data, a checksum and a stop signal, wherein:
the synchronous signal is positioned at the head of the data frame, and when the synchronous signal is detected by the receiving end, the analysis of the data frame is started;
the stop signal is positioned at the tail part of the data frame, and the analysis of the data frame is ended when the receiving end detects the stop signal.
Further, the receiving end judges according to the obtained comparison result:
if the comparison results are the same, the verification is performed by transmitting valid data into the data bus;
if the comparison results are different, the current data frame is discarded and the error state is transmitted into the data bus after the verification failure.
In a second aspect, the present invention provides an apparatus for implementing communication with a single signal conductor, including:
a transmitting-receiving selector, which configures the current node as a transmitting end to transmit data or as a receiving end to receive data;
the data frame generation module receives and encapsulates the effective data transmitted by the data bus to generate a data frame;
the data frame analysis module is used for receiving and analyzing the data frames transmitted by the single signal line to obtain effective data;
and the bus control module is used for transmitting the effective data transmitted by the data bus to the data frame generation module, or receiving the effective data/error state transmitted by the data frame analysis module and transmitting the effective data/error state to the data bus.
Further, when the current node is used as the transmitting end:
the bus control module receives effective data transmitted by the data bus and transmits the effective data to the data frame generation module;
the data frame generation module adds synchronous information at the head of the effective data, transmits the effective data into the checksum generator to generate a corresponding checksum, adds the checksum to the tail of the effective data, and adds a stop signal at the tail of the checksum to form a data frame;
and sending the data frame to a receiving end through a single signal wire to finish one-time communication.
Further, when the current node is used as the receiving end:
the data frame analysis module receives the data frame transmitted by the single signal line, deserializes the current data frame, and transmits the deserialized effective data, the corresponding data and the data into the checksum verification module;
and if the test is passed, the effective data is transmitted into the data bus through the bus control module, and if the test is not passed, the current data frame is discarded and the error state is transmitted into the data bus.
Further, a pull-up resistor and a pull-down resistor are arranged outside the node, and time-sharing multiplexing is performed through control logic;
enabling a pull-down resistor when the current node is configured as a transmitting end, and setting output as open-drain output;
the pull-up resistor is enabled when the front node is configured as the receiving end and the output is set to a push-pull output.
Compared with the prior art, the method and the device for realizing communication by the single signal wire have the following beneficial effects:
the single signal wire serially transmits data and has an error correction function, so that the data transmission quality is ensured, meanwhile, the data wires are reduced, the data alignment of multi-signal wire communication is not needed to be considered, the resource consumption of SoC design is reduced, the complexity of a hardware system is reduced, the operation efficiency is improved, and the practical use cost is reduced.
Drawings
The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description serve to explain the invention. In the drawings:
fig. 1 is a flow chart of a method for implementing communication by a single signal wire according to an embodiment of the present invention;
fig. 2 is a schematic signal waveform diagram of synchronization information according to an embodiment of the present invention;
FIG. 3 is a schematic diagram of signal waveforms of a logic "1" data bit according to an embodiment of the present invention;
FIG. 4 is a schematic diagram showing waveforms of logic "0" data bits according to an embodiment of the present invention;
FIG. 5 is a schematic diagram of signal waveforms of stop information according to an embodiment of the present invention;
fig. 6 is a schematic structural diagram of a device for implementing communication by using a single signal wire according to an embodiment of the present invention.
Detailed Description
It should be noted that, without conflict, the embodiments of the present invention and features of the embodiments may be combined with each other.
The invention will be described in detail below with reference to the drawings in connection with embodiments.
Embodiment one:
as shown in fig. 1: a method for enabling communication over a single signal conductor, comprising:
two nodes are respectively configured before communication, wherein one node is used as a transmitting end, and the other node is used as a receiving end; under the solicited money without configuration, the node defaults to a sending end;
the transmitting end generates a checksum according to the effective data to be transmitted;
the transmitting end serially transmits a data frame containing effective data and checksum to the receiving end through a single signal wire;
the receiving end adds the received effective data and the checksum, and judges whether the calculated result is 0 or not;
and the receiving end sends the effective data or the error report to the data bus according to the judging result to finish the communication between the two nodes.
The process of obtaining the checksum according to the effective data is as follows: the result of adding the values on each data bit of the valid data is converted into binary system, and the binary system is inverted to obtain a corresponding checksum.
And converting the result obtained by adding the effective data and the corresponding checksum into binary and inverting the binary, if the inverted value is 0, transmitting the effective data to a data bus through verification, and if the inverted value is not 0, transmitting an error report to the data bus without verification.
The transmitting end encodes the data frame by adjusting the duty ratio of the high level and the low level, and the receiving end analyzes the received data frame according to the tolerance range of the duty ratio;
the duty cycle represents: the high state time of the digital signal in the fixed period is a proportion of the total time of the fixed period.
The process of the transmitting end for encoding the data frame by adjusting the duty ratio of the high level and the low level comprises the following steps:
the transmitting end divides the data frame into binary bit streams according to bits, and different duty ratios are used for each binary bit to represent different logic levels;
for example: logic 1 is encoded as a square wave with a high level duty cycle of 75%, and logic 0 is encoded as a square wave with a high level duty cycle of 25%.
The process of analyzing the received data frame by the receiving end according to the tolerance range of the duty ratio comprises the following steps:
the receiving end measures the high level time of each data bit, calculates the duty ratio of each data bit, and judges the logic level of each data bit according to the tolerance range of the duty ratio, for example: the duty ratio is judged to be logic 1 at 70% -80%, and the duty ratio is judged to be logic 0 at 20% -30%; the determined data bits are combined into bytes and parsed in frame format.
The data frame sent by the sending end consists of four parts, namely a synchronizing signal, effective data, a checksum and a stop signal, wherein:
as shown in fig. 2: the synchronous signal is positioned at the head of the data frame and consists of a T1 low level and a T2 high level, the start of one frame of data is represented, the high and low levels of the synchronous signal are far longer than the level duration of a single logic 1 data bit or a logic 0 data bit, so that the error identification data frame of a receiving end is reduced, and the analysis of the data frame is started when the receiving end detects the synchronous signal;
as shown in fig. 3 and 4: the effective data and the checksum form a main message together, the checksum is positioned at the tail part of the effective data, the main message is split into a plurality of logic 1 data bits and logic 0 data bits in a small-end mode, so that the main message is transmitted through a single signal line in series, the high level duration time T4 of the logic 1 data bits is redundant with the low level T3, and the low level duration time T5 of the logic 0 data bits is redundant with the high level T6.
The small end schema (littleen) is a data representation and storage means that represents: a group of low order bytes of data is stored at a starting address, and high order bytes are stored at a higher address; the least significant bits (Least Significant Bit, LSB) of the data are stored in the least significant bits of the least significant byte and the most significant bits (Most Significant Bit, MSB) are stored in the most significant bits of the most significant byte.
As shown in fig. 5: the stop signal is positioned at the tail part of the data frame and consists of a T7 low level and a T8 high level, the transmission is in an idle state and is in a high level, and when the receiving end detects the stop signal, the analysis of the data frame is finished.
The receiving end judges according to the obtained comparison result:
if the comparison results are the same, the verification is performed by transmitting valid data into the data bus;
if the comparison results are different, the current data frame is discarded and the checking error state is transmitted into the data bus.
Embodiment two:
as shown in fig. 6: an apparatus for enabling communication with a single signal conductor, comprising:
a transmitting-receiving selector, which configures the current node as a transmitting end to transmit data or as a receiving end to receive data;
the data frame generation module receives and encapsulates the effective data transmitted by the data bus to generate a data frame;
the data frame analysis module is used for receiving and analyzing the data frames transmitted by the single signal line to obtain effective data;
and the bus control module is used for transmitting the effective data transmitted by the data bus to the data frame generation module, or receiving the effective data or the error state transmitted by the data frame analysis module and transmitting the effective data or the error state to the data bus.
When the current node is used as a transmitting end:
the bus control module receives effective data transmitted by the data bus and transmits the effective data to the data frame generation module;
the data frame generation module adds synchronous information at the head of the effective data, transmits the effective data into the checksum generator to generate a corresponding checksum, adds the checksum to the tail of the effective data, and adds a stop signal at the tail of the checksum to form a data frame;
and sending the data frame to a receiving end through a single signal wire to finish one-time communication.
When the current node is used as a receiving end:
the data frame analysis module receives the data frame transmitted by the single signal wire, deserializes the current data frame, and transmits the deserialized effective data, the corresponding data and the data into the checksum verification module;
and if the test is passed, the effective data is transmitted into the data bus through the bus control module, and if the test is not passed, the current data frame is discarded and the error state is transmitted into the data bus.
The data frame deserializing refers to a process that a receiving end analyzes and converts a data frame transmitted in series, and recovers the serial data into parallel data, and the data frame deserializing method comprises the following steps:
timing sampling is carried out on the received serial bit stream, and the complete digital waveform is restored;
analyzing data bits from the waveform, and detecting logic 0 or logic 1 of each data bit;
recombining the resolved binary bits into bytes or code groups;
identifying information such as a synchronous head, a data field, a check code and the like according to the data frame format;
and extracting the byte sequence in the data domain to obtain the original parallel data of the transmission.
A pull-up resistor and a pull-down resistor are arranged outside the node, and time-sharing multiplexing is performed through control logic;
enabling a pull-down resistor when the current node is configured as a transmitting end, and setting output as open-drain output;
the pull-up resistor is enabled when the front node is configured as the receiving end and the output is set to a push-pull output.
The output of the transmitting end is set as open-drain output and connected with a pull-down resistor to be low level, and when no receiving end is connected, the node enters a dormant power-saving state;
enabling an internal pull-up resistor to a high level when a receiving end is accessed, and waking up a node by the pull-up resistor of the receiving end to start communication;
after the transmitting end detects the level change of the receiving end, the receiving end is informed of being connected with the starting communication protocol, the receiving end is disconnected after the communication is completed, and the level of the transmitting end is pulled down again to enter a dormant power saving state.
Those of ordinary skill in the art will appreciate that the elements and method steps of each example described in connection with the embodiments disclosed herein may be implemented as electronic hardware, computer software, or combinations of both, and that the elements and steps of each example have been described generally in terms of functionality in the foregoing description to clearly illustrate this interchangeability of hardware and software. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the solution. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present invention.
In the several embodiments provided in this application, it should be understood that the disclosed methods and systems may be implemented in other ways. For example, the above-described division of units is merely a logical function division, and there may be another division manner when actually implemented, for example, a plurality of units or components may be combined or may be integrated into another system, or some features may be omitted or not performed. The units may or may not be physically separate, and components shown as units may or may not be physical units, may be located in one place, or may be distributed over a plurality of network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the embodiment of the present invention.
Finally, it should be noted that: the above embodiments are only for illustrating the technical solution of the present invention, and not for limiting the same; although the invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments can be modified or some or all of the technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit of the invention, and are intended to be included within the scope of the appended claims and description.
The foregoing description of the preferred embodiments of the invention is not intended to be limiting, but rather is intended to cover all modifications, equivalents, alternatives, and improvements that fall within the spirit and scope of the invention.
Claims (8)
1. A method for enabling communication over a single signal conductor, comprising:
two nodes are respectively configured before communication, wherein one node is used as a transmitting end, and the other node is used as a receiving end;
the transmitting end generates a checksum according to the effective data to be transmitted;
the transmitting end serially transmits a data frame containing effective data and checksum to the receiving end through a single signal wire;
the receiving end adds the received effective data and the checksum, and judges whether the calculated result is 0 or not;
and the receiving end sends the effective data or the error report to the data bus according to the judging result to finish the communication between the two nodes.
2. A method of enabling communications over a single signal conductor as claimed in claim 1, wherein:
the transmitting end encodes the data frame by adjusting the duty ratio of the high level and the low level, and the receiving end analyzes the received data frame according to the tolerance range of the duty ratio;
the duty cycle represents: the high state time of the digital signal in the fixed period is a proportion of the total time of the fixed period.
3. A method of enabling communications over a single signal conductor as claimed in claim 1, wherein:
the data frame sent by the sending end consists of four parts, namely a synchronizing signal, effective data, a checksum and a stop signal, wherein:
the synchronous signal is positioned at the head of the data frame, and when the synchronous signal is detected by the receiving end, the analysis of the data frame is started;
the stop signal is positioned at the tail part of the data frame, and the analysis of the data frame is ended when the receiving end detects the stop signal.
4. A method of enabling communications over a single signal conductor as claimed in claim 1, wherein:
the receiving end judges according to the obtained comparison result:
if the comparison results are the same, the verification is performed by transmitting valid data into the data bus;
if the comparison results are different, the current data frame is discarded and the error state is transmitted into the data bus after the verification failure.
5. An apparatus for effecting communication over a single signal conductor, comprising:
a transmitting-receiving selector, which configures the current node as a transmitting end to transmit data or as a receiving end to receive data;
the data frame generation module receives and encapsulates the effective data transmitted by the data bus to generate a data frame;
the data frame analysis module is used for receiving and analyzing the data frames transmitted by the single signal line to obtain effective data;
and the bus control module is used for transmitting the effective data transmitted by the data bus to the data frame generation module, or receiving the effective data/error state transmitted by the data frame analysis module and transmitting the effective data/error state to the data bus.
6. The apparatus for effecting communication with a single signal conductor of claim 5 wherein:
when the current node is used as a transmitting end:
the bus control module receives effective data transmitted by the data bus and transmits the effective data to the data frame generation module;
the data frame generation module adds synchronous information at the head of the effective data, transmits the effective data into the checksum generator to generate a corresponding checksum, adds the checksum to the tail of the effective data, and adds a stop signal at the tail of the checksum to form a data frame;
and sending the data frame to a receiving end through a single signal wire to finish one-time communication.
7. The apparatus for effecting communication with a single signal conductor of claim 6 wherein:
when the current node is used as a receiving end:
the data frame analysis module receives the data frame transmitted by the single signal line, deserializes the current data frame, and transmits the deserialized effective data, the corresponding data and the data into the checksum verification module;
and if the test is passed, the effective data is transmitted into the data bus through the bus control module, and if the test is not passed, the current data frame is discarded and the error state is transmitted into the data bus.
8. The apparatus for effecting communication with a single signal conductor of claim 5 wherein:
a pull-up resistor and a pull-down resistor are arranged outside the node, and time-sharing multiplexing is performed through control logic;
enabling a pull-down resistor when the current node is configured as a transmitting end, and setting output as open-drain output;
the pull-up resistor is enabled when the front node is configured as the receiving end and the output is set to a push-pull output.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202311210158.7A CN117254888A (en) | 2023-09-19 | 2023-09-19 | Method and device for realizing communication by single signal wire |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202311210158.7A CN117254888A (en) | 2023-09-19 | 2023-09-19 | Method and device for realizing communication by single signal wire |
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| CN117254888A true CN117254888A (en) | 2023-12-19 |
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| CN202311210158.7A Pending CN117254888A (en) | 2023-09-19 | 2023-09-19 | Method and device for realizing communication by single signal wire |
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