CN117254872A

CN117254872A - Method, system, equipment and storage medium for acquiring high-precision time stamp

Info

Publication number: CN117254872A
Application number: CN202311534276.3A
Authority: CN
Inventors: 沈文博
Original assignee: Jiangsu Xinertai Intelligent Equipment Co ltd
Current assignee: Jiangsu Xinertai Intelligent Equipment Co ltd
Priority date: 2023-11-17
Filing date: 2023-11-17
Publication date: 2023-12-19
Anticipated expiration: 2043-11-17
Also published as: CN117254872B

Abstract

The embodiment of the invention provides a method, a system, equipment and a storage medium for acquiring a high-precision time stamp. The method comprises the following steps: 4 paths of time stamps are generated by adopting a 400M clock, and different-frequency sampling is performed by adopting a 350M clock; adding Gray codes to the codes of the 4 paths of time stamps to obtain Gray code codes; a time stamp is determined by the gray code encoding. According to the invention, under the application scene of realizing high-precision time stamp by using FPGA, based on the idea of multi-phase sampling, the time stamp precision lower than 1ns is realized by adding various new methods such as different-frequency multi-phase sampling, gray time stamp coding, sampling data correction and the like, and the currently commonly adopted 2.5ns time stamp precision is improved by 4 times or more.

Description

Method, system, equipment and storage medium for acquiring high-precision time stamp

Technical Field

Embodiments of the present invention relate to the field of computer systems, and more particularly, to a method, a system, a device, and a storage medium for obtaining a high-precision timestamp.

Background

This section is intended to provide a background or context to the embodiments of the invention that are recited in the claims. The description herein is not admitted to be prior art by inclusion in this section.

Latency is an important parameter for network testing, and a time stamp (timestamp) mechanism is one of the key elements of time synchronization and latency testing. Fig. 1 shows a common example flow of latency testing. The sender and the receiver both adopt 400M clocks to generate time stamps, the time stamp precision corresponds to 2.5ns, and the network packet sending logic of the FPGA operates at 350MHz, so in order to solve the problem of clock domain crossing, the time stamp generated by the 400M clocks passes through an asynchronous FIFO and is used by the sending logic of 350M. When each network packet is transmitted, the corresponding time stamp is taken out and embedded into the network packet, at the receiving end, the receiving logic takes out the time stamp t1 at the transmitting time, then the time t2 at the packet receiving time is obtained, and the delay of the network packet can be obtained through t2-t 1. It is apparent that the accuracy of the delay test depends on the accuracy of the time stamp.

With the advent of the 5G age and the advent of higher rate ethernet technologies, such as 400GE/800GE network technologies, the accuracy of time stamping is increasingly required. The requirement of the 5G communication device for time synchronization bias between network elements is 5ns. While the time required for 800GE to send a 64 byte network frame is 0.84ns, a time stamp less than 0.84ns is theoretically required to distinguish the delay difference between two different network packets.

The following three methods are commonly used to improve the accuracy of the time stamp:

firstly, the frequency of a clock used for generating the time stamp is increased, for example, for a 1000M network, the time stamp is generated by adopting a 125M clock, and the precision of 8ns is correspondingly increased; when the network speed comes to 100G, a 400M clock is commonly used to generate a timestamp, corresponding to a timestamp accuracy of 2.5 ns. In the current implementation scheme adopting hardware to precisely test time delay, the FPGA is an important device. Because of the process and device characteristics of the FPGA, the running frequency of the internal logic is much lower than that of a CPU, and the clock with the frequency of more than 500MHz is very difficult or impossible to realize, and when the time stamp with the frequency of less than 1ns is needed to be realized, the clock with the frequency of 1GHz is corresponding, and the method is not feasible to realize directly in the scene of the FPGA.

The second method is multiphase sampling, and the patent document CN112953669 mentions that the invention discloses a method and a system for improving the precision of a time stamp, and relates to the field of time synchronization; the rising edge position of the frame positioning identification signal is obtained through a LVDS SERDES interface, a real-time sampling indication signal is generated at the same time, and the current real-time is taken as an initial time stamp T; generating a sampling error compensation value delta t1 based on a non-zero sampling value corresponding to the real-time sampling indication signal; and obtaining the current oversampling state based on the statistical result, wherein different oversampling states correspond to different oversampling error compensation values Deltat 2, and the final timestamp is equal to the sum of the initial timestamp T, the sampling error compensation value Deltat 1 and the oversampling error compensation value Deltat 2. The invention has simple implementation and lower time sequence requirement on the FPGA device. In the method, the clock and data wiring is not easy to accurately control in the FPGA, so that the error is large, and the specific implementation effect is not ideal. If there is no ingenious mechanism, the multi-phase sampling does have the problems that the wiring of the data and the clock is not easy to control, sampling errors occur, and the like, and the compensation method mentioned in the application cannot directly improve the precision of the time stamp, but only reduces the error value of the time stamp.

Disclosure of Invention

In this context, embodiments of the present invention desire to provide a method, a system, an apparatus, and a storage medium for obtaining a high-precision timestamp.

In a first aspect of the embodiment of the present invention, there is provided a method for obtaining a high-precision timestamp, including:

4 paths of time stamps are generated by adopting a 400M clock, and different-frequency sampling is performed by adopting a 350M clock;

adding Gray codes to the codes of the 4 paths of time stamps to obtain Gray code codes;

a time stamp is determined by the gray code encoding.

In one example of this implementation, the generating the 4-way timestamp using the 400M clock includes:

generating 4 reference clocks with different phases of a 400M clock through a phase-locked loop (PLL) of an FPGA, wherein the phases are respectively deviated by 0 degree, 90 degrees, 180 degrees and 270 degrees;

the four reference clocks respectively drive the four binary counters to generate four time stamps, the resolution of each time stamp is 2.5ns, and the phases are correspondingly different from 0 degree, 90 degrees, 180 degrees and 270 degrees.

In an embodiment of the present invention, the adding a gray code to the 4-way timestamp code to obtain a gray code includes:

and adding a Gray code to the codes of the 4 paths of time stamps to obtain Gray code codes corresponding to the 4 paths of time stamps.

In an example of this implementation, the determining the timestamp by the gray code includes:

determining Gray code corresponding to the current time stamp by four paths of Gray code codes;

and the Gray code codes are converted into a current time stamp.

In an example of this embodiment, the determining, by four-way gray code, the gray code corresponding to the current timestamp includes:

when the four-way Gray code is coded as N ', N-1', N-1', N-1', the current timestamp is (N-1 ');

when the four-way Gray code is coded as N ', N ', N-1', N-1', then the current timestamp is (N-1 ' +1/4);

when the four-way Gray code is coded as N ', N ', N ', N-1', then the current timestamp is (N-1 ' +1/2);

when the four-way gray code is encoded as N ', then the current timestamp is (N-1' +3/4).

In a second aspect of the embodiments of the present invention, there is provided a high-precision time stamp obtaining system, including:

the sampling module is used for generating 4 paths of time stamps by adopting a 400M clock and performing different-frequency sampling by adopting a 350M clock;

the correction module is used for adding Gray codes to the codes of the 4 paths of time stamps to obtain Gray code codes;

and the time stamp determining module is used for determining a time stamp by the Gray code.

In one example of this implementation manner, the generating 4-way timestamp using 400M clock in the sampling module includes the following specific implementation steps:

In one example of this embodiment, the correction module is specifically configured to:

In one example of this implementation, the timestamp determination module includes:

the preliminary determination submodule is used for determining the Gray code corresponding to the current time stamp by four paths of Gray code codes;

and the conversion sub-module is used for being coded and converted into the current time stamp by the Gray code.

In one example of this implementation, the preliminary determination submodule is specifically configured to:

In a third aspect of embodiments of the present invention, there is provided a computing device comprising: at least one processor, memory, and input output unit; wherein the memory is for storing a computer program and the processor is for invoking the computer program stored in the memory to perform the method of any of the first aspects.

In a fourth aspect of the embodiments of the present invention, there is provided a computer readable storage medium comprising instructions which, when run on a computer, cause the computer to perform the method of any of the first aspects.

According to the method, the system, the equipment and the storage medium for acquiring the high-precision time stamp, based on the idea of multi-phase sampling in the application scene of realizing the high-precision time stamp by using the FPGA, the time stamp precision lower than 1ns is realized by adding various new methods such as different-frequency multi-phase sampling, gray time stamp coding, sampling data correction and the like, and the currently commonly adopted 2.5ns time stamp precision is improved by 4 times or more.

Drawings

The above, as well as additional purposes, features, and advantages of exemplary embodiments of the present invention will become readily apparent from the following detailed description when read in conjunction with the accompanying drawings. Several embodiments of the present invention are illustrated by way of example, and not by way of limitation, in the figures of the accompanying drawings and in which:

FIG. 1 is a functional diagram of a prior art test network packet delay;

FIG. 2 is a flow chart of a method for obtaining a high-precision time stamp according to the present invention;

FIG. 3 is a schematic diagram of a prior art multi-phase sampling;

FIG. 4 is a method for obtaining a time stamp of a transmitting direction in a conventional method in the prior art;

fig. 5 is a schematic diagram of an application scenario of a method for acquiring a timestamp from a sending direction according to an embodiment of the present invention;

FIG. 6 is a schematic diagram of setup time/hold time according to an embodiment of the present invention;

FIG. 7 is a schematic diagram illustrating sampling at a variation boundary of Gray code data according to an embodiment of the present invention;

FIG. 8 schematically illustrates a schematic structural diagram of a medium according to an embodiment of the present invention;

FIG. 9 schematically illustrates a structural diagram of a computing device in accordance with embodiments of the present invention.

Detailed Description

The principles and spirit of the present invention will be described below with reference to several exemplary embodiments. It should be understood that these embodiments are presented merely to enable those skilled in the art to better understand and practice the invention and are not intended to limit the scope of the invention in any way. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.

Those skilled in the art will appreciate that embodiments of the invention may be implemented as a system, apparatus, device, method, or computer program product. Accordingly, the present disclosure may be embodied in the following forms, namely: complete hardware, complete software (including firmware, resident software, micro-code, etc.), or a combination of hardware and software.

According to the embodiment of the invention, a method, a system, equipment and a storage medium for acquiring a high-precision time stamp are provided.

It should be noted that any number of elements in the figures are for illustration and not limitation, and that any naming is used for distinction only and not for limitation.

The principles and spirit of the present invention are explained in detail below with reference to several representative embodiments thereof.

Referring to fig. 2, fig. 2 is a flowchart of a method for obtaining a high-precision timestamp according to an embodiment of the present invention. It should be noted that embodiments of the present invention may be applied to any scenario where applicable.

The invention aims to realize the time stamp precision lower than 1ns by adding various new methods such as different-frequency multi-phase sampling, gray time stamp coding, sampling data correction and the like based on the idea of multi-phase sampling under the application scene of realizing high-precision time stamps by using an FPGA, and improve the currently commonly adopted 2.5ns time stamp precision by 4 times or more.

Fig. 2 shows a flow of a method for obtaining a high-precision timestamp according to an embodiment of the present invention, including:

step S101, 4 paths of time stamps are generated by adopting a 400M clock, and different-frequency sampling is performed by adopting a 350M clock;

step S102, adding Gray codes to codes of the 4 paths of time stamps to obtain Gray code codes;

step S103, determining a time stamp by the gray code.

It will be understood that all of the parameters set forth in the following examples are illustrative, and that the present invention is not limited to any particular parameter, and that modifications and variations may be made by those skilled in the art without departing from the principles of the invention, and are to be considered as being within the scope of the invention.

As shown in fig. 3, the reference clock is generated by a low frequency high precision clock source, such as a high precision crystal oscillator. The reference clock generates 4 different phase versions of the 400M clock by the phase-locked loop PLL of the FPGA, with the phases being offset by 0, 90, 180 and 270 degrees, respectively.

The four clocks drive four binary counters, respectively, to produce four time stamps, each with a resolution of 2.5ns, and the phases are correspondingly different by 0 degrees, 90 degrees, 180 degrees and 270 degrees.

To this end, we analyze the related circuitry that generates the time stamps in the conventional method in connection with fig. 4. Assuming that the time-stamped packet transmission logic operates at 350M clock, it is common practice to generate a counter value (time stamp) per cycle in the 400M clock domain and write this value to the asynchronous FIFO, and the 350M clock reads one data from the FIFO per cycle, if there is a packet transmission, embed the time stamp into the packet, and throw it away if no packet is transmitted. Since the write is 400M, the read is 350M, and the rate mismatch necessarily results in FIFO fullness at some point resulting in lost data, and as a result there is no loss of value for individual time stamps, affecting test accuracy with a small probability, but not accuracy.

Step S101, adopting 400M clock to generate 4 paths of time stamps, and adopting 350M clock to perform inter-frequency sampling, specifically comprising the following steps:

as shown in fig. 5, the present invention still generates a 4-way timestamp with four versions of the 400M clock, but the sampling clock is replaced with a 350M clock that takes the clock domain where the logic is located. This can eliminate one FIFO. This is inter-frequency sampling. The sampled signal is a random signal with respect to the 400M time stamped signal.

In most cases, the time stamp signal has sufficient setup and hold time relative to the sampled signal that there is no data sampling error, and the time stamp can be determined by:

if the four sample values are N, N-1, then the current timestamp is (N-1);

if the four sample values are N, N, N-1, then the current timestamp is (N-1+1/4);

if the four sample values are N, N, N, N-1, then the current timestamp is (N-1+1/2);

(4) if the four sample values are N, N, N, N, then the current timestamp is (N-1+3/4).

Step S102, adding Gray codes to the codes of the 4 paths of time stamps to obtain Gray code codes, wherein the method specifically comprises the following steps:

in another embodiment of the present invention, gray coding and sampling data correction are used to accurately obtain a high-precision time stamp, so that the problem that the 350M sampling clock and the 400M clock generating the time stamp are different clock domains and the possibility of sampling errors across the Clock Domains (CDC) exists because of the classical setup time/hold time problem in digital circuit design is solved. As shown in fig. 6, to ensure that the sampled data is correct, the data must be stable long enough, i.e., at least t (setup), when the sampled signal arrives, and at least t (hold) when the sampling is completed.

For a 400M clock that generates a timestamp, the sampled 350M clock is an asynchronous clock and can be considered a random signal. This signal is entirely likely to occur at the boundary of the binary time stamp signal change, thus violating the setup and hold times, resulting in sampling errors in the multi-bit signal, resulting in erroneous time values.

Gray codes in digital circuits have a good property of only one bit being in error between adjacent counts. We can add a gray code conversion to the encoding of the time stamp to avoid multi-bit simultaneous switching. For distinction, the timestamp count is marked with an apostrophe in fig. 6, indicating the count of gray codes.

Step S103, determining a timestamp by the gray code, specifically including:

and the Gray code codes are converted into a current time stamp.

Of course, gray code is only convenient in digital implementation, and gray code needs to be converted back into binary system for operation when the time delay is actually calculated. In another embodiment of the present invention, in order to verify the accuracy of the technical solution of the present invention, the following description is presented with reference to an example, as shown in fig. 7:

the sampling pulse is located exactly at the boundary where the first time stamp changes from N-1 'to N', at which time the second three-four time stamp meets the setup time and the hold time. The first path of time stamp may be misplaced due to setup/hold time, and the second, third and fourth paths may not be misplaced. However, due to the nature of Gray codes, the possible sample values can only be of two sets, namely (N-1 ', N-1', N-1', N-1') and (N ', N-1', N-1', N-1').

We analyze the pattern of data errors and the correction method as follows.

Assuming that the sampling pulse is to the left of the first dashed line in fig. 6 and the sampling value is (N-1' ), there is no error at this time;

it is assumed that the sampling pulse is to the left of the first dashed line in fig. 6, and the sampling value is (N ', N-1'), which does not occur;

an error occurs at this time, assuming that the sampling pulse is to the right of the first dashed line in fig. 6 and the sampling value is (N-1' ). The true value is (N-1 '+0) and the timestamp from the sample is (N-2' +3/4), the error value is 1/4 clock cycles, and the measured value is less than the true value.

Assuming that the sampling pulse is to the right of the first dashed line in fig. 6 and the sampling value is (N ', N-1'), this case is error free;

that is, on average, only one error occurs in four cases, the error value is 1/4, so the statistically error value is 1/16 clock cycle.

Under the current process conditions, the setup time and hold time of the FPGA are very small relative toFor one period of the timestamp, assuming that its duty cycle is p, the probability of true error is* And p. If p isThen the probability of true error is only. This is a fairly low probability and the correction method can add to the final delay statisticNo software correction is made for a clock cycle, or to tolerate such small errors.

Having described the method of an exemplary embodiment of the present invention, a high accuracy timestamp acquisition system of an exemplary embodiment of the present invention is described next with reference to fig. 5, comprising:

As an alternative implementation manner, the 4-way timestamp generated by using the 400M clock in the sampling module comprises the following specific implementation steps:

As an alternative embodiment, the correction module is specifically configured to:

As an alternative embodiment, the timestamp determining module includes:

Having described the method and apparatus of the exemplary embodiments of the present invention, reference is next made to fig. 8 for a description of a computer readable storage medium of the exemplary embodiments of the present invention, and reference is made to fig. 8 for a description of a computer readable storage medium, an optical disc 80, having a computer program (i.e., a program product) stored thereon that, when executed by a processor, implements the steps described in the above method embodiments, for example, generating a 4-way timestamp using a 400M clock and performing an inter-frequency sampling using a 350M clock; adding Gray codes to the codes of the 4 paths of time stamps to obtain Gray code codes; determining a time stamp from the gray code; the specific implementation of each step is not repeated here.

It should be noted that examples of the computer readable storage medium may also include, but are not limited to, a phase change memory (PRAM), a Static Random Access Memory (SRAM), a Dynamic Random Access Memory (DRAM), other types of Random Access Memory (RAM), a Read Only Memory (ROM), an Electrically Erasable Programmable Read Only Memory (EEPROM), a flash memory, or other optical or magnetic storage medium, which will not be described in detail herein.

Having described the methods, apparatus and media of exemplary embodiments of the present invention, next, a computing device for processing the acquisition method of high precision time stamps of exemplary embodiments of the present invention is described with reference to fig. 9.

FIG. 9 illustrates a block diagram of an exemplary computing device 90 suitable for use in implementing embodiments of the invention, the computing device 90 may be a computer system or a server. The computing device 90 shown in fig. 9 is merely an example and should not be taken as limiting the functionality and scope of use of embodiments of the present invention.

As shown in fig. 9, components of computing device 90 may include, but are not limited to: one or more processors or processing units 901, a system memory 902, a bus 903 that connects the various system components (including the system memory 902 and the processing units 901).

Computing device 90 typically includes a variety of computer system readable media. Such media can be any available media that is accessible by computing device 90 and includes both volatile and nonvolatile media, removable and non-removable media.

The system memory 902 may include computer system readable media in the form of volatile memory, such as Random Access Memory (RAM) 9021 and/or cache memory 9022. Computing device 90 may further include other removable/non-removable, volatile/nonvolatile computer system storage media. By way of example only, ROM9023 may be used to read from or write to non-removable, nonvolatile magnetic media (not shown in FIG. 9, commonly referred to as a "hard disk drive"). Although not shown in fig. 9, a magnetic disk drive for reading from and writing to a removable non-volatile magnetic disk (e.g., a "floppy disk"), and an optical disk drive for reading from or writing to a removable non-volatile optical disk (e.g., a CD-ROM, DVD-ROM, or other optical media), may be provided. In such cases, each drive may be coupled to bus 903 via one or more data media interfaces. The system memory 902 may include at least one program product having a set (e.g., at least one) of program modules configured to carry out the functions of the embodiments of the invention.

A program/utility 9025 having a set (at least one) of program modules 9024 may be stored, for example, in system memory 902, and such program modules 9024 include, but are not limited to: an operating system, one or more application programs, other program modules, and program data, each or some combination of which may include an implementation of a network environment. Program modules 9024 generally perform the functions and/or methods of the described embodiments of the invention.

The computing device 90 may also communicate with one or more external devices 904 (e.g., keyboard, pointing device, display, etc.). Such communication may occur through an input/output (I/O) interface 905. Moreover, the computing device 90 may also communicate with one or more networks such as a Local Area Network (LAN), a Wide Area Network (WAN) and/or a public network, such as the Internet, through the network adapter 906. As shown in fig. 9, the network adapter 906 communicates with other modules of the computing device 90 (e.g., processing unit 901, etc.) over bus 903. It should be appreciated that although not shown in fig. 9, other hardware and/or software modules may be used in connection with computing device 90.

The processing unit 901 performs various functional applications and data processing by running a program stored in the system memory 902, for example, generating 4-way time stamps using a 400M clock and performing inter-frequency sampling using a 350M clock; adding Gray codes to the codes of the 4 paths of time stamps to obtain Gray code codes; a time stamp is determined by the gray code encoding. The specific implementation of each step is not repeated here. It should be noted that although in the above detailed description a number of units/modules or sub-units/sub-modules of the high precision time stamp acquisition method processing apparatus are mentioned, such a division is merely exemplary and not mandatory. Indeed, the features and functionality of two or more units/modules described above may be embodied in one unit/module in accordance with embodiments of the present invention. Conversely, the features and functions of one unit/module described above may be further divided into ones that are embodied by a plurality of units/modules.

In the description of the present invention, it should be noted that the terms "first," "second," and "third" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.

It will be clear to those skilled in the art that, for convenience and brevity of description, specific working procedures of the above-described systems, apparatuses and units may refer to corresponding procedures in the foregoing method embodiments, and are not repeated herein.

In the several embodiments provided by the present invention, it should be understood that the disclosed systems, devices, and methods may be implemented in other manners. The above-described apparatus embodiments are merely illustrative, for example, the division of the units is merely a logical function division, and there may be other manners of division in actual implementation, and for example, multiple units or components may be combined or integrated into another system, or some features may be omitted, or not performed. Alternatively, the coupling or direct coupling or communication connection shown or discussed with each other may be through some communication interface, device or unit indirect coupling or communication connection, which may be in electrical, mechanical or other form.

The units described as separate units may or may not be physically separate, and units shown as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

In addition, each functional unit in the embodiments of the present invention may be integrated in one processing unit, or each unit may exist alone physically, or two or more units may be integrated in one unit.

The functions, if implemented in the form of software functional units and sold or used as a stand-alone product, may be stored in a non-volatile computer readable storage medium executable by a processor. Based on this understanding, the technical solution of the present invention may be embodied essentially or in a part contributing to the prior art or in a part of the technical solution, in the form of a software product stored in a storage medium, comprising several instructions for causing a computer device (which may be a personal computer, a server, a network device, etc.) to perform all or part of the steps of the method according to the embodiments of the present invention. And the aforementioned storage medium includes: a U-disk, a removable hard disk, a Read-Only Memory (ROM), a random access Memory (RAM, random Access Memory), a magnetic disk, or an optical disk, or other various media capable of storing program codes.

Finally, it should be noted that: the above examples are only specific embodiments of the present invention, and are not intended to limit the scope of the present invention, but it should be understood by those skilled in the art that the present invention is not limited thereto, and that the present invention is described in detail with reference to the foregoing examples: any person skilled in the art may modify or easily conceive of the technical solution described in the foregoing embodiments, or perform equivalent substitution of some of the technical features, while remaining within the technical scope of the present disclosure; such modifications, changes or substitutions do not depart from the spirit and scope of the technical solutions of the embodiments of the present invention, and are intended to be included in the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.

Furthermore, although the operations of the methods of the present invention are depicted in the drawings in a particular order, this is not required to either imply that the operations must be performed in that particular order or that all of the illustrated operations be performed to achieve desirable results. Additionally or alternatively, certain steps may be omitted, multiple steps combined into one step to perform, and/or one step decomposed into multiple steps to perform.

Claims

1. A method for obtaining a high-precision timestamp, comprising:

a time stamp is determined by the gray code encoding.

2. The method for obtaining a high-precision time stamp according to claim 1, wherein the generating the 4-way time stamp using the 400M clock comprises:

3. The method for obtaining the high-precision time stamp according to claim 1, wherein the adding gray codes to the 4-way time stamp codes to obtain gray code codes comprises:

4. The method of obtaining a high precision time stamp according to claim 1, wherein the determining a time stamp from the gray code comprises:

and the Gray code codes are converted into a current time stamp.

5. The method for obtaining the high-precision time stamp according to claim 4, wherein determining the gray code corresponding to the current time stamp from four-way gray code codes comprises:

6. A high precision time stamp acquisition system, comprising:

7. The system for obtaining high-precision time stamps according to claim 6, wherein the generating 4-way time stamps using 400M clock in the sampling module comprises:

8. A computing device, the computing device comprising:

at least one processor, memory, and input output unit;

the memory is used for storing a computer program, and the processor is used for calling the computer program stored in the memory to execute the method for acquiring the high-precision time stamp according to any one of claims 1-5.

9. A computer readable storage medium comprising instructions which, when run on a computer, cause the computer to perform a method of obtaining a high precision timestamp according to any one of claims 1 to 5.