CN117253957A - Passivation film and method for improving reliability of flip chip - Google Patents
Passivation film and method for improving reliability of flip chip Download PDFInfo
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- CN117253957A CN117253957A CN202311497204.6A CN202311497204A CN117253957A CN 117253957 A CN117253957 A CN 117253957A CN 202311497204 A CN202311497204 A CN 202311497204A CN 117253957 A CN117253957 A CN 117253957A
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- dielectric layer
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- passivation film
- chip
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- 238000002161 passivation Methods 0.000 title claims abstract description 34
- 238000000034 method Methods 0.000 title claims abstract description 13
- 238000007788 roughening Methods 0.000 claims abstract description 28
- 238000000151 deposition Methods 0.000 claims abstract description 8
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 claims description 20
- 229910052751 metal Inorganic materials 0.000 claims description 20
- 239000002184 metal Substances 0.000 claims description 20
- 238000005530 etching Methods 0.000 claims description 10
- 229920002120 photoresistant polymer Polymers 0.000 claims description 9
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 5
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 5
- 238000001312 dry etching Methods 0.000 claims description 5
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 claims description 5
- RVTZCBVAJQQJTK-UHFFFAOYSA-N oxygen(2-);zirconium(4+) Chemical compound [O-2].[O-2].[Zr+4] RVTZCBVAJQQJTK-UHFFFAOYSA-N 0.000 claims description 5
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 5
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 5
- 238000001039 wet etching Methods 0.000 claims description 5
- 229910001928 zirconium oxide Inorganic materials 0.000 claims description 5
- 230000007797 corrosion Effects 0.000 claims description 4
- 238000005260 corrosion Methods 0.000 claims description 4
- 239000011248 coating agent Substances 0.000 claims description 3
- 238000000576 coating method Methods 0.000 claims description 3
- 238000003795 desorption Methods 0.000 abstract 1
- 230000005012 migration Effects 0.000 description 3
- 238000013508 migration Methods 0.000 description 3
- 230000007547 defect Effects 0.000 description 2
- 150000002500 ions Chemical class 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 238000002360 preparation method Methods 0.000 description 2
- 150000001875 compounds Chemical class 0.000 description 1
- 230000001276 controlling effect Effects 0.000 description 1
- 238000005336 cracking Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 229910052736 halogen Inorganic materials 0.000 description 1
- 150000002367 halogens Chemical class 0.000 description 1
- 238000005286 illumination Methods 0.000 description 1
- 238000001459 lithography Methods 0.000 description 1
- 229910021645 metal ion Inorganic materials 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 238000005192 partition Methods 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 230000001105 regulatory effect Effects 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 238000004901 spalling Methods 0.000 description 1
- 238000000992 sputter etching Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 238000002834 transmittance Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/44—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the coatings, e.g. passivation layer or anti-reflective coating
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2933/00—Details relating to devices covered by the group H01L33/00 but not provided for in its subgroups
- H01L2933/0008—Processes
- H01L2933/0025—Processes relating to coatings
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- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Formation Of Insulating Films (AREA)
Abstract
According to the passivation film and the passivation film method for improving the reliability of the flip chip, a second medium layer with lower density is deposited on a first medium layer with higher density, wherein the first medium layer with higher density is reserved in the step position area of the chip, and the first medium layers in other areas are manufactured into micro-coarsening structures; according to the passivation film prepared by depositing two dielectric layers with different densities and selectively micro-roughening the first dielectric layer with higher density, the adhesion of the dielectric film of the passivation layer is improved, the stress of the passivation film is reduced, the problems of microcrack, micro-defect, film desorption and the like caused by large stress are avoided, the electromigration problem of the step position is solved, and the reliability of the chip is improved.
Description
Technical Field
The invention relates to the field of chip packaging, in particular to a passivation film for improving the reliability of a flip chip.
Background
With the wider application of flip LED chips in the fields of high light efficiency, high-power illumination and Mini/Micro LED display, higher requirements are put forward on the reliability and yield of flip LEDs, and especially in the field of Micro display, the scene of ppm level failure rate is required to be achieved. Among these, electromigration is a major reliability problem affecting interconnect leads, where the geometry and shape of the leads, the grain structure within the interconnect leads, etc. have a significant impact on electromigration. In particular, the step coverage of the chip is poor in the unlimited forming process, the thickness is reduced, the current density is increased at the step, and the chip is more likely to be broken, so that the reliability of the chip is poor.
A passivation layer is covered above the metal film, so that the probability of movement of metal ions from the inside to the surface can be reduced, and surface diffusion is restrained, but the existing passivation layer is insufficient in density, and the problems of film spalling and the like easily occur due to high stress of the high-density film.
Disclosure of Invention
In order to solve the above problems, the present invention proposes a passivation film for improving the reliability of a flip chip.
The main content of the invention comprises:
a passivation film for improving reliability of flip chip comprises a first area and a second area, wherein the first area is a corresponding area of a chip step position, and the rest areas are the second area; the first area and the second area comprise a first dielectric layer deposited on the chip metal film and a second dielectric layer deposited on the first dielectric layer; the density of the first medium layer is greater than that of the second medium layer; a micro-roughening structure is formed on one surface of the first dielectric layer of the second region facing the second dielectric layer, and the first dielectric layer of the first region is not roughened.
Preferably, the hydrofluoric acid corrosion rate of the first dielectric layer is 1-10 mu m/min; the hydrofluoric acid corrosion rate of the second dielectric layer is 20-50 mu m/min.
Preferably, the ratio of the thickness of the second dielectric layer to the thickness of the first dielectric layer is greater than 1 and less than 10.
Preferably, the thickness of the first dielectric layer in the second region after forming the micro-roughening structure is not less than 10-100nm.
Preferably, the micro-roughening structure is formed by wet etching or dry etching.
Preferably, the material of the first dielectric layer and the second dielectric layer is one or more of silicon oxide, aluminum oxide, silicon nitride and zirconium oxide.
The invention also provides a method for improving the reliability of the flip chip, which comprises the following steps:
s1, depositing a first dielectric layer on a metal film of a chip;
s2, etching a micro-roughening structure on the first dielectric layer of the first area; the first area is a corresponding area of the chip step position;
s3, depositing a second dielectric layer on the first dielectric layer;
wherein the density of the first medium layer is greater than that of the second medium layer; and the ratio of the thickness of the second dielectric layer to the thickness of the first dielectric layer is greater than 1 and less than 10.
Preferably, the specific steps in step S2 include:
s21, coating photoresist on the first dielectric layer;
s22, perforating the photoresist of the first dielectric layer of the second area according to a set pattern;
s23, etching the first dielectric layer by wet etching or dry etching to obtain the micro-roughening structure.
Preferably, the roughness of the micro-coarsening structure is 50-300nm; the pure hydrofluoric acid rate of the first dielectric layer is 1-10 mu m/min; the pure hydrofluoric acid rate of the second dielectric layer is 20-50 mu m/min; and the thickness of the first dielectric layer in the second area, which remains after the micro-roughening structure is formed, is not less than 10-100nm.
Preferably, the ratio of the refractive index of the second dielectric layer to the refractive index of the first dielectric layer is 0.94-0.99; the first dielectric layer and the second dielectric layer are made of one or more of silicon oxide, aluminum oxide, silicon nitride and zirconium oxide.
Compared with the prior art, the passivation film and the method for improving the reliability of the flip chip provided by the invention have the advantages that a second dielectric layer with lower density is deposited on a first dielectric layer with higher density, the first dielectric layer with higher density is completely reserved in the step position area of the chip, and a micro-roughening structure is formed on the first dielectric layer in other areas; according to the passivation film prepared by depositing two dielectric layers with different densities and micro-roughening the first dielectric layer with higher density by partition, the problem of electromigration at the step position is solved, the stress of the conventional passivation film is improved, the problems of microcracks, micro defects and the like caused by large stress are avoided, and the reliability of a chip is improved.
Drawings
FIG. 1 is a schematic view of a passivation film according to the present invention;
FIG. 2 is a schematic diagram of a process for preparing a passivation film according to the present invention;
1-chip; 10-step position; 2-an insulating layer; 3-a lower metal film; 4-passivation film; 41-a first dielectric layer; 410-the remainder after micro-roughening; 42-a second dielectric layer; 43-micro-roughening structure; 5-coating a metal film; 6-photoresist.
Detailed Description
The technical scheme protected by the invention is specifically described below with reference to the accompanying drawings.
The invention provides a novel passivation film, which can solve the problems of microcracks, microdefects and the like caused by overlarge stress during the growth of the conventional passivation film, and even the problem of falling of a film layer, thereby influencing the reliability of a chip.
As shown in fig. 1, the passivation film provided by the invention comprises a double-layer structure, and because the step position 10 of the chip 1 is more prone to metal electromigration, in order to ensure the reliability of the step position, different structural designs are adopted for covering the first area of the step position 10 and the second area outside the step position. Specifically, the passivation film includes a first dielectric layer 41 and a second dielectric layer 42 disposed up and down; the first dielectric layer 41 in the second area is subjected to micro-roughening treatment, then a micro-roughening structure is formed, a certain thickness is reserved, the first dielectric layer 41 corresponding to the step position 10 is kept on the original surface without micro-roughening treatment, and then the second dielectric layer 42 is directly deposited on the first dielectric layer 41 subjected to micro-roughening treatment, so that the passivation film can be obtained, the first dielectric layer 41 and the second dielectric layer 42 in the second area are connected through the micro-roughening structure, namely, the contact part of the first dielectric layer 41 and the second dielectric layer in the second area is the micro-roughening structure 43, the micro-roughening structure 43 not only can enhance the bonding force between the first dielectric layer 41 and the second dielectric layer 42, but also can release the stress of the first dielectric layer 41, and avoid the micro-cracking problem caused by overlarge stress; the contact portion of the first dielectric layer 41 in the first region (i.e. the step position 10) and the second dielectric layer 42 maintains the original high density, so that the problem of electromigration of metal at the wall step position 10 can be effectively solved, and the low-density second dielectric layer 42 deposited on the same can release the stress of the first dielectric layer 41 to a certain extent.
The corresponding micro-roughening structure is obtained by etching the surface of the first dielectric layer 41 of the second area facing the second dielectric layer 42, so that the first area of the passivation film finally obtained, namely the step position 10 of the chip 1, has a complete first dielectric layer 41, and the first dielectric layer 41 of the second area is combined with the second dielectric layer 42 after roughening, so that the step position has better metal migration resistance, and meanwhile, the connection reliability of the first dielectric layer and the second dielectric layer is ensured; the micro-roughened structure in fig. 1 is only illustrative, and the shape and size of the micro-roughened structure produced by actual preparation can be controlled by the relevant preparation process.
Because the dielectric layer with lower density is a loose structure, metal atoms are easier to form short-circuit European leakage failure through the loose structure, so that the dielectric layer with higher density is generally selected for preventing electromigration of the metal atoms and ensuring antistatic property of a chip in the field, but the first dielectric film with higher density is easy to cause the problem of short-circuit between an upper metal film and a lower metal film due to microcrack and micro defects caused by stress growth, thereby causing the failure of the chip. According to the invention, a first dielectric film with higher density is firstly selected and deposited on a metal film layer, and then a second dielectric layer with lower density is covered above the first dielectric layer, so that the stress problem is improved. Specifically, the corrosion rate of the first dielectric layer through pure hydrofluoric acid is 1-10 mu m/min; and the second dielectric layer is corroded by pure hydrofluoric acid at a rate of 20-50 mu m/min.
Still further, the ratio of the thickness of the second dielectric layer 42 to the thickness of the first dielectric layer 41 is greater than 1 and less than 10, and the thickness of the remaining portion 410 of the first dielectric layer after micro-roughening remains not less than 10-100nm, i.e. the thickness of the second dielectric layer 42 needs to be greater than the thickness of the first dielectric layer 41; the second dielectric layer 42 is deposited on the first dielectric layer 41, which not only plays a role in protection, but also can maintain stronger adhesion. The passivation film at the step position 10 in the prior art is generally smaller than the thickness of other parts, but the metal migration problem is more likely to occur at the step position 10, and the passivation film can solve the problem in the prior art.
In one embodiment, the materials of the first dielectric layer 41 and the second dielectric layer 42 are one of silicon oxide, aluminum oxide, silicon nitride and zirconium oxide, and the refractive index ratio of the second dielectric layer 42 to the first dielectric layer 41 is 0.94-0.99, and the light transmittance is high in the visible light range and is more than 95%.
Referring to fig. 2, how to form the passivation film of the present invention on the chip to ensure the reliability of the chip will be described in detail.
Firstly, depositing a metal film on a chip structure with steps, wherein the chip structure is a structure comprising an insulating layer 2, firstly depositing an upper metal film 3 on the chip structure, and then manufacturing a first dielectric layer 41 on the upper metal film 3;
then, a micro-roughening structure on the first dielectric layer of the second region is fabricated, specifically, photoresist 6 is coated on the first dielectric layer 41, then, a semiconductor lithography technology is used to keep the photoresist in the first region (step position), as shown in fig. 2, and the photoresist in the second region is perforated, then, the first dielectric layer is etched by adopting a wet etching or dry etching process until the thickness of the first dielectric layer remains not less than 10-100nm, so as to obtain the first dielectric layer with the micro-roughening structure.
Then, a second dielectric layer 42 is formed on the first dielectric layer 41 having the micro-roughening structure, thereby obtaining the passivation film of the present invention.
When the first dielectric layer is subjected to photoetching and perforating, photoresist with multiple reserved step positions within 10% of the periphery can be selected, namely, the complete first dielectric layer is reserved within a certain range outside the step positions, so that the metal migration resistance is further improved. The second area can be etched by adopting an ion etching method, etching gas is generally halogen simple substance or compound gas containing F ions and Cl ions, and the like, and the etching depth is regulated and controlled by controlling the etching power, time and other technological parameters so as to ensure the thickness reserved by the first dielectric layer after etching, so that the first dielectric layer can be connected with the second dielectric layer reliably and simultaneously can act together to improve the stress problem.
The foregoing description is only illustrative of the present invention and is not intended to limit the scope of the invention, and all equivalent structures or equivalent processes or direct or indirect application in other related technical fields are included in the scope of the present invention.
Claims (10)
1. The passivation film is characterized by comprising a first area and a second area, wherein the first area is a corresponding area of a chip step position, and the rest areas are the second area; the first area and the second area comprise a first dielectric layer deposited on the chip metal film and a second dielectric layer deposited on the first dielectric layer; the density of the first medium layer is greater than that of the second medium layer; a micro-roughening structure is formed on one surface of the first dielectric layer of the second region facing the second dielectric layer, and the first dielectric layer of the first region is not roughened.
2. The passivation film for improving reliability of flip chip according to claim 1, wherein the hydrofluoric acid etching rate of the first dielectric layer is 1-10 μm/min; the hydrofluoric acid corrosion rate of the second dielectric layer is 20-50 mu m/min.
3. A passivation film for improving reliability of a flip chip according to claim 1, wherein the ratio of the thickness of the second dielectric layer to the thickness of the first dielectric layer is greater than 1 and less than 10.
4. A passivation film for improving reliability of flip chip according to claim 2, wherein the thickness of the first dielectric layer in the second region remaining after forming the micro-roughened structure is not less than 10-100nm.
5. The passivation film for improving reliability of flip chip of claim 1, wherein the micro-roughened structure is formed by wet etching or dry etching.
6. The passivation film for improving reliability of flip chip according to claim 1, wherein the first dielectric layer and the second dielectric layer are made of one or more of silicon oxide, aluminum oxide, silicon nitride, and zirconium oxide.
7. A method of improving flip chip reliability comprising the steps of:
s1, depositing a first dielectric layer on a metal film of a chip;
s2, etching a micro-roughening structure on the first dielectric layer of the first area; the first area is a corresponding area of the chip step position;
s3, depositing a second dielectric layer on the first dielectric layer;
wherein the density of the first medium layer is greater than that of the second medium layer; and the ratio of the thickness of the second dielectric layer to the thickness of the first dielectric layer is greater than 1 and less than 10.
8. The method of improving reliability of flip-chip as set forth in claim 7, wherein the specific steps in step S2 include:
s21, coating photoresist on the first dielectric layer;
s22, perforating the photoresist of the first dielectric layer of the second area according to a set pattern;
s23, etching the first dielectric layer by wet etching or dry etching to obtain the micro-roughening structure.
9. The method of improving reliability of flip chip of claim 7, wherein the micro-roughened structure has a roughness of 50-300nm; the pure hydrofluoric acid rate of the first dielectric layer is 1-10 mu m/min; the pure hydrofluoric acid rate of the second dielectric layer is 20-50 mu m/min; and the thickness of the first dielectric layer in the second area, which remains after the micro-roughening structure is formed, is not less than 10-100nm.
10. The method of claim 7, wherein the first dielectric layer and the second dielectric layer are made of one or more of silicon oxide, aluminum oxide, silicon nitride, and zirconium oxide.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202311497204.6A CN117253957A (en) | 2023-11-10 | 2023-11-10 | Passivation film and method for improving reliability of flip chip |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202311497204.6A CN117253957A (en) | 2023-11-10 | 2023-11-10 | Passivation film and method for improving reliability of flip chip |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN117253957A true CN117253957A (en) | 2023-12-19 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202311497204.6A Pending CN117253957A (en) | 2023-11-10 | 2023-11-10 | Passivation film and method for improving reliability of flip chip |
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| Country | Link |
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| CN (1) | CN117253957A (en) |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20110042797A1 (en) * | 2009-08-19 | 2011-02-24 | Samsung Electronics Co., Ltd | Semiconductor package and method of manufacturing the same |
| CN104201264A (en) * | 2014-09-10 | 2014-12-10 | 厦门乾照光电股份有限公司 | Production method of infrared light-emitting diode with high-reliability electrodes |
| CN107195747A (en) * | 2017-06-01 | 2017-09-22 | 华南理工大学 | A kind of micron-scale flip LED chips and preparation method thereof |
| CN113745381A (en) * | 2021-09-08 | 2021-12-03 | 福建兆元光电有限公司 | Mini LED chip and manufacturing method thereof |
-
2023
- 2023-11-10 CN CN202311497204.6A patent/CN117253957A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20110042797A1 (en) * | 2009-08-19 | 2011-02-24 | Samsung Electronics Co., Ltd | Semiconductor package and method of manufacturing the same |
| CN104201264A (en) * | 2014-09-10 | 2014-12-10 | 厦门乾照光电股份有限公司 | Production method of infrared light-emitting diode with high-reliability electrodes |
| CN107195747A (en) * | 2017-06-01 | 2017-09-22 | 华南理工大学 | A kind of micron-scale flip LED chips and preparation method thereof |
| CN113745381A (en) * | 2021-09-08 | 2021-12-03 | 福建兆元光电有限公司 | Mini LED chip and manufacturing method thereof |
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