CN117250702B - Photoelectric co-packaging module and photoelectric co-packaging method - Google Patents
Photoelectric co-packaging module and photoelectric co-packaging method Download PDFInfo
- Publication number
- CN117250702B CN117250702B CN202311548061.7A CN202311548061A CN117250702B CN 117250702 B CN117250702 B CN 117250702B CN 202311548061 A CN202311548061 A CN 202311548061A CN 117250702 B CN117250702 B CN 117250702B
- Authority
- CN
- China
- Prior art keywords
- integrated chip
- layer
- redistribution
- optical
- packaging
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 238000004806 packaging method and process Methods 0.000 title claims abstract description 74
- 238000000034 method Methods 0.000 title claims abstract description 20
- 230000003287 optical effect Effects 0.000 claims abstract description 104
- 239000013307 optical fiber Substances 0.000 claims abstract description 29
- 230000005693 optoelectronics Effects 0.000 claims description 31
- 230000008878 coupling Effects 0.000 claims description 26
- 238000010168 coupling process Methods 0.000 claims description 26
- 238000005859 coupling reaction Methods 0.000 claims description 26
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 12
- 229910052710 silicon Inorganic materials 0.000 claims description 12
- 239000010703 silicon Substances 0.000 claims description 12
- 230000007704 transition Effects 0.000 claims description 5
- 239000000853 adhesive Substances 0.000 claims description 4
- 230000001070 adhesive effect Effects 0.000 claims description 4
- 230000010354 integration Effects 0.000 abstract description 8
- 238000005265 energy consumption Methods 0.000 abstract description 3
- 230000000694 effects Effects 0.000 abstract description 2
- 239000000835 fiber Substances 0.000 description 8
- 239000011295 pitch Substances 0.000 description 8
- 230000005540 biological transmission Effects 0.000 description 5
- 238000005516 engineering process Methods 0.000 description 4
- 239000003292 glue Substances 0.000 description 4
- 230000017525 heat dissipation Effects 0.000 description 4
- 238000004891 communication Methods 0.000 description 3
- 229910000679 solder Inorganic materials 0.000 description 3
- 238000003491 array Methods 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000002955 isolation Methods 0.000 description 2
- 238000012545 processing Methods 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 238000013500 data storage Methods 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 239000004519 grease Substances 0.000 description 1
- 230000003993 interaction Effects 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229920001296 polysiloxane Polymers 0.000 description 1
- 230000008569 process Effects 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 230000008054 signal transmission Effects 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 238000003466 welding Methods 0.000 description 1
Classifications
-
- G—PHYSICS
- G02—OPTICS
- G02B—OPTICAL ELEMENTS, SYSTEMS OR APPARATUS
- G02B6/00—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings
- G02B6/24—Coupling light guides
- G02B6/42—Coupling light guides with opto-electronic elements
- G02B6/4201—Packages, e.g. shape, construction, internal or external details
- G02B6/4251—Sealed packages
-
- G—PHYSICS
- G02—OPTICS
- G02B—OPTICAL ELEMENTS, SYSTEMS OR APPARATUS
- G02B6/00—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings
- G02B6/24—Coupling light guides
- G02B6/42—Coupling light guides with opto-electronic elements
- G02B6/4201—Packages, e.g. shape, construction, internal or external details
- G02B6/4219—Mechanical fixtures for holding or positioning the elements relative to each other in the couplings; Alignment methods for the elements, e.g. measuring or observing methods especially used therefor
- G02B6/4236—Fixing or mounting methods of the aligned elements
- G02B6/424—Mounting of the optical light guide
-
- G—PHYSICS
- G02—OPTICS
- G02B—OPTICAL ELEMENTS, SYSTEMS OR APPARATUS
- G02B6/00—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings
- G02B6/24—Coupling light guides
- G02B6/42—Coupling light guides with opto-electronic elements
- G02B6/4201—Packages, e.g. shape, construction, internal or external details
- G02B6/4219—Mechanical fixtures for holding or positioning the elements relative to each other in the couplings; Alignment methods for the elements, e.g. measuring or observing methods especially used therefor
- G02B6/4236—Fixing or mounting methods of the aligned elements
- G02B6/4244—Mounting of the optical elements
-
- G—PHYSICS
- G02—OPTICS
- G02B—OPTICAL ELEMENTS, SYSTEMS OR APPARATUS
- G02B6/00—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings
- G02B6/24—Coupling light guides
- G02B6/42—Coupling light guides with opto-electronic elements
- G02B6/4201—Packages, e.g. shape, construction, internal or external details
- G02B6/4219—Mechanical fixtures for holding or positioning the elements relative to each other in the couplings; Alignment methods for the elements, e.g. measuring or observing methods especially used therefor
- G02B6/4236—Fixing or mounting methods of the aligned elements
- G02B6/4245—Mounting of the opto-electronic elements
Landscapes
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Optics & Photonics (AREA)
- Optical Couplings Of Light Guides (AREA)
- Light Receiving Elements (AREA)
Abstract
The invention relates to a photoelectric co-packaging module and a photoelectric co-packaging method. The photoelectric co-packaging module comprises an intermediate layer, a photon integrated chip, an electronic integrated chip and an optical fiber array; the interposer includes a mounting slot, a redistribution layer, and a redistribution waveguide layer; the photon integrated chip is arranged in the mounting groove and comprises at least one first electric connection part and at least one first optical connection part, and the first optical connection part is optically coupled with the redistribution waveguide layer; the optical fiber array is coupled with the redistribution waveguide layer so as to realize optical packaging; the electronic integrated chip comprises a plurality of second electric connection parts, wherein part of the second electric connection parts are used for electrically connecting the first electric connection parts, and the other part of the second electric connection parts are used for electrically connecting the rewiring layer so as to realize circuit packaging. The photoelectric co-packaging module can achieve at least one effect of improving integration density, improving interconnection bandwidth and reducing energy consumption.
Description
Technical Field
The invention relates to the technical field of chip packaging, in particular to a photoelectric co-packaging module and a photoelectric co-packaging method.
Background
With the rapid development of 5G information technology, the information amount of a data center is suddenly increased, the conventional electrical interconnection technology cannot meet the current demand, and instead, the optical interconnection technology has the advantages of high bandwidth, high speed, low power consumption and the like in the aspects of data storage, transmission and processing.
The silicon-based photoelectronic chip has the advantages of high bandwidth, small volume, low power consumption and the like, and can be mass-produced in a large scale and at low cost by utilizing a CMOS (complementary metal Oxide Semiconductor) process. The traditional packaging modes of the silicon-based optoelectronic integrated chip generally have the modes of wire bonding, surface mounting and the like, and the packaging generally has the problems of small interconnection bandwidth, large occupied area, low integration density and the like, so that the silicon-based optoelectronic integrated chip is not beneficial to being applied to the optical interconnection information technology in a large scale.
Disclosure of Invention
Based on this, it is necessary to provide a photoelectric co-packaging module and a photoelectric co-packaging method for at least one of the problems of small interconnection bandwidth, large occupied area, low integration density, and the like in a packaging manner.
An optoelectronic co-package module comprising:
the interposer comprises a mounting groove, a re-wiring layer and a re-wiring waveguide layer, wherein the re-wiring layer and the re-wiring waveguide layer are arranged on the periphery of the mounting groove, and the re-wiring waveguide layer is used for coupling the light source module;
a photonic integrated chip mounted in the mounting groove, the photonic integrated chip including at least one first electrical connection and at least one optical connection, the optical connection being coupled to the redistribution waveguide layer;
the optical fiber array is connected with the redistribution waveguide layer in a coupling packaging mode so as to realize optical packaging;
the electronic integrated chip, a part of the electronic integrated chip is stacked on the rewiring layer, and another part of the electronic integrated chip is stacked on the photon integrated chip, and the electronic integrated chip comprises at least one second electric connection part and at least one third electric connection part, wherein the second electric connection part is electrically connected with the first electric connection part, and the third electric connection part is electrically connected with the rewiring layer so as to realize circuit packaging.
The light source module is coupled with the optical input port of the photon integrated chip through the redistribution waveguide layer, so that the photon integrated chip receives optical signals; the optical signal can form an optical output signal after being processed by photoelectric information of the photon integrated chip; the optical output end of the photon integrated chip is coupled to the redistribution waveguide layer, and then the output of an optical output signal is realized through the optical fiber array.
The rewiring layer is manufactured on the intermediate layer, so that the circuit connection part of the photon integrated chip can be directly packaged with the electronic integrated chip, the direct interconnection of pins between the optical chip and the electronic chip is realized, the connection, impedance matching and transmission speed of a signal wire are optimized, and the signal loss and delay are reduced.
The photoelectric co-packaging module provided by the invention solves at least one of the problems of long interconnection length, large occupied area, low integration density and the like in the existing packaging mode, and further reduces energy consumption.
In one embodiment, the first electrical connection and the optical connection are disposed on different sides of the photonic integrated chip;
the redistribution layer and the redistribution waveguide layer are disposed on different sides of the interposer.
By arranging the first electric connection part and the optical connection part on different sides of the photon integrated chip, the optical package and the electric package part are not interfered with each other, and the interference of electromagnetic signals can be avoided;
by providing the redistribution layer and the redistribution waveguide layer on different sides of the interposer, interference with the redistribution layer and the redistribution waveguide layer may also be reduced.
In one embodiment, the electronic integrated chip is provided with at least one, and the first electrical connection is provided with at least one group; each electronic integrated chip is correspondingly connected with each group of first electric connection parts.
The plurality of electronic integrated chips are electrically connected into the same photon integrated chip, so that the integration density of the photoelectric co-packaging module can be improved, and the photon integrated chips can be connected with electronic integrated chips with different functions, different numbers and different specifications and sizes, so that the photoelectric co-packaging module can realize different functions.
In one embodiment, the first electrical connection portion, the second electrical connection portion, and the third electrical connection portion are electrode pins; the rewiring layer is provided with a plurality of electrode pins, and the electrode pins of the rewiring layer are electrically connected with the first electrical connection part.
The first electric connection part and the second electric connection part are arranged as electrode pins, so that the first electric connection part and the second electric connection part are connected conveniently. The rewiring layer is provided with a plurality of electrode pins, so that the connection between the rewiring layer and the photonic integrated chip is facilitated.
In one embodiment, the interposer is a silicon interposer.
The interposer is arranged as the silicon interposer, so that the interposer has good heat dissipation performance, and the thermal expansion coefficient of the interposer can be consistent with that of the photonic integrated chip and the electronic integrated chip, thereby effectively reducing the power consumption of the photoelectric co-packaging module and improving the performance of the photoelectric co-packaging module.
In one embodiment, the optical connection is a first optical coupler and the redistribution waveguide layer includes a second optical coupler, the first optical coupler being coupled with the second optical coupler.
By providing the first optical coupler and the second optical coupler, coupling of the optical connection portion with the redistribution layer may be facilitated.
In one embodiment, the redistribution waveguide layer includes a third optical coupler coupled to the optical fiber array, and a plurality of second optical couplers fan-out transitions to a plurality of third optical couplers, and a pitch of two adjacent third optical couplers is greater than a pitch of two adjacent second optical couplers.
The second optical couplers and the third optical couplers are connected in a fan-out transition mode, and the distance between the second optical couplers is smaller, so that the distance between the first optical couplers is kept smaller, the area of an optical connecting part is reduced, the size of a photon integrated chip is further reduced, more flexibility and convenience are provided for the design of optical packaging in the photoelectric co-packaging module, and the difficulty of an optical packaging part is greatly reduced; and the spacing of the third optical couplers can be directly optically coupled with a common type of optical fiber array, for example, so that the transmission of optical signals can be realized.
In one embodiment, the interposer includes opposite upper and lower layers, the redistribution layer and the redistribution waveguide layer are disposed on the upper layer, and the lower layer is provided with a fourth electrical connection portion, and the fourth electrical connection portion is electrically connected to the redistribution layer.
By arranging the fourth electric connection part and realizing the connection between the fourth electric connection part and the upper-layer component, the photoelectric co-packaging module can be electrically connected with a circuit control device such as an external printed circuit board.
In one embodiment, the photonic integrated chip is adhered and fixed in the mounting groove by heat conduction glue, and the upper end surface of the photonic integrated chip is flush with the upper end surface of the interposer.
By adopting the heat-conducting glue, the photonic integrated chip can be firmly arranged in the mounting groove, and the heat conduction between the photonic integrated chip and the intermediate layer is facilitated; in addition, the flush effect of the upper end face of the photon integrated chip and the upper end face of the medium layer is convenient to realize. The upper end face of the photonic integrated chip is arranged to be flush with the upper end face of the intermediate layer, so that the photonic integrated chip is connected with other components.
In one embodiment, the optical fiber array is connected to the redistribution waveguide layer by way of a coupling package.
By selecting a proper coupling packaging mode, the connection between the optical fiber array and the redistribution waveguide layer is facilitated.
In one embodiment, the light source module is stacked on the redistribution waveguide layer or disposed on one side of the redistribution waveguide layer.
By stacking the light source on the re-distributed waveguide layer or on one side of the re-distributed waveguide layer, the connection between the light source and the re-distributed waveguide layer is facilitated.
In one embodiment, the wafer is divided into one or more intermediaries, and each intermediaries is connected with at least one photonic integrated chip, at least one electronic integrated chip and at least one optical fiber array.
The photoelectric co-packaging module can be suitable for wafer level packaging by dividing a plurality of preset areas on a wafer to serve as an intermediate layer.
The invention also provides a photoelectric co-packaging method, which comprises the following steps:
a mounting groove is formed in the intermediate layer, and a rewiring layer and a rewiring waveguide layer are arranged on the periphery of the mounting groove;
mounting a photonic integrated chip in the mounting groove and coupling the photonic integrated chip to the redistribution waveguide layer;
connecting the optical fiber array with the redistribution waveguide layer in a coupling packaging mode;
stacking a portion of an electronic integrated chip on the photonic integrated chip and electrically connecting with the photonic integrated chip; and stacking another part of the electronic integrated chip on the rewiring layer and electrically connecting the rewiring layer.
By the photoelectric co-packaging method, electrical packaging and optical packaging can be simultaneously realized, the integration density and interconnection bandwidth of chip packaging can be improved, and then energy consumption can be reduced.
The photoelectric co-packaging method based on silicon provided by the invention can be applied to wafer level packaging.
In one embodiment, the method further comprises:
at least one preset area is divided on the wafer, and each preset area is used as one medium layer.
The photoelectric co-packaging method can be applied to wafer level packaging by dividing a wafer into one or more preset areas and enabling each preset area to serve as an intermediate layer.
In one embodiment, a light source module is coupled to the redistribution waveguide layer.
The integration of the light source module in the photoelectric co-packaging module is beneficial to improving the integration level of the photoelectric co-packaging module.
Drawings
FIG. 1 is a schematic structural diagram of an optoelectronic co-package module according to an embodiment of the present invention;
FIG. 2 is a plan cross-sectional view of an interposer according to one embodiment of the present invention;
FIG. 3 is a plan view cross-section of a portion of the structure of an optoelectronic co-package module in accordance with one embodiment of the present invention;
FIG. 4 is a plan view cross-section of an embodiment of the present invention in which fiber arrays are connected using end-face coupled packages;
FIG. 5 is a plan view cross-section of an embodiment of the present invention in which the fiber arrays are connected using vertical coupling packages;
FIG. 6 is a schematic structural diagram of an optoelectronic co-package module according to an embodiment of the present invention;
fig. 7 is a flowchart of a method of co-packaging an optoelectronic package according to an embodiment of the invention.
Reference numerals:
1. an interposer; 11. a mounting groove; 12. a connection unit; 121. a rewiring layer; 122. re-distributing the waveguide layer; 2. a photonic integrated chip; 21. a first electrical connection; 22. an optical connection section; 3. an electronic integrated chip; 31. a second electrical connection; 32. a third electrical connection; 5. an optical fiber array; 6. an upper layer; 7. a lower layer; 71. a fourth electrical connection; 100. a wafer; 101. a preset area; 200. and a light source module.
Detailed Description
In order that the above objects, features and advantages of the invention will be readily understood, a more particular description of the invention will be rendered by reference to the appended drawings. In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present invention. The present invention may be embodied in many other forms than described herein and similarly modified by those skilled in the art without departing from the spirit of the invention, whereby the invention is not limited to the specific embodiments disclosed below.
In the description of the present invention, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", "axial", "radial", "circumferential", etc. indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings are merely for convenience in describing the present invention and simplifying the description, and do not indicate or imply that the device or element being referred to must have a specific orientation, be configured and operated in a specific orientation, and therefore should not be construed as limiting the present invention.
Furthermore, the terms "first," "second," and the like, are used for descriptive purposes only and are not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include at least one such feature. In the description of the present invention, the meaning of "plurality" means at least two, for example, two, three, etc., unless specifically defined otherwise.
In the present invention, unless explicitly specified and limited otherwise, the terms "mounted," "connected," "secured," and the like are to be construed broadly, and may be, for example, fixedly connected, detachably connected, or integrally formed; can be mechanically or electrically connected; either directly or indirectly, through intermediaries, or both, may be in communication with each other or in interaction with each other, unless expressly defined otherwise. The specific meaning of the above terms in the present invention can be understood by those of ordinary skill in the art according to the specific circumstances.
In the present invention, unless expressly stated or limited otherwise, a first feature "up" or "down" a second feature may be the first and second features in direct contact, or the first and second features in indirect contact via an intervening medium. Moreover, a first feature being "above," "over" and "on" a second feature may be a first feature being directly above or obliquely above the second feature, or simply indicating that the first feature is level higher than the second feature. The first feature being "under", "below" and "beneath" the second feature may be the first feature being directly under or obliquely below the second feature, or simply indicating that the first feature is less level than the second feature.
It will be understood that when an element is referred to as being "fixed" or "disposed" on another element, it can be directly on the other element or intervening elements may also be present. When an element is referred to as being "connected" to another element, it can be directly connected to the other element or intervening elements may also be present. The terms "vertical," "horizontal," "upper," "lower," "left," "right," and the like are used herein for illustrative purposes only and are not meant to be the only embodiment.
As shown in fig. 1 and 2, an optoelectronic co-package module according to an embodiment of the present invention includes an interposer 1, a photonic integrated chip 2, an electronic integrated chip 3, and an optical fiber array 5.
With further reference to fig. 2 and 3, the interposer 1 includes opposite upper and lower layers 6 and 7, and the upper layer 6 of the interposer 1 may be provided with at least one mounting slot 11 and at least one connection unit 12, the connection unit 12 including a redistribution layer 121 and a redistribution waveguide layer 122.
The redistribution layer 121 and the redistribution waveguide layer 122 may be disposed immediately or adjacent to the mounting groove 11, and in particular, a space between the redistribution layer 121 and the mounting groove 11 may be smaller than a mounting size of the electronic integrated chip 3, that is, smaller than a space between two mounting ends of the electronic integrated chip 3, where one of the two mounting ends of the electronic integrated chip 3 is used to connect the electronic integrated chip 3 and the other is used to connect the photonic integrated chip 2.
The redistribution layer 121 and the redistribution waveguide layer 122 may be disposed on different sides of the interposer 1 such that they are separated from each other, avoiding interference with each other. Illustratively, the redistribution layer 121 and the redistribution waveguide layer 122 are disposed on opposite sides of the interposer 1 to enhance isolation between the redistribution layer 121 and the redistribution waveguide layer 122. For example, redistribution layer 121 is located on the left side of interposer 1 as shown in fig. 1, and redistribution layer 122 is located on the right side of interposer 1 as shown in fig. 1. Alternatively, the redistribution layer 121 may also be located on the upper and lower sides of the interposer 1 as shown in fig. 1.
Illustratively, the interposer 1 may be a silicon interposer, and the thermal expansion coefficient of the silicon interposer may be consistent with that of the optoelectronic chip, so as to facilitate heat dissipation and heat conduction of the chip.
The rewiring layer 121 may be used for electrical connection with the electronic integrated chip 3 and other components. The re-wiring layer 121 may include a copper film or an aluminum film, and the structure of the re-wiring layer 121 may be customized according to actual packaging requirements. In addition, in order to facilitate connection between the redistribution layer 121 and the electronic integrated chips 3, the redistribution layer 121 may further be provided with a plurality of electrode pins, where the redistribution layer 121 is electrically connected to the electronic integrated chips 3 through the electrode pins, and the number and arrangement of the electrode pins in the redistribution layer 121 are adapted to the number and arrangement of the electronic integrated chips 3 to be connected to the redistribution layer 121.
The redistribution layer 122 may be configured to couple with the photonic integrated chip 2, the optical fiber array 5, and the light source module 200, so that an optical signal emitted by the light source module 200 may be transmitted to the redistribution layer 122 first, and then transmitted to the photonic integrated chip 2 through the redistribution layer 122; after processing the input optical signal, the photonic integrated chip 2 outputs the processed optical signal to the redistribution waveguide layer 122, and transmits the optical signal to the optical fiber array 5 through the redistribution waveguide layer 122, so that the optical fiber array 5 can output the optical signal. Thus, by coupling photonic integrated chip 2 and fiber array 5 to redistribution layer 122, an optical package may be realized.
The light source module 200 is an optical signal emitting device, for example, the light source module 200 is a chip embedded with a laser. The output port of light source module 200 may be in coupling alignment with the optical input port of redistribution waveguide layer 122 such that optical signals emitted by light source module 200 may be transmitted to redistribution waveguide layer 122. The light source module 200 may be disposed on a side of the interposer 1 where optical packaging is performed, for example, on a side of the interposer 1 where the redistribution waveguide layer 122 is disposed, to ensure that the optical packaging portion and the electrical packaging portion do not interfere with each other. Specifically, the light source module 200 may be stacked on the re-distribution waveguide layer 122 or disposed at one side of the re-distribution waveguide layer 122 so as to be coupled with the re-distribution waveguide layer 122.
The redistribution waveguide layer 122 may be an optical waveguide structure formed on the interposer 1 by a material such as silicon, silicon nitride, or the like, so that the redistribution waveguide layer 122 has functions of transmission, coupling, splitting, or the like of an optical signal.
The mounting groove 11 may be a groove recessed downward from the upper end surface of the interposer 1, and the mounting groove 11 may be used to accommodate the photonic integrated chip 2. The dimensions of the mounting groove 11 may be slightly larger than the dimensions of the photonic integrated chip 2 to facilitate embedding of the photonic integrated chip 2 within the mounting groove 11.
The lower layer 7 of the interposer 1 may be provided with a fourth electrical connection 71, the fourth electrical connection 71 being capable of making electrical connection with an external device and the rewiring layer 121, so that the optoelectronic co-package module may be electrically connected to the external device for signal transmission. The fourth electrical connection portion 71 may be an electrode pin, and the interposer 1 may be soldered to an external device through the fourth electrical connection portion 71 to achieve electrical connection between the fourth electrical connection portion 71 and the external device; meanwhile, the interposer 1 may further be provided with through silicon vias, which communicate the rewiring layer 121 and the fourth electrical connection portions 71, so as to achieve electrical connection of the fourth electrical connection portions 71 and the rewiring layer 121. The external device is a device to be mounted with the optoelectronic co-packaging module, for example, the external device is a circuit control device such as a printed circuit board.
The photonic integrated chip 2 is mounted in the mounting groove 11. The photonic integrated chip 2 may be flush with the upper end surface of the interposer 1 after being mounted in the mounting groove 11. When other substances are disposed between the photonic integrated chip 2 and the mounting groove 11, the size of the photonic integrated chip 2 may be slightly smaller than the size of the mounting groove 11; for example, the photonic integrated chip 2 is adhered in the mounting groove 11 by a heat-conducting adhesive, and the heat-conducting adhesive compensates the difference between the height of the photonic integrated chip 2 and the depth of the mounting groove 11, so that the photonic integrated chip 2 is flush with the upper end surface of the interposer 1. The photonic integrated chip 2 may be adhesively fixed in the mounting groove 11 by a heat conductive adhesive only at the bottom, for example. The heat-conducting glue is a shapable substance with good heat dissipation and adhesiveness, such as heat-conducting silicone grease with good heat dissipation performance.
The photonic integrated chip 2 may comprise at least one first electrical connection 21 and at least one optical connection 22. The first electrical connection 21 may be used for electrical connection with the electronic integrated chip 3. The optical connection 22 may be used to couple with the redistribution waveguide layer 122. To avoid interference in terms of position or interference in the direction of electromagnetic signals between the electronic integrated chip 3 and the redistribution waveguide layer 122, the first electrical connection portion 21 and the first optical connection portion 22 may be disposed on different sides of the photonic integrated chip 2. Preferably, the first electrical connection portion 21 and the optical connection portion 22 are preferentially disposed on opposite sides of the photonic integrated chip 2, so as to improve the isolation between the first electrical connection portion 21 and the optical connection portion 22, so that the optical package and the electrical package portion do not interfere with each other, and interference of electromagnetic signals is avoided.
The first electrical connection portion 21 may be located on an upper end face of the photonic integrated chip 2, so that the first electrical connection portion 21 may be flush with an upper end face of the interposer 1, and a position of the first electrical connection portion 21 may correspond to a position of the redistribution layer 121, so that the remaining electrical connection portions of the electronic integrated chip 3 and the position of the redistribution layer 121 are soldered and packaged, and the first electrical connection portion 21 and the redistribution layer 121 may be used for electrically connecting the electronic integrated chip 3, so as to facilitate electrical packaging. The position of the optical connection portion 22 may correspond to the redistribution waveguide layer 122, so as to facilitate coupling between the optical connection portion 22 and the redistribution waveguide layer 122, thereby facilitating the photoelectric packaging of the subsequent photonic integrated chips.
The first electrical connection portion 21 may specifically be an electrode pin, and the first electrical connection portion 21 is welded with the electrode pin of the rewiring layer 121; the optical connection 22 may be an optical coupler.
In some embodiments, photonic integrated chip 2 may include a plurality of first optical couplers. The redistribution layer 122 may include a plurality of second optical couplers. The first optical couplers and the second optical couplers are coupled to each other, so that the photonic integrated chip 2 and the redistribution waveguide layer 122 can realize optical coupling, and the pitches of the plurality of second optical couplers are smaller, so that the pitches of the first optical couplers can be reduced, and the size of the photonic integrated chip 2 is further reduced.
Illustratively, redistribution layer 122 includes a plurality of third optical couplers for coupling with fiber array 5. The third optical coupler is optically connected to the second optical coupler. The plurality of third optical couplers may be connected to the plurality of second optical couplers by way of a fan-out transition. The spacing between the plurality of second optical couplers is less than the spacing between the plurality of third optical couplers. The pitch of the plurality of third optical couplers is the same as the pitch between the optical fibers of the conventional optical fiber array so that the plurality of third optical couplers can be coupled with the conventional optical fiber array 5.
In this embodiment, the spacing between the second optical couplers is 50um, and after the fan-out transition between the second optical couplers and the third optical couplers, the spacing between the third optical couplers is 127um, and the specification between the channels of the optical fiber array 5 is 127um, so that the optical fiber array 5 can be coupled with the third optical couplers, and then be optically connected to the photonic integrated chip 2 for coupling transmission of light.
The electronic integrated chip 3 may be provided as one or more. When the electronic integrated chips 3 are provided in plural, the plural electronic integrated chips 3 may have different functions, different numbers, different scales, so that the optoelectronic co-package module integrating the plural electronic integrated chips 3 can realize a plurality of functions that it has. Each electronic integrated chip 3 includes at least one second electrical connection portion 31 and at least one third electrical connection portion 32, wherein the second electrical connection portion 31 is disposed at one mounting end of the electronic integrated chip 3, and the third electrical connection portion 32 is disposed at the other mounting end of the electronic integrated chip 3, so that the mounting size of the electronic integrated chip 3 can be the space between the second electrical connection portion 31 and the third electrical connection portion 32. When the second electrical connection portion 31 and the third electrical connection portion 32 are provided in plurality, the mounting size of the electronic integrated chip 3 may be the minimum pitch between the second electrical connection portion 31 and the third electrical connection portion 32.
The second electrical connection portion 31 is configured to electrically connect with the first electrical connection portion 21, so as to connect the electronic integrated chip 3 with the photonic integrated chip 2; the third electrical connection portion 32 is for electrical connection with the rewiring layer 121; the electronic package is realized by connecting the electronic integrated chip 3 with the photonic integrated chip 2 and the rewiring layer 121, respectively. The second electrical connection portion 31 and the third electrical connection portion 32 may be located at different edges of the electronic integrated chip 3, or may be distributed on left and right sides of the same edge of the electronic integrated chip 3. The second electrical connection portion 31 may be an electrode pin for connection with the first electrical connection portion 21, and the third electrical connection portion 32 may be an electrode pin for connection with the rewiring layer 121. The second electrical connection 31 may be in solder communication with the first electrical connection 21 of the photonic integrated chip 2 by means of solder balls.
When the electronic integrated chip 3 is provided in plurality, the first electrical connection portions 21 of the photonic integrated chip 2 may be provided in plurality and distributed on multiple sides of the photonic integrated chip 2, for example, on the left side of the photonic integrated chip 2, and on the upper and lower sides adjacent to the left side, the first electrical connection portions 21 are provided, and on the right side, the optical connection portions 22 are provided.
Referring to fig. 4 and 5, the optical fiber array 5 may be coupled to the redistribution waveguide layer 122 in a manner of selecting a vertical coupling package or an end-face coupling package according to the kind of the optical coupler.
As shown in fig. 6, the optoelectronic co-package module of the present invention can be applied to wafer level package. Specifically, the optoelectronic co-packaging module may further include a wafer 100, where the wafer 100 may divide one or more preset areas 101, each preset area 101 may be used as an interposer 1, and each preset area 101 may be further connected with a photonic integrated chip 2, an electronic integrated chip 3, and an optical fiber array 5 for connection with the interposer 1, so that optoelectronic co-packaging may be completed in each preset area 101, that is, each preset area 101 may form a packaging unit with optoelectronic co-packaging, and the packaging unit may include components such as the interposer 1, the photonic integrated chip 2, the electronic integrated chip 3, and the optical fiber array 5 in one preset area 101.
The plurality of package units formed on the wafer 100 may be packaged together into a photovoltaic co-package module, or the plurality of package units may be individually packaged after being divided.
As shown in fig. 7, the present invention further provides a method for co-packaging an optoelectronic package, including:
step S2: the interposer 1 is provided with a mounting groove 11, and a redistribution layer 121 and a redistribution layer 122 are provided on the periphery of the mounting groove 11. The pitch between the rewiring layer 121 and the mounting groove 11 is smaller than the mounting size of the electronic integrated chip 3.
Step S3: the photonic integrated chip 2 is mounted in the mounting groove 11. The photonic integrated chip 2 is also coupled to a redistribution layer 122. For example, coupling the first optocoupler with the second optocoupler.
Step S4: stacking a part of the electronic integrated chip 3 on the photonic integrated chip 2 and electrically connecting with the photonic integrated chip 2; another part of the electronic integrated chip 3 is stacked on the rewiring layer 121 and is electrically connected to the rewiring layer 121.
Step S5: the fiber array 5 is coupled to a redistribution layer 122. For example, a third optical coupler is coupled to the fiber array 5.
The step S3 may specifically include: the bottom of the mounting groove 11 is coated with heat-conducting glue, and then the photonic integrated chip 2 is mounted in the mounting groove 11, so that the photonic integrated chip 2 is adhered and fixed in the mounting groove 11.
The step S4 may specifically include: stacking a mounting end of the electronic integrated chip 3 corresponding to the photonic integrated chip 2 on the photonic integrated chip 2, and performing welding communication with the first electric connection part 21 of the photonic integrated chip 2 through a solder ball by the second electric connection part 31 positioned at the mounting end; a mounting end of the electronic integrated chip 3 corresponding to the rewiring layer 121 is stacked on the rewiring layer 121, and soldered to an electrode pin of the rewiring layer 121 through a third electrical connection portion 32 located at the mounting end.
In step S5: the fiber array 5 may be connected to the redistribution waveguide layer 122 by means of a vertical coupling package or an end-face coupling package.
Illustratively, the optoelectronic co-packaging method further comprises: step S6: light source module 200 is coupled to the redistribution layer 122. The light source module 200 may be stacked on the re-distribution waveguide layer 122, or the light source module 200 may be mounted on one side of the re-distribution waveguide layer 122.
In addition, the photoelectric co-packaging method of the present invention can also be applied to wafer level packaging, and when the photoelectric co-packaging method is also applied to wafer level packaging, the photoelectric co-packaging method further includes:
step S1: at least one preset area 101 is formed on the wafer 100, and each preset area 101 is used as an interposer 1. The wafer 100 may be a silicon wafer.
In step S5: the fiber array 5 may be connected to the redistribution waveguide layer 122 by means of a vertical coupling package.
Wherein step S1 may be performed before step S2, and step S6 may be performed after step S5.
The technical features of the above-described embodiments may be arbitrarily combined, and all possible combinations of the technical features in the above-described embodiments are not described for brevity of description, however, as long as there is no contradiction between the combinations of the technical features, they should be considered as the scope of the description.
The above examples illustrate only a few embodiments of the invention, which are described in detail and are not to be construed as limiting the scope of the invention. It should be noted that it will be apparent to those skilled in the art that several variations and modifications can be made without departing from the spirit of the invention, which are all within the scope of the invention. Accordingly, the scope of protection of the present invention is to be determined by the appended claims.
Claims (13)
1. An optoelectronic co-package module, comprising:
an interposer (1) comprising a mounting groove (11), a redistribution layer (121) and a redistribution waveguide layer (122), wherein the redistribution layer (121) and the redistribution waveguide layer (122) are arranged on the periphery side of the mounting groove (11), and the redistribution waveguide layer (122) is used for coupling with a light source module (200);
a photonic integrated chip (2) mounted to the mounting groove (11), the photonic integrated chip (2) comprising at least one first electrical connection (21) and at least one optical connection (22), the optical connection (22) being coupled to the redistribution layer (122);
an optical fiber array (5), wherein the optical fiber array (5) is connected with the redistribution waveguide layer (122) in a coupling packaging mode so as to realize optical packaging;
an electronic integrated chip (3), a part of the electronic integrated chip (3) is stacked on the rewiring layer (121), another part of the electronic integrated chip (3) is stacked on the photonic integrated chip (2), the electronic integrated chip (3) comprises at least one second electric connection part (31) and at least one third electric connection part (32), the second electric connection part (31) is electrically connected with the first electric connection part (21), and the third electric connection part (32) is electrically connected with the rewiring layer (121) so as to realize circuit packaging.
2. The optoelectronic co-package module according to claim 1, characterized in that the first electrical connection (21) and the optical connection (22) are provided on different sides of the photonic integrated chip (2);
the redistribution layer (121) and the redistribution waveguide layer (122) are disposed on different sides of the interposer (1).
3. The optoelectronic co-packaging module according to claim 2, characterized in that the electronic integrated chip (3) is provided with at least one, the first electrical connection (21) being provided with at least one group; each electronic integrated chip (3) is correspondingly connected with each group of the first electric connection parts (21).
4. The optoelectronic co-package module of claim 1, wherein the first electrical connection (21), the second electrical connection (31) and the third electrical connection (32) are electrode pins;
the rewiring layer (121) is provided with a plurality of electrode pins, and the electrode pins of the rewiring layer (121) are electrically connected with the first electrical connection part (21).
5. The optoelectronic co-package module of claim 4, wherein the interposer (1) is a silicon interposer.
6. The optoelectronic co-package module of claim 1, wherein the optical connection (22) is a first optical coupler, the redistribution waveguide layer (122) comprises a second optical coupler and a third optical coupler, the first optical coupler is coupled to the second optical coupler, and the third optical coupler is coupled to the optical fiber array (5);
the fan-out transition of the plurality of second optical couplers to the plurality of third optical couplers is performed, and the distance between two adjacent third optical couplers is larger than the distance between two adjacent second optical couplers.
7. The optoelectronic co-package module of claim 1, wherein the interposer (1) comprises opposing upper (6) and lower (7) layers, the redistribution layer (121) and the redistribution layer (122) being disposed on the upper layer (6), the lower layer (7) being provided with a fourth electrical connection (71), the fourth electrical connection (71) being electrically connected to the redistribution layer (121).
8. The optoelectronic co-package module according to claim 1, wherein the photonic integrated chip (2) is fixed in the mounting groove (11) by means of a thermally conductive adhesive, and an upper end surface of the photonic integrated chip (2) is flush with an upper end surface of the interposer (1).
9. The optoelectronic co-package module according to claim 1, characterized in that the optical fiber array (5) is connected to the redistribution waveguide layer (122) by means of a coupling package;
the light source module (200) is stacked on the re-distribution waveguide layer (122) or is arranged on one side of the re-distribution waveguide layer (122).
10. The optoelectronic co-package module of claim 1, comprising a wafer (100), the wafer (100) being divided by one or more of the interposers (1), each interposer (1) being connected with at least one photonic integrated chip (2), at least one electronic integrated chip (3) and at least one optical fiber array (5).
11. A method of optoelectronic co-packaging comprising:
a mounting groove (11) is formed in the interposer (1), and a rewiring layer (121) and a rewiring waveguide layer (122) are arranged on the periphery of the mounting groove (11);
-mounting a photonic integrated chip (2) in the mounting groove (11) and coupling the photonic integrated chip (2) to the redistribution waveguide layer (122);
connecting the optical fiber array (5) with the redistribution waveguide layer (122) in a coupling packaging mode;
stacking a part of an electronic integrated chip (3) on the photonic integrated chip (2) and electrically connecting with the photonic integrated chip (2); another part of the electronic integrated chip (3) is stacked on the rewiring layer (121) and is electrically connected with the rewiring layer (121).
12. The optoelectronic co-packaging method of claim 11, further comprising:
at least one predetermined area (101) is divided on the wafer (100), and each predetermined area (101) is used as one interposer (1).
13. The optoelectronic co-packaging method of claim 11, further comprising: a light source module (200) is coupled to the redistribution layer (122).
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202311548061.7A CN117250702B (en) | 2023-11-20 | 2023-11-20 | Photoelectric co-packaging module and photoelectric co-packaging method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202311548061.7A CN117250702B (en) | 2023-11-20 | 2023-11-20 | Photoelectric co-packaging module and photoelectric co-packaging method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN117250702A CN117250702A (en) | 2023-12-19 |
| CN117250702B true CN117250702B (en) | 2024-02-23 |
Family
ID=89135475
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202311548061.7A Active CN117250702B (en) | 2023-11-20 | 2023-11-20 | Photoelectric co-packaging module and photoelectric co-packaging method |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN117250702B (en) |
Citations (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2001242331A (en) * | 2000-03-01 | 2001-09-07 | Nippon Telegr & Teleph Corp <Ntt> | Semiconductor device |
| JP2006053473A (en) * | 2004-08-16 | 2006-02-23 | Sony Corp | Optical waveguide module and mounting structure thereof |
| CN110635848A (en) * | 2018-06-25 | 2019-12-31 | 台湾积体电路制造股份有限公司 | Optical transceiver |
| WO2020237706A1 (en) * | 2019-05-30 | 2020-12-03 | 上海新微技术研发中心有限公司 | Method for packaging silicon optical module, and silicon optical module |
| CN113053835A (en) * | 2019-12-26 | 2021-06-29 | 台湾积体电路制造股份有限公司 | Semiconductor package and method of forming the same |
| CN114830003A (en) * | 2019-10-31 | 2022-07-29 | 埃亚尔实验室公司 | Vertically integrated photonic chiplets for in-package optical interconnects |
| CN114899155A (en) * | 2022-06-08 | 2022-08-12 | 华天科技（昆山）电子有限公司 | Multi-type multi-quantity chip three-dimensional stacking integrated packaging structure and manufacturing method thereof |
| CN115376929A (en) * | 2021-05-19 | 2022-11-22 | 联合微电子中心有限责任公司 | Wafer-level fan-out type packaged photoelectric module and preparation method thereof |
| CN115542458A (en) * | 2022-11-30 | 2022-12-30 | 中国电子科技集团公司信息科学研究院 | Heterogeneous integrated photoelectric micro-system and manufacturing method thereof |
| CN218938553U (en) * | 2022-10-19 | 2023-04-28 | 深南电路股份有限公司 | Photoelectric co-packaging structure |
| CN116960002A (en) * | 2023-09-21 | 2023-10-27 | 盛合晶微半导体(江阴)有限公司 | Photoelectric integrated semiconductor packaging structure and preparation method thereof |
-
2023
- 2023-11-20 CN CN202311548061.7A patent/CN117250702B/en active Active
Patent Citations (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2001242331A (en) * | 2000-03-01 | 2001-09-07 | Nippon Telegr & Teleph Corp <Ntt> | Semiconductor device |
| JP2006053473A (en) * | 2004-08-16 | 2006-02-23 | Sony Corp | Optical waveguide module and mounting structure thereof |
| CN110635848A (en) * | 2018-06-25 | 2019-12-31 | 台湾积体电路制造股份有限公司 | Optical transceiver |
| WO2020237706A1 (en) * | 2019-05-30 | 2020-12-03 | 上海新微技术研发中心有限公司 | Method for packaging silicon optical module, and silicon optical module |
| CN114830003A (en) * | 2019-10-31 | 2022-07-29 | 埃亚尔实验室公司 | Vertically integrated photonic chiplets for in-package optical interconnects |
| CN113053835A (en) * | 2019-12-26 | 2021-06-29 | 台湾积体电路制造股份有限公司 | Semiconductor package and method of forming the same |
| CN115376929A (en) * | 2021-05-19 | 2022-11-22 | 联合微电子中心有限责任公司 | Wafer-level fan-out type packaged photoelectric module and preparation method thereof |
| CN114899155A (en) * | 2022-06-08 | 2022-08-12 | 华天科技（昆山）电子有限公司 | Multi-type multi-quantity chip three-dimensional stacking integrated packaging structure and manufacturing method thereof |
| CN218938553U (en) * | 2022-10-19 | 2023-04-28 | 深南电路股份有限公司 | Photoelectric co-packaging structure |
| CN115542458A (en) * | 2022-11-30 | 2022-12-30 | 中国电子科技集团公司信息科学研究院 | Heterogeneous integrated photoelectric micro-system and manufacturing method thereof |
| CN116960002A (en) * | 2023-09-21 | 2023-10-27 | 盛合晶微半导体(江阴)有限公司 | Photoelectric integrated semiconductor packaging structure and preparation method thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| CN117250702A (en) | 2023-12-19 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US7470069B1 (en) | Optoelectronic MCM package | |
| JP4653190B2 (en) | Photoelectric conversion module capable of directly optically connecting light emitting element array and optical waveguide array, and method for manufacturing the photoelectric conversion module | |
| US20080008477A1 (en) | Optical transmission between devices on circuit board | |
| US9111925B2 (en) | Process for enhanced 3D integration and structures generated using the same | |
| CN109287092B (en) | Optical module | |
| US20060016962A1 (en) | Photoelectric transducer and photoelectric transducer element array | |
| US7622700B2 (en) | Photo-electric conversion apparatus with alternating photoelectric conversion elements | |
| US20240053558A1 (en) | Integration of oe devices with ics | |
| JP3725453B2 (en) | Semiconductor device | |
| CN112216672A (en) | Hybrid carrier plate, manufacturing method thereof, assembly and optical module | |
| US6396967B1 (en) | Optoelectronic integrated circuit device | |
| JP2004286835A (en) | Optical element mounted device, its manufacturing method, and wiring board with the optical element mounted device | |
| CN117250702B (en) | Photoelectric co-packaging module and photoelectric co-packaging method | |
| CN218767433U (en) | Optical module | |
| CN114488419A (en) | Optical module packaging structure | |
| CN219831453U (en) | Chip system packaging structure | |
| CN117170047B (en) | High-speed optical module based on three-dimensional packaging form | |
| CN115542478B (en) | Three-dimensional packaging structure and packaging method based on photoelectric chip double-sided process | |
| JP4654807B2 (en) | Optical information processing equipment | |
| KR100765465B1 (en) | Structure of stacking and packaging silicon chips using a long-wavelength optical sources | |
| US11143549B2 (en) | Electronic packaging structure and method for manufacturing the electronic packaging structure with optical guide die separate from electronic package and photonic die | |
| JP3553403B2 (en) | High-speed signal processor | |
| CN112216665A (en) | Optical module | |
| CN112216688A (en) | Support plate and optical module | |
| JP2006108150A (en) | Semiconductor device and mounting method thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |